Lines Matching +full:0 +full:x2d
27 {19, 19, 4, 0},
28 {26, 102, 5, 0},
29 {53, 112, 6, 0},
30 {41, 100, 7, 0},
31 {83, 108, 8, 0},
32 {87, 118, 9, 0},
33 {95, 115, 12, 0},
34 {108, 108, 13, 0},
35 {83, 83, 17, 0},
36 {67, 98, 20, 0},
37 {121, 121, 24, 0},
38 {99, 99, 29, 0},
58 {22, 22, 2, 0},
59 {28, 28, 3, 0},
104 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
105 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
106 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
107 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
108 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
109 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
110 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
111 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
112 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
113 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
114 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
115 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
116 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
117 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
121 {VIACR, CR07, 0x10, 0x10}, /* [0] vertical total (bit 8)
129 {VIACR, CR08, 0xFF, 0x00}, /* [0-4] preset row scan
131 {VIACR, CR09, 0xDF, 0x40}, /* [0-4] max scan line
135 {VIACR, CR0A, 0xFF, 0x1E}, /* [0-4] cursor start
137 {VIACR, CR0B, 0xFF, 0x00}, /* [0-4] cursor end
139 {VIACR, CR0E, 0xFF, 0x00}, /* [0-7] cursor location (high) */
140 {VIACR, CR0F, 0xFF, 0x00}, /* [0-7] cursor location (low) */
141 {VIACR, CR11, 0xF0, 0x80}, /* [0-3] vertical retrace end
144 {VIACR, CR14, 0xFF, 0x00}, /* [0-4] underline location
147 {VIACR, CR17, 0xFF, 0x63}, /* [0-1] mapping of display address 13-14
153 {VIACR, CR18, 0xFF, 0xFF}, /* [0-7] line compare */
158 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
166 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
168 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
173 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
175 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
180 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
182 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
188 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
190 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
195 /* Index 0x00~0x03 */
196 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
197 0x2A,
198 0x2A},
199 /* Index 0x04~0x07 */
200 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
201 0x2A,
202 0x2A},
203 /* Index 0x08~0x0B */
204 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
205 0x3F,
206 0x3F},
207 /* Index 0x0C~0x0F */
208 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
209 0x3F,
210 0x3F},
211 /* Index 0x10~0x13 */
212 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
213 0x0B,
214 0x0B},
215 /* Index 0x14~0x17 */
216 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
217 0x18,
218 0x18},
219 /* Index 0x18~0x1B */
220 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
221 0x28,
222 0x28},
223 /* Index 0x1C~0x1F */
224 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
225 0x3F,
226 0x3F},
227 /* Index 0x20~0x23 */
228 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
229 0x00,
230 0x3F},
231 /* Index 0x24~0x27 */
232 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
233 0x00,
234 0x10},
235 /* Index 0x28~0x2B */
236 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
237 0x2F,
238 0x00},
239 /* Index 0x2C~0x2F */
240 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
241 0x3F,
242 0x00},
243 /* Index 0x30~0x33 */
244 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
245 0x3F,
246 0x2F},
247 /* Index 0x34~0x37 */
248 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
249 0x10,
250 0x3F},
251 /* Index 0x38~0x3B */
252 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
253 0x1F,
254 0x3F},
255 /* Index 0x3C~0x3F */
256 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
257 0x1F,
258 0x27},
259 /* Index 0x40~0x43 */
260 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
261 0x3F,
262 0x1F},
263 /* Index 0x44~0x47 */
264 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
265 0x3F,
266 0x1F},
267 /* Index 0x48~0x4B */
268 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
269 0x3F,
270 0x37},
271 /* Index 0x4C~0x4F */
272 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
273 0x27,
274 0x3F},
275 /* Index 0x50~0x53 */
276 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
277 0x2D,
278 0x3F},
279 /* Index 0x54~0x57 */
280 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
281 0x2D,
282 0x31},
283 /* Index 0x58~0x5B */
284 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
285 0x3A,
286 0x2D},
287 /* Index 0x5C~0x5F */
288 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
289 0x3F,
290 0x2D},
291 /* Index 0x60~0x63 */
292 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
293 0x3F,
294 0x3A},
295 /* Index 0x64~0x67 */
296 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
297 0x31,
298 0x3F},
299 /* Index 0x68~0x6B */
300 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
301 0x00,
302 0x1C},
303 /* Index 0x6C~0x6F */
304 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
305 0x00,
306 0x07},
307 /* Index 0x70~0x73 */
308 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
309 0x15,
310 0x00},
311 /* Index 0x74~0x77 */
312 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
313 0x1C,
314 0x00},
315 /* Index 0x78~0x7B */
316 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
317 0x1C,
318 0x15},
319 /* Index 0x7C~0x7F */
320 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
321 0x07,
322 0x1C},
323 /* Index 0x80~0x83 */
324 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
325 0x0E,
326 0x1C},
327 /* Index 0x84~0x87 */
328 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
329 0x0E,
330 0x11},
331 /* Index 0x88~0x8B */
332 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
333 0x18,
334 0x0E},
335 /* Index 0x8C~0x8F */
336 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
337 0x1C,
338 0x0E},
339 /* Index 0x90~0x93 */
340 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
341 0x1C,
342 0x18},
343 /* Index 0x94~0x97 */
344 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
345 0x11,
346 0x1C},
347 /* Index 0x98~0x9B */
348 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
349 0x14,
350 0x1C},
351 /* Index 0x9C~0x9F */
352 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
353 0x14,
354 0x16},
355 /* Index 0xA0~0xA3 */
356 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
357 0x1A,
358 0x14},
359 /* Index 0xA4~0xA7 */
360 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
361 0x1C,
362 0x14},
363 /* Index 0xA8~0xAB */
364 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
365 0x1C,
366 0x1A},
367 /* Index 0xAC~0xAF */
368 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
369 0x16,
370 0x1C},
371 /* Index 0xB0~0xB3 */
372 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
373 0x00,
374 0x10},
375 /* Index 0xB4~0xB7 */
376 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
377 0x00,
378 0x04},
379 /* Index 0xB8~0xBB */
380 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
381 0x0C,
382 0x00},
383 /* Index 0xBC~0xBF */
384 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
385 0x10,
386 0x00},
387 /* Index 0xC0~0xC3 */
388 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
389 0x10,
390 0x0C},
391 /* Index 0xC4~0xC7 */
392 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
393 0x04,
394 0x10},
395 /* Index 0xC8~0xCB */
396 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
397 0x08,
398 0x10},
399 /* Index 0xCC~0xCF */
400 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
401 0x08,
402 0x0A},
403 /* Index 0xD0~0xD3 */
404 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
405 0x0E,
406 0x08},
407 /* Index 0xD4~0xD7 */
408 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
409 0x10,
410 0x08},
411 /* Index 0xD8~0xDB */
412 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
413 0x10,
414 0x0E},
415 /* Index 0xDC~0xDF */
416 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
417 0x0A,
418 0x10},
419 /* Index 0xE0~0xE3 */
420 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
421 0x0B,
422 0x10},
423 /* Index 0xE4~0xE7 */
424 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
425 0x0B,
426 0x0C},
427 /* Index 0xE8~0xEB */
428 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
429 0x0F,
430 0x0B},
431 /* Index 0xEC~0xEF */
432 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
433 0x10,
434 0x0B},
435 /* Index 0xF0~0xF3 */
436 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
437 0x10,
438 0x0F},
439 /* Index 0xF4~0xF7 */
440 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
441 0x0C,
442 0x10},
443 /* Index 0xF8~0xFB */
444 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
445 0x00,
446 0x00},
447 /* Index 0xFC~0xFF */
448 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
449 0x00,
450 0x00}
485 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); in viafb_unlock_crt()
486 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
511 return 0; in get_dvi_devices()
517 return 0; in get_dvi_devices()
525 return 0; in get_dvi_devices()
554 return 0; in get_lcd_devices()
560 int crt_iga_path = 0; in viafb_set_iga_path()
601 viafb_SAMM_ON = 0; in viafb_set_iga_path()
624 viaparinfo->shared->iga1_devices = 0; in viafb_set_iga_path()
625 viaparinfo->shared->iga2_devices = 0; in viafb_set_iga_path()
673 outb(0xFF, 0x3C6); /* bit mask of palette */ in set_color_register()
674 outb(index, 0x3C8); in set_color_register()
675 outb(red, 0x3C9); in set_color_register()
676 outb(green, 0x3C9); in set_color_register()
677 outb(blue, 0x3C9); in set_color_register()
682 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); in viafb_set_primary_color_register()
688 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); in viafb_set_secondary_color_register()
698 value = 0x00; in set_source_common()
717 value = 0x00; in set_crt_source()
720 value = 0x40; in set_crt_source()
727 via_write_reg_mask(VIASR, 0x16, value, 0x40); in set_crt_source()
732 set_source_common(0x6C, 7, iga); in set_ldvp0_source()
737 set_source_common(0x93, 7, iga); in set_ldvp1_source()
742 set_source_common(0x96, 4, iga); in set_dvp0_source()
747 set_source_common(0x9B, 4, iga); in set_dvp1_source()
752 set_source_common(0x99, 4, iga); in set_lvds1_source()
757 set_source_common(0x97, 4, iga); in set_lvds2_source()
784 value = 0x00; in set_crt_state()
787 value = 0x10; in set_crt_state()
790 value = 0x20; in set_crt_state()
793 value = 0x30; in set_crt_state()
799 via_write_reg_mask(VIACR, 0x36, value, 0x30); in set_crt_state()
808 value = 0xC0; in set_dvp0_state()
811 value = 0x00; in set_dvp0_state()
817 via_write_reg_mask(VIASR, 0x1E, value, 0xC0); in set_dvp0_state()
826 value = 0x30; in set_dvp1_state()
829 value = 0x00; in set_dvp1_state()
835 via_write_reg_mask(VIASR, 0x1E, value, 0x30); in set_dvp1_state()
844 value = 0x03; in set_lvds1_state()
847 value = 0x00; in set_lvds1_state()
853 via_write_reg_mask(VIASR, 0x2A, value, 0x03); in set_lvds1_state()
862 value = 0x0C; in set_lvds2_state()
865 value = 0x00; in set_lvds2_state()
871 via_write_reg_mask(VIASR, 0x2A, value, 0x0C); in set_lvds2_state()
902 via_write_misc_reg_mask(polarity << 6, 0xC0); in via_set_sync_polarity()
904 via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); in via_set_sync_polarity()
906 via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); in via_set_sync_polarity()
908 via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); in via_set_sync_polarity()
914 u32 odev = 0; in via_parse_odev()
920 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { in via_parse_odev()
939 int i, count = 0; in via_odev_to_seq()
941 for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { in via_odev_to_seq()
943 if (count > 0) in via_odev_to_seq()
959 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); in load_fix_bit_crtc_reg()
961 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
963 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
964 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */ in load_fix_bit_crtc_reg()
971 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); in load_fix_bit_crtc_reg()
974 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
983 int bit_num = 0; in viafb_load_reg()
990 for (i = 0; i < viafb_load_reg_num; i++) { in viafb_load_reg()
991 reg_mask = 0; in viafb_load_reg()
992 data = 0; in viafb_load_reg()
1021 for (i = 0; i < ItemNum; i++) in viafb_write_regx()
1056 int iga1_fifo_max_depth = 0, iga1_fifo_threshold = in viafb_load_FIFO_reg()
1057 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0; in viafb_load_FIFO_reg()
1058 int iga2_fifo_max_depth = 0, iga2_fifo_threshold = in viafb_load_FIFO_reg()
1059 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0; in viafb_load_FIFO_reg()
1390 struct via_pll_config cur, up, down, best = {0, 1, 0}; in get_pll_config()
1394 for (i = 0; i < size; i++) { in get_pll_config()
1466 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ in viafb_set_vclock()
1529 if (flag == 0) { in viafb_update_device_setting()
1552 viafb_write_reg(CR4F, VIACR, 0x55); in init_gfx_chip_info()
1553 if (viafb_read_reg(VIACR, CR4F) != 0x55) in init_gfx_chip_info()
1566 if (tmp & 0x02) { in init_gfx_chip_info()
1569 } else if (tmp & 0x40) { in init_gfx_chip_info()
1681 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1683 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1684 for (i = 0; i < 256; i++) { in viafb_init_dac()
1690 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1694 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
1695 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1696 for (i = 0; i < 256; i++) { in viafb_init_dac()
1702 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1710 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); in device_screen_off()
1716 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); in device_screen_on()
1727 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1731 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); in set_display_channel()
1734 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); in set_display_channel()
1739 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); in set_display_channel()
1742 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); in set_display_channel()
1749 u8 polarity = 0; in get_sync()
1763 outb(0x00, VIAAR); in hw_init()
1800 via_write_reg_mask(VIACR, 0x45, 0x00, 0x01); in hw_init()
1803 via_write_reg_mask(VIACR, 0xFD, 0, 0x80); /* VX900 hw scale on IGA2 */ in hw_init()
1814 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); in hw_init()
1817 for (i = 0; i < StdGR; i++) in hw_init()
1821 for (i = 0; i < StdAR; i++) { in hw_init()
1828 outb(0x20, VIAAR); in hw_init()
1835 int j, cxres = 0, cyres = 0; in viafb_setmode()
1853 for (j = 0; j < res_patch_table[0].table_length; j++) { in viafb_setmode()
1854 index = res_patch_table[0].io_reg_table[j].index; in viafb_setmode()
1855 port = res_patch_table[0].io_reg_table[j].port; in viafb_setmode()
1856 value = res_patch_table[0].io_reg_table[j].value; in viafb_setmode()
1857 mask = res_patch_table[0].io_reg_table[j].mask; in viafb_setmode()
1895 viafb_fill_crtc_timing(&viafbinfo->var, 0, 0, in viafb_setmode()
1915 viafb_dvi_set_mode(&viafbinfo->var, 0, 0, in viafb_setmode()
1931 viafb_lcd_set_mode(&viafbinfo->var, 0, 0, in viafb_setmode()
1948 viafb_lcd_set_mode(&viafbinfo->var, 0, 0, in viafb_setmode()
2047 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2055 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2056 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); in disable_second_display_channel()
2068 p_gfx_dpa_setting->DVP0, 0x0F); in viafb_set_dpa_gfx()
2087 p_gfx_dpa_setting->DVP1, 0x0F); in viafb_set_dpa_gfx()
2091 p_gfx_dpa_setting->DVP1Driving, 0x0F); in viafb_set_dpa_gfx()
2098 p_gfx_dpa_setting->DFPHigh, 0x0F); in viafb_set_dpa_gfx()
2105 p_gfx_dpa_setting->DFPLow, 0x0F); in viafb_set_dpa_gfx()
2112 p_gfx_dpa_setting->DFPHigh, 0x0F); in viafb_set_dpa_gfx()
2114 p_gfx_dpa_setting->DFPLow, 0x0F); in viafb_set_dpa_gfx()