Lines Matching full:cycle
477 dma_addr_t pci_base, u32 aspace, u32 cycle) in tsi148_slave_set() argument
565 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { in tsi148_slave_set()
577 /* Setup cycle types */ in tsi148_slave_set()
579 if (cycle & VME_BLT) in tsi148_slave_set()
581 if (cycle & VME_MBLT) in tsi148_slave_set()
583 if (cycle & VME_2eVME) in tsi148_slave_set()
585 if (cycle & VME_2eSST) in tsi148_slave_set()
587 if (cycle & VME_2eSSTB) in tsi148_slave_set()
595 if (cycle & VME_SUPER) in tsi148_slave_set()
597 if (cycle & VME_USER) in tsi148_slave_set()
599 if (cycle & VME_PROG) in tsi148_slave_set()
601 if (cycle & VME_DATA) in tsi148_slave_set()
622 dma_addr_t *pci_base, u32 *aspace, u32 *cycle) in tsi148_slave_get() argument
661 *cycle = 0; in tsi148_slave_get()
688 *cycle |= VME_2eSST160; in tsi148_slave_get()
690 *cycle |= VME_2eSST267; in tsi148_slave_get()
692 *cycle |= VME_2eSST320; in tsi148_slave_get()
695 *cycle |= VME_BLT; in tsi148_slave_get()
697 *cycle |= VME_MBLT; in tsi148_slave_get()
699 *cycle |= VME_2eVME; in tsi148_slave_get()
701 *cycle |= VME_2eSST; in tsi148_slave_get()
703 *cycle |= VME_2eSSTB; in tsi148_slave_get()
706 *cycle |= VME_SUPER; in tsi148_slave_get()
708 *cycle |= VME_USER; in tsi148_slave_get()
710 *cycle |= VME_PROG; in tsi148_slave_get()
712 *cycle |= VME_DATA; in tsi148_slave_get()
813 u32 cycle, u32 dwidth) in tsi148_master_set() argument
915 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { in tsi148_master_set()
927 /* Setup cycle types */ in tsi148_master_set()
928 if (cycle & VME_BLT) { in tsi148_master_set()
932 if (cycle & VME_MBLT) { in tsi148_master_set()
936 if (cycle & VME_2eVME) { in tsi148_master_set()
940 if (cycle & VME_2eSST) { in tsi148_master_set()
944 if (cycle & VME_2eSSTB) { in tsi148_master_set()
1006 if (cycle & VME_SUPER) in tsi148_master_set()
1008 if (cycle & VME_PROG) in tsi148_master_set()
1055 u32 *cycle, u32 *dwidth) in __tsi148_master_get() argument
1095 *cycle = 0; in __tsi148_master_get()
1123 *cycle |= VME_2eSST160; in __tsi148_master_get()
1125 *cycle |= VME_2eSST267; in __tsi148_master_get()
1127 *cycle |= VME_2eSST320; in __tsi148_master_get()
1129 /* Setup cycle types */ in __tsi148_master_get()
1131 *cycle |= VME_SCT; in __tsi148_master_get()
1133 *cycle |= VME_BLT; in __tsi148_master_get()
1135 *cycle |= VME_MBLT; in __tsi148_master_get()
1137 *cycle |= VME_2eVME; in __tsi148_master_get()
1139 *cycle |= VME_2eSST; in __tsi148_master_get()
1141 *cycle |= VME_2eSSTB; in __tsi148_master_get()
1144 *cycle |= VME_SUPER; in __tsi148_master_get()
1146 *cycle |= VME_USER; in __tsi148_master_get()
1149 *cycle |= VME_PROG; in __tsi148_master_get()
1151 *cycle |= VME_DATA; in __tsi148_master_get()
1165 u32 *cycle, u32 *dwidth) in tsi148_master_get() argument
1172 cycle, dwidth); in tsi148_master_get()
1184 u32 aspace, cycle, dwidth; in tsi148_master_read() local
1197 &cycle, &dwidth); in tsi148_master_read()
1210 * cycle configured for the transfer is used and splits it in tsi148_master_read()
1212 * overhead of needlessly forcing small transfers for the entire cycle. in tsi148_master_read()
1270 u32 aspace, cycle, dwidth; in tsi148_master_write() local
1287 &cycle, &dwidth); in tsi148_master_write()
1363 * Perform an RMW cycle on the VME bus.
1424 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_src_attributes() argument
1431 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { in tsi148_dma_set_vme_src_attributes()
1443 /* Setup cycle types */ in tsi148_dma_set_vme_src_attributes()
1444 if (cycle & VME_SCT) in tsi148_dma_set_vme_src_attributes()
1447 if (cycle & VME_BLT) in tsi148_dma_set_vme_src_attributes()
1450 if (cycle & VME_MBLT) in tsi148_dma_set_vme_src_attributes()
1453 if (cycle & VME_2eVME) in tsi148_dma_set_vme_src_attributes()
1456 if (cycle & VME_2eSST) in tsi148_dma_set_vme_src_attributes()
1459 if (cycle & VME_2eSSTB) { in tsi148_dma_set_vme_src_attributes()
1513 if (cycle & VME_SUPER) in tsi148_dma_set_vme_src_attributes()
1515 if (cycle & VME_PROG) in tsi148_dma_set_vme_src_attributes()
1524 u32 aspace, u32 cycle, u32 dwidth) in tsi148_dma_set_vme_dest_attributes() argument
1531 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { in tsi148_dma_set_vme_dest_attributes()
1543 /* Setup cycle types */ in tsi148_dma_set_vme_dest_attributes()
1544 if (cycle & VME_SCT) in tsi148_dma_set_vme_dest_attributes()
1547 if (cycle & VME_BLT) in tsi148_dma_set_vme_dest_attributes()
1550 if (cycle & VME_MBLT) in tsi148_dma_set_vme_dest_attributes()
1553 if (cycle & VME_2eVME) in tsi148_dma_set_vme_dest_attributes()
1556 if (cycle & VME_2eSST) in tsi148_dma_set_vme_dest_attributes()
1559 if (cycle & VME_2eSSTB) { in tsi148_dma_set_vme_dest_attributes()
1613 if (cycle & VME_SUPER) in tsi148_dma_set_vme_dest_attributes()
1615 if (cycle & VME_PROG) in tsi148_dma_set_vme_dest_attributes()
1700 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1737 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); in tsi148_dma_list_add()
1931 u32 aspace, u32 cycle) in tsi148_lm_set() argument
1974 if (cycle & VME_SUPER) in tsi148_lm_set()
1976 if (cycle & VME_USER) in tsi148_lm_set()
1978 if (cycle & VME_PROG) in tsi148_lm_set()
1980 if (cycle & VME_DATA) in tsi148_lm_set()
1998 unsigned long long *lm_base, u32 *aspace, u32 *cycle) in tsi148_lm_get() argument
2030 *cycle |= VME_SUPER; in tsi148_lm_get()
2032 *cycle |= VME_USER; in tsi148_lm_get()
2034 *cycle |= VME_PROG; in tsi148_lm_get()
2036 *cycle |= VME_DATA; in tsi148_lm_get()