Lines Matching full:only
32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
111 #define CLK_TVENC 270 /* Exynos4210 only */
126 #define CLK_MDNIE0 285 /* Exynos4412 only */
129 #define CLK_FIMD1 288 /* Exynos4210 only */
130 #define CLK_MIE1 289 /* Exynos4210 only */
131 #define CLK_DSIM1 290 /* Exynos4210 only */
132 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
136 #define CLK_SATA_PHY 295 /* Exynos4210 only */
143 #define CLK_SATA 302 /* Exynos4210 only */
190 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
193 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
194 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
195 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
196 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
197 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
198 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
199 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
200 #define CLK_MCUISP 360 /* Exynos4x12 only */
201 #define CLK_GICISP 361 /* Exynos4x12 only */
202 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
203 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
204 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
206 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
207 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
208 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
209 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
210 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
211 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
212 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
213 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
214 #define CLK_UART_ISP 374 /* Exynos4x12 only */
215 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
216 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
217 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
218 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
219 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
220 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
221 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
222 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
237 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
251 #define CLK_PPMULCD1 409 /* Exynos4210 only */
260 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
261 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
263 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
265 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
268 #define CLK_DIV_C2C 458 /* Exynos4x12 only */