Lines Matching full:some

41 #define	AT91_CKGR_UCKR		0x1C			/* UTMI Clock Register [some SAM9] */
51 #define		AT91_PMC_MOSCRCEN	(1    <<  3)		/* Main On-Chip RC Oscillator Enable [some SAM9] */
55 #define		AT91_PMC_MOSCSEL	(1    << 24)		/* Main Oscillator Selection [some SAM9] */
56 #define		AT91_PMC_CFDEN		(1    << 25)		/* Clock Failure Detector Enable [some SAM9] */
83 #define			AT91_PMC_CSS_UPLL		(3 << 0)	/* [some SAM9 only] */
110 #define			AT91SAM9_PMC_MDIV_6		(3 << 8)	/* [some SAM9 only] */
111 #define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
112 #define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
115 #define		AT91_PMC_PLLADIV2	(1 << 12)		/* PLLA divisor by 2 [some SAM9 only] */
120 #define	AT91_PMC_USB		0x38			/* USB Clock Register [some SAM9 only] */
129 #define	AT91_PMC_SMD		0x3c			/* Soft Modem Clock Register [some SAM9 only] */
136 #define			AT91_PMC_CSS_MASTER		(4 << 0)	/* [some SAM9 only] */
148 #define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [some SAM9] */
149 #define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Oscillator Selection [some SAM9] */
154 #define		AT91_PMC_MOSCSELS	(1 << 16)		/* Main Oscillator Selection [some SAM9] */
155 #define		AT91_PMC_MOSCRCS	(1 << 17)		/* Main On-Chip RC [some SAM9] */
156 #define		AT91_PMC_CFDEV		(1 << 18)		/* Clock Failure Detector Event [some SAM9] */
175 #define AT91_PMC_PROT		0xe4			/* Write Protect Mode Register [some SAM9] */
180 #define AT91_PMC_WPSR		0xe8			/* Write Protect Status Register [some SAM9] */
188 #define AT91_PMC_PCR		0x10c			/* Peripheral Control Register [some SAM9 and SAMA5] */