Lines Matching +full:write +full:- +full:protect
50 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
57 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
61 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
67 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
68 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
78 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
118 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
119 #define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
120 #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
121 #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
123 #define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
124 #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
125 #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */