Lines Matching +full:clock +full:- +full:error +full:- +full:detect
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
48 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
49 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
50 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
51 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
52 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
53 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
54 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
55 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
56 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
57 #define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */
60 #define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1)
61 #define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1)
62 #define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1)
67 #define AK4114_CM1 (1<<5) /* Master Clock Operation Select */
68 #define AK4114_CM0 (1<<4) /* Master Clock Operation Select */
69 #define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */
70 #define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */
79 #define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */
80 #define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */
81 #define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */
82 #define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */
83 #define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */
85 #define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = I…
88 #define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */
89 #define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */
113 #define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */
132 #define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
133 #define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
136 #define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */
137 #define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */
138 #define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */
139 #define AK4114_PAR (1<<0) /* parity error or biphase error status, 0 = no error, 1 = error */
154 #define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */
155 #define AK4114_CCRC (1<<0) /* CRC for channel status, 0 = no error, 1 = error */