Lines Matching +full:48 +full:- +full:bit
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <sound/pcm-indirect.h>
40 /* ------------------- DEFINES -------------------- */
44 #define MAXPAGES0 4096 /* 32 bit mode */
45 #define MAXPAGES1 8192 /* 31 bit mode */
52 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
53 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
54 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
70 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
72 /* accessed. For non per-channel registers the */
82 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
108 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
116 /* the bit in H/CLIPL or H/CLIPH corresponding */
121 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
126 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
130 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
131 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
132 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
133 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
135 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
146 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
147 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
151 /* NOTE: This bit must always be enabled */
163 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
164 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
193 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
198 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
199 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
202 /* they are not rate-locked to the external */
206 /* the SPDIF V-bit indicates invalid audio */
221 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
222 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
233 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
239 /* they are not rate-locked to the external */
252 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
256 //For Audigy, MPU port move to 0x70-0x74 ptr register
279 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
303 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
305 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
306 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
332 /* 0x00000000 2-channel output. */
333 /* 0x00000200 8-channel output. */
336 /* bit 0: Enable P16V audio.
337 * bit 1: Lock P16V record memory cache.
338 * bit 2: Lock P16V playback memory cache.
339 * bit 3: Dummy record insert zero samples.
340 * bit 8: Record 8-channel in phase.
341 * bit 9: Playback 8-channel in phase.
342 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
343 * bit 13: Playback mixer enable.
344 * bit 14: Route SRC48 mixer output to fx engine.
345 * bit 15: Enable IEEE 1394 chip.
369 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
435 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
464 #define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
470 #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
473 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
479 /* 0x8000-n == 666*n usec delay */
483 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
498 /* 0x8000-n == 666*n usec delay */
502 /* 0x8000-n == 666*n usec delay */
506 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
518 /* 0x8000-n == 666*n usec delay */
536 /* Signed 2's complement, +/- one octave peak extremes */
539 /* Signed 2's complement, +/- six octaves peak extremes */
543 /* Signed 2's complement, +/- one octave extremes */
545 /* Signed 2's complement, +/- three octave extremes */
550 /* Signed 2's complement, with +/- 12dB extremes */
556 /* Signed 2's complement, +/- one octave extremes */
561 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
584 /* 0x30-3f seem to be the same as 0x20-2f */
602 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
615 /* When set, each bit enables the writing of the */
617 /* 0x20-0x3f) to host memory. This mode of recording */
618 /* is 16bit, 48KHz only. All 32 channels can be enabled */
649 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
652 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
655 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
657 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
665 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
714 #define CDCS 0x50 /* CD-ROM digital channel status register */
732 // NOTE: 0x54,55,56: 64-bit
745 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
753 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
754 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
755 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
759 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
761 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
765 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
781 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
782 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
793 // NOTE: 0x60,61,62: 64-bit
794 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
808 /* Note that these values can vary +/- by a small amount */
814 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
818 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
828 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
831 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
864 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
865 /* Each bit selects a channel for recording */
866 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
867 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
900 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
918 /* 0x7c, 0x7e "high bit is used for filtering" */
932 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
933 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
939 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
943 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
1028 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1032 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1038 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1040 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1046 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1054 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1060 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1070 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1077 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1084 /* 0x14 - 0x1f Unused R/W registers */
1101 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1102 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1104 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1105 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1108 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1109 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1111 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1112 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1114 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1115 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1117 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1118 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1120 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1121 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1122 /* 0x30 - 0x3f Unused Read only registers */
1128 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1129 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1130 * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1147 * 0x04, 0x00-0x07: Hana ADAT
1159 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1160 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1161 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1170 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1175 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1176 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1177 * 0x06-0x07: Not used
1180 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1181 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1187 * 0x04-0x07: Not used
1190 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1191 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1197 * 0x04-0x07: Not used
1200 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1201 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1202 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1211 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1215 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1216 * 0x05-0x07: Not used
1220 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1222 * - 16 x EMU_DST_ALICE2_EMU32_X.
1224 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1225 /* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
1227 * setup of mixer control for each destination - see emumixer.c -
1246 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1250 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1254 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1258 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1262 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1266 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1268 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1272 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1274 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1278 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1280 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1284 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1286 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1288 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1290 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1294 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1307 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1311 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1318 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1320 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1327 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1328 * 0x00,0x00-0x1f: Silence
1329 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1340 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1341 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1342 * 0x04, 0x00-0x07: Hana ADAT
1345 * 0x06-0x07: Not used
1351 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1352 * 0x00,0x00-0x1f: Silence
1353 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1362 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1367 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1368 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1369 * 0x04, 0x00-0x07: Hana3 ADAT
1372 * 0x06-0x07: Not used
1375 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1376 * 0x00,0x00-0x1f: Silence
1380 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1381 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1385 * 0x06-0x07: Not used
1388 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1389 * 0x00,0x00-0x1f: Silence
1393 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1394 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1398 * 0x06-0x07: Not used
1401 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1402 * 0x00,0x00-0x1f: Silence
1403 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1412 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1416 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1417 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1418 * 0x04-0x07: Not used
1422 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1423 * destinations using mixer control for each destination - see emumixer.c
1425 * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
1429 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1433 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1437 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1441 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1445 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1449 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1453 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1457 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1461 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1465 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1472 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1474 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1478 /* Microdock S/PDIF Left, 1st or 48kHz only */
1482 /* Microdock S/PDIF Right, 1st or 48kHz only */
1491 /* ------------------- STRUCTURES -------------------- */
1571 …efine snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (P…
1600 unsigned int channels; /* 16-bit channels count */
1662 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1669 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1680 const char *id; /* for backward compatibility - can be NULL if not needed */
1686 unsigned int adc_pads; /* bit mask */
1687 unsigned int dac_pads; /* bit mask */
1859 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >>… in snd_emu10k1_wc()