Lines Matching +full:adc +full:- +full:joystick
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <sound/pcm-indirect.h>
40 /* ------------------- DEFINES -------------------- */
52 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
70 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
72 /* accessed. For non per-channel registers the */
103 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
104 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
108 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
121 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
126 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
130 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
131 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
132 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
133 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
135 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
146 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
147 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
158 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
163 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
164 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
198 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
199 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
202 /* they are not rate-locked to the external */
206 /* the SPDIF V-bit indicates invalid audio */
221 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
222 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
229 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
233 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
239 /* they are not rate-locked to the external */
252 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
256 //For Audigy, MPU port move to 0x70-0x74 ptr register
279 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
306 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
332 /* 0x00000000 2-channel output. */
333 /* 0x00000200 8-channel output. */
340 * bit 8: Record 8-channel in phase.
341 * bit 9: Playback 8-channel in phase.
342 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
353 #define JOYSTICK1 0x00 /* Analog joystick port register */
354 #define JOYSTICK2 0x01 /* Analog joystick port register */
355 #define JOYSTICK3 0x02 /* Analog joystick port register */
356 #define JOYSTICK4 0x03 /* Analog joystick port register */
357 #define JOYSTICK5 0x04 /* Analog joystick port register */
358 #define JOYSTICK6 0x05 /* Analog joystick port register */
359 #define JOYSTICK7 0x06 /* Analog joystick port register */
360 #define JOYSTICK8 0x07 /* Analog joystick port register */
364 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
365 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
369 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
435 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
479 /* 0x8000-n == 666*n usec delay */
483 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
498 /* 0x8000-n == 666*n usec delay */
502 /* 0x8000-n == 666*n usec delay */
506 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
518 /* 0x8000-n == 666*n usec delay */
536 /* Signed 2's complement, +/- one octave peak extremes */
539 /* Signed 2's complement, +/- six octaves peak extremes */
543 /* Signed 2's complement, +/- one octave extremes */
545 /* Signed 2's complement, +/- three octave extremes */
550 /* Signed 2's complement, with +/- 12dB extremes */
556 /* Signed 2's complement, +/- one octave extremes */
561 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
584 /* 0x30-3f seem to be the same as 0x20-2f */
592 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
617 /* 0x20-0x3f) to host memory. This mode of recording */
651 #define ADCBA 0x46 /* ADC buffer address register */
657 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
661 #define ADCBS 0x4a /* ADC buffer size register */
665 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
667 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
714 #define CDCS 0x50 /* CD-ROM digital channel status register */
732 // NOTE: 0x54,55,56: 64-bit
753 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
754 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
755 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
759 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
761 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
765 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
781 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
782 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
793 // NOTE: 0x60,61,62: 64-bit
794 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
808 /* Note that these values can vary +/- by a small amount */
814 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
817 #define ADCIDX 0x64 /* ADC recording buffer index register */
828 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
831 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
866 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
867 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
881 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
900 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
932 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
933 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
1054 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1055 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1056 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1057 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1058 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1084 /* 0x14 - 0x1f Unused R/W registers */
1122 /* 0x30 - 0x3f Unused Read only registers */
1129 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1130 * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1147 * 0x04, 0x00-0x07: Hana ADAT
1160 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1161 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1170 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1175 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1176 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1177 * 0x06-0x07: Not used
1181 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1187 * 0x04-0x07: Not used
1191 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1197 * 0x04-0x07: Not used
1201 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1202 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1211 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1215 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1216 * 0x05-0x07: Not used
1220 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1222 * - 16 x EMU_DST_ALICE2_EMU32_X.
1224 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1225 /* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
1227 * setup of mixer control for each destination - see emumixer.c -
1328 * 0x00,0x00-0x1f: Silence
1329 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1332 * 0x01, 0x08: Dock ADC 1 Left
1333 * 0x01, 0x0c: Dock ADC 1 Right
1334 * 0x01, 0x10: Dock ADC 2 Left
1335 * 0x01, 0x14: Dock ADC 2 Right
1336 * 0x01, 0x18: Dock ADC 3 Left
1337 * 0x01, 0x1c: Dock ADC 3 Right
1338 * 0x02, 0x00: Hana ADC Left
1339 * 0x02, 0x01: Hana ADC Right
1340 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1341 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1342 * 0x04, 0x00-0x07: Hana ADAT
1345 * 0x06-0x07: Not used
1352 * 0x00,0x00-0x1f: Silence
1353 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1356 * 0x01, 0x08: Dock ADC 1 Left
1357 * 0x01, 0x0c: Dock ADC 1 Right
1358 * 0x01, 0x10: Dock ADC 2 Left
1360 * 0x01, 0x14: Dock ADC 2 Right
1362 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1363 * 0x01, 0x18: Dock ADC 3 Left
1364 * 0x01, 0x1c: Dock ADC 3 Right
1365 * 0x02, 0x00: Hanoa ADC Left
1366 * 0x02, 0x01: Hanoa ADC Right
1367 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1368 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1369 * 0x04, 0x00-0x07: Hana3 ADAT
1372 * 0x06-0x07: Not used
1376 * 0x00,0x00-0x1f: Silence
1378 * 0x02, 0x00: ADC Left
1379 * 0x02, 0x01: ADC Right
1380 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1381 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1385 * 0x06-0x07: Not used
1389 * 0x00,0x00-0x1f: Silence
1391 * 0x02, 0x00: ADC Left
1392 * 0x02, 0x01: ADC Right
1393 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1394 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1398 * 0x06-0x07: Not used
1402 * 0x00,0x00-0x1f: Silence
1403 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1406 * 0x01, 0x08: Dock ADC 1 Left
1407 * 0x01, 0x0c: Dock ADC 1 Right
1408 * 0x01, 0x10: Dock ADC 2 Left
1410 * 0x01, 0x14: Dock ADC 2 Right
1412 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1413 * 0x01, 0x18: Dock ADC 3 Left
1414 * 0x01, 0x1c: Dock ADC 3 Right
1416 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1417 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1418 * 0x04-0x07: Not used
1422 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1423 * destinations using mixer control for each destination - see emumixer.c
1425 * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
1461 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1462 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1463 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1464 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1465 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1466 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1467 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1468 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1491 /* ------------------- STRUCTURES -------------------- */
1571 …efine snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (P…
1600 unsigned int channels; /* 16-bit channels count */
1669 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1675 unsigned char i2c_adc; /* I2C interface for ADC */
1676 unsigned char adc_1361t; /* Use Philips 1361T ADC */
1680 const char *id; /* for backward compatibility - can be NULL if not needed */
1859 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >>… in snd_emu10k1_wc()