Lines Matching +full:tx +full:- +full:enable
2 * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
23 #define AACI_TXCR 0x004 /* 17 bits Control Tx FIFO */
26 #define AACI_IE 0x010 /* 7 bits Int Enable */
39 #define AACI_SLIEN 0x070 /* slot interrupt enable */
52 * TX/RX fifo control register (CR). P48
54 #define CR_FEN (1 << 16) /* fifo enable */
72 #define CR_EN (1 << 0) /* transmit enable */
79 #define SR_TXU (1 << 9) /* tx underrun */
81 #define SR_TXB (1 << 7) /* tx busy */
83 #define SR_TXFF (1 << 5) /* tx fifo full */
85 #define SR_TXHE (1 << 3) /* tx fifo half empty */
87 #define SR_TXFE (1 << 1) /* tx fifo empty */
94 #define ISR_URINTR (1 << 5) /* tx underflow */
97 #define ISR_TXINTR (1 << 2) /* tx fifo intr */
98 #define ISR_RXTOINTR (1 << 1) /* tx timeout */
99 #define ISR_TXCINTR (1 << 0) /* tx complete */
102 * interrupt enable register bits.
116 #define ISR_UR (1 << 5) /* tx fifo underrun */
119 #define ISR_TX (1 << 2) /* tx interrupt status */
121 #define ISR_TXC (1 << 0) /* tx complete */
124 * interrupt enable. P52
127 #define IE_UR (1 << 5) /* tx fifo underrun */
130 #define IE_TX (1 << 2) /* tx interrupt status */
132 #define IE_TXC (1 << 0) /* tx complete */
137 #define SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
139 #define SLFR_12TXE (1 << 11) /* slot 12 tx empty */
141 #define SLFR_2TXE (1 << 9) /* slot 2 tx empty */
143 #define SLFR_1TXE (1 << 7) /* slot 1 tx empty */
145 #define SLFR_12TXB (1 << 5) /* slot 12 tx busy */
147 #define SLFR_2TXB (1 << 3) /* slot 2 tx busy */
149 #define SLFR_1TXB (1 << 1) /* slot 1 tx busy */
173 #define MAINCR_DMAEN (1 << 9) /* dma enable */
174 #define MAINCR_SL12TXEN (1 << 8) /* slot 12 transmit enable */
175 #define MAINCR_SL12RXEN (1 << 7) /* slot 12 receive enable */
176 #define MAINCR_SL2TXEN (1 << 6) /* slot 2 transmit enable */
177 #define MAINCR_SL2RXEN (1 << 5) /* slot 2 receive enable */
178 #define MAINCR_SL1TXEN (1 << 4) /* slot 1 transmit enable */
179 #define MAINCR_SL1RXEN (1 << 3) /* slot 1 receive enable */
182 #define MAINCR_IE (1 << 0) /* aaci interface enable */