Lines Matching +full:switch +full:- +full:freq
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 * Copyright 2011-2012 Maxim Integrated Products
256 switch (reg) { in max98090_volatile_register()
269 switch (reg) { in max98090_readable_register()
283 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
284 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
287 dev_err(max98090->component->dev, in max98090_reset()
304 -600, 600, 0);
307 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
312 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
317 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
319 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
321 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
322 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
326 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
327 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
331 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
332 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
333 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
334 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
339 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
340 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
341 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
342 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
347 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
348 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
349 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
360 (struct soc_mixer_control *)kcontrol->private_value; in max98090_get_enab_tlv()
361 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_get_enab_tlv()
362 unsigned int val = snd_soc_component_read32(component, mc->reg); in max98090_get_enab_tlv()
365 switch (mc->reg) { in max98090_get_enab_tlv()
367 select = &(max98090->pa1en); in max98090_get_enab_tlv()
370 select = &(max98090->pa2en); in max98090_get_enab_tlv()
373 select = &(max98090->sidetone); in max98090_get_enab_tlv()
376 return -EINVAL; in max98090_get_enab_tlv()
379 val = (val >> mc->shift) & mask; in max98090_get_enab_tlv()
383 val = val - 1; in max98090_get_enab_tlv()
390 ucontrol->value.integer.value[0] = val; in max98090_get_enab_tlv()
400 (struct soc_mixer_control *)kcontrol->private_value; in max98090_put_enab_tlv()
401 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_put_enab_tlv()
402 unsigned int sel = ucontrol->value.integer.value[0]; in max98090_put_enab_tlv()
403 unsigned int val = snd_soc_component_read32(component, mc->reg); in max98090_put_enab_tlv()
406 switch (mc->reg) { in max98090_put_enab_tlv()
408 select = &(max98090->pa1en); in max98090_put_enab_tlv()
411 select = &(max98090->pa2en); in max98090_put_enab_tlv()
414 select = &(max98090->sidetone); in max98090_put_enab_tlv()
417 return -EINVAL; in max98090_put_enab_tlv()
420 val = (val >> mc->shift) & mask; in max98090_put_enab_tlv()
432 snd_soc_component_update_bits(component, mc->reg, in max98090_put_enab_tlv()
433 mask << mc->shift, in max98090_put_enab_tlv()
434 sel << mc->shift); in max98090_put_enab_tlv()
518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
604 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
606 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
608 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
671 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
673 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
676 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
678 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
681 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
683 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
694 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
702 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
707 M98090_FLT_DMIC34HPF_NUM - 1, 0),
710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
725 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_micinput_event()
739 unsigned int val = snd_soc_component_read32(component, w->reg); in max98090_micinput_event()
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { in max98090_micinput_event()
748 max98090->pa1en = val - 1; /* Update for volatile */ in max98090_micinput_event()
750 max98090->pa2en = val - 1; /* Update for volatile */ in max98090_micinput_event()
754 switch (event) { in max98090_micinput_event()
757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
758 val = max98090->pa1en + 1; in max98090_micinput_event()
760 val = max98090->pa2en + 1; in max98090_micinput_event()
767 return -EINVAL; in max98090_micinput_event()
770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, in max98090_micinput_event()
774 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, in max98090_micinput_event()
783 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_shdn_event()
787 max98090->shdn_pending = true; in max98090_shdn_event()
832 /* LINEA mixer switch */
834 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
836 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
838 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
840 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
844 /* LINEB mixer switch */
846 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
848 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
850 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
852 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
856 /* Left ADC mixer switch */
858 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
860 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
862 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
864 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
866 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
868 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
870 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
874 /* Right ADC mixer switch */
876 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
878 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
880 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
882 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
884 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
886 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
888 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
948 /* Left speaker mixer switch */
951 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
953 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
955 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
957 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
959 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
961 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
965 /* Right speaker mixer switch */
968 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
970 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
972 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
974 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
976 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
978 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
982 /* Left headphone mixer switch */
984 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
986 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
988 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
990 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
992 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
994 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
998 /* Right headphone mixer switch */
1000 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1002 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1004 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1006 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1008 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1010 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1014 /* Left receiver mixer switch */
1016 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1018 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1020 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1022 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1024 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1026 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1030 /* Right receiver mixer switch */
1032 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1034 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1036 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1038 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1040 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1042 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1277 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1278 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1279 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1280 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1281 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1282 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1283 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1286 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1287 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1288 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1289 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1290 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1291 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1292 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1295 {"LINEA Mixer", "IN1 Switch", "IN1"},
1296 {"LINEA Mixer", "IN3 Switch", "IN3"},
1297 {"LINEA Mixer", "IN5 Switch", "IN5"},
1298 {"LINEA Mixer", "IN34 Switch", "IN34"},
1301 {"LINEB Mixer", "IN2 Switch", "IN2"},
1302 {"LINEB Mixer", "IN4 Switch", "IN4"},
1303 {"LINEB Mixer", "IN6 Switch", "IN6"},
1304 {"LINEB Mixer", "IN56 Switch", "IN56"},
1355 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1356 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1357 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1358 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1359 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1360 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1363 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1364 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1365 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1366 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1367 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1368 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1371 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1372 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1373 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1374 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1375 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1376 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1379 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1380 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1381 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1382 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1383 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1384 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1387 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1388 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1389 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1390 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1391 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1392 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1395 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1396 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1397 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1398 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1399 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1400 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1452 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1463 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1506 if (!max98090->sysclk) { in max98090_configure_bclk()
1507 dev_err(component->dev, "No SYSCLK configured\n"); in max98090_configure_bclk()
1511 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1512 dev_err(component->dev, "No audio clocks configured\n"); in max98090_configure_bclk()
1524 if ((pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1525 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1526 dev_dbg(component->dev, in max98090_configure_bclk()
1541 if ((user_pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1542 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1543 dev_dbg(component->dev, in max98090_configure_bclk()
1545 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", in max98090_configure_bclk()
1580 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1581 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1582 do_div(ni, (unsigned long long int)max98090->sysclk); in max98090_configure_bclk()
1583 dev_info(component->dev, "No better method found\n"); in max98090_configure_bclk()
1584 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); in max98090_configure_bclk()
1593 struct snd_soc_component *component = codec_dai->component; in max98090_dai_set_fmt()
1598 max98090->dai_fmt = fmt; in max98090_dai_set_fmt()
1599 cdata = &max98090->dai[0]; in max98090_dai_set_fmt()
1601 if (fmt != cdata->fmt) { in max98090_dai_set_fmt()
1602 cdata->fmt = fmt; in max98090_dai_set_fmt()
1605 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { in max98090_dai_set_fmt()
1607 /* Set to slave mode PLL - MAS mode off */ in max98090_dai_set_fmt()
1614 max98090->master = false; in max98090_dai_set_fmt()
1618 if (max98090->tdm_slots == 4) { in max98090_dai_set_fmt()
1622 } else if (max98090->tdm_slots == 3) { in max98090_dai_set_fmt()
1631 max98090->master = true; in max98090_dai_set_fmt()
1636 dev_err(component->dev, "DAI clock mode unsupported"); in max98090_dai_set_fmt()
1637 return -EINVAL; in max98090_dai_set_fmt()
1642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { in max98090_dai_set_fmt()
1654 dev_err(component->dev, "DAI format unsupported"); in max98090_dai_set_fmt()
1655 return -EINVAL; in max98090_dai_set_fmt()
1658 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { in max98090_dai_set_fmt()
1671 dev_err(component->dev, "DAI invert mode unsupported"); in max98090_dai_set_fmt()
1672 return -EINVAL; in max98090_dai_set_fmt()
1681 if (max98090->tdm_slots > 1) in max98090_dai_set_fmt()
1694 struct snd_soc_component *component = codec_dai->component; in max98090_set_tdm_slot()
1697 cdata = &max98090->dai[0]; in max98090_set_tdm_slot()
1700 return -EINVAL; in max98090_set_tdm_slot()
1702 max98090->tdm_slots = slots; in max98090_set_tdm_slot()
1703 max98090->tdm_width = slot_width; in max98090_set_tdm_slot()
1705 if (max98090->tdm_slots > 1) { in max98090_set_tdm_slot()
1721 cdata->fmt = 0; in max98090_set_tdm_slot()
1722 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); in max98090_set_tdm_slot()
1733 switch (level) { in max98090_set_bias_level()
1745 if (IS_ERR(max98090->mclk)) in max98090_set_bias_level()
1749 clk_disable_unprepare(max98090->mclk); in max98090_set_bias_level()
1751 ret = clk_prepare_enable(max98090->mclk); in max98090_set_bias_level()
1759 ret = regcache_sync(max98090->regmap); in max98090_set_bias_level()
1761 dev_err(component->dev, in max98090_set_bias_level()
1769 /* Set internal pull-up to lowest power mode */ in max98090_set_bias_level()
1772 regcache_mark_dirty(max98090->regmap); in max98090_set_bias_level()
1787 int freq; member
1792 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1796 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1797 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1798 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1799 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1800 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1801 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1807 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1808 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1809 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1810 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1811 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1812 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1818 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1819 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1820 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1821 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1822 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1823 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1829 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1830 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1831 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1832 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1833 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1834 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1840 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1841 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1842 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1843 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1844 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1845 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1858 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); in max98090_find_divisor()
1880 m1 = pclk - dmic_table[i-1].pclk; in max98090_find_closest_pclk()
1881 m2 = dmic_table[i].pclk - pclk; in max98090_find_closest_pclk()
1883 return i - 1; in max98090_find_closest_pclk()
1889 return -EINVAL; in max98090_find_closest_pclk()
1907 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { in max98090_configure_dmic()
1912 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; in max98090_configure_dmic()
1915 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, in max98090_configure_dmic()
1919 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, in max98090_configure_dmic()
1930 struct snd_soc_component *component = dai->component; in max98090_dai_startup()
1932 unsigned int fmt = max98090->dai_fmt; in max98090_dai_startup()
1934 /* Remove 24-bit format support if it is not in right justified mode. */ in max98090_dai_startup()
1936 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; in max98090_dai_startup()
1937 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); in max98090_dai_startup()
1946 struct snd_soc_component *component = dai->component; in max98090_dai_hw_params()
1950 cdata = &max98090->dai[0]; in max98090_dai_hw_params()
1951 max98090->bclk = snd_soc_params_to_bclk(params); in max98090_dai_hw_params()
1953 max98090->bclk *= 2; in max98090_dai_hw_params()
1955 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1957 switch (params_width(params)) { in max98090_dai_hw_params()
1963 return -EINVAL; in max98090_dai_hw_params()
1966 if (max98090->master) in max98090_dai_hw_params()
1969 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
1972 if (max98090->lrclk < 24000) in max98090_dai_hw_params()
1980 if (max98090->lrclk < 50000) in max98090_dai_hw_params()
1987 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, in max98090_dai_hw_params()
1988 max98090->lrclk); in max98090_dai_hw_params()
1997 int clk_id, unsigned int freq, int dir) in max98090_dai_set_sysclk() argument
1999 struct snd_soc_component *component = dai->component; in max98090_dai_set_sysclk()
2003 if (freq == max98090->sysclk) in max98090_dai_set_sysclk()
2006 if (!IS_ERR(max98090->mclk)) { in max98090_dai_set_sysclk()
2007 freq = clk_round_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2008 clk_set_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2016 if ((freq >= 10000000) && (freq <= 20000000)) { in max98090_dai_set_sysclk()
2019 max98090->pclk = freq; in max98090_dai_set_sysclk()
2020 } else if ((freq > 20000000) && (freq <= 40000000)) { in max98090_dai_set_sysclk()
2023 max98090->pclk = freq >> 1; in max98090_dai_set_sysclk()
2024 } else if ((freq > 40000000) && (freq <= 60000000)) { in max98090_dai_set_sysclk()
2027 max98090->pclk = freq >> 2; in max98090_dai_set_sysclk()
2029 dev_err(component->dev, "Invalid master clock frequency\n"); in max98090_dai_set_sysclk()
2030 return -EINVAL; in max98090_dai_set_sysclk()
2033 max98090->sysclk = freq; in max98090_dai_set_sysclk()
2040 struct snd_soc_component *component = codec_dai->component; in max98090_dai_digital_mute()
2053 struct snd_soc_component *component = dai->component; in max98090_dai_trigger()
2056 switch (cmd) { in max98090_dai_trigger()
2060 if (!max98090->master && dai->active == 1) in max98090_dai_trigger()
2062 &max98090->pll_det_enable_work, in max98090_dai_trigger()
2068 if (!max98090->master && dai->active == 1) in max98090_dai_trigger()
2069 schedule_work(&max98090->pll_det_disable_work); in max98090_dai_trigger()
2083 struct snd_soc_component *component = max98090->component; in max98090_pll_det_enable_work()
2092 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_pll_det_enable_work()
2098 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_pll_det_enable_work()
2102 &max98090->jack_work, in max98090_pll_det_enable_work()
2115 struct snd_soc_component *component = max98090->component; in max98090_pll_det_disable_work()
2117 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_pll_det_disable_work()
2126 struct snd_soc_component *component = max98090->component; in max98090_pll_work()
2131 dev_info_ratelimited(component->dev, "PLL unlocked\n"); in max98090_pll_work()
2155 struct snd_soc_component *component = max98090->component; in max98090_jack_work()
2160 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { in max98090_jack_work()
2179 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { in max98090_jack_work()
2181 dev_dbg(component->dev, "No Headset Detected\n"); in max98090_jack_work()
2183 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_jack_work()
2190 if (max98090->jack_state == in max98090_jack_work()
2193 dev_dbg(component->dev, in max98090_jack_work()
2210 dev_dbg(component->dev, "Headphone Detected\n"); in max98090_jack_work()
2212 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; in max98090_jack_work()
2219 dev_dbg(component->dev, "Headset Detected\n"); in max98090_jack_work()
2221 max98090->jack_state = M98090_JACK_STATE_HEADSET; in max98090_jack_work()
2228 dev_dbg(component->dev, "Unrecognized Jack Status\n"); in max98090_jack_work()
2232 snd_soc_jack_report(max98090->jack, status, in max98090_jack_work()
2239 struct snd_soc_component *component = max98090->component; in max98090_interrupt()
2248 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); in max98090_interrupt()
2250 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_interrupt()
2253 dev_err(component->dev, in max98090_interrupt()
2259 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); in max98090_interrupt()
2262 dev_err(component->dev, in max98090_interrupt()
2268 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", in max98090_interrupt()
2277 dev_err(component->dev, "M98090_CLD_MASK\n"); in max98090_interrupt()
2280 dev_dbg(component->dev, "M98090_SLD_MASK\n"); in max98090_interrupt()
2283 dev_dbg(component->dev, "M98090_ULK_MASK\n"); in max98090_interrupt()
2288 dev_dbg(component->dev, "M98090_JDET_MASK\n"); in max98090_interrupt()
2290 pm_wakeup_event(component->dev, 100); in max98090_interrupt()
2293 &max98090->jack_work, in max98090_interrupt()
2298 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); in max98090_interrupt()
2301 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); in max98090_interrupt()
2307 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2324 dev_dbg(component->dev, "max98090_mic_detect\n"); in max98090_mic_detect()
2326 max98090->jack = jack; in max98090_mic_detect()
2338 snd_soc_jack_report(max98090->jack, 0, in max98090_mic_detect()
2342 &max98090->jack_work, in max98090_mic_detect()
2392 dev_dbg(component->dev, "max98090_probe\n"); in max98090_probe()
2394 max98090->mclk = devm_clk_get(component->dev, "mclk"); in max98090_probe()
2395 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) in max98090_probe()
2396 return -EPROBE_DEFER; in max98090_probe()
2398 max98090->component = component; in max98090_probe()
2405 max98090->sysclk = (unsigned)-1; in max98090_probe()
2406 max98090->pclk = (unsigned)-1; in max98090_probe()
2407 max98090->master = false; in max98090_probe()
2409 cdata = &max98090->dai[0]; in max98090_probe()
2410 cdata->rate = (unsigned)-1; in max98090_probe()
2411 cdata->fmt = (unsigned)-1; in max98090_probe()
2413 max98090->lin_state = 0; in max98090_probe()
2414 max98090->pa1en = 0; in max98090_probe()
2415 max98090->pa2en = 0; in max98090_probe()
2419 dev_err(component->dev, "Failed to read device revision: %d\n", in max98090_probe()
2426 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); in max98090_probe()
2429 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); in max98090_probe()
2432 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); in max98090_probe()
2435 if (max98090->devtype != devtype) { in max98090_probe()
2436 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); in max98090_probe()
2437 max98090->devtype = devtype; in max98090_probe()
2440 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_probe()
2442 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); in max98090_probe()
2443 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, in max98090_probe()
2445 INIT_WORK(&max98090->pll_det_disable_work, in max98090_probe()
2474 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); in max98090_probe()
2477 dev_info(component->dev, "use default 2.8v micbias\n"); in max98090_probe()
2479 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); in max98090_probe()
2496 cancel_delayed_work_sync(&max98090->jack_work); in max98090_remove()
2497 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_remove()
2498 cancel_work_sync(&max98090->pll_det_disable_work); in max98090_remove()
2499 max98090->component = NULL; in max98090_remove()
2507 if (max98090->shdn_pending) { in max98090_seq_notifier()
2513 max98090->shdn_pending = false; in max98090_seq_notifier()
2550 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), in max98090_i2c_probe()
2553 return -ENOMEM; in max98090_i2c_probe()
2555 if (ACPI_HANDLE(&i2c->dev)) { in max98090_i2c_probe()
2556 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, in max98090_i2c_probe()
2557 &i2c->dev); in max98090_i2c_probe()
2559 dev_err(&i2c->dev, "No driver data\n"); in max98090_i2c_probe()
2560 return -EINVAL; in max98090_i2c_probe()
2562 driver_data = acpi_id->driver_data; in max98090_i2c_probe()
2564 driver_data = i2c_id->driver_data; in max98090_i2c_probe()
2567 max98090->devtype = driver_data; in max98090_i2c_probe()
2569 max98090->pdata = i2c->dev.platform_data; in max98090_i2c_probe()
2571 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", in max98090_i2c_probe()
2572 &max98090->dmic_freq); in max98090_i2c_probe()
2574 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; in max98090_i2c_probe()
2576 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); in max98090_i2c_probe()
2577 if (IS_ERR(max98090->regmap)) { in max98090_i2c_probe()
2578 ret = PTR_ERR(max98090->regmap); in max98090_i2c_probe()
2579 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in max98090_i2c_probe()
2583 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in max98090_i2c_probe()
2587 dev_err(&i2c->dev, "request_irq failed: %d\n", in max98090_i2c_probe()
2592 ret = devm_snd_soc_register_component(&i2c->dev, in max98090_i2c_probe()
2601 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); in max98090_i2c_shutdown()
2607 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2609 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2626 regcache_cache_only(max98090->regmap, false); in max98090_runtime_resume()
2630 regcache_sync(max98090->regmap); in max98090_runtime_resume()
2639 regcache_cache_only(max98090->regmap, true); in max98090_runtime_suspend()
2651 regcache_mark_dirty(max98090->regmap); in max98090_resume()
2656 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_resume()
2658 regcache_sync(max98090->regmap); in max98090_resume()