Lines Matching +full:0 +full:xf005
17 #define CDC_D_REVISION1 (0xf000)
18 #define CDC_D_PERPH_SUBTYPE (0xf005)
19 #define CDC_D_INT_EN_SET (0xf015)
20 #define CDC_D_INT_EN_CLR (0xf016)
25 #define CDC_D_CDC_RST_CTL (0xf046)
27 #define RST_CTL_DIG_SW_RST_N_RESET 0
30 #define CDC_D_CDC_TOP_CLK_CTL (0xf048)
35 #define CDC_D_CDC_ANA_CLK_CTL (0xf049)
36 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0)
37 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0)
43 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A)
44 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0)
55 #define CDC_D_CDC_CONN_TX1_CTL (0xf050)
56 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0)
57 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0
58 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1
59 #define CONN_TX1_SERIAL_TX1_ZERO 0x2
61 #define CDC_D_CDC_CONN_TX2_CTL (0xf051)
62 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0)
63 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0
64 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1
65 #define CONN_TX2_SERIAL_TX2_ZERO 0x2
66 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052)
67 #define CDC_D_CDC_CONN_RX1_CTL (0xf053)
68 #define CDC_D_CDC_CONN_RX2_CTL (0xf054)
69 #define CDC_D_CDC_CONN_RX3_CTL (0xf055)
70 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056)
71 #define CDC_D_SEC_ACCESS (0xf0D0)
72 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA)
73 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB)
74 #define CDC_A_REVISION1 (0xf100)
75 #define CDC_A_REVISION2 (0xf101)
76 #define CDC_A_REVISION3 (0xf102)
77 #define CDC_A_REVISION4 (0xf103)
78 #define CDC_A_PERPH_TYPE (0xf104)
79 #define CDC_A_PERPH_SUBTYPE (0xf105)
80 #define CDC_A_INT_RT_STS (0xf110)
81 #define CDC_A_INT_SET_TYPE (0xf111)
82 #define CDC_A_INT_POLARITY_HIGH (0xf112)
83 #define CDC_A_INT_POLARITY_LOW (0xf113)
84 #define CDC_A_INT_LATCHED_CLR (0xf114)
85 #define CDC_A_INT_EN_SET (0xf115)
86 #define CDC_A_INT_EN_CLR (0xf116)
87 #define CDC_A_INT_LATCHED_STS (0xf118)
88 #define CDC_A_INT_PENDING_STS (0xf119)
89 #define CDC_A_INT_MID_SEL (0xf11A)
90 #define CDC_A_INT_PRIORITY (0xf11B)
91 #define CDC_A_MICB_1_EN (0xf140)
95 #define MICB_1_EN_EXT_BYP_CAP 0
99 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4)
101 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0)
102 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0
104 #define CDC_A_MICB_1_VAL (0xf141)
109 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3)
110 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3)
111 #define CDC_A_MICB_1_CTL (0xf142)
120 #define CDC_A_MICB_1_INT_RBIAS (0xf143)
123 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0
127 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0
131 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0
134 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0
138 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0
139 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0)
140 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0)
141 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0
143 #define CDC_A_MICB_2_EN (0xf144)
147 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145)
148 #define CDC_A_MASTER_BIAS_CTL (0xf146)
149 #define CDC_A_MBHC_DET_CTL_1 (0xf147)
153 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0)
160 #define CDC_A_MBHC_DET_CTL_2 (0xf150)
166 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0)
167 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0)
168 #define CDC_A_MBHC_FSM_CTL (0xf151)
171 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4)
173 #define CDC_A_MBHC_DBNC_TIMER (0xf152)
175 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4)
176 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153)
177 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154)
178 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155)
179 #define CDC_A_MBHC_BTN3_CTL (0xf156)
180 #define CDC_A_MBHC_BTN4_CTL (0xf157)
187 #define CDC_A_MBHC_RESULT_1 (0xf158)
188 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0)
189 #define CDC_A_TX_1_EN (0xf160)
190 #define CDC_A_TX_2_EN (0xf161)
191 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162)
192 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163)
193 #define CDC_A_TX_1_2_ATEST_CTL (0xf164)
194 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165)
195 #define CDC_A_TX_3_EN (0xf167)
196 #define CDC_A_NCP_EN (0xf180)
197 #define CDC_A_NCP_CLK (0xf181)
198 #define CDC_A_NCP_FBCTRL (0xf183)
201 #define CDC_A_NCP_BIAS (0xf184)
202 #define CDC_A_NCP_VCTRL (0xf185)
203 #define CDC_A_NCP_TEST (0xf186)
204 #define CDC_A_NCP_CLIM_ADDR (0xf187)
205 #define CDC_A_RX_CLOCK_DIVIDER (0xf190)
206 #define CDC_A_RX_COM_OCP_CTL (0xf191)
207 #define CDC_A_RX_COM_OCP_COUNT (0xf192)
208 #define CDC_A_RX_COM_BIAS_DAC (0xf193)
211 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0)
212 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0)
214 #define CDC_A_RX_HPH_BIAS_PA (0xf194)
215 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195)
216 #define CDC_A_RX_HPH_BIAS_CNP (0xf196)
217 #define CDC_A_RX_HPH_CNP_EN (0xf197)
218 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B)
221 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D)
225 #define CDC_A_RX_EAR_CTL (0xf19E)
226 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0)
227 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0)
229 #define CDC_A_SPKR_DAC_CTL (0xf1B0)
231 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0
233 #define CDC_A_SPKR_DRV_CTL (0xf1B2)
234 #define SPKR_DRV_CTL_DEF_MASK 0xEF
242 #define SPKR_DRV_GAIN_SET BIT(0)
247 #define CDC_A_SPKR_OCP_CTL (0xf1B4)
248 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5)
249 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0)
250 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0)
251 #define SPKR_PWRSTG_CTL_MASK 0xE0
259 #define CDC_A_SPKR_DRV_DBG (0xf1B7)
260 #define CDC_A_CURRENT_LIMIT (0xf1C0)
261 #define CDC_A_BOOST_EN_CTL (0xf1C3)
262 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4)
263 #define CDC_A_SEC_ACCESS (0xf1D0)
264 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA)
265 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB)
321 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text);
324 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0)
332 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */
333 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0);
336 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain),
337 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain),
338 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain),
365 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); in pm8916_wcd_analog_micbias_enable()
381 return 0; in pm8916_wcd_analog_enable_micbias_ext()
391 snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); in pm8916_wcd_analog_enable_micbias_int()
404 return 0; in pm8916_wcd_analog_enable_micbias_int()
467 0); in pm8916_mbhc_configure_bias()
478 vrefs = &priv->vref_btn_micb[0]; in pm8916_mbhc_configure_bias()
480 vrefs = &priv->vref_btn_cs[0]; in pm8916_mbhc_configure_bias()
484 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { in pm8916_mbhc_configure_bias()
496 return 0; in pm8916_mbhc_configure_bias()
503 u32 plug_type = 0; in pm8916_wcd_setup_mbhc()
543 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); in pm8916_wcd_setup_mbhc()
622 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); in pm8916_wcd_analog_enable_adc()
633 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); in pm8916_wcd_analog_enable_adc()
645 return 0; in pm8916_wcd_analog_enable_adc()
683 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); in pm8916_wcd_analog_enable_spk_pa()
689 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); in pm8916_wcd_analog_enable_spk_pa()
692 return 0; in pm8916_wcd_analog_enable_spk_pa()
696 {CDC_A_RX_COM_OCP_CTL, 0xD1},
697 {CDC_A_RX_COM_OCP_COUNT, 0xFF},
698 {CDC_D_SEC_ACCESS, 0xA5},
699 {CDC_D_PERPH_RESET_CTL3, 0x0F},
700 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F},
701 {CDC_A_NCP_FBCTRL, 0x28},
702 {CDC_A_SPKR_DRV_CTL, 0x69},
703 {CDC_A_SPKR_DRV_DBG, 0x01},
704 {CDC_A_BOOST_EN_CTL, 0x5F},
705 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88},
706 {CDC_A_SEC_ACCESS, 0xA5},
707 {CDC_A_PERPH_RESET_CTL3, 0x0F},
708 {CDC_A_CURRENT_LIMIT, 0x82},
709 {CDC_A_SPKR_DAC_CTL, 0x03},
710 {CDC_A_SPKR_OCP_CTL, 0xE1},
711 {CDC_A_MASTER_BIAS_CTL, 0x30},
720 if (err != 0) { in pm8916_wcd_analog_probe()
734 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); in pm8916_wcd_analog_probe()
735 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); in pm8916_wcd_analog_probe()
737 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) in pm8916_wcd_analog_probe()
749 return 0; in pm8916_wcd_analog_probe()
757 RST_CTL_DIG_SW_RST_N_MASK, 0); in pm8916_wcd_analog_remove()
849 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
850 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
851 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
852 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0),
860 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
862 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0),
863 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux),
864 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
865 0),
866 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0),
867 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux),
868 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
869 0),
870 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
876 6, 0, NULL, 0,
880 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0),
881 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0),
883 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0),
884 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0),
887 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0,
891 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0,
896 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0,
899 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0,
903 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0,
907 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0,
911 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0,
916 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
917 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
919 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
920 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
923 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL,
924 0),
925 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL,
926 0),
927 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0),
928 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0),
932 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0),
933 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0),
934 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0),
936 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0),
937 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0),
938 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL,
939 0),
942 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0),
944 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0),
955 return 0; in pm8916_wcd_analog_set_jack()
971 snd_soc_jack_report(priv->jack, 0, btn_mask); in mbhc_btn_release_irq_handler()
987 case 0xf: in mbhc_btn_press_irq_handler()
990 case 0x7: in mbhc_btn_press_irq_handler()
993 case 0x3: in mbhc_btn_press_irq_handler()
996 case 0x1: in mbhc_btn_press_irq_handler()
999 case 0x0: in mbhc_btn_press_irq_handler()
1055 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); in pm8916_mbhc_switch_irq_handler()
1064 [0] = {
1066 .id = 0,
1137 &priv->vref_btn_cs[0], in pm8916_wcd_analog_parse_dt()
1139 if (rval < 0) { in pm8916_wcd_analog_parse_dt()
1144 &priv->vref_btn_micb[0], in pm8916_wcd_analog_parse_dt()
1146 if (rval < 0) in pm8916_wcd_analog_parse_dt()
1155 return 0; in pm8916_wcd_analog_parse_dt()
1169 if (ret < 0) in pm8916_wcd_analog_spmi_probe()
1178 for (i = 0; i < ARRAY_SIZE(supply_names); i++) in pm8916_wcd_analog_spmi_probe()
1189 if (ret < 0) { in pm8916_wcd_analog_spmi_probe()
1195 if (irq < 0) { in pm8916_wcd_analog_spmi_probe()
1210 if (irq < 0) { in pm8916_wcd_analog_spmi_probe()
1224 if (irq < 0) { in pm8916_wcd_analog_spmi_probe()
1252 return 0; in pm8916_wcd_analog_spmi_remove()