Lines Matching +full:ch3 +full:- +full:0
27 #include <sound/soc-dapm.h>
42 { 1, 0x0 },
43 { 2, 0x2 },
44 { 4, 0x3 },
45 { 8, 0x4 },
46 { 16, 0x5 },
47 { 32, 0x6 },
48 { 3, 0x7 },
49 { 6, 0xa },
50 { 12, 0xb },
51 { 24, 0xc },
56 { 512000, 0x01 },
57 { 256000, 0x02 },
58 { 128000, 0x04 },
59 { 64000, 0x08 },
60 { 32000, 0x10 },
61 { 8000, 0x20 },
62 { 4000, 0x40 },
66 { 1, 0x0 },
67 { 2, 0x1 },
68 { 4, 0x2 },
69 { 8, 0x3 },
77 { 256, 0 }, /* OSR 256, SRC 1 */
81 {NAU8540_REG_POWER_MANAGEMENT, 0x0000},
82 {NAU8540_REG_CLOCK_CTRL, 0x0000},
83 {NAU8540_REG_CLOCK_SRC, 0x0000},
84 {NAU8540_REG_FLL1, 0x0001},
85 {NAU8540_REG_FLL2, 0x3126},
86 {NAU8540_REG_FLL3, 0x0008},
87 {NAU8540_REG_FLL4, 0x0010},
88 {NAU8540_REG_FLL5, 0xC000},
89 {NAU8540_REG_FLL6, 0x6000},
90 {NAU8540_REG_FLL_VCO_RSV, 0xF13C},
91 {NAU8540_REG_PCM_CTRL0, 0x000B},
92 {NAU8540_REG_PCM_CTRL1, 0x3010},
93 {NAU8540_REG_PCM_CTRL2, 0x0800},
94 {NAU8540_REG_PCM_CTRL3, 0x0000},
95 {NAU8540_REG_PCM_CTRL4, 0x000F},
96 {NAU8540_REG_ALC_CONTROL_1, 0x0000},
97 {NAU8540_REG_ALC_CONTROL_2, 0x700B},
98 {NAU8540_REG_ALC_CONTROL_3, 0x0022},
99 {NAU8540_REG_ALC_CONTROL_4, 0x1010},
100 {NAU8540_REG_ALC_CONTROL_5, 0x1010},
101 {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000},
102 {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000},
103 {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000},
104 {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000},
105 {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000},
106 {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000},
107 {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000},
108 {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000},
109 {NAU8540_REG_HPF_FILTER_CH12, 0x0000},
110 {NAU8540_REG_HPF_FILTER_CH34, 0x0000},
111 {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002},
112 {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400},
113 {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400},
114 {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400},
115 {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400},
116 {NAU8540_REG_DIGITAL_MUX, 0x00E4},
117 {NAU8540_REG_GPIO_CTRL, 0x0000},
118 {NAU8540_REG_MISC_CTRL, 0x0000},
119 {NAU8540_REG_I2C_CTRL, 0xEFFF},
120 {NAU8540_REG_VMID_CTRL, 0x0000},
121 {NAU8540_REG_MUTE, 0x0000},
122 {NAU8540_REG_ANALOG_ADC1, 0x0011},
123 {NAU8540_REG_ANALOG_ADC2, 0x0020},
124 {NAU8540_REG_ANALOG_PWR, 0x0000},
125 {NAU8540_REG_MIC_BIAS, 0x0004},
126 {NAU8540_REG_REFERENCE, 0x0000},
127 {NAU8540_REG_FEPGA1, 0x0000},
128 {NAU8540_REG_FEPGA2, 0x0000},
129 {NAU8540_REG_FEPGA3, 0x0101},
130 {NAU8540_REG_FEPGA4, 0x0101},
131 {NAU8540_REG_PWR, 0x0000},
186 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
187 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
191 0, 0x520, 0, adc_vol_tlv),
193 0, 0x520, 0, adc_vol_tlv),
195 0, 0x520, 0, adc_vol_tlv),
197 0, 0x520, 0, adc_vol_tlv),
200 0, 0x25, 0, fepga_gain_tlv),
202 8, 0x25, 0, fepga_gain_tlv),
204 0, 0x25, 0, fepga_gain_tlv),
206 8, 0x25, 0, fepga_gain_tlv),
222 SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum);
231 digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel);
239 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in adc_power_control()
245 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in adc_power_control()
246 NAU8540_I2S_DO12_TRI, 0); in adc_power_control()
247 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in adc_power_control()
248 NAU8540_I2S_DO34_TRI, 0); in adc_power_control()
250 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in adc_power_control()
252 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in adc_power_control()
255 return 0; in adc_power_control()
261 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in aiftx_power_control()
265 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001); in aiftx_power_control()
266 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000); in aiftx_power_control()
268 return 0; in aiftx_power_control()
272 SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0),
273 SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0),
280 SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0),
281 SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0),
282 SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0),
283 SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0),
286 NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control,
289 NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control,
292 NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control,
295 NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control,
298 SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0),
299 SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0),
300 SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0),
301 SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0),
304 SND_SOC_NOPM, 0, 0, &digital_ch4_mux),
305 SND_SOC_DAPM_MUX("Digital CH3 Mux",
306 SND_SOC_NOPM, 0, 0, &digital_ch3_mux),
308 SND_SOC_NOPM, 0, 0, &digital_ch2_mux),
310 SND_SOC_NOPM, 0, 0, &digital_ch1_mux),
312 SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0,
329 {"ADC CH3", NULL, "ADC3"},
339 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
344 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
347 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
348 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
349 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
350 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
354 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
359 {"AIFTX", NULL, "Digital CH3 Mux"},
366 return -EINVAL; in nau8540_clock_check()
369 dev_err(nau8540->dev, "exceed the maximum frequency of CLK_ADC\n"); in nau8540_clock_check()
370 return -EINVAL; in nau8540_clock_check()
373 return 0; in nau8540_clock_check()
379 struct snd_soc_component *component = dai->component; in nau8540_hw_params()
381 unsigned int val_len = 0, osr; in nau8540_hw_params()
389 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr); in nau8540_hw_params()
392 return -EINVAL; in nau8540_hw_params()
393 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_hw_params()
411 return -EINVAL; in nau8540_hw_params()
414 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, in nau8540_hw_params()
417 return 0; in nau8540_hw_params()
422 struct snd_soc_component *component = dai->component; in nau8540_set_fmt()
424 unsigned int ctrl1_val = 0, ctrl2_val = 0; in nau8540_set_fmt()
433 return -EINVAL; in nau8540_set_fmt()
443 return -EINVAL; in nau8540_set_fmt()
464 return -EINVAL; in nau8540_set_fmt()
467 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, in nau8540_set_fmt()
470 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in nau8540_set_fmt()
472 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in nau8540_set_fmt()
473 NAU8540_I2S_DO34_OE, 0); in nau8540_set_fmt()
475 return 0; in nau8540_set_fmt()
479 * nau8540_set_tdm_slot - configure DAI TX TDM.
482 * 0xf for normal 4 channel TDM.
483 * 0xf0 for shifted 4 channel TDM
493 struct snd_soc_component *component = dai->component; in nau8540_set_tdm_slot()
495 unsigned int ctrl2_val = 0, ctrl4_val = 0; in nau8540_set_tdm_slot()
497 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf))) in nau8540_set_tdm_slot()
498 return -EINVAL; in nau8540_set_tdm_slot()
501 if (tx_mask & 0xf0) { in nau8540_set_tdm_slot()
507 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4, in nau8540_set_tdm_slot()
510 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, in nau8540_set_tdm_slot()
512 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, in nau8540_set_tdm_slot()
516 return 0; in nau8540_set_tdm_slot()
531 .name = "nau8540-hifi",
543 * nau8540_calc_fll_param - Calculate FLL parameters.
550 * Returns 0 for success or negative error code.
559 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. in nau8540_calc_fll_param()
562 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { in nau8540_calc_fll_param()
568 return -EINVAL; in nau8540_calc_fll_param()
569 fll_param->clk_ref_div = fll_pre_scalar[i].val; in nau8540_calc_fll_param()
572 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { in nau8540_calc_fll_param()
577 return -EINVAL; in nau8540_calc_fll_param()
578 fll_param->ratio = fll_ratio[i].val; in nau8540_calc_fll_param()
581 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be in nau8540_calc_fll_param()
585 fvco_max = 0; in nau8540_calc_fll_param()
587 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { in nau8540_calc_fll_param()
596 return -EINVAL; in nau8540_calc_fll_param()
597 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; in nau8540_calc_fll_param()
599 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional in nau8540_calc_fll_param()
602 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); in nau8540_calc_fll_param()
603 fll_param->fll_int = (fvco >> 16) & 0x3FF; in nau8540_calc_fll_param()
604 fll_param->fll_frac = fvco & 0xFFFF; in nau8540_calc_fll_param()
605 return 0; in nau8540_calc_fll_param()
613 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); in nau8540_fll_apply()
616 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT)); in nau8540_fll_apply()
617 /* FLL 16-bit fractional input */ in nau8540_fll_apply()
618 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); in nau8540_fll_apply()
619 /* FLL 10-bit integer input */ in nau8540_fll_apply()
621 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int); in nau8540_fll_apply()
622 /* FLL pre-scaler */ in nau8540_fll_apply()
625 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT); in nau8540_fll_apply()
629 NAU8540_REG_FLL6, NAU8540_DCO_EN, 0); in nau8540_fll_apply()
630 if (fll_param->fll_frac) { in nau8540_fll_apply()
644 NAU8540_SDM_EN | NAU8540_CUTOFF500, 0); in nau8540_fll_apply()
658 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
660 NAU8540_FLL_CLK_SRC_MCLK | 0); in nau8540_set_pll()
664 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
667 (0xf << NAU8540_GAIN_ERR_SFT)); in nau8540_set_pll()
671 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, in nau8540_set_pll()
674 (0xf << NAU8540_GAIN_ERR_SFT)); in nau8540_set_pll()
678 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id); in nau8540_set_pll()
679 return -EINVAL; in nau8540_set_pll()
681 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", in nau8540_set_pll()
686 if (ret < 0) { in nau8540_set_pll()
687 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); in nau8540_set_pll()
690 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", in nau8540_set_pll()
694 nau8540_fll_apply(nau8540->regmap, &fll_param); in nau8540_set_pll()
696 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_pll()
699 return 0; in nau8540_set_pll()
710 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_sysclk()
712 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, in nau8540_set_sysclk()
713 NAU8540_DCO_EN, 0); in nau8540_set_sysclk()
717 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, in nau8540_set_sysclk()
719 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, in nau8540_set_sysclk()
724 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id); in nau8540_set_sysclk()
725 return -EINVAL; in nau8540_set_sysclk()
728 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", in nau8540_set_sysclk()
731 return 0; in nau8540_set_sysclk()
736 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); in nau8540_reset_chip()
737 regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); in nau8540_reset_chip()
742 struct regmap *regmap = nau8540->regmap; in nau8540_init_regs()
747 NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT)); in nau8540_init_regs()
781 regcache_cache_only(nau8540->regmap, true); in nau8540_suspend()
782 regcache_mark_dirty(nau8540->regmap); in nau8540_suspend()
784 return 0; in nau8540_suspend()
791 regcache_cache_only(nau8540->regmap, false); in nau8540_resume()
792 regcache_sync(nau8540->regmap); in nau8540_resume()
794 return 0; in nau8540_resume()
832 struct device *dev = &i2c->dev; in nau8540_i2c_probe()
839 return -ENOMEM; in nau8540_i2c_probe()
843 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config); in nau8540_i2c_probe()
844 if (IS_ERR(nau8540->regmap)) in nau8540_i2c_probe()
845 return PTR_ERR(nau8540->regmap); in nau8540_i2c_probe()
846 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value); in nau8540_i2c_probe()
847 if (ret < 0) { in nau8540_i2c_probe()
853 nau8540->dev = dev; in nau8540_i2c_probe()
854 nau8540_reset_chip(nau8540->regmap); in nau8540_i2c_probe()
862 { "nau8540", 0 },