Lines Matching +full:vref +full:- +full:source
2 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
28 #include <sound/soc-dapm.h>
252 regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN); in rt1305_reg_init()
384 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
409 static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source, in rt1305_is_rc_clk_from_pll() argument
413 snd_soc_dapm_to_component(source->dapm); in rt1305_is_rc_clk_from_pll()
419 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 && in rt1305_is_rc_clk_from_pll()
426 static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, in rt1305_is_sys_clk_from_pll() argument
430 snd_soc_dapm_to_component(source->dapm); in rt1305_is_sys_clk_from_pll()
433 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1) in rt1305_is_sys_clk_from_pll()
443 snd_soc_dapm_to_component(w->dapm); in rt1305_classd_event()
486 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
494 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
496 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
498 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
572 { "DAC", NULL, "VREF" },
576 { "DAC", NULL, "DISC VREF" },
577 { "DAC", NULL, "FASTB VREF" },
578 { "DAC", NULL, "ULTRA FAST VREF" },
617 return -EINVAL; in rt1305_get_clk_info()
624 return -EINVAL; in rt1305_get_clk_info()
630 struct snd_soc_component *component = dai->component; in rt1305_hw_params()
635 rt1305->lrck = params_rate(params); in rt1305_hw_params()
636 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck); in rt1305_hw_params()
638 dev_warn(component->dev, "Force using PLL "); in rt1305_hw_params()
640 rt1305->lrck * 64, rt1305->lrck * 256); in rt1305_hw_params()
642 rt1305->lrck * 256, SND_SOC_CLOCK_IN); in rt1305_hw_params()
647 dev_err(component->dev, "Unsupported frame size: %d\n", in rt1305_hw_params()
649 return -EINVAL; in rt1305_hw_params()
653 rt1305->bclk = rt1305->lrck * (32 << bclk_ms); in rt1305_hw_params()
655 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", in rt1305_hw_params()
656 bclk_ms, pre_div, dai->id); in rt1305_hw_params()
658 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1305_hw_params()
659 rt1305->lrck, pre_div, dai->id); in rt1305_hw_params()
675 return -EINVAL; in rt1305_hw_params()
678 switch (dai->id) { in rt1305_hw_params()
687 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt1305_hw_params()
688 return -EINVAL; in rt1305_hw_params()
699 struct snd_soc_component *component = dai->component; in rt1305_set_dai_fmt()
706 rt1305->master = 1; in rt1305_set_dai_fmt()
710 rt1305->master = 0; in rt1305_set_dai_fmt()
713 return -EINVAL; in rt1305_set_dai_fmt()
723 return -EINVAL; in rt1305_set_dai_fmt()
739 return -EINVAL; in rt1305_set_dai_fmt()
742 switch (dai->id) { in rt1305_set_dai_fmt()
751 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id); in rt1305_set_dai_fmt()
752 return -EINVAL; in rt1305_set_dai_fmt()
758 int clk_id, int source, unsigned int freq, int dir) in rt1305_set_component_sysclk() argument
763 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src) in rt1305_set_component_sysclk()
780 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt1305_set_component_sysclk()
781 return -EINVAL; in rt1305_set_component_sysclk()
785 rt1305->sysclk = freq; in rt1305_set_component_sysclk()
786 rt1305->sysclk_src = clk_id; in rt1305_set_component_sysclk()
788 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", in rt1305_set_component_sysclk()
795 int pll_id, int source, unsigned int freq_in, in rt1305_set_component_pll() argument
802 if (source == rt1305->pll_src && freq_in == rt1305->pll_in && in rt1305_set_component_pll()
803 freq_out == rt1305->pll_out) in rt1305_set_component_pll()
807 dev_dbg(component->dev, "PLL disabled\n"); in rt1305_set_component_pll()
809 rt1305->pll_in = 0; in rt1305_set_component_pll()
810 rt1305->pll_out = 0; in rt1305_set_component_pll()
817 switch (source) { in rt1305_set_component_pll()
840 dev_err(component->dev, "Unknown PLL Source %d\n", source); in rt1305_set_component_pll()
841 return -EINVAL; in rt1305_set_component_pll()
846 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); in rt1305_set_component_pll()
850 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n", in rt1305_set_component_pll()
861 rt1305->pll_in = freq_in; in rt1305_set_component_pll()
862 rt1305->pll_out = freq_out; in rt1305_set_component_pll()
863 rt1305->pll_src = source; in rt1305_set_component_pll()
872 rt1305->component = component; in rt1305_probe()
884 rt1305_reset(rt1305->regmap); in rt1305_remove()
892 regcache_cache_only(rt1305->regmap, true); in rt1305_suspend()
893 regcache_mark_dirty(rt1305->regmap); in rt1305_suspend()
902 regcache_cache_only(rt1305->regmap, false); in rt1305_resume()
903 regcache_sync(rt1305->regmap); in rt1305_resume()
924 .name = "rt1305-aif",
1000 regcache_cache_bypass(rt1305->regmap, true); in rt1305_calibrate()
1002 rt1305_reset(rt1305->regmap); in rt1305_calibrate()
1003 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219); in rt1305_calibrate()
1004 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548); in rt1305_calibrate()
1005 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); in rt1305_calibrate()
1006 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000); in rt1305_calibrate()
1007 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600); in rt1305_calibrate()
1008 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0); in rt1305_calibrate()
1009 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); in rt1305_calibrate()
1010 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); in rt1305_calibrate()
1011 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); in rt1305_calibrate()
1014 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); in rt1305_calibrate()
1016 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000); in rt1305_calibrate()
1017 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0); in rt1305_calibrate()
1018 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc); in rt1305_calibrate()
1019 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320); in rt1305_calibrate()
1020 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000); in rt1305_calibrate()
1021 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); in rt1305_calibrate()
1022 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); in rt1305_calibrate()
1023 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0); in rt1305_calibrate()
1024 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); in rt1305_calibrate()
1025 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); in rt1305_calibrate()
1026 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); in rt1305_calibrate()
1029 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080); in rt1305_calibrate()
1030 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); in rt1305_calibrate()
1031 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880); in rt1305_calibrate()
1032 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0); in rt1305_calibrate()
1033 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0); in rt1305_calibrate()
1034 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20); in rt1305_calibrate()
1035 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000); in rt1305_calibrate()
1036 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000); in rt1305_calibrate()
1038 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb); in rt1305_calibrate()
1039 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb); in rt1305_calibrate()
1041 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb); in rt1305_calibrate()
1042 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb); in rt1305_calibrate()
1047 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542); in rt1305_calibrate()
1048 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0); in rt1305_calibrate()
1049 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff); in rt1305_calibrate()
1050 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe); in rt1305_calibrate()
1051 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13); in rt1305_calibrate()
1052 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650); in rt1305_calibrate()
1054 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064); in rt1305_calibrate()
1055 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770); in rt1305_calibrate()
1056 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c); in rt1305_calibrate()
1057 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200); in rt1305_calibrate()
1058 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); in rt1305_calibrate()
1059 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); in rt1305_calibrate()
1061 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); in rt1305_calibrate()
1062 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); in rt1305_calibrate()
1074 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200); in rt1305_calibrate()
1075 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00); in rt1305_calibrate()
1076 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80); in rt1305_calibrate()
1078 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh); in rt1305_calibrate()
1079 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl); in rt1305_calibrate()
1091 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec); in rt1305_calibrate()
1095 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e, in rt1305_calibrate()
1097 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f, in rt1305_calibrate()
1099 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe, in rt1305_calibrate()
1101 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd, in rt1305_calibrate()
1108 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe); in rt1305_calibrate()
1110 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442); in rt1305_calibrate()
1111 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000); in rt1305_calibrate()
1112 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400); in rt1305_calibrate()
1113 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000); in rt1305_calibrate()
1114 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000); in rt1305_calibrate()
1115 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020); in rt1305_calibrate()
1116 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000); in rt1305_calibrate()
1118 regcache_cache_bypass(rt1305->regmap, false); in rt1305_calibrate()
1128 rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv), in rt1305_i2c_probe()
1131 return -ENOMEM; in rt1305_i2c_probe()
1135 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap); in rt1305_i2c_probe()
1136 if (IS_ERR(rt1305->regmap)) { in rt1305_i2c_probe()
1137 ret = PTR_ERR(rt1305->regmap); in rt1305_i2c_probe()
1138 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt1305_i2c_probe()
1143 regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val); in rt1305_i2c_probe()
1145 dev_err(&i2c->dev, in rt1305_i2c_probe()
1147 return -ENODEV; in rt1305_i2c_probe()
1150 rt1305_reset(rt1305->regmap); in rt1305_i2c_probe()
1153 return devm_snd_soc_register_component(&i2c->dev, in rt1305_i2c_probe()
1162 rt1305_reset(rt1305->regmap); in rt1305_i2c_shutdown()