Lines Matching +full:0 +full:x1
16 #define RT5616_RESET 0x00
17 #define RT5616_VERSION_ID 0xfd
18 #define RT5616_VENDOR_ID 0xfe
19 #define RT5616_DEVICE_ID 0xff
21 #define RT5616_HP_VOL 0x02
22 #define RT5616_LOUT_CTRL1 0x03
23 #define RT5616_LOUT_CTRL2 0x05
25 #define RT5616_IN1_IN2 0x0d
26 #define RT5616_INL1_INR1_VOL 0x0f
28 #define RT5616_DAC1_DIG_VOL 0x19
29 #define RT5616_ADC_DIG_VOL 0x1c
30 #define RT5616_ADC_BST_VOL 0x1e
32 #define RT5616_STO1_ADC_MIXER 0x27
33 #define RT5616_AD_DA_MIXER 0x29
34 #define RT5616_STO_DAC_MIXER 0x2a
37 #define RT5616_REC_L1_MIXER 0x3b
38 #define RT5616_REC_L2_MIXER 0x3c
39 #define RT5616_REC_R1_MIXER 0x3d
40 #define RT5616_REC_R2_MIXER 0x3e
42 #define RT5616_HPO_MIXER 0x45
43 #define RT5616_OUT_L1_MIXER 0x4d
44 #define RT5616_OUT_L2_MIXER 0x4e
45 #define RT5616_OUT_L3_MIXER 0x4f
46 #define RT5616_OUT_R1_MIXER 0x50
47 #define RT5616_OUT_R2_MIXER 0x51
48 #define RT5616_OUT_R3_MIXER 0x52
49 #define RT5616_LOUT_MIXER 0x53
51 #define RT5616_PWR_DIG1 0x61
52 #define RT5616_PWR_DIG2 0x62
53 #define RT5616_PWR_ANLG1 0x63
54 #define RT5616_PWR_ANLG2 0x64
55 #define RT5616_PWR_MIXER 0x65
56 #define RT5616_PWR_VOL 0x66
58 #define RT5616_PRIV_INDEX 0x6a
59 #define RT5616_PRIV_DATA 0x6c
61 #define RT5616_I2S1_SDP 0x70
62 #define RT5616_ADDA_CLK1 0x73
63 #define RT5616_ADDA_CLK2 0x74
66 #define RT5616_GLB_CLK 0x80
67 #define RT5616_PLL_CTRL1 0x81
68 #define RT5616_PLL_CTRL2 0x82
69 #define RT5616_HP_OVCD 0x8b
70 #define RT5616_DEPOP_M1 0x8e
71 #define RT5616_DEPOP_M2 0x8f
72 #define RT5616_DEPOP_M3 0x90
73 #define RT5616_CHARGE_PUMP 0x91
74 #define RT5616_PV_DET_SPK_G 0x92
75 #define RT5616_MICBIAS 0x93
76 #define RT5616_A_JD_CTL1 0x94
77 #define RT5616_A_JD_CTL2 0x95
79 #define RT5616_EQ_CTRL1 0xb0
80 #define RT5616_EQ_CTRL2 0xb1
81 #define RT5616_WIND_FILTER 0xb2
82 #define RT5616_DRC_AGC_1 0xb4
83 #define RT5616_DRC_AGC_2 0xb5
84 #define RT5616_DRC_AGC_3 0xb6
85 #define RT5616_SVOL_ZC 0xb7
86 #define RT5616_JD_CTRL1 0xbb
87 #define RT5616_JD_CTRL2 0xbc
88 #define RT5616_IRQ_CTRL1 0xbd
89 #define RT5616_IRQ_CTRL2 0xbe
90 #define RT5616_INT_IRQ_ST 0xbf
91 #define RT5616_GPIO_CTRL1 0xc0
92 #define RT5616_GPIO_CTRL2 0xc1
93 #define RT5616_GPIO_CTRL3 0xc2
94 #define RT5616_PGM_REG_ARR1 0xc8
95 #define RT5616_PGM_REG_ARR2 0xc9
96 #define RT5616_PGM_REG_ARR3 0xca
97 #define RT5616_PGM_REG_ARR4 0xcb
98 #define RT5616_PGM_REG_ARR5 0xcc
99 #define RT5616_SCB_FUNC 0xcd
100 #define RT5616_SCB_CTRL 0xce
101 #define RT5616_BASE_BACK 0xcf
102 #define RT5616_MP3_PLUS1 0xd0
103 #define RT5616_MP3_PLUS2 0xd1
104 #define RT5616_ADJ_HPF_CTRL1 0xd3
105 #define RT5616_ADJ_HPF_CTRL2 0xd4
106 #define RT5616_HP_CALIB_AMP_DET 0xd6
107 #define RT5616_HP_CALIB2 0xd7
108 #define RT5616_SV_ZCD1 0xd9
109 #define RT5616_SV_ZCD2 0xda
110 #define RT5616_D_MISC 0xfa
112 #define RT5616_DUMMY2 0xfb
113 #define RT5616_DUMMY3 0xfc
117 #define RT5616_BIAS_CUR1 0x12
118 #define RT5616_BIAS_CUR3 0x14
119 #define RT5616_CLSD_INT_REG1 0x1c
120 #define RT5616_MAMP_INT_REG2 0x37
121 #define RT5616_CHOP_DAC_ADC 0x3d
122 #define RT5616_3D_SPK 0x63
123 #define RT5616_WND_1 0x6c
124 #define RT5616_WND_2 0x6d
125 #define RT5616_WND_3 0x6e
126 #define RT5616_WND_4 0x6f
127 #define RT5616_WND_5 0x70
128 #define RT5616_WND_8 0x73
129 #define RT5616_DIP_SPK_INF 0x75
130 #define RT5616_HP_DCC_INT1 0x77
131 #define RT5616_EQ_BW_LOP 0xa0
132 #define RT5616_EQ_GN_LOP 0xa1
133 #define RT5616_EQ_FC_BP1 0xa2
134 #define RT5616_EQ_BW_BP1 0xa3
135 #define RT5616_EQ_GN_BP1 0xa4
136 #define RT5616_EQ_FC_BP2 0xa5
137 #define RT5616_EQ_BW_BP2 0xa6
138 #define RT5616_EQ_GN_BP2 0xa7
139 #define RT5616_EQ_FC_BP3 0xa8
140 #define RT5616_EQ_BW_BP3 0xa9
141 #define RT5616_EQ_GN_BP3 0xaa
142 #define RT5616_EQ_FC_BP4 0xab
143 #define RT5616_EQ_BW_BP4 0xac
144 #define RT5616_EQ_GN_BP4 0xad
145 #define RT5616_EQ_FC_HIP1 0xae
146 #define RT5616_EQ_GN_HIP1 0xaf
147 #define RT5616_EQ_FC_HIP2 0xb0
148 #define RT5616_EQ_BW_HIP2 0xb1
149 #define RT5616_EQ_GN_HIP2 0xb2
150 #define RT5616_EQ_PRE_VOL 0xb3
151 #define RT5616_EQ_PST_VOL 0xb4
155 #define RT5616_L_MUTE (0x1 << 15)
157 #define RT5616_VOL_L_MUTE (0x1 << 14)
159 #define RT5616_R_MUTE (0x1 << 7)
161 #define RT5616_VOL_R_MUTE (0x1 << 6)
163 #define RT5616_L_VOL_MASK (0x3f << 8)
165 #define RT5616_R_VOL_MASK (0x3f)
166 #define RT5616_R_VOL_SFT 0
168 /* LOUT Control 2(0x05) */
169 #define RT5616_EN_DFO (0x1 << 15)
171 /* IN1 and IN2 Control (0x0d) */
172 /* IN3 and IN4 Control (0x0e) */
173 #define RT5616_BST_MASK1 (0xf<<12)
175 #define RT5616_BST_MASK2 (0xf<<8)
177 #define RT5616_IN_DF1 (0x1 << 7)
179 #define RT5616_IN_DF2 (0x1 << 6)
182 /* INL1 and INR1 Volume Control (0x0f) */
183 #define RT5616_INL_VOL_MASK (0x1f << 8)
185 #define RT5616_INR_SEL_MASK (0x1 << 7)
187 #define RT5616_INR_SEL_IN4N (0x0 << 7)
188 #define RT5616_INR_SEL_MONON (0x1 << 7)
189 #define RT5616_INR_VOL_MASK (0x1f)
190 #define RT5616_INR_VOL_SFT 0
192 /* DAC1 Digital Volume (0x19) */
193 #define RT5616_DAC_L1_VOL_MASK (0xff << 8)
195 #define RT5616_DAC_R1_VOL_MASK (0xff)
196 #define RT5616_DAC_R1_VOL_SFT 0
198 /* DAC2 Digital Volume (0x1a) */
199 #define RT5616_DAC_L2_VOL_MASK (0xff << 8)
201 #define RT5616_DAC_R2_VOL_MASK (0xff)
202 #define RT5616_DAC_R2_VOL_SFT 0
204 /* ADC Digital Volume Control (0x1c) */
205 #define RT5616_ADC_L_VOL_MASK (0x7f << 8)
207 #define RT5616_ADC_R_VOL_MASK (0x7f)
208 #define RT5616_ADC_R_VOL_SFT 0
210 /* Mono ADC Digital Volume Control (0x1d) */
211 #define RT5616_M_MONO_ADC_L (0x1 << 15)
213 #define RT5616_MONO_ADC_L_VOL_MASK (0x7f << 8)
215 #define RT5616_M_MONO_ADC_R (0x1 << 7)
217 #define RT5616_MONO_ADC_R_VOL_MASK (0x7f)
218 #define RT5616_MONO_ADC_R_VOL_SFT 0
220 /* ADC Boost Volume Control (0x1e) */
221 #define RT5616_ADC_L_BST_MASK (0x3 << 14)
223 #define RT5616_ADC_R_BST_MASK (0x3 << 12)
225 #define RT5616_ADC_COMP_MASK (0x3 << 10)
228 /* Stereo ADC1 Mixer Control (0x27) */
229 #define RT5616_M_STO1_ADC_L1 (0x1 << 14)
231 #define RT5616_M_STO1_ADC_R1 (0x1 << 6)
234 /* ADC Mixer to DAC Mixer Control (0x29) */
235 #define RT5616_M_ADCMIX_L (0x1 << 15)
237 #define RT5616_M_IF1_DAC_L (0x1 << 14)
239 #define RT5616_M_ADCMIX_R (0x1 << 7)
241 #define RT5616_M_IF1_DAC_R (0x1 << 6)
244 /* Stereo DAC Mixer Control (0x2a) */
245 #define RT5616_M_DAC_L1_MIXL (0x1 << 14)
247 #define RT5616_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
249 #define RT5616_M_DAC_R1_MIXL (0x1 << 9)
251 #define RT5616_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
253 #define RT5616_M_DAC_R1_MIXR (0x1 << 6)
255 #define RT5616_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
257 #define RT5616_M_DAC_L1_MIXR (0x1 << 1)
259 #define RT5616_DAC_L1_STO_R_VOL_MASK (0x1)
260 #define RT5616_DAC_L1_STO_R_VOL_SFT 0
262 /* DD Mixer Control (0x2b) */
263 #define RT5616_M_STO_DD_L1 (0x1 << 14)
265 #define RT5616_STO_DD_L1_VOL_MASK (0x1 << 13)
267 #define RT5616_M_STO_DD_L2 (0x1 << 12)
269 #define RT5616_STO_DD_L2_VOL_MASK (0x1 << 11)
271 #define RT5616_M_STO_DD_R2_L (0x1 << 10)
273 #define RT5616_STO_DD_R2_L_VOL_MASK (0x1 << 9)
275 #define RT5616_M_STO_DD_R1 (0x1 << 6)
277 #define RT5616_STO_DD_R1_VOL_MASK (0x1 << 5)
279 #define RT5616_M_STO_DD_R2 (0x1 << 4)
281 #define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
283 #define RT5616_M_STO_DD_L2_R (0x1 << 2)
285 #define RT5616_STO_DD_L2_R_VOL_MASK (0x1 << 1)
288 /* Digital Mixer Control (0x2c) */
289 #define RT5616_M_STO_L_DAC_L (0x1 << 15)
291 #define RT5616_STO_L_DAC_L_VOL_MASK (0x1 << 14)
293 #define RT5616_M_DAC_L2_DAC_L (0x1 << 13)
295 #define RT5616_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
297 #define RT5616_M_STO_R_DAC_R (0x1 << 11)
299 #define RT5616_STO_R_DAC_R_VOL_MASK (0x1 << 10)
301 #define RT5616_M_DAC_R2_DAC_R (0x1 << 9)
303 #define RT5616_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
306 /* DSP Path Control 1 (0x2d) */
307 #define RT5616_RXDP_SRC_MASK (0x1 << 15)
309 #define RT5616_RXDP_SRC_NOR (0x0 << 15)
310 #define RT5616_RXDP_SRC_DIV3 (0x1 << 15)
311 #define RT5616_TXDP_SRC_MASK (0x1 << 14)
313 #define RT5616_TXDP_SRC_NOR (0x0 << 14)
314 #define RT5616_TXDP_SRC_DIV3 (0x1 << 14)
316 /* DSP Path Control 2 (0x2e) */
317 #define RT5616_DAC_L2_SEL_MASK (0x3 << 14)
319 #define RT5616_DAC_L2_SEL_IF2 (0x0 << 14)
320 #define RT5616_DAC_L2_SEL_IF3 (0x1 << 14)
321 #define RT5616_DAC_L2_SEL_TXDC (0x2 << 14)
322 #define RT5616_DAC_L2_SEL_BASS (0x3 << 14)
323 #define RT5616_DAC_R2_SEL_MASK (0x3 << 12)
325 #define RT5616_DAC_R2_SEL_IF2 (0x0 << 12)
326 #define RT5616_DAC_R2_SEL_IF3 (0x1 << 12)
327 #define RT5616_DAC_R2_SEL_TXDC (0x2 << 12)
328 #define RT5616_IF2_ADC_L_SEL_MASK (0x1 << 11)
330 #define RT5616_IF2_ADC_L_SEL_TXDP (0x0 << 11)
331 #define RT5616_IF2_ADC_L_SEL_PASS (0x1 << 11)
332 #define RT5616_IF2_ADC_R_SEL_MASK (0x1 << 10)
334 #define RT5616_IF2_ADC_R_SEL_TXDP (0x0 << 10)
335 #define RT5616_IF2_ADC_R_SEL_PASS (0x1 << 10)
336 #define RT5616_RXDC_SEL_MASK (0x3 << 8)
338 #define RT5616_RXDC_SEL_NOR (0x0 << 8)
339 #define RT5616_RXDC_SEL_L2R (0x1 << 8)
340 #define RT5616_RXDC_SEL_R2L (0x2 << 8)
341 #define RT5616_RXDC_SEL_SWAP (0x3 << 8)
342 #define RT5616_RXDP_SEL_MASK (0x3 << 6)
344 #define RT5616_RXDP_SEL_NOR (0x0 << 6)
345 #define RT5616_RXDP_SEL_L2R (0x1 << 6)
346 #define RT5616_RXDP_SEL_R2L (0x2 << 6)
347 #define RT5616_RXDP_SEL_SWAP (0x3 << 6)
348 #define RT5616_TXDC_SEL_MASK (0x3 << 4)
350 #define RT5616_TXDC_SEL_NOR (0x0 << 4)
351 #define RT5616_TXDC_SEL_L2R (0x1 << 4)
352 #define RT5616_TXDC_SEL_R2L (0x2 << 4)
353 #define RT5616_TXDC_SEL_SWAP (0x3 << 4)
354 #define RT5616_TXDP_SEL_MASK (0x3 << 2)
356 #define RT5616_TXDP_SEL_NOR (0x0 << 2)
357 #define RT5616_TXDP_SEL_L2R (0x1 << 2)
358 #define RT5616_TXDP_SEL_R2L (0x2 << 2)
359 #define RT5616_TRXDP_SEL_SWAP (0x3 << 2)
361 /* REC Left Mixer Control 1 (0x3b) */
362 #define RT5616_G_LN_L2_RM_L_MASK (0x7 << 13)
364 #define RT5616_G_LN_L1_RM_L_MASK (0x7 << 10)
366 #define RT5616_G_BST3_RM_L_MASK (0x7 << 4)
368 #define RT5616_G_BST2_RM_L_MASK (0x7 << 1)
371 /* REC Left Mixer Control 2 (0x3c) */
372 #define RT5616_G_BST1_RM_L_MASK (0x7 << 13)
374 #define RT5616_G_OM_L_RM_L_MASK (0x7 << 10)
376 #define RT5616_M_IN2_L_RM_L (0x1 << 6)
378 #define RT5616_M_IN1_L_RM_L (0x1 << 5)
380 #define RT5616_M_BST3_RM_L (0x1 << 3)
382 #define RT5616_M_BST2_RM_L (0x1 << 2)
384 #define RT5616_M_BST1_RM_L (0x1 << 1)
386 #define RT5616_M_OM_L_RM_L (0x1)
387 #define RT5616_M_OM_L_RM_L_SFT 0
389 /* REC Right Mixer Control 1 (0x3d) */
390 #define RT5616_G_IN2_R_RM_R_MASK (0x7 << 13)
392 #define RT5616_G_IN1_R_RM_R_MASK (0x7 << 10)
394 #define RT5616_G_BST3_RM_R_MASK (0x7 << 4)
396 #define RT5616_G_BST2_RM_R_MASK (0x7 << 1)
399 /* REC Right Mixer Control 2 (0x3e) */
400 #define RT5616_G_BST1_RM_R_MASK (0x7 << 13)
402 #define RT5616_G_OM_R_RM_R_MASK (0x7 << 10)
404 #define RT5616_M_IN2_R_RM_R (0x1 << 6)
406 #define RT5616_M_IN1_R_RM_R (0x1 << 5)
408 #define RT5616_M_BST3_RM_R (0x1 << 3)
410 #define RT5616_M_BST2_RM_R (0x1 << 2)
412 #define RT5616_M_BST1_RM_R (0x1 << 1)
414 #define RT5616_M_OM_R_RM_R (0x1)
415 #define RT5616_M_OM_R_RM_R_SFT 0
417 /* HPMIX Control (0x45) */
418 #define RT5616_M_DAC1_HM (0x1 << 14)
420 #define RT5616_M_HPVOL_HM (0x1 << 13)
422 #define RT5616_G_HPOMIX_MASK (0x1 << 12)
425 /* SPK Left Mixer Control (0x46) */
426 #define RT5616_G_RM_L_SM_L_MASK (0x3 << 14)
428 #define RT5616_G_IN_L_SM_L_MASK (0x3 << 12)
430 #define RT5616_G_DAC_L1_SM_L_MASK (0x3 << 10)
432 #define RT5616_G_DAC_L2_SM_L_MASK (0x3 << 8)
434 #define RT5616_G_OM_L_SM_L_MASK (0x3 << 6)
436 #define RT5616_M_RM_L_SM_L (0x1 << 5)
438 #define RT5616_M_IN_L_SM_L (0x1 << 4)
440 #define RT5616_M_DAC_L1_SM_L (0x1 << 3)
442 #define RT5616_M_DAC_L2_SM_L (0x1 << 2)
444 #define RT5616_M_OM_L_SM_L (0x1 << 1)
447 /* SPK Right Mixer Control (0x47) */
448 #define RT5616_G_RM_R_SM_R_MASK (0x3 << 14)
450 #define RT5616_G_IN_R_SM_R_MASK (0x3 << 12)
452 #define RT5616_G_DAC_R1_SM_R_MASK (0x3 << 10)
454 #define RT5616_G_DAC_R2_SM_R_MASK (0x3 << 8)
456 #define RT5616_G_OM_R_SM_R_MASK (0x3 << 6)
458 #define RT5616_M_RM_R_SM_R (0x1 << 5)
460 #define RT5616_M_IN_R_SM_R (0x1 << 4)
462 #define RT5616_M_DAC_R1_SM_R (0x1 << 3)
464 #define RT5616_M_DAC_R2_SM_R (0x1 << 2)
466 #define RT5616_M_OM_R_SM_R (0x1 << 1)
469 /* SPOLMIX Control (0x48) */
470 #define RT5616_M_DAC_R1_SPM_L (0x1 << 15)
472 #define RT5616_M_DAC_L1_SPM_L (0x1 << 14)
474 #define RT5616_M_SV_R_SPM_L (0x1 << 13)
476 #define RT5616_M_SV_L_SPM_L (0x1 << 12)
478 #define RT5616_M_BST1_SPM_L (0x1 << 11)
481 /* SPORMIX Control (0x49) */
482 #define RT5616_M_DAC_R1_SPM_R (0x1 << 13)
484 #define RT5616_M_SV_R_SPM_R (0x1 << 12)
486 #define RT5616_M_BST1_SPM_R (0x1 << 11)
489 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
490 #define RT5616_SPO_CLSD_RATIO_MASK (0x7)
491 #define RT5616_SPO_CLSD_RATIO_SFT 0
493 /* Mono Output Mixer Control (0x4c) */
494 #define RT5616_M_DAC_R2_MM (0x1 << 15)
496 #define RT5616_M_DAC_L2_MM (0x1 << 14)
498 #define RT5616_M_OV_R_MM (0x1 << 13)
500 #define RT5616_M_OV_L_MM (0x1 << 12)
502 #define RT5616_M_BST1_MM (0x1 << 11)
504 #define RT5616_G_MONOMIX_MASK (0x1 << 10)
507 /* Output Left Mixer Control 1 (0x4d) */
508 #define RT5616_G_BST2_OM_L_MASK (0x7 << 10)
510 #define RT5616_G_BST1_OM_L_MASK (0x7 << 7)
512 #define RT5616_G_IN1_L_OM_L_MASK (0x7 << 4)
514 #define RT5616_G_RM_L_OM_L_MASK (0x7 << 1)
517 /* Output Left Mixer Control 2 (0x4e) */
518 #define RT5616_G_DAC_L1_OM_L_MASK (0x7 << 7)
520 #define RT5616_G_IN2_L_OM_L_MASK (0x7 << 4)
523 /* Output Left Mixer Control 3 (0x4f) */
524 #define RT5616_M_IN2_L_OM_L (0x1 << 9)
526 #define RT5616_M_BST2_OM_L (0x1 << 6)
528 #define RT5616_M_BST1_OM_L (0x1 << 5)
530 #define RT5616_M_IN1_L_OM_L (0x1 << 4)
532 #define RT5616_M_RM_L_OM_L (0x1 << 3)
534 #define RT5616_M_DAC_L1_OM_L (0x1)
535 #define RT5616_M_DAC_L1_OM_L_SFT 0
537 /* Output Right Mixer Control 1 (0x50) */
538 #define RT5616_G_BST2_OM_R_MASK (0x7 << 10)
540 #define RT5616_G_BST1_OM_R_MASK (0x7 << 7)
542 #define RT5616_G_IN1_R_OM_R_MASK (0x7 << 4)
544 #define RT5616_G_RM_R_OM_R_MASK (0x7 << 1)
547 /* Output Right Mixer Control 2 (0x51) */
548 #define RT5616_G_DAC_R1_OM_R_MASK (0x7 << 7)
550 #define RT5616_G_IN2_R_OM_R_MASK (0x7 << 4)
553 /* Output Right Mixer Control 3 (0x52) */
554 #define RT5616_M_IN2_R_OM_R (0x1 << 9)
556 #define RT5616_M_BST2_OM_R (0x1 << 6)
558 #define RT5616_M_BST1_OM_R (0x1 << 5)
560 #define RT5616_M_IN1_R_OM_R (0x1 << 4)
562 #define RT5616_M_RM_R_OM_R (0x1 << 3)
564 #define RT5616_M_DAC_R1_OM_R (0x1)
565 #define RT5616_M_DAC_R1_OM_R_SFT 0
567 /* LOUT Mixer Control (0x53) */
568 #define RT5616_M_DAC_L1_LM (0x1 << 15)
570 #define RT5616_M_DAC_R1_LM (0x1 << 14)
572 #define RT5616_M_OV_L_LM (0x1 << 13)
574 #define RT5616_M_OV_R_LM (0x1 << 12)
576 #define RT5616_G_LOUTMIX_MASK (0x1 << 11)
579 /* Power Management for Digital 1 (0x61) */
580 #define RT5616_PWR_I2S1 (0x1 << 15)
582 #define RT5616_PWR_I2S2 (0x1 << 14)
584 #define RT5616_PWR_DAC_L1 (0x1 << 12)
586 #define RT5616_PWR_DAC_R1 (0x1 << 11)
588 #define RT5616_PWR_ADC_L (0x1 << 2)
590 #define RT5616_PWR_ADC_R (0x1 << 1)
593 /* Power Management for Digital 2 (0x62) */
594 #define RT5616_PWR_ADC_STO1_F (0x1 << 15)
596 #define RT5616_PWR_DAC_STO1_F (0x1 << 11)
599 /* Power Management for Analog 1 (0x63) */
600 #define RT5616_PWR_VREF1 (0x1 << 15)
602 #define RT5616_PWR_FV1 (0x1 << 14)
604 #define RT5616_PWR_MB (0x1 << 13)
606 #define RT5616_PWR_LM (0x1 << 12)
608 #define RT5616_PWR_BG (0x1 << 11)
610 #define RT5616_PWR_HP_L (0x1 << 7)
612 #define RT5616_PWR_HP_R (0x1 << 6)
614 #define RT5616_PWR_HA (0x1 << 5)
616 #define RT5616_PWR_VREF2 (0x1 << 4)
618 #define RT5616_PWR_FV2 (0x1 << 3)
620 #define RT5616_PWR_LDO (0x1 << 2)
622 #define RT5616_PWR_LDO_DVO_MASK (0x3)
623 #define RT5616_PWR_LDO_DVO_1_0V 0
628 /* Power Management for Analog 2 (0x64) */
629 #define RT5616_PWR_BST1 (0x1 << 15)
631 #define RT5616_PWR_BST2 (0x1 << 14)
633 #define RT5616_PWR_MB1 (0x1 << 11)
635 #define RT5616_PWR_PLL (0x1 << 9)
637 #define RT5616_PWR_BST1_OP2 (0x1 << 5)
639 #define RT5616_PWR_BST2_OP2 (0x1 << 4)
641 #define RT5616_PWR_BST3_OP2 (0x1 << 3)
643 #define RT5616_PWR_JD_M (0x1 << 2)
645 #define RT5616_PWR_JD2 (0x1 << 1)
647 #define RT5616_PWR_JD3 (0x1)
648 #define RT5616_PWM_JD3_BIT 0
650 /* Power Management for Mixer (0x65) */
651 #define RT5616_PWR_OM_L (0x1 << 15)
653 #define RT5616_PWR_OM_R (0x1 << 14)
655 #define RT5616_PWR_RM_L (0x1 << 11)
657 #define RT5616_PWR_RM_R (0x1 << 10)
660 /* Power Management for Volume (0x66) */
661 #define RT5616_PWR_OV_L (0x1 << 13)
663 #define RT5616_PWR_OV_R (0x1 << 12)
665 #define RT5616_PWR_HV_L (0x1 << 11)
667 #define RT5616_PWR_HV_R (0x1 << 10)
669 #define RT5616_PWR_IN1_L (0x1 << 9)
671 #define RT5616_PWR_IN1_R (0x1 << 8)
673 #define RT5616_PWR_IN2_L (0x1 << 7)
675 #define RT5616_PWR_IN2_R (0x1 << 6)
678 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
679 #define RT5616_I2S_MS_MASK (0x1 << 15)
681 #define RT5616_I2S_MS_M (0x0 << 15)
682 #define RT5616_I2S_MS_S (0x1 << 15)
683 #define RT5616_I2S_O_CP_MASK (0x3 << 10)
685 #define RT5616_I2S_O_CP_OFF (0x0 << 10)
686 #define RT5616_I2S_O_CP_U_LAW (0x1 << 10)
687 #define RT5616_I2S_O_CP_A_LAW (0x2 << 10)
688 #define RT5616_I2S_I_CP_MASK (0x3 << 8)
690 #define RT5616_I2S_I_CP_OFF (0x0 << 8)
691 #define RT5616_I2S_I_CP_U_LAW (0x1 << 8)
692 #define RT5616_I2S_I_CP_A_LAW (0x2 << 8)
693 #define RT5616_I2S_BP_MASK (0x1 << 7)
695 #define RT5616_I2S_BP_NOR (0x0 << 7)
696 #define RT5616_I2S_BP_INV (0x1 << 7)
697 #define RT5616_I2S_DL_MASK (0x3 << 2)
699 #define RT5616_I2S_DL_16 (0x0 << 2)
700 #define RT5616_I2S_DL_20 (0x1 << 2)
701 #define RT5616_I2S_DL_24 (0x2 << 2)
702 #define RT5616_I2S_DL_8 (0x3 << 2)
703 #define RT5616_I2S_DF_MASK (0x3)
704 #define RT5616_I2S_DF_SFT 0
705 #define RT5616_I2S_DF_I2S (0x0)
706 #define RT5616_I2S_DF_LEFT (0x1)
707 #define RT5616_I2S_DF_PCM_A (0x2)
708 #define RT5616_I2S_DF_PCM_B (0x3)
710 /* ADC/DAC Clock Control 1 (0x73) */
711 #define RT5616_I2S_PD1_MASK (0x7 << 12)
713 #define RT5616_I2S_PD1_1 (0x0 << 12)
714 #define RT5616_I2S_PD1_2 (0x1 << 12)
715 #define RT5616_I2S_PD1_3 (0x2 << 12)
716 #define RT5616_I2S_PD1_4 (0x3 << 12)
717 #define RT5616_I2S_PD1_6 (0x4 << 12)
718 #define RT5616_I2S_PD1_8 (0x5 << 12)
719 #define RT5616_I2S_PD1_12 (0x6 << 12)
720 #define RT5616_I2S_PD1_16 (0x7 << 12)
721 #define RT5616_I2S_BCLK_MS2_MASK (0x1 << 11)
722 #define RT5616_DAC_OSR_MASK (0x3 << 2)
724 #define RT5616_DAC_OSR_128 (0x0 << 2)
725 #define RT5616_DAC_OSR_64 (0x1 << 2)
726 #define RT5616_DAC_OSR_32 (0x2 << 2)
727 #define RT5616_DAC_OSR_128_3 (0x3 << 2)
728 #define RT5616_ADC_OSR_MASK (0x3)
729 #define RT5616_ADC_OSR_SFT 0
730 #define RT5616_ADC_OSR_128 (0x0)
731 #define RT5616_ADC_OSR_64 (0x1)
732 #define RT5616_ADC_OSR_32 (0x2)
733 #define RT5616_ADC_OSR_128_3 (0x3)
735 /* ADC/DAC Clock Control 2 (0x74) */
736 #define RT5616_DAHPF_EN (0x1 << 11)
738 #define RT5616_ADHPF_EN (0x1 << 10)
741 /* TDM Control 1 (0x77) */
742 #define RT5616_TDM_INTEL_SEL_MASK (0x1 << 15)
744 #define RT5616_TDM_INTEL_SEL_64 (0x0 << 15)
745 #define RT5616_TDM_INTEL_SEL_50 (0x1 << 15)
746 #define RT5616_TDM_MODE_SEL_MASK (0x1 << 14)
748 #define RT5616_TDM_MODE_SEL_NOR (0x0 << 14)
749 #define RT5616_TDM_MODE_SEL_TDM (0x1 << 14)
750 #define RT5616_TDM_CH_NUM_SEL_MASK (0x3 << 12)
752 #define RT5616_TDM_CH_NUM_SEL_2 (0x0 << 12)
753 #define RT5616_TDM_CH_NUM_SEL_4 (0x1 << 12)
754 #define RT5616_TDM_CH_NUM_SEL_6 (0x2 << 12)
755 #define RT5616_TDM_CH_NUM_SEL_8 (0x3 << 12)
756 #define RT5616_TDM_CH_LEN_SEL_MASK (0x3 << 10)
758 #define RT5616_TDM_CH_LEN_SEL_16 (0x0 << 10)
759 #define RT5616_TDM_CH_LEN_SEL_20 (0x1 << 10)
760 #define RT5616_TDM_CH_LEN_SEL_24 (0x2 << 10)
761 #define RT5616_TDM_CH_LEN_SEL_32 (0x3 << 10)
762 #define RT5616_TDM_ADC_SEL_MASK (0x1 << 9)
764 #define RT5616_TDM_ADC_SEL_NOR (0x0 << 9)
765 #define RT5616_TDM_ADC_SEL_SWAP (0x1 << 9)
766 #define RT5616_TDM_ADC_START_SEL_MASK (0x1 << 8)
768 #define RT5616_TDM_ADC_START_SEL_SL0 (0x0 << 8)
769 #define RT5616_TDM_ADC_START_SEL_SL4 (0x1 << 8)
770 #define RT5616_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
772 #define RT5616_TDM_I2S_CH2_SEL_LR (0x0 << 6)
773 #define RT5616_TDM_I2S_CH2_SEL_RL (0x1 << 6)
774 #define RT5616_TDM_I2S_CH2_SEL_LL (0x2 << 6)
775 #define RT5616_TDM_I2S_CH2_SEL_RR (0x3 << 6)
776 #define RT5616_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
778 #define RT5616_TDM_I2S_CH4_SEL_LR (0x0 << 4)
779 #define RT5616_TDM_I2S_CH4_SEL_RL (0x1 << 4)
780 #define RT5616_TDM_I2S_CH4_SEL_LL (0x2 << 4)
781 #define RT5616_TDM_I2S_CH4_SEL_RR (0x3 << 4)
782 #define RT5616_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
784 #define RT5616_TDM_I2S_CH6_SEL_LR (0x0 << 2)
785 #define RT5616_TDM_I2S_CH6_SEL_RL (0x1 << 2)
786 #define RT5616_TDM_I2S_CH6_SEL_LL (0x2 << 2)
787 #define RT5616_TDM_I2S_CH6_SEL_RR (0x3 << 2)
788 #define RT5616_TDM_I2S_CH8_SEL_MASK (0x3)
789 #define RT5616_TDM_I2S_CH8_SEL_SFT 0
790 #define RT5616_TDM_I2S_CH8_SEL_LR (0x0)
791 #define RT5616_TDM_I2S_CH8_SEL_RL (0x1)
792 #define RT5616_TDM_I2S_CH8_SEL_LL (0x2)
793 #define RT5616_TDM_I2S_CH8_SEL_RR (0x3)
795 /* TDM Control 2 (0x78) */
796 #define RT5616_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
798 #define RT5616_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
799 #define RT5616_TDM_LRCK_POL_SEL_INV (0x1 << 15)
800 #define RT5616_TDM_CH_VAL_SEL_MASK (0x1 << 14)
802 #define RT5616_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
803 #define RT5616_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
804 #define RT5616_TDM_CH_VAL_EN (0x1 << 13)
806 #define RT5616_TDM_LPBK_EN (0x1 << 12)
808 #define RT5616_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
810 #define RT5616_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
811 #define RT5616_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
812 #define RT5616_TDM_END_EDGE_SEL_MASK (0x1 << 10)
814 #define RT5616_TDM_END_EDGE_SEL_POS (0x0 << 10)
815 #define RT5616_TDM_END_EDGE_SEL_NEG (0x1 << 10)
816 #define RT5616_TDM_END_EDGE_EN (0x1 << 9)
818 #define RT5616_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
820 #define RT5616_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
821 #define RT5616_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
822 #define RT5616_M_TDM2_L (0x1 << 7)
824 #define RT5616_M_TDM2_R (0x1 << 6)
826 #define RT5616_M_TDM4_L (0x1 << 5)
828 #define RT5616_M_TDM4_R (0x1 << 4)
831 /* Global Clock Control (0x80) */
832 #define RT5616_SCLK_SRC_MASK (0x3 << 14)
834 #define RT5616_SCLK_SRC_MCLK (0x0 << 14)
835 #define RT5616_SCLK_SRC_PLL1 (0x1 << 14)
836 #define RT5616_PLL1_SRC_MASK (0x3 << 12)
838 #define RT5616_PLL1_SRC_MCLK (0x0 << 12)
839 #define RT5616_PLL1_SRC_BCLK1 (0x1 << 12)
840 #define RT5616_PLL1_SRC_BCLK2 (0x2 << 12)
841 #define RT5616_PLL1_PD_MASK (0x1 << 3)
843 #define RT5616_PLL1_PD_1 (0x0 << 3)
844 #define RT5616_PLL1_PD_2 (0x1 << 3)
848 /* PLL M/N/K Code Control 1 (0x81) */
849 #define RT5616_PLL_N_MAX 0x1ff
852 #define RT5616_PLL_K_MAX 0x1f
854 #define RT5616_PLL_K_SFT 0
856 /* PLL M/N/K Code Control 2 (0x82) */
857 #define RT5616_PLL_M_MAX 0xf
860 #define RT5616_PLL_M_BP (0x1 << 11)
863 /* PLL tracking mode 1 (0x83) */
864 #define RT5616_STO1_T_MASK (0x1 << 15)
866 #define RT5616_STO1_T_SCLK (0x0 << 15)
867 #define RT5616_STO1_T_LRCK1 (0x1 << 15)
868 #define RT5616_STO2_T_MASK (0x1 << 12)
870 #define RT5616_STO2_T_I2S2 (0x0 << 12)
871 #define RT5616_STO2_T_LRCK2 (0x1 << 12)
872 #define RT5616_ASRC2_REF_MASK (0x1 << 11)
874 #define RT5616_ASRC2_REF_LRCK2 (0x0 << 11)
875 #define RT5616_ASRC2_REF_LRCK1 (0x1 << 11)
876 #define RT5616_DMIC_1_M_MASK (0x1 << 9)
878 #define RT5616_DMIC_1_M_NOR (0x0 << 9)
879 #define RT5616_DMIC_1_M_ASYN (0x1 << 9)
881 /* PLL tracking mode 2 (0x84) */
882 #define RT5616_STO1_ASRC_EN (0x1 << 15)
884 #define RT5616_STO2_ASRC_EN (0x1 << 14)
886 #define RT5616_STO1_DAC_M_MASK (0x1 << 13)
888 #define RT5616_STO1_DAC_M_NOR (0x0 << 13)
889 #define RT5616_STO1_DAC_M_ASRC (0x1 << 13)
890 #define RT5616_STO2_DAC_M_MASK (0x1 << 12)
892 #define RT5616_STO2_DAC_M_NOR (0x0 << 12)
893 #define RT5616_STO2_DAC_M_ASRC (0x1 << 12)
894 #define RT5616_ADC_M_MASK (0x1 << 11)
896 #define RT5616_ADC_M_NOR (0x0 << 11)
897 #define RT5616_ADC_M_ASRC (0x1 << 11)
898 #define RT5616_I2S1_R_D_MASK (0x1 << 4)
900 #define RT5616_I2S1_R_D_DIS (0x0 << 4)
901 #define RT5616_I2S1_R_D_EN (0x1 << 4)
902 #define RT5616_I2S2_R_D_MASK (0x1 << 3)
904 #define RT5616_I2S2_R_D_DIS (0x0 << 3)
905 #define RT5616_I2S2_R_D_EN (0x1 << 3)
906 #define RT5616_PRE_SCLK_MASK (0x3)
907 #define RT5616_PRE_SCLK_SFT 0
908 #define RT5616_PRE_SCLK_512 (0x0)
909 #define RT5616_PRE_SCLK_1024 (0x1)
910 #define RT5616_PRE_SCLK_2048 (0x2)
912 /* PLL tracking mode 3 (0x85) */
913 #define RT5616_I2S1_RATE_MASK (0xf << 12)
915 #define RT5616_I2S2_RATE_MASK (0xf << 8)
917 #define RT5616_G_ASRC_LP_MASK (0x1 << 3)
919 #define RT5616_ASRC_LP_F_M (0x1 << 2)
921 #define RT5616_ASRC_LP_F_NOR (0x0 << 2)
922 #define RT5616_ASRC_LP_F_SB (0x1 << 2)
923 #define RT5616_FTK_PH_DET_MASK (0x3)
924 #define RT5616_FTK_PH_DET_SFT 0
925 #define RT5616_FTK_PH_DET_DIV1 (0x0)
926 #define RT5616_FTK_PH_DET_DIV2 (0x1)
927 #define RT5616_FTK_PH_DET_DIV4 (0x2)
928 #define RT5616_FTK_PH_DET_DIV8 (0x3)
930 /*PLL tracking mode 6 (0x89) */
931 #define RT5616_I2S1_PD_MASK (0x7 << 12)
933 #define RT5616_I2S2_PD_MASK (0x7 << 8)
936 /*PLL tracking mode 7 (0x8a) */
937 #define RT5616_FSI1_RATE_MASK (0xf << 12)
939 #define RT5616_FSI2_RATE_MASK (0xf << 8)
942 /* HPOUT Over Current Detection (0x8b) */
943 #define RT5616_HP_OVCD_MASK (0x1 << 10)
945 #define RT5616_HP_OVCD_DIS (0x0 << 10)
946 #define RT5616_HP_OVCD_EN (0x1 << 10)
947 #define RT5616_HP_OC_TH_MASK (0x3 << 8)
949 #define RT5616_HP_OC_TH_90 (0x0 << 8)
950 #define RT5616_HP_OC_TH_105 (0x1 << 8)
951 #define RT5616_HP_OC_TH_120 (0x2 << 8)
952 #define RT5616_HP_OC_TH_135 (0x3 << 8)
954 /* Depop Mode Control 1 (0x8e) */
955 #define RT5616_SMT_TRIG_MASK (0x1 << 15)
957 #define RT5616_SMT_TRIG_DIS (0x0 << 15)
958 #define RT5616_SMT_TRIG_EN (0x1 << 15)
959 #define RT5616_HP_L_SMT_MASK (0x1 << 9)
961 #define RT5616_HP_L_SMT_DIS (0x0 << 9)
962 #define RT5616_HP_L_SMT_EN (0x1 << 9)
963 #define RT5616_HP_R_SMT_MASK (0x1 << 8)
965 #define RT5616_HP_R_SMT_DIS (0x0 << 8)
966 #define RT5616_HP_R_SMT_EN (0x1 << 8)
967 #define RT5616_HP_CD_PD_MASK (0x1 << 7)
969 #define RT5616_HP_CD_PD_DIS (0x0 << 7)
970 #define RT5616_HP_CD_PD_EN (0x1 << 7)
971 #define RT5616_RSTN_MASK (0x1 << 6)
973 #define RT5616_RSTN_DIS (0x0 << 6)
974 #define RT5616_RSTN_EN (0x1 << 6)
975 #define RT5616_RSTP_MASK (0x1 << 5)
977 #define RT5616_RSTP_DIS (0x0 << 5)
978 #define RT5616_RSTP_EN (0x1 << 5)
979 #define RT5616_HP_CO_MASK (0x1 << 4)
981 #define RT5616_HP_CO_DIS (0x0 << 4)
982 #define RT5616_HP_CO_EN (0x1 << 4)
983 #define RT5616_HP_CP_MASK (0x1 << 3)
985 #define RT5616_HP_CP_PD (0x0 << 3)
986 #define RT5616_HP_CP_PU (0x1 << 3)
987 #define RT5616_HP_SG_MASK (0x1 << 2)
989 #define RT5616_HP_SG_DIS (0x0 << 2)
990 #define RT5616_HP_SG_EN (0x1 << 2)
991 #define RT5616_HP_DP_MASK (0x1 << 1)
993 #define RT5616_HP_DP_PD (0x0 << 1)
994 #define RT5616_HP_DP_PU (0x1 << 1)
995 #define RT5616_HP_CB_MASK (0x1)
996 #define RT5616_HP_CB_SFT 0
997 #define RT5616_HP_CB_PD (0x0)
998 #define RT5616_HP_CB_PU (0x1)
1000 /* Depop Mode Control 2 (0x8f) */
1001 #define RT5616_DEPOP_MASK (0x1 << 13)
1003 #define RT5616_DEPOP_AUTO (0x0 << 13)
1004 #define RT5616_DEPOP_MAN (0x1 << 13)
1005 #define RT5616_RAMP_MASK (0x1 << 12)
1007 #define RT5616_RAMP_DIS (0x0 << 12)
1008 #define RT5616_RAMP_EN (0x1 << 12)
1009 #define RT5616_BPS_MASK (0x1 << 11)
1011 #define RT5616_BPS_DIS (0x0 << 11)
1012 #define RT5616_BPS_EN (0x1 << 11)
1013 #define RT5616_FAST_UPDN_MASK (0x1 << 10)
1015 #define RT5616_FAST_UPDN_DIS (0x0 << 10)
1016 #define RT5616_FAST_UPDN_EN (0x1 << 10)
1017 #define RT5616_MRES_MASK (0x3 << 8)
1019 #define RT5616_MRES_15MO (0x0 << 8)
1020 #define RT5616_MRES_25MO (0x1 << 8)
1021 #define RT5616_MRES_35MO (0x2 << 8)
1022 #define RT5616_MRES_45MO (0x3 << 8)
1023 #define RT5616_VLO_MASK (0x1 << 7)
1025 #define RT5616_VLO_3V (0x0 << 7)
1026 #define RT5616_VLO_32V (0x1 << 7)
1027 #define RT5616_DIG_DP_MASK (0x1 << 6)
1029 #define RT5616_DIG_DP_DIS (0x0 << 6)
1030 #define RT5616_DIG_DP_EN (0x1 << 6)
1031 #define RT5616_DP_TH_MASK (0x3 << 4)
1034 /* Depop Mode Control 3 (0x90) */
1035 #define RT5616_CP_SYS_MASK (0x7 << 12)
1037 #define RT5616_CP_FQ1_MASK (0x7 << 8)
1039 #define RT5616_CP_FQ2_MASK (0x7 << 4)
1041 #define RT5616_CP_FQ3_MASK (0x7)
1042 #define RT5616_CP_FQ3_SFT 0
1043 #define RT5616_CP_FQ_1_5_KHZ 0
1052 /* HPOUT charge pump (0x91) */
1053 #define RT5616_OSW_L_MASK (0x1 << 11)
1055 #define RT5616_OSW_L_DIS (0x0 << 11)
1056 #define RT5616_OSW_L_EN (0x1 << 11)
1057 #define RT5616_OSW_R_MASK (0x1 << 10)
1059 #define RT5616_OSW_R_DIS (0x0 << 10)
1060 #define RT5616_OSW_R_EN (0x1 << 10)
1061 #define RT5616_PM_HP_MASK (0x3 << 8)
1063 #define RT5616_PM_HP_LV (0x0 << 8)
1064 #define RT5616_PM_HP_MV (0x1 << 8)
1065 #define RT5616_PM_HP_HV (0x2 << 8)
1066 #define RT5616_IB_HP_MASK (0x3 << 6)
1068 #define RT5616_IB_HP_125IL (0x0 << 6)
1069 #define RT5616_IB_HP_25IL (0x1 << 6)
1070 #define RT5616_IB_HP_5IL (0x2 << 6)
1071 #define RT5616_IB_HP_1IL (0x3 << 6)
1073 /* Micbias Control (0x93) */
1074 #define RT5616_MIC1_BS_MASK (0x1 << 15)
1076 #define RT5616_MIC1_BS_9AV (0x0 << 15)
1077 #define RT5616_MIC1_BS_75AV (0x1 << 15)
1078 #define RT5616_MIC1_CLK_MASK (0x1 << 13)
1080 #define RT5616_MIC1_CLK_DIS (0x0 << 13)
1081 #define RT5616_MIC1_CLK_EN (0x1 << 13)
1082 #define RT5616_MIC1_OVCD_MASK (0x1 << 11)
1084 #define RT5616_MIC1_OVCD_DIS (0x0 << 11)
1085 #define RT5616_MIC1_OVCD_EN (0x1 << 11)
1086 #define RT5616_MIC1_OVTH_MASK (0x3 << 9)
1088 #define RT5616_MIC1_OVTH_600UA (0x0 << 9)
1089 #define RT5616_MIC1_OVTH_1500UA (0x1 << 9)
1090 #define RT5616_MIC1_OVTH_2000UA (0x2 << 9)
1091 #define RT5616_PWR_MB_MASK (0x1 << 5)
1093 #define RT5616_PWR_MB_PD (0x0 << 5)
1094 #define RT5616_PWR_MB_PU (0x1 << 5)
1095 #define RT5616_PWR_CLK12M_MASK (0x1 << 4)
1097 #define RT5616_PWR_CLK12M_PD (0x0 << 4)
1098 #define RT5616_PWR_CLK12M_PU (0x1 << 4)
1100 /* Analog JD Control 1 (0x94) */
1101 #define RT5616_JD2_CMP_MASK (0x7 << 12)
1103 #define RT5616_JD_PU (0x1 << 11)
1105 #define RT5616_JD_PD (0x1 << 10)
1107 #define RT5616_JD_MODE_SEL_MASK (0x3 << 8)
1109 #define RT5616_JD_MODE_SEL_M0 (0x0 << 8)
1110 #define RT5616_JD_MODE_SEL_M1 (0x1 << 8)
1111 #define RT5616_JD_MODE_SEL_M2 (0x2 << 8)
1112 #define RT5616_JD_M_CMP (0x7 << 4)
1114 #define RT5616_JD_M_PU (0x1 << 3)
1116 #define RT5616_JD_M_PD (0x1 << 2)
1118 #define RT5616_JD_M_MODE_SEL_MASK (0x3)
1119 #define RT5616_JD_M_MODE_SEL_SFT 0
1120 #define RT5616_JD_M_MODE_SEL_M0 (0x0)
1121 #define RT5616_JD_M_MODE_SEL_M1 (0x1)
1122 #define RT5616_JD_M_MODE_SEL_M2 (0x2)
1124 /* Analog JD Control 2 (0x95) */
1125 #define RT5616_JD3_CMP_MASK (0x7 << 12)
1128 /* EQ Control 1 (0xb0) */
1129 #define RT5616_EQ_SRC_MASK (0x1 << 15)
1131 #define RT5616_EQ_SRC_DAC (0x0 << 15)
1132 #define RT5616_EQ_SRC_ADC (0x1 << 15)
1133 #define RT5616_EQ_UPD (0x1 << 14)
1135 #define RT5616_EQ_CD_MASK (0x1 << 13)
1137 #define RT5616_EQ_CD_DIS (0x0 << 13)
1138 #define RT5616_EQ_CD_EN (0x1 << 13)
1139 #define RT5616_EQ_DITH_MASK (0x3 << 8)
1141 #define RT5616_EQ_DITH_NOR (0x0 << 8)
1142 #define RT5616_EQ_DITH_LSB (0x1 << 8)
1143 #define RT5616_EQ_DITH_LSB_1 (0x2 << 8)
1144 #define RT5616_EQ_DITH_LSB_2 (0x3 << 8)
1145 #define RT5616_EQ_CD_F (0x1 << 7)
1147 #define RT5616_EQ_STA_HP2 (0x1 << 6)
1149 #define RT5616_EQ_STA_HP1 (0x1 << 5)
1151 #define RT5616_EQ_STA_BP4 (0x1 << 4)
1153 #define RT5616_EQ_STA_BP3 (0x1 << 3)
1155 #define RT5616_EQ_STA_BP2 (0x1 << 2)
1157 #define RT5616_EQ_STA_BP1 (0x1 << 1)
1159 #define RT5616_EQ_STA_LP (0x1)
1160 #define RT5616_EQ_STA_LP_BIT 0
1162 /* EQ Control 2 (0xb1) */
1163 #define RT5616_EQ_HPF1_M_MASK (0x1 << 8)
1165 #define RT5616_EQ_HPF1_M_HI (0x0 << 8)
1166 #define RT5616_EQ_HPF1_M_1ST (0x1 << 8)
1167 #define RT5616_EQ_LPF1_M_MASK (0x1 << 7)
1169 #define RT5616_EQ_LPF1_M_LO (0x0 << 7)
1170 #define RT5616_EQ_LPF1_M_1ST (0x1 << 7)
1171 #define RT5616_EQ_HPF2_MASK (0x1 << 6)
1173 #define RT5616_EQ_HPF2_DIS (0x0 << 6)
1174 #define RT5616_EQ_HPF2_EN (0x1 << 6)
1175 #define RT5616_EQ_HPF1_MASK (0x1 << 5)
1177 #define RT5616_EQ_HPF1_DIS (0x0 << 5)
1178 #define RT5616_EQ_HPF1_EN (0x1 << 5)
1179 #define RT5616_EQ_BPF4_MASK (0x1 << 4)
1181 #define RT5616_EQ_BPF4_DIS (0x0 << 4)
1182 #define RT5616_EQ_BPF4_EN (0x1 << 4)
1183 #define RT5616_EQ_BPF3_MASK (0x1 << 3)
1185 #define RT5616_EQ_BPF3_DIS (0x0 << 3)
1186 #define RT5616_EQ_BPF3_EN (0x1 << 3)
1187 #define RT5616_EQ_BPF2_MASK (0x1 << 2)
1189 #define RT5616_EQ_BPF2_DIS (0x0 << 2)
1190 #define RT5616_EQ_BPF2_EN (0x1 << 2)
1191 #define RT5616_EQ_BPF1_MASK (0x1 << 1)
1193 #define RT5616_EQ_BPF1_DIS (0x0 << 1)
1194 #define RT5616_EQ_BPF1_EN (0x1 << 1)
1195 #define RT5616_EQ_LPF_MASK (0x1)
1196 #define RT5616_EQ_LPF_SFT 0
1197 #define RT5616_EQ_LPF_DIS (0x0)
1198 #define RT5616_EQ_LPF_EN (0x1)
1199 #define RT5616_EQ_CTRL_MASK (0x7f)
1201 /* Memory Test (0xb2) */
1202 #define RT5616_MT_MASK (0x1 << 15)
1204 #define RT5616_MT_DIS (0x0 << 15)
1205 #define RT5616_MT_EN (0x1 << 15)
1207 /* DRC/AGC Control 1 (0xb4) */
1208 #define RT5616_DRC_AGC_P_MASK (0x1 << 15)
1210 #define RT5616_DRC_AGC_P_DAC (0x0 << 15)
1211 #define RT5616_DRC_AGC_P_ADC (0x1 << 15)
1212 #define RT5616_DRC_AGC_MASK (0x1 << 14)
1214 #define RT5616_DRC_AGC_DIS (0x0 << 14)
1215 #define RT5616_DRC_AGC_EN (0x1 << 14)
1216 #define RT5616_DRC_AGC_UPD (0x1 << 13)
1218 #define RT5616_DRC_AGC_AR_MASK (0x1f << 8)
1220 #define RT5616_DRC_AGC_R_MASK (0x7 << 5)
1222 #define RT5616_DRC_AGC_R_48K (0x1 << 5)
1223 #define RT5616_DRC_AGC_R_96K (0x2 << 5)
1224 #define RT5616_DRC_AGC_R_192K (0x3 << 5)
1225 #define RT5616_DRC_AGC_R_441K (0x5 << 5)
1226 #define RT5616_DRC_AGC_R_882K (0x6 << 5)
1227 #define RT5616_DRC_AGC_R_1764K (0x7 << 5)
1228 #define RT5616_DRC_AGC_RC_MASK (0x1f)
1229 #define RT5616_DRC_AGC_RC_SFT 0
1231 /* DRC/AGC Control 2 (0xb5) */
1232 #define RT5616_DRC_AGC_POB_MASK (0x3f << 8)
1234 #define RT5616_DRC_AGC_CP_MASK (0x1 << 7)
1236 #define RT5616_DRC_AGC_CP_DIS (0x0 << 7)
1237 #define RT5616_DRC_AGC_CP_EN (0x1 << 7)
1238 #define RT5616_DRC_AGC_CPR_MASK (0x3 << 5)
1240 #define RT5616_DRC_AGC_CPR_1_1 (0x0 << 5)
1241 #define RT5616_DRC_AGC_CPR_1_2 (0x1 << 5)
1242 #define RT5616_DRC_AGC_CPR_1_3 (0x2 << 5)
1243 #define RT5616_DRC_AGC_CPR_1_4 (0x3 << 5)
1244 #define RT5616_DRC_AGC_PRB_MASK (0x1f)
1245 #define RT5616_DRC_AGC_PRB_SFT 0
1247 /* DRC/AGC Control 3 (0xb6) */
1248 #define RT5616_DRC_AGC_NGB_MASK (0xf << 12)
1250 #define RT5616_DRC_AGC_TAR_MASK (0x1f << 7)
1252 #define RT5616_DRC_AGC_NG_MASK (0x1 << 6)
1254 #define RT5616_DRC_AGC_NG_DIS (0x0 << 6)
1255 #define RT5616_DRC_AGC_NG_EN (0x1 << 6)
1256 #define RT5616_DRC_AGC_NGH_MASK (0x1 << 5)
1258 #define RT5616_DRC_AGC_NGH_DIS (0x0 << 5)
1259 #define RT5616_DRC_AGC_NGH_EN (0x1 << 5)
1260 #define RT5616_DRC_AGC_NGT_MASK (0x1f)
1261 #define RT5616_DRC_AGC_NGT_SFT 0
1263 /* Jack Detect Control 1 (0xbb) */
1264 #define RT5616_JD_MASK (0x7 << 13)
1266 #define RT5616_JD_DIS (0x0 << 13)
1267 #define RT5616_JD_GPIO1 (0x1 << 13)
1268 #define RT5616_JD_GPIO2 (0x2 << 13)
1269 #define RT5616_JD_GPIO3 (0x3 << 13)
1270 #define RT5616_JD_GPIO4 (0x4 << 13)
1271 #define RT5616_JD_GPIO5 (0x5 << 13)
1272 #define RT5616_JD_GPIO6 (0x6 << 13)
1273 #define RT5616_JD_HP_MASK (0x1 << 11)
1275 #define RT5616_JD_HP_DIS (0x0 << 11)
1276 #define RT5616_JD_HP_EN (0x1 << 11)
1277 #define RT5616_JD_HP_TRG_MASK (0x1 << 10)
1279 #define RT5616_JD_HP_TRG_LO (0x0 << 10)
1280 #define RT5616_JD_HP_TRG_HI (0x1 << 10)
1281 #define RT5616_JD_SPL_MASK (0x1 << 9)
1283 #define RT5616_JD_SPL_DIS (0x0 << 9)
1284 #define RT5616_JD_SPL_EN (0x1 << 9)
1285 #define RT5616_JD_SPL_TRG_MASK (0x1 << 8)
1287 #define RT5616_JD_SPL_TRG_LO (0x0 << 8)
1288 #define RT5616_JD_SPL_TRG_HI (0x1 << 8)
1289 #define RT5616_JD_SPR_MASK (0x1 << 7)
1291 #define RT5616_JD_SPR_DIS (0x0 << 7)
1292 #define RT5616_JD_SPR_EN (0x1 << 7)
1293 #define RT5616_JD_SPR_TRG_MASK (0x1 << 6)
1295 #define RT5616_JD_SPR_TRG_LO (0x0 << 6)
1296 #define RT5616_JD_SPR_TRG_HI (0x1 << 6)
1297 #define RT5616_JD_LO_MASK (0x1 << 3)
1299 #define RT5616_JD_LO_DIS (0x0 << 3)
1300 #define RT5616_JD_LO_EN (0x1 << 3)
1301 #define RT5616_JD_LO_TRG_MASK (0x1 << 2)
1303 #define RT5616_JD_LO_TRG_LO (0x0 << 2)
1304 #define RT5616_JD_LO_TRG_HI (0x1 << 2)
1306 /* Jack Detect Control 2 (0xbc) */
1307 #define RT5616_JD_TRG_SEL_MASK (0x7 << 9)
1309 #define RT5616_JD_TRG_SEL_GPIO (0x0 << 9)
1310 #define RT5616_JD_TRG_SEL_JD1_1 (0x1 << 9)
1311 #define RT5616_JD_TRG_SEL_JD1_2 (0x2 << 9)
1312 #define RT5616_JD_TRG_SEL_JD2 (0x3 << 9)
1313 #define RT5616_JD_TRG_SEL_JD3 (0x4 << 9)
1314 #define RT5616_JD3_IRQ_EN (0x1 << 8)
1316 #define RT5616_JD3_EN_STKY (0x1 << 7)
1318 #define RT5616_JD3_INV (0x1 << 6)
1321 /* IRQ Control 1 (0xbd) */
1322 #define RT5616_IRQ_JD_MASK (0x1 << 15)
1324 #define RT5616_IRQ_JD_BP (0x0 << 15)
1325 #define RT5616_IRQ_JD_NOR (0x1 << 15)
1326 #define RT5616_JD_STKY_MASK (0x1 << 13)
1328 #define RT5616_JD_STKY_DIS (0x0 << 13)
1329 #define RT5616_JD_STKY_EN (0x1 << 13)
1330 #define RT5616_JD_P_MASK (0x1 << 11)
1332 #define RT5616_JD_P_NOR (0x0 << 11)
1333 #define RT5616_JD_P_INV (0x1 << 11)
1334 #define RT5616_JD1_1_IRQ_EN (0x1 << 9)
1336 #define RT5616_JD1_1_EN_STKY (0x1 << 8)
1338 #define RT5616_JD1_1_INV (0x1 << 7)
1340 #define RT5616_JD1_2_IRQ_EN (0x1 << 6)
1342 #define RT5616_JD1_2_EN_STKY (0x1 << 5)
1344 #define RT5616_JD1_2_INV (0x1 << 4)
1346 #define RT5616_JD2_IRQ_EN (0x1 << 3)
1348 #define RT5616_JD2_EN_STKY (0x1 << 2)
1350 #define RT5616_JD2_INV (0x1 << 1)
1353 /* IRQ Control 2 (0xbe) */
1354 #define RT5616_IRQ_MB1_OC_MASK (0x1 << 15)
1356 #define RT5616_IRQ_MB1_OC_BP (0x0 << 15)
1357 #define RT5616_IRQ_MB1_OC_NOR (0x1 << 15)
1358 #define RT5616_MB1_OC_STKY_MASK (0x1 << 11)
1360 #define RT5616_MB1_OC_STKY_DIS (0x0 << 11)
1361 #define RT5616_MB1_OC_STKY_EN (0x1 << 11)
1362 #define RT5616_MB1_OC_P_MASK (0x1 << 7)
1364 #define RT5616_MB1_OC_P_NOR (0x0 << 7)
1365 #define RT5616_MB1_OC_P_INV (0x1 << 7)
1366 #define RT5616_MB2_OC_P_MASK (0x1 << 6)
1367 #define RT5616_MB1_OC_CLR (0x1 << 3)
1369 #define RT5616_STA_GPIO8 (0x1)
1370 #define RT5616_STA_GPIO8_BIT 0
1372 /* Internal Status and GPIO status (0xbf) */
1373 #define RT5616_STA_JD3 (0x1 << 15)
1375 #define RT5616_STA_JD2 (0x1 << 14)
1377 #define RT5616_STA_JD1_2 (0x1 << 13)
1379 #define RT5616_STA_JD1_1 (0x1 << 12)
1381 #define RT5616_STA_GP7 (0x1 << 11)
1383 #define RT5616_STA_GP6 (0x1 << 10)
1385 #define RT5616_STA_GP5 (0x1 << 9)
1387 #define RT5616_STA_GP1 (0x1 << 8)
1389 #define RT5616_STA_GP2 (0x1 << 7)
1391 #define RT5616_STA_GP3 (0x1 << 6)
1393 #define RT5616_STA_GP4 (0x1 << 5)
1395 #define RT5616_STA_GP_JD (0x1 << 4)
1398 /* GPIO Control 1 (0xc0) */
1399 #define RT5616_GP1_PIN_MASK (0x1 << 15)
1401 #define RT5616_GP1_PIN_GPIO1 (0x0 << 15)
1402 #define RT5616_GP1_PIN_IRQ (0x1 << 15)
1403 #define RT5616_GP2_PIN_MASK (0x1 << 14)
1405 #define RT5616_GP2_PIN_GPIO2 (0x0 << 14)
1406 #define RT5616_GP2_PIN_DMIC1_SCL (0x1 << 14)
1407 #define RT5616_GPIO_M_MASK (0x1 << 9)
1409 #define RT5616_GPIO_M_FLT (0x0 << 9)
1410 #define RT5616_GPIO_M_PH (0x1 << 9)
1411 #define RT5616_I2S2_SEL_MASK (0x1 << 8)
1413 #define RT5616_I2S2_SEL_I2S (0x0 << 8)
1414 #define RT5616_I2S2_SEL_GPIO (0x1 << 8)
1415 #define RT5616_GP5_PIN_MASK (0x1 << 7)
1417 #define RT5616_GP5_PIN_GPIO5 (0x0 << 7)
1418 #define RT5616_GP5_PIN_IRQ (0x1 << 7)
1419 #define RT5616_GP6_PIN_MASK (0x1 << 6)
1421 #define RT5616_GP6_PIN_GPIO6 (0x0 << 6)
1422 #define RT5616_GP6_PIN_DMIC_SDA (0x1 << 6)
1423 #define RT5616_GP7_PIN_MASK (0x1 << 5)
1425 #define RT5616_GP7_PIN_GPIO7 (0x0 << 5)
1426 #define RT5616_GP7_PIN_IRQ (0x1 << 5)
1427 #define RT5616_GP8_PIN_MASK (0x1 << 4)
1429 #define RT5616_GP8_PIN_GPIO8 (0x0 << 4)
1430 #define RT5616_GP8_PIN_DMIC_SDA (0x1 << 4)
1431 #define RT5616_GPIO_PDM_SEL_MASK (0x1 << 3)
1433 #define RT5616_GPIO_PDM_SEL_GPIO (0x0 << 3)
1434 #define RT5616_GPIO_PDM_SEL_PDM (0x1 << 3)
1436 /* GPIO Control 2 (0xc1) */
1437 #define RT5616_GP5_DR_MASK (0x1 << 14)
1439 #define RT5616_GP5_DR_IN (0x0 << 14)
1440 #define RT5616_GP5_DR_OUT (0x1 << 14)
1441 #define RT5616_GP5_OUT_MASK (0x1 << 13)
1443 #define RT5616_GP5_OUT_LO (0x0 << 13)
1444 #define RT5616_GP5_OUT_HI (0x1 << 13)
1445 #define RT5616_GP5_P_MASK (0x1 << 12)
1447 #define RT5616_GP5_P_NOR (0x0 << 12)
1448 #define RT5616_GP5_P_INV (0x1 << 12)
1449 #define RT5616_GP4_DR_MASK (0x1 << 11)
1451 #define RT5616_GP4_DR_IN (0x0 << 11)
1452 #define RT5616_GP4_DR_OUT (0x1 << 11)
1453 #define RT5616_GP4_OUT_MASK (0x1 << 10)
1455 #define RT5616_GP4_OUT_LO (0x0 << 10)
1456 #define RT5616_GP4_OUT_HI (0x1 << 10)
1457 #define RT5616_GP4_P_MASK (0x1 << 9)
1459 #define RT5616_GP4_P_NOR (0x0 << 9)
1460 #define RT5616_GP4_P_INV (0x1 << 9)
1461 #define RT5616_GP3_DR_MASK (0x1 << 8)
1463 #define RT5616_GP3_DR_IN (0x0 << 8)
1464 #define RT5616_GP3_DR_OUT (0x1 << 8)
1465 #define RT5616_GP3_OUT_MASK (0x1 << 7)
1467 #define RT5616_GP3_OUT_LO (0x0 << 7)
1468 #define RT5616_GP3_OUT_HI (0x1 << 7)
1469 #define RT5616_GP3_P_MASK (0x1 << 6)
1471 #define RT5616_GP3_P_NOR (0x0 << 6)
1472 #define RT5616_GP3_P_INV (0x1 << 6)
1473 #define RT5616_GP2_DR_MASK (0x1 << 5)
1475 #define RT5616_GP2_DR_IN (0x0 << 5)
1476 #define RT5616_GP2_DR_OUT (0x1 << 5)
1477 #define RT5616_GP2_OUT_MASK (0x1 << 4)
1479 #define RT5616_GP2_OUT_LO (0x0 << 4)
1480 #define RT5616_GP2_OUT_HI (0x1 << 4)
1481 #define RT5616_GP2_P_MASK (0x1 << 3)
1483 #define RT5616_GP2_P_NOR (0x0 << 3)
1484 #define RT5616_GP2_P_INV (0x1 << 3)
1485 #define RT5616_GP1_DR_MASK (0x1 << 2)
1487 #define RT5616_GP1_DR_IN (0x0 << 2)
1488 #define RT5616_GP1_DR_OUT (0x1 << 2)
1489 #define RT5616_GP1_OUT_MASK (0x1 << 1)
1491 #define RT5616_GP1_OUT_LO (0x0 << 1)
1492 #define RT5616_GP1_OUT_HI (0x1 << 1)
1493 #define RT5616_GP1_P_MASK (0x1)
1494 #define RT5616_GP1_P_SFT 0
1495 #define RT5616_GP1_P_NOR (0x0)
1496 #define RT5616_GP1_P_INV (0x1)
1498 /* GPIO Control 3 (0xc2) */
1499 #define RT5616_GP8_DR_MASK (0x1 << 8)
1501 #define RT5616_GP8_DR_IN (0x0 << 8)
1502 #define RT5616_GP8_DR_OUT (0x1 << 8)
1503 #define RT5616_GP8_OUT_MASK (0x1 << 7)
1505 #define RT5616_GP8_OUT_LO (0x0 << 7)
1506 #define RT5616_GP8_OUT_HI (0x1 << 7)
1507 #define RT5616_GP8_P_MASK (0x1 << 6)
1509 #define RT5616_GP8_P_NOR (0x0 << 6)
1510 #define RT5616_GP8_P_INV (0x1 << 6)
1511 #define RT5616_GP7_DR_MASK (0x1 << 5)
1513 #define RT5616_GP7_DR_IN (0x0 << 5)
1514 #define RT5616_GP7_DR_OUT (0x1 << 5)
1515 #define RT5616_GP7_OUT_MASK (0x1 << 4)
1517 #define RT5616_GP7_OUT_LO (0x0 << 4)
1518 #define RT5616_GP7_OUT_HI (0x1 << 4)
1519 #define RT5616_GP7_P_MASK (0x1 << 3)
1521 #define RT5616_GP7_P_NOR (0x0 << 3)
1522 #define RT5616_GP7_P_INV (0x1 << 3)
1523 #define RT5616_GP6_DR_MASK (0x1 << 2)
1525 #define RT5616_GP6_DR_IN (0x0 << 2)
1526 #define RT5616_GP6_DR_OUT (0x1 << 2)
1527 #define RT5616_GP6_OUT_MASK (0x1 << 1)
1529 #define RT5616_GP6_OUT_LO (0x0 << 1)
1530 #define RT5616_GP6_OUT_HI (0x1 << 1)
1531 #define RT5616_GP6_P_MASK (0x1)
1532 #define RT5616_GP6_P_SFT 0
1533 #define RT5616_GP6_P_NOR (0x0)
1534 #define RT5616_GP6_P_INV (0x1)
1536 /* Scramble Control (0xce) */
1537 #define RT5616_SCB_SWAP_MASK (0x1 << 15)
1539 #define RT5616_SCB_SWAP_DIS (0x0 << 15)
1540 #define RT5616_SCB_SWAP_EN (0x1 << 15)
1541 #define RT5616_SCB_MASK (0x1 << 14)
1543 #define RT5616_SCB_DIS (0x0 << 14)
1544 #define RT5616_SCB_EN (0x1 << 14)
1546 /* Baseback Control (0xcf) */
1547 #define RT5616_BB_MASK (0x1 << 15)
1549 #define RT5616_BB_DIS (0x0 << 15)
1550 #define RT5616_BB_EN (0x1 << 15)
1551 #define RT5616_BB_CT_MASK (0x7 << 12)
1553 #define RT5616_BB_CT_A (0x0 << 12)
1554 #define RT5616_BB_CT_B (0x1 << 12)
1555 #define RT5616_BB_CT_C (0x2 << 12)
1556 #define RT5616_BB_CT_D (0x3 << 12)
1557 #define RT5616_M_BB_L_MASK (0x1 << 9)
1559 #define RT5616_M_BB_R_MASK (0x1 << 8)
1561 #define RT5616_M_BB_HPF_L_MASK (0x1 << 7)
1563 #define RT5616_M_BB_HPF_R_MASK (0x1 << 6)
1565 #define RT5616_G_BB_BST_MASK (0x3f)
1566 #define RT5616_G_BB_BST_SFT 0
1568 /* MP3 Plus Control 1 (0xd0) */
1569 #define RT5616_M_MP3_L_MASK (0x1 << 15)
1571 #define RT5616_M_MP3_R_MASK (0x1 << 14)
1573 #define RT5616_M_MP3_MASK (0x1 << 13)
1575 #define RT5616_M_MP3_DIS (0x0 << 13)
1576 #define RT5616_M_MP3_EN (0x1 << 13)
1577 #define RT5616_EG_MP3_MASK (0x1f << 8)
1579 #define RT5616_MP3_HLP_MASK (0x1 << 7)
1581 #define RT5616_MP3_HLP_DIS (0x0 << 7)
1582 #define RT5616_MP3_HLP_EN (0x1 << 7)
1583 #define RT5616_M_MP3_ORG_L_MASK (0x1 << 6)
1585 #define RT5616_M_MP3_ORG_R_MASK (0x1 << 5)
1588 /* MP3 Plus Control 2 (0xd1) */
1589 #define RT5616_MP3_WT_MASK (0x1 << 13)
1591 #define RT5616_MP3_WT_1_4 (0x0 << 13)
1592 #define RT5616_MP3_WT_1_2 (0x1 << 13)
1593 #define RT5616_OG_MP3_MASK (0x1f << 8)
1595 #define RT5616_HG_MP3_MASK (0x3f)
1596 #define RT5616_HG_MP3_SFT 0
1598 /* 3D HP Control 1 (0xd2) */
1599 #define RT5616_3D_CF_MASK (0x1 << 15)
1601 #define RT5616_3D_CF_DIS (0x0 << 15)
1602 #define RT5616_3D_CF_EN (0x1 << 15)
1603 #define RT5616_3D_HP_MASK (0x1 << 14)
1605 #define RT5616_3D_HP_DIS (0x0 << 14)
1606 #define RT5616_3D_HP_EN (0x1 << 14)
1607 #define RT5616_3D_BT_MASK (0x1 << 13)
1609 #define RT5616_3D_BT_DIS (0x0 << 13)
1610 #define RT5616_3D_BT_EN (0x1 << 13)
1611 #define RT5616_3D_1F_MIX_MASK (0x3 << 11)
1613 #define RT5616_3D_HP_M_MASK (0x1 << 10)
1615 #define RT5616_3D_HP_M_SUR (0x0 << 10)
1616 #define RT5616_3D_HP_M_FRO (0x1 << 10)
1617 #define RT5616_M_3D_HRTF_MASK (0x1 << 9)
1619 #define RT5616_M_3D_D2H_MASK (0x1 << 8)
1621 #define RT5616_M_3D_D2R_MASK (0x1 << 7)
1623 #define RT5616_M_3D_REVB_MASK (0x1 << 6)
1626 /* Adjustable high pass filter control 1 (0xd3) */
1627 #define RT5616_2ND_HPF_MASK (0x1 << 15)
1629 #define RT5616_2ND_HPF_DIS (0x0 << 15)
1630 #define RT5616_2ND_HPF_EN (0x1 << 15)
1631 #define RT5616_HPF_CF_L_MASK (0x7 << 12)
1633 #define RT5616_HPF_CF_R_MASK (0x7 << 8)
1635 #define RT5616_ZD_T_MASK (0x3 << 6)
1637 #define RT5616_ZD_F_MASK (0x3 << 4)
1639 #define RT5616_ZD_F_IM (0x0 << 4)
1640 #define RT5616_ZD_F_ZC_IM (0x1 << 4)
1641 #define RT5616_ZD_F_ZC_IOD (0x2 << 4)
1642 #define RT5616_ZD_F_UN (0x3 << 4)
1644 /* Adjustable high pass filter control 2 (0xd4) */
1645 #define RT5616_HPF_CF_L_NUM_MASK (0x3f << 8)
1647 #define RT5616_HPF_CF_R_NUM_MASK (0x3f)
1648 #define RT5616_HPF_CF_R_NUM_SFT 0
1650 /* HP calibration control and Amp detection (0xd6) */
1651 #define RT5616_SI_DAC_MASK (0x1 << 11)
1653 #define RT5616_SI_DAC_AUTO (0x0 << 11)
1654 #define RT5616_SI_DAC_TEST (0x1 << 11)
1655 #define RT5616_DC_CAL_M_MASK (0x1 << 10)
1657 #define RT5616_DC_CAL_M_NOR (0x0 << 10)
1658 #define RT5616_DC_CAL_M_CAL (0x1 << 10)
1659 #define RT5616_DC_CAL_MASK (0x1 << 9)
1661 #define RT5616_DC_CAL_DIS (0x0 << 9)
1662 #define RT5616_DC_CAL_EN (0x1 << 9)
1663 #define RT5616_HPD_RCV_MASK (0x7 << 6)
1665 #define RT5616_HPD_PS_MASK (0x1 << 5)
1667 #define RT5616_HPD_PS_DIS (0x0 << 5)
1668 #define RT5616_HPD_PS_EN (0x1 << 5)
1669 #define RT5616_CAL_M_MASK (0x1 << 4)
1671 #define RT5616_CAL_M_DEP (0x0 << 4)
1672 #define RT5616_CAL_M_CAL (0x1 << 4)
1673 #define RT5616_CAL_MASK (0x1 << 3)
1675 #define RT5616_CAL_DIS (0x0 << 3)
1676 #define RT5616_CAL_EN (0x1 << 3)
1677 #define RT5616_CAL_TEST_MASK (0x1 << 2)
1679 #define RT5616_CAL_TEST_DIS (0x0 << 2)
1680 #define RT5616_CAL_TEST_EN (0x1 << 2)
1681 #define RT5616_CAL_P_MASK (0x3)
1682 #define RT5616_CAL_P_SFT 0
1683 #define RT5616_CAL_P_NONE (0x0)
1684 #define RT5616_CAL_P_CAL (0x1)
1685 #define RT5616_CAL_P_DAC_CAL (0x2)
1687 /* Soft volume and zero cross control 1 (0xd9) */
1688 #define RT5616_SV_MASK (0x1 << 15)
1690 #define RT5616_SV_DIS (0x0 << 15)
1691 #define RT5616_SV_EN (0x1 << 15)
1692 #define RT5616_OUT_SV_MASK (0x1 << 13)
1694 #define RT5616_OUT_SV_DIS (0x0 << 13)
1695 #define RT5616_OUT_SV_EN (0x1 << 13)
1696 #define RT5616_HP_SV_MASK (0x1 << 12)
1698 #define RT5616_HP_SV_DIS (0x0 << 12)
1699 #define RT5616_HP_SV_EN (0x1 << 12)
1700 #define RT5616_ZCD_DIG_MASK (0x1 << 11)
1702 #define RT5616_ZCD_DIG_DIS (0x0 << 11)
1703 #define RT5616_ZCD_DIG_EN (0x1 << 11)
1704 #define RT5616_ZCD_MASK (0x1 << 10)
1706 #define RT5616_ZCD_PD (0x0 << 10)
1707 #define RT5616_ZCD_PU (0x1 << 10)
1708 #define RT5616_M_ZCD_MASK (0x3f << 4)
1710 #define RT5616_M_ZCD_OM_L (0x1 << 7)
1711 #define RT5616_M_ZCD_OM_R (0x1 << 6)
1712 #define RT5616_M_ZCD_RM_L (0x1 << 5)
1713 #define RT5616_M_ZCD_RM_R (0x1 << 4)
1714 #define RT5616_SV_DLY_MASK (0xf)
1715 #define RT5616_SV_DLY_SFT 0
1717 /* Soft volume and zero cross control 2 (0xda) */
1718 #define RT5616_ZCD_HP_MASK (0x1 << 15)
1720 #define RT5616_ZCD_HP_DIS (0x0 << 15)
1721 #define RT5616_ZCD_HP_EN (0x1 << 15)
1723 /* Digital Misc Control (0xfa) */
1724 #define RT5616_I2S2_MS_SP_MASK (0x1 << 8)
1726 #define RT5616_I2S2_MS_SP_64 (0x0 << 8)
1727 #define RT5616_I2S2_MS_SP_50 (0x1 << 8)
1728 #define RT5616_CLK_DET_EN (0x1 << 3)
1730 #define RT5616_AMP_DET_EN (0x1 << 1)
1732 #define RT5616_D_GATE_EN (0x1)
1733 #define RT5616_D_GATE_EN_SFT 0
1736 /* 3D Speaker Control (0x63) */
1737 #define RT5616_3D_SPK_MASK (0x1 << 15)
1739 #define RT5616_3D_SPK_DIS (0x0 << 15)
1740 #define RT5616_3D_SPK_EN (0x1 << 15)
1741 #define RT5616_3D_SPK_M_MASK (0x3 << 13)
1743 #define RT5616_3D_SPK_CG_MASK (0x1f << 8)
1745 #define RT5616_3D_SPK_SG_MASK (0x1f)
1746 #define RT5616_3D_SPK_SG_SFT 0
1748 /* Wind Noise Detection Control 1 (0x6c) */
1749 #define RT5616_WND_MASK (0x1 << 15)
1751 #define RT5616_WND_DIS (0x0 << 15)
1752 #define RT5616_WND_EN (0x1 << 15)
1754 /* Wind Noise Detection Control 2 (0x6d) */
1755 #define RT5616_WND_FC_NW_MASK (0x3f << 10)
1757 #define RT5616_WND_FC_WK_MASK (0x3f << 4)
1760 /* Wind Noise Detection Control 3 (0x6e) */
1761 #define RT5616_HPF_FC_MASK (0x3f << 6)
1763 #define RT5616_WND_FC_ST_MASK (0x3f)
1764 #define RT5616_WND_FC_ST_SFT 0
1766 /* Wind Noise Detection Control 4 (0x6f) */
1767 #define RT5616_WND_TH_LO_MASK (0x3ff)
1768 #define RT5616_WND_TH_LO_SFT 0
1770 /* Wind Noise Detection Control 5 (0x70) */
1771 #define RT5616_WND_TH_HI_MASK (0x3ff)
1772 #define RT5616_WND_TH_HI_SFT 0
1774 /* Wind Noise Detection Control 8 (0x73) */
1775 #define RT5616_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1777 #define RT5616_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1785 /* Dipole Speaker Interface (0x75) */
1786 #define RT5616_DP_ATT_MASK (0x3 << 14)
1788 #define RT5616_DP_SPK_MASK (0x1 << 10)
1790 #define RT5616_DP_SPK_DIS (0x0 << 10)
1791 #define RT5616_DP_SPK_EN (0x1 << 10)
1793 /* EQ Pre Volume Control (0xb3) */
1794 #define RT5616_EQ_PRE_VOL_MASK (0xffff)
1795 #define RT5616_EQ_PRE_VOL_SFT 0
1797 /* EQ Post Volume Control (0xb4) */
1798 #define RT5616_EQ_PST_VOL_MASK (0xffff)
1799 #define RT5616_EQ_PST_VOL_SFT 0