Lines Matching full:x1
155 #define RT5616_L_MUTE (0x1 << 15)
157 #define RT5616_VOL_L_MUTE (0x1 << 14)
159 #define RT5616_R_MUTE (0x1 << 7)
161 #define RT5616_VOL_R_MUTE (0x1 << 6)
169 #define RT5616_EN_DFO (0x1 << 15)
177 #define RT5616_IN_DF1 (0x1 << 7)
179 #define RT5616_IN_DF2 (0x1 << 6)
185 #define RT5616_INR_SEL_MASK (0x1 << 7)
188 #define RT5616_INR_SEL_MONON (0x1 << 7)
211 #define RT5616_M_MONO_ADC_L (0x1 << 15)
215 #define RT5616_M_MONO_ADC_R (0x1 << 7)
229 #define RT5616_M_STO1_ADC_L1 (0x1 << 14)
231 #define RT5616_M_STO1_ADC_R1 (0x1 << 6)
235 #define RT5616_M_ADCMIX_L (0x1 << 15)
237 #define RT5616_M_IF1_DAC_L (0x1 << 14)
239 #define RT5616_M_ADCMIX_R (0x1 << 7)
241 #define RT5616_M_IF1_DAC_R (0x1 << 6)
245 #define RT5616_M_DAC_L1_MIXL (0x1 << 14)
247 #define RT5616_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
249 #define RT5616_M_DAC_R1_MIXL (0x1 << 9)
251 #define RT5616_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
253 #define RT5616_M_DAC_R1_MIXR (0x1 << 6)
255 #define RT5616_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
257 #define RT5616_M_DAC_L1_MIXR (0x1 << 1)
259 #define RT5616_DAC_L1_STO_R_VOL_MASK (0x1)
263 #define RT5616_M_STO_DD_L1 (0x1 << 14)
265 #define RT5616_STO_DD_L1_VOL_MASK (0x1 << 13)
267 #define RT5616_M_STO_DD_L2 (0x1 << 12)
269 #define RT5616_STO_DD_L2_VOL_MASK (0x1 << 11)
271 #define RT5616_M_STO_DD_R2_L (0x1 << 10)
273 #define RT5616_STO_DD_R2_L_VOL_MASK (0x1 << 9)
275 #define RT5616_M_STO_DD_R1 (0x1 << 6)
277 #define RT5616_STO_DD_R1_VOL_MASK (0x1 << 5)
279 #define RT5616_M_STO_DD_R2 (0x1 << 4)
281 #define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
283 #define RT5616_M_STO_DD_L2_R (0x1 << 2)
285 #define RT5616_STO_DD_L2_R_VOL_MASK (0x1 << 1)
289 #define RT5616_M_STO_L_DAC_L (0x1 << 15)
291 #define RT5616_STO_L_DAC_L_VOL_MASK (0x1 << 14)
293 #define RT5616_M_DAC_L2_DAC_L (0x1 << 13)
295 #define RT5616_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
297 #define RT5616_M_STO_R_DAC_R (0x1 << 11)
299 #define RT5616_STO_R_DAC_R_VOL_MASK (0x1 << 10)
301 #define RT5616_M_DAC_R2_DAC_R (0x1 << 9)
303 #define RT5616_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
307 #define RT5616_RXDP_SRC_MASK (0x1 << 15)
310 #define RT5616_RXDP_SRC_DIV3 (0x1 << 15)
311 #define RT5616_TXDP_SRC_MASK (0x1 << 14)
314 #define RT5616_TXDP_SRC_DIV3 (0x1 << 14)
320 #define RT5616_DAC_L2_SEL_IF3 (0x1 << 14)
326 #define RT5616_DAC_R2_SEL_IF3 (0x1 << 12)
328 #define RT5616_IF2_ADC_L_SEL_MASK (0x1 << 11)
331 #define RT5616_IF2_ADC_L_SEL_PASS (0x1 << 11)
332 #define RT5616_IF2_ADC_R_SEL_MASK (0x1 << 10)
335 #define RT5616_IF2_ADC_R_SEL_PASS (0x1 << 10)
339 #define RT5616_RXDC_SEL_L2R (0x1 << 8)
345 #define RT5616_RXDP_SEL_L2R (0x1 << 6)
351 #define RT5616_TXDC_SEL_L2R (0x1 << 4)
357 #define RT5616_TXDP_SEL_L2R (0x1 << 2)
376 #define RT5616_M_IN2_L_RM_L (0x1 << 6)
378 #define RT5616_M_IN1_L_RM_L (0x1 << 5)
380 #define RT5616_M_BST3_RM_L (0x1 << 3)
382 #define RT5616_M_BST2_RM_L (0x1 << 2)
384 #define RT5616_M_BST1_RM_L (0x1 << 1)
386 #define RT5616_M_OM_L_RM_L (0x1)
404 #define RT5616_M_IN2_R_RM_R (0x1 << 6)
406 #define RT5616_M_IN1_R_RM_R (0x1 << 5)
408 #define RT5616_M_BST3_RM_R (0x1 << 3)
410 #define RT5616_M_BST2_RM_R (0x1 << 2)
412 #define RT5616_M_BST1_RM_R (0x1 << 1)
414 #define RT5616_M_OM_R_RM_R (0x1)
418 #define RT5616_M_DAC1_HM (0x1 << 14)
420 #define RT5616_M_HPVOL_HM (0x1 << 13)
422 #define RT5616_G_HPOMIX_MASK (0x1 << 12)
436 #define RT5616_M_RM_L_SM_L (0x1 << 5)
438 #define RT5616_M_IN_L_SM_L (0x1 << 4)
440 #define RT5616_M_DAC_L1_SM_L (0x1 << 3)
442 #define RT5616_M_DAC_L2_SM_L (0x1 << 2)
444 #define RT5616_M_OM_L_SM_L (0x1 << 1)
458 #define RT5616_M_RM_R_SM_R (0x1 << 5)
460 #define RT5616_M_IN_R_SM_R (0x1 << 4)
462 #define RT5616_M_DAC_R1_SM_R (0x1 << 3)
464 #define RT5616_M_DAC_R2_SM_R (0x1 << 2)
466 #define RT5616_M_OM_R_SM_R (0x1 << 1)
470 #define RT5616_M_DAC_R1_SPM_L (0x1 << 15)
472 #define RT5616_M_DAC_L1_SPM_L (0x1 << 14)
474 #define RT5616_M_SV_R_SPM_L (0x1 << 13)
476 #define RT5616_M_SV_L_SPM_L (0x1 << 12)
478 #define RT5616_M_BST1_SPM_L (0x1 << 11)
482 #define RT5616_M_DAC_R1_SPM_R (0x1 << 13)
484 #define RT5616_M_SV_R_SPM_R (0x1 << 12)
486 #define RT5616_M_BST1_SPM_R (0x1 << 11)
494 #define RT5616_M_DAC_R2_MM (0x1 << 15)
496 #define RT5616_M_DAC_L2_MM (0x1 << 14)
498 #define RT5616_M_OV_R_MM (0x1 << 13)
500 #define RT5616_M_OV_L_MM (0x1 << 12)
502 #define RT5616_M_BST1_MM (0x1 << 11)
504 #define RT5616_G_MONOMIX_MASK (0x1 << 10)
524 #define RT5616_M_IN2_L_OM_L (0x1 << 9)
526 #define RT5616_M_BST2_OM_L (0x1 << 6)
528 #define RT5616_M_BST1_OM_L (0x1 << 5)
530 #define RT5616_M_IN1_L_OM_L (0x1 << 4)
532 #define RT5616_M_RM_L_OM_L (0x1 << 3)
534 #define RT5616_M_DAC_L1_OM_L (0x1)
554 #define RT5616_M_IN2_R_OM_R (0x1 << 9)
556 #define RT5616_M_BST2_OM_R (0x1 << 6)
558 #define RT5616_M_BST1_OM_R (0x1 << 5)
560 #define RT5616_M_IN1_R_OM_R (0x1 << 4)
562 #define RT5616_M_RM_R_OM_R (0x1 << 3)
564 #define RT5616_M_DAC_R1_OM_R (0x1)
568 #define RT5616_M_DAC_L1_LM (0x1 << 15)
570 #define RT5616_M_DAC_R1_LM (0x1 << 14)
572 #define RT5616_M_OV_L_LM (0x1 << 13)
574 #define RT5616_M_OV_R_LM (0x1 << 12)
576 #define RT5616_G_LOUTMIX_MASK (0x1 << 11)
580 #define RT5616_PWR_I2S1 (0x1 << 15)
582 #define RT5616_PWR_I2S2 (0x1 << 14)
584 #define RT5616_PWR_DAC_L1 (0x1 << 12)
586 #define RT5616_PWR_DAC_R1 (0x1 << 11)
588 #define RT5616_PWR_ADC_L (0x1 << 2)
590 #define RT5616_PWR_ADC_R (0x1 << 1)
594 #define RT5616_PWR_ADC_STO1_F (0x1 << 15)
596 #define RT5616_PWR_DAC_STO1_F (0x1 << 11)
600 #define RT5616_PWR_VREF1 (0x1 << 15)
602 #define RT5616_PWR_FV1 (0x1 << 14)
604 #define RT5616_PWR_MB (0x1 << 13)
606 #define RT5616_PWR_LM (0x1 << 12)
608 #define RT5616_PWR_BG (0x1 << 11)
610 #define RT5616_PWR_HP_L (0x1 << 7)
612 #define RT5616_PWR_HP_R (0x1 << 6)
614 #define RT5616_PWR_HA (0x1 << 5)
616 #define RT5616_PWR_VREF2 (0x1 << 4)
618 #define RT5616_PWR_FV2 (0x1 << 3)
620 #define RT5616_PWR_LDO (0x1 << 2)
629 #define RT5616_PWR_BST1 (0x1 << 15)
631 #define RT5616_PWR_BST2 (0x1 << 14)
633 #define RT5616_PWR_MB1 (0x1 << 11)
635 #define RT5616_PWR_PLL (0x1 << 9)
637 #define RT5616_PWR_BST1_OP2 (0x1 << 5)
639 #define RT5616_PWR_BST2_OP2 (0x1 << 4)
641 #define RT5616_PWR_BST3_OP2 (0x1 << 3)
643 #define RT5616_PWR_JD_M (0x1 << 2)
645 #define RT5616_PWR_JD2 (0x1 << 1)
647 #define RT5616_PWR_JD3 (0x1)
651 #define RT5616_PWR_OM_L (0x1 << 15)
653 #define RT5616_PWR_OM_R (0x1 << 14)
655 #define RT5616_PWR_RM_L (0x1 << 11)
657 #define RT5616_PWR_RM_R (0x1 << 10)
661 #define RT5616_PWR_OV_L (0x1 << 13)
663 #define RT5616_PWR_OV_R (0x1 << 12)
665 #define RT5616_PWR_HV_L (0x1 << 11)
667 #define RT5616_PWR_HV_R (0x1 << 10)
669 #define RT5616_PWR_IN1_L (0x1 << 9)
671 #define RT5616_PWR_IN1_R (0x1 << 8)
673 #define RT5616_PWR_IN2_L (0x1 << 7)
675 #define RT5616_PWR_IN2_R (0x1 << 6)
679 #define RT5616_I2S_MS_MASK (0x1 << 15)
682 #define RT5616_I2S_MS_S (0x1 << 15)
686 #define RT5616_I2S_O_CP_U_LAW (0x1 << 10)
691 #define RT5616_I2S_I_CP_U_LAW (0x1 << 8)
693 #define RT5616_I2S_BP_MASK (0x1 << 7)
696 #define RT5616_I2S_BP_INV (0x1 << 7)
700 #define RT5616_I2S_DL_20 (0x1 << 2)
706 #define RT5616_I2S_DF_LEFT (0x1)
714 #define RT5616_I2S_PD1_2 (0x1 << 12)
721 #define RT5616_I2S_BCLK_MS2_MASK (0x1 << 11)
725 #define RT5616_DAC_OSR_64 (0x1 << 2)
731 #define RT5616_ADC_OSR_64 (0x1)
736 #define RT5616_DAHPF_EN (0x1 << 11)
738 #define RT5616_ADHPF_EN (0x1 << 10)
742 #define RT5616_TDM_INTEL_SEL_MASK (0x1 << 15)
745 #define RT5616_TDM_INTEL_SEL_50 (0x1 << 15)
746 #define RT5616_TDM_MODE_SEL_MASK (0x1 << 14)
749 #define RT5616_TDM_MODE_SEL_TDM (0x1 << 14)
753 #define RT5616_TDM_CH_NUM_SEL_4 (0x1 << 12)
759 #define RT5616_TDM_CH_LEN_SEL_20 (0x1 << 10)
762 #define RT5616_TDM_ADC_SEL_MASK (0x1 << 9)
765 #define RT5616_TDM_ADC_SEL_SWAP (0x1 << 9)
766 #define RT5616_TDM_ADC_START_SEL_MASK (0x1 << 8)
769 #define RT5616_TDM_ADC_START_SEL_SL4 (0x1 << 8)
773 #define RT5616_TDM_I2S_CH2_SEL_RL (0x1 << 6)
779 #define RT5616_TDM_I2S_CH4_SEL_RL (0x1 << 4)
785 #define RT5616_TDM_I2S_CH6_SEL_RL (0x1 << 2)
791 #define RT5616_TDM_I2S_CH8_SEL_RL (0x1)
796 #define RT5616_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
799 #define RT5616_TDM_LRCK_POL_SEL_INV (0x1 << 15)
800 #define RT5616_TDM_CH_VAL_SEL_MASK (0x1 << 14)
803 #define RT5616_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
804 #define RT5616_TDM_CH_VAL_EN (0x1 << 13)
806 #define RT5616_TDM_LPBK_EN (0x1 << 12)
808 #define RT5616_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
811 #define RT5616_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
812 #define RT5616_TDM_END_EDGE_SEL_MASK (0x1 << 10)
815 #define RT5616_TDM_END_EDGE_SEL_NEG (0x1 << 10)
816 #define RT5616_TDM_END_EDGE_EN (0x1 << 9)
818 #define RT5616_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
821 #define RT5616_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
822 #define RT5616_M_TDM2_L (0x1 << 7)
824 #define RT5616_M_TDM2_R (0x1 << 6)
826 #define RT5616_M_TDM4_L (0x1 << 5)
828 #define RT5616_M_TDM4_R (0x1 << 4)
835 #define RT5616_SCLK_SRC_PLL1 (0x1 << 14)
839 #define RT5616_PLL1_SRC_BCLK1 (0x1 << 12)
841 #define RT5616_PLL1_PD_MASK (0x1 << 3)
844 #define RT5616_PLL1_PD_2 (0x1 << 3)
860 #define RT5616_PLL_M_BP (0x1 << 11)
864 #define RT5616_STO1_T_MASK (0x1 << 15)
867 #define RT5616_STO1_T_LRCK1 (0x1 << 15)
868 #define RT5616_STO2_T_MASK (0x1 << 12)
871 #define RT5616_STO2_T_LRCK2 (0x1 << 12)
872 #define RT5616_ASRC2_REF_MASK (0x1 << 11)
875 #define RT5616_ASRC2_REF_LRCK1 (0x1 << 11)
876 #define RT5616_DMIC_1_M_MASK (0x1 << 9)
879 #define RT5616_DMIC_1_M_ASYN (0x1 << 9)
882 #define RT5616_STO1_ASRC_EN (0x1 << 15)
884 #define RT5616_STO2_ASRC_EN (0x1 << 14)
886 #define RT5616_STO1_DAC_M_MASK (0x1 << 13)
889 #define RT5616_STO1_DAC_M_ASRC (0x1 << 13)
890 #define RT5616_STO2_DAC_M_MASK (0x1 << 12)
893 #define RT5616_STO2_DAC_M_ASRC (0x1 << 12)
894 #define RT5616_ADC_M_MASK (0x1 << 11)
897 #define RT5616_ADC_M_ASRC (0x1 << 11)
898 #define RT5616_I2S1_R_D_MASK (0x1 << 4)
901 #define RT5616_I2S1_R_D_EN (0x1 << 4)
902 #define RT5616_I2S2_R_D_MASK (0x1 << 3)
905 #define RT5616_I2S2_R_D_EN (0x1 << 3)
909 #define RT5616_PRE_SCLK_1024 (0x1)
917 #define RT5616_G_ASRC_LP_MASK (0x1 << 3)
919 #define RT5616_ASRC_LP_F_M (0x1 << 2)
922 #define RT5616_ASRC_LP_F_SB (0x1 << 2)
926 #define RT5616_FTK_PH_DET_DIV2 (0x1)
943 #define RT5616_HP_OVCD_MASK (0x1 << 10)
946 #define RT5616_HP_OVCD_EN (0x1 << 10)
950 #define RT5616_HP_OC_TH_105 (0x1 << 8)
955 #define RT5616_SMT_TRIG_MASK (0x1 << 15)
958 #define RT5616_SMT_TRIG_EN (0x1 << 15)
959 #define RT5616_HP_L_SMT_MASK (0x1 << 9)
962 #define RT5616_HP_L_SMT_EN (0x1 << 9)
963 #define RT5616_HP_R_SMT_MASK (0x1 << 8)
966 #define RT5616_HP_R_SMT_EN (0x1 << 8)
967 #define RT5616_HP_CD_PD_MASK (0x1 << 7)
970 #define RT5616_HP_CD_PD_EN (0x1 << 7)
971 #define RT5616_RSTN_MASK (0x1 << 6)
974 #define RT5616_RSTN_EN (0x1 << 6)
975 #define RT5616_RSTP_MASK (0x1 << 5)
978 #define RT5616_RSTP_EN (0x1 << 5)
979 #define RT5616_HP_CO_MASK (0x1 << 4)
982 #define RT5616_HP_CO_EN (0x1 << 4)
983 #define RT5616_HP_CP_MASK (0x1 << 3)
986 #define RT5616_HP_CP_PU (0x1 << 3)
987 #define RT5616_HP_SG_MASK (0x1 << 2)
990 #define RT5616_HP_SG_EN (0x1 << 2)
991 #define RT5616_HP_DP_MASK (0x1 << 1)
994 #define RT5616_HP_DP_PU (0x1 << 1)
995 #define RT5616_HP_CB_MASK (0x1)
998 #define RT5616_HP_CB_PU (0x1)
1001 #define RT5616_DEPOP_MASK (0x1 << 13)
1004 #define RT5616_DEPOP_MAN (0x1 << 13)
1005 #define RT5616_RAMP_MASK (0x1 << 12)
1008 #define RT5616_RAMP_EN (0x1 << 12)
1009 #define RT5616_BPS_MASK (0x1 << 11)
1012 #define RT5616_BPS_EN (0x1 << 11)
1013 #define RT5616_FAST_UPDN_MASK (0x1 << 10)
1016 #define RT5616_FAST_UPDN_EN (0x1 << 10)
1020 #define RT5616_MRES_25MO (0x1 << 8)
1023 #define RT5616_VLO_MASK (0x1 << 7)
1026 #define RT5616_VLO_32V (0x1 << 7)
1027 #define RT5616_DIG_DP_MASK (0x1 << 6)
1030 #define RT5616_DIG_DP_EN (0x1 << 6)
1053 #define RT5616_OSW_L_MASK (0x1 << 11)
1056 #define RT5616_OSW_L_EN (0x1 << 11)
1057 #define RT5616_OSW_R_MASK (0x1 << 10)
1060 #define RT5616_OSW_R_EN (0x1 << 10)
1064 #define RT5616_PM_HP_MV (0x1 << 8)
1069 #define RT5616_IB_HP_25IL (0x1 << 6)
1074 #define RT5616_MIC1_BS_MASK (0x1 << 15)
1077 #define RT5616_MIC1_BS_75AV (0x1 << 15)
1078 #define RT5616_MIC1_CLK_MASK (0x1 << 13)
1081 #define RT5616_MIC1_CLK_EN (0x1 << 13)
1082 #define RT5616_MIC1_OVCD_MASK (0x1 << 11)
1085 #define RT5616_MIC1_OVCD_EN (0x1 << 11)
1089 #define RT5616_MIC1_OVTH_1500UA (0x1 << 9)
1091 #define RT5616_PWR_MB_MASK (0x1 << 5)
1094 #define RT5616_PWR_MB_PU (0x1 << 5)
1095 #define RT5616_PWR_CLK12M_MASK (0x1 << 4)
1098 #define RT5616_PWR_CLK12M_PU (0x1 << 4)
1103 #define RT5616_JD_PU (0x1 << 11)
1105 #define RT5616_JD_PD (0x1 << 10)
1110 #define RT5616_JD_MODE_SEL_M1 (0x1 << 8)
1114 #define RT5616_JD_M_PU (0x1 << 3)
1116 #define RT5616_JD_M_PD (0x1 << 2)
1121 #define RT5616_JD_M_MODE_SEL_M1 (0x1)
1129 #define RT5616_EQ_SRC_MASK (0x1 << 15)
1132 #define RT5616_EQ_SRC_ADC (0x1 << 15)
1133 #define RT5616_EQ_UPD (0x1 << 14)
1135 #define RT5616_EQ_CD_MASK (0x1 << 13)
1138 #define RT5616_EQ_CD_EN (0x1 << 13)
1142 #define RT5616_EQ_DITH_LSB (0x1 << 8)
1145 #define RT5616_EQ_CD_F (0x1 << 7)
1147 #define RT5616_EQ_STA_HP2 (0x1 << 6)
1149 #define RT5616_EQ_STA_HP1 (0x1 << 5)
1151 #define RT5616_EQ_STA_BP4 (0x1 << 4)
1153 #define RT5616_EQ_STA_BP3 (0x1 << 3)
1155 #define RT5616_EQ_STA_BP2 (0x1 << 2)
1157 #define RT5616_EQ_STA_BP1 (0x1 << 1)
1159 #define RT5616_EQ_STA_LP (0x1)
1163 #define RT5616_EQ_HPF1_M_MASK (0x1 << 8)
1166 #define RT5616_EQ_HPF1_M_1ST (0x1 << 8)
1167 #define RT5616_EQ_LPF1_M_MASK (0x1 << 7)
1170 #define RT5616_EQ_LPF1_M_1ST (0x1 << 7)
1171 #define RT5616_EQ_HPF2_MASK (0x1 << 6)
1174 #define RT5616_EQ_HPF2_EN (0x1 << 6)
1175 #define RT5616_EQ_HPF1_MASK (0x1 << 5)
1178 #define RT5616_EQ_HPF1_EN (0x1 << 5)
1179 #define RT5616_EQ_BPF4_MASK (0x1 << 4)
1182 #define RT5616_EQ_BPF4_EN (0x1 << 4)
1183 #define RT5616_EQ_BPF3_MASK (0x1 << 3)
1186 #define RT5616_EQ_BPF3_EN (0x1 << 3)
1187 #define RT5616_EQ_BPF2_MASK (0x1 << 2)
1190 #define RT5616_EQ_BPF2_EN (0x1 << 2)
1191 #define RT5616_EQ_BPF1_MASK (0x1 << 1)
1194 #define RT5616_EQ_BPF1_EN (0x1 << 1)
1195 #define RT5616_EQ_LPF_MASK (0x1)
1198 #define RT5616_EQ_LPF_EN (0x1)
1202 #define RT5616_MT_MASK (0x1 << 15)
1205 #define RT5616_MT_EN (0x1 << 15)
1208 #define RT5616_DRC_AGC_P_MASK (0x1 << 15)
1211 #define RT5616_DRC_AGC_P_ADC (0x1 << 15)
1212 #define RT5616_DRC_AGC_MASK (0x1 << 14)
1215 #define RT5616_DRC_AGC_EN (0x1 << 14)
1216 #define RT5616_DRC_AGC_UPD (0x1 << 13)
1222 #define RT5616_DRC_AGC_R_48K (0x1 << 5)
1234 #define RT5616_DRC_AGC_CP_MASK (0x1 << 7)
1237 #define RT5616_DRC_AGC_CP_EN (0x1 << 7)
1241 #define RT5616_DRC_AGC_CPR_1_2 (0x1 << 5)
1252 #define RT5616_DRC_AGC_NG_MASK (0x1 << 6)
1255 #define RT5616_DRC_AGC_NG_EN (0x1 << 6)
1256 #define RT5616_DRC_AGC_NGH_MASK (0x1 << 5)
1259 #define RT5616_DRC_AGC_NGH_EN (0x1 << 5)
1267 #define RT5616_JD_GPIO1 (0x1 << 13)
1273 #define RT5616_JD_HP_MASK (0x1 << 11)
1276 #define RT5616_JD_HP_EN (0x1 << 11)
1277 #define RT5616_JD_HP_TRG_MASK (0x1 << 10)
1280 #define RT5616_JD_HP_TRG_HI (0x1 << 10)
1281 #define RT5616_JD_SPL_MASK (0x1 << 9)
1284 #define RT5616_JD_SPL_EN (0x1 << 9)
1285 #define RT5616_JD_SPL_TRG_MASK (0x1 << 8)
1288 #define RT5616_JD_SPL_TRG_HI (0x1 << 8)
1289 #define RT5616_JD_SPR_MASK (0x1 << 7)
1292 #define RT5616_JD_SPR_EN (0x1 << 7)
1293 #define RT5616_JD_SPR_TRG_MASK (0x1 << 6)
1296 #define RT5616_JD_SPR_TRG_HI (0x1 << 6)
1297 #define RT5616_JD_LO_MASK (0x1 << 3)
1300 #define RT5616_JD_LO_EN (0x1 << 3)
1301 #define RT5616_JD_LO_TRG_MASK (0x1 << 2)
1304 #define RT5616_JD_LO_TRG_HI (0x1 << 2)
1310 #define RT5616_JD_TRG_SEL_JD1_1 (0x1 << 9)
1314 #define RT5616_JD3_IRQ_EN (0x1 << 8)
1316 #define RT5616_JD3_EN_STKY (0x1 << 7)
1318 #define RT5616_JD3_INV (0x1 << 6)
1322 #define RT5616_IRQ_JD_MASK (0x1 << 15)
1325 #define RT5616_IRQ_JD_NOR (0x1 << 15)
1326 #define RT5616_JD_STKY_MASK (0x1 << 13)
1329 #define RT5616_JD_STKY_EN (0x1 << 13)
1330 #define RT5616_JD_P_MASK (0x1 << 11)
1333 #define RT5616_JD_P_INV (0x1 << 11)
1334 #define RT5616_JD1_1_IRQ_EN (0x1 << 9)
1336 #define RT5616_JD1_1_EN_STKY (0x1 << 8)
1338 #define RT5616_JD1_1_INV (0x1 << 7)
1340 #define RT5616_JD1_2_IRQ_EN (0x1 << 6)
1342 #define RT5616_JD1_2_EN_STKY (0x1 << 5)
1344 #define RT5616_JD1_2_INV (0x1 << 4)
1346 #define RT5616_JD2_IRQ_EN (0x1 << 3)
1348 #define RT5616_JD2_EN_STKY (0x1 << 2)
1350 #define RT5616_JD2_INV (0x1 << 1)
1354 #define RT5616_IRQ_MB1_OC_MASK (0x1 << 15)
1357 #define RT5616_IRQ_MB1_OC_NOR (0x1 << 15)
1358 #define RT5616_MB1_OC_STKY_MASK (0x1 << 11)
1361 #define RT5616_MB1_OC_STKY_EN (0x1 << 11)
1362 #define RT5616_MB1_OC_P_MASK (0x1 << 7)
1365 #define RT5616_MB1_OC_P_INV (0x1 << 7)
1366 #define RT5616_MB2_OC_P_MASK (0x1 << 6)
1367 #define RT5616_MB1_OC_CLR (0x1 << 3)
1369 #define RT5616_STA_GPIO8 (0x1)
1373 #define RT5616_STA_JD3 (0x1 << 15)
1375 #define RT5616_STA_JD2 (0x1 << 14)
1377 #define RT5616_STA_JD1_2 (0x1 << 13)
1379 #define RT5616_STA_JD1_1 (0x1 << 12)
1381 #define RT5616_STA_GP7 (0x1 << 11)
1383 #define RT5616_STA_GP6 (0x1 << 10)
1385 #define RT5616_STA_GP5 (0x1 << 9)
1387 #define RT5616_STA_GP1 (0x1 << 8)
1389 #define RT5616_STA_GP2 (0x1 << 7)
1391 #define RT5616_STA_GP3 (0x1 << 6)
1393 #define RT5616_STA_GP4 (0x1 << 5)
1395 #define RT5616_STA_GP_JD (0x1 << 4)
1399 #define RT5616_GP1_PIN_MASK (0x1 << 15)
1402 #define RT5616_GP1_PIN_IRQ (0x1 << 15)
1403 #define RT5616_GP2_PIN_MASK (0x1 << 14)
1406 #define RT5616_GP2_PIN_DMIC1_SCL (0x1 << 14)
1407 #define RT5616_GPIO_M_MASK (0x1 << 9)
1410 #define RT5616_GPIO_M_PH (0x1 << 9)
1411 #define RT5616_I2S2_SEL_MASK (0x1 << 8)
1414 #define RT5616_I2S2_SEL_GPIO (0x1 << 8)
1415 #define RT5616_GP5_PIN_MASK (0x1 << 7)
1418 #define RT5616_GP5_PIN_IRQ (0x1 << 7)
1419 #define RT5616_GP6_PIN_MASK (0x1 << 6)
1422 #define RT5616_GP6_PIN_DMIC_SDA (0x1 << 6)
1423 #define RT5616_GP7_PIN_MASK (0x1 << 5)
1426 #define RT5616_GP7_PIN_IRQ (0x1 << 5)
1427 #define RT5616_GP8_PIN_MASK (0x1 << 4)
1430 #define RT5616_GP8_PIN_DMIC_SDA (0x1 << 4)
1431 #define RT5616_GPIO_PDM_SEL_MASK (0x1 << 3)
1434 #define RT5616_GPIO_PDM_SEL_PDM (0x1 << 3)
1437 #define RT5616_GP5_DR_MASK (0x1 << 14)
1440 #define RT5616_GP5_DR_OUT (0x1 << 14)
1441 #define RT5616_GP5_OUT_MASK (0x1 << 13)
1444 #define RT5616_GP5_OUT_HI (0x1 << 13)
1445 #define RT5616_GP5_P_MASK (0x1 << 12)
1448 #define RT5616_GP5_P_INV (0x1 << 12)
1449 #define RT5616_GP4_DR_MASK (0x1 << 11)
1452 #define RT5616_GP4_DR_OUT (0x1 << 11)
1453 #define RT5616_GP4_OUT_MASK (0x1 << 10)
1456 #define RT5616_GP4_OUT_HI (0x1 << 10)
1457 #define RT5616_GP4_P_MASK (0x1 << 9)
1460 #define RT5616_GP4_P_INV (0x1 << 9)
1461 #define RT5616_GP3_DR_MASK (0x1 << 8)
1464 #define RT5616_GP3_DR_OUT (0x1 << 8)
1465 #define RT5616_GP3_OUT_MASK (0x1 << 7)
1468 #define RT5616_GP3_OUT_HI (0x1 << 7)
1469 #define RT5616_GP3_P_MASK (0x1 << 6)
1472 #define RT5616_GP3_P_INV (0x1 << 6)
1473 #define RT5616_GP2_DR_MASK (0x1 << 5)
1476 #define RT5616_GP2_DR_OUT (0x1 << 5)
1477 #define RT5616_GP2_OUT_MASK (0x1 << 4)
1480 #define RT5616_GP2_OUT_HI (0x1 << 4)
1481 #define RT5616_GP2_P_MASK (0x1 << 3)
1484 #define RT5616_GP2_P_INV (0x1 << 3)
1485 #define RT5616_GP1_DR_MASK (0x1 << 2)
1488 #define RT5616_GP1_DR_OUT (0x1 << 2)
1489 #define RT5616_GP1_OUT_MASK (0x1 << 1)
1492 #define RT5616_GP1_OUT_HI (0x1 << 1)
1493 #define RT5616_GP1_P_MASK (0x1)
1496 #define RT5616_GP1_P_INV (0x1)
1499 #define RT5616_GP8_DR_MASK (0x1 << 8)
1502 #define RT5616_GP8_DR_OUT (0x1 << 8)
1503 #define RT5616_GP8_OUT_MASK (0x1 << 7)
1506 #define RT5616_GP8_OUT_HI (0x1 << 7)
1507 #define RT5616_GP8_P_MASK (0x1 << 6)
1510 #define RT5616_GP8_P_INV (0x1 << 6)
1511 #define RT5616_GP7_DR_MASK (0x1 << 5)
1514 #define RT5616_GP7_DR_OUT (0x1 << 5)
1515 #define RT5616_GP7_OUT_MASK (0x1 << 4)
1518 #define RT5616_GP7_OUT_HI (0x1 << 4)
1519 #define RT5616_GP7_P_MASK (0x1 << 3)
1522 #define RT5616_GP7_P_INV (0x1 << 3)
1523 #define RT5616_GP6_DR_MASK (0x1 << 2)
1526 #define RT5616_GP6_DR_OUT (0x1 << 2)
1527 #define RT5616_GP6_OUT_MASK (0x1 << 1)
1530 #define RT5616_GP6_OUT_HI (0x1 << 1)
1531 #define RT5616_GP6_P_MASK (0x1)
1534 #define RT5616_GP6_P_INV (0x1)
1537 #define RT5616_SCB_SWAP_MASK (0x1 << 15)
1540 #define RT5616_SCB_SWAP_EN (0x1 << 15)
1541 #define RT5616_SCB_MASK (0x1 << 14)
1544 #define RT5616_SCB_EN (0x1 << 14)
1547 #define RT5616_BB_MASK (0x1 << 15)
1550 #define RT5616_BB_EN (0x1 << 15)
1554 #define RT5616_BB_CT_B (0x1 << 12)
1557 #define RT5616_M_BB_L_MASK (0x1 << 9)
1559 #define RT5616_M_BB_R_MASK (0x1 << 8)
1561 #define RT5616_M_BB_HPF_L_MASK (0x1 << 7)
1563 #define RT5616_M_BB_HPF_R_MASK (0x1 << 6)
1569 #define RT5616_M_MP3_L_MASK (0x1 << 15)
1571 #define RT5616_M_MP3_R_MASK (0x1 << 14)
1573 #define RT5616_M_MP3_MASK (0x1 << 13)
1576 #define RT5616_M_MP3_EN (0x1 << 13)
1579 #define RT5616_MP3_HLP_MASK (0x1 << 7)
1582 #define RT5616_MP3_HLP_EN (0x1 << 7)
1583 #define RT5616_M_MP3_ORG_L_MASK (0x1 << 6)
1585 #define RT5616_M_MP3_ORG_R_MASK (0x1 << 5)
1589 #define RT5616_MP3_WT_MASK (0x1 << 13)
1592 #define RT5616_MP3_WT_1_2 (0x1 << 13)
1599 #define RT5616_3D_CF_MASK (0x1 << 15)
1602 #define RT5616_3D_CF_EN (0x1 << 15)
1603 #define RT5616_3D_HP_MASK (0x1 << 14)
1606 #define RT5616_3D_HP_EN (0x1 << 14)
1607 #define RT5616_3D_BT_MASK (0x1 << 13)
1610 #define RT5616_3D_BT_EN (0x1 << 13)
1613 #define RT5616_3D_HP_M_MASK (0x1 << 10)
1616 #define RT5616_3D_HP_M_FRO (0x1 << 10)
1617 #define RT5616_M_3D_HRTF_MASK (0x1 << 9)
1619 #define RT5616_M_3D_D2H_MASK (0x1 << 8)
1621 #define RT5616_M_3D_D2R_MASK (0x1 << 7)
1623 #define RT5616_M_3D_REVB_MASK (0x1 << 6)
1627 #define RT5616_2ND_HPF_MASK (0x1 << 15)
1630 #define RT5616_2ND_HPF_EN (0x1 << 15)
1640 #define RT5616_ZD_F_ZC_IM (0x1 << 4)
1651 #define RT5616_SI_DAC_MASK (0x1 << 11)
1654 #define RT5616_SI_DAC_TEST (0x1 << 11)
1655 #define RT5616_DC_CAL_M_MASK (0x1 << 10)
1658 #define RT5616_DC_CAL_M_CAL (0x1 << 10)
1659 #define RT5616_DC_CAL_MASK (0x1 << 9)
1662 #define RT5616_DC_CAL_EN (0x1 << 9)
1665 #define RT5616_HPD_PS_MASK (0x1 << 5)
1668 #define RT5616_HPD_PS_EN (0x1 << 5)
1669 #define RT5616_CAL_M_MASK (0x1 << 4)
1672 #define RT5616_CAL_M_CAL (0x1 << 4)
1673 #define RT5616_CAL_MASK (0x1 << 3)
1676 #define RT5616_CAL_EN (0x1 << 3)
1677 #define RT5616_CAL_TEST_MASK (0x1 << 2)
1680 #define RT5616_CAL_TEST_EN (0x1 << 2)
1684 #define RT5616_CAL_P_CAL (0x1)
1688 #define RT5616_SV_MASK (0x1 << 15)
1691 #define RT5616_SV_EN (0x1 << 15)
1692 #define RT5616_OUT_SV_MASK (0x1 << 13)
1695 #define RT5616_OUT_SV_EN (0x1 << 13)
1696 #define RT5616_HP_SV_MASK (0x1 << 12)
1699 #define RT5616_HP_SV_EN (0x1 << 12)
1700 #define RT5616_ZCD_DIG_MASK (0x1 << 11)
1703 #define RT5616_ZCD_DIG_EN (0x1 << 11)
1704 #define RT5616_ZCD_MASK (0x1 << 10)
1707 #define RT5616_ZCD_PU (0x1 << 10)
1710 #define RT5616_M_ZCD_OM_L (0x1 << 7)
1711 #define RT5616_M_ZCD_OM_R (0x1 << 6)
1712 #define RT5616_M_ZCD_RM_L (0x1 << 5)
1713 #define RT5616_M_ZCD_RM_R (0x1 << 4)
1718 #define RT5616_ZCD_HP_MASK (0x1 << 15)
1721 #define RT5616_ZCD_HP_EN (0x1 << 15)
1724 #define RT5616_I2S2_MS_SP_MASK (0x1 << 8)
1727 #define RT5616_I2S2_MS_SP_50 (0x1 << 8)
1728 #define RT5616_CLK_DET_EN (0x1 << 3)
1730 #define RT5616_AMP_DET_EN (0x1 << 1)
1732 #define RT5616_D_GATE_EN (0x1)
1737 #define RT5616_3D_SPK_MASK (0x1 << 15)
1740 #define RT5616_3D_SPK_EN (0x1 << 15)
1749 #define RT5616_WND_MASK (0x1 << 15)
1752 #define RT5616_WND_EN (0x1 << 15)
1775 #define RT5616_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1777 #define RT5616_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1788 #define RT5616_DP_SPK_MASK (0x1 << 10)
1791 #define RT5616_DP_SPK_EN (0x1 << 10)