Lines Matching +full:10 +full:- +full:11
2 * rt5640.h -- RT5640 ALSA SoC audio driver
17 #include <dt-bindings/sound/rt5640.h>
24 /* I/O - Output */
29 /* I/O - Input */
33 /* I/O - ADC/DAC/DMIC */
40 /* Mixer - D-D */
50 /* Mixer - ADC */
55 /* Mixer - DAC */
80 /* Format - ADC/DAC */
86 /* Function - Analog */
104 /* Function - Digital */
263 #define RT5640_ADC_COMP_MASK (0x3 << 10)
264 #define RT5640_ADC_COMP_SFT 10
275 #define RT5640_ADC_2_SRC_MASK (0x3 << 10)
276 #define RT5640_ADC_2_SRC_SFT 10
277 #define RT5640_ADC_2_SRC_DMIC1 (0x0 << 10)
278 #define RT5640_ADC_2_SRC_DMIC2 (0x1 << 10)
279 #define RT5640_ADC_2_SRC_DACMIX (0x2 << 10)
294 #define RT5640_MONO_ADC_L2_SRC_MASK (0x3 << 10)
295 #define RT5640_MONO_ADC_L2_SRC_SFT 10
296 #define RT5640_MONO_ADC_L2_SRC_DMIC_L1 (0x0 << 10)
297 #define RT5640_MONO_ADC_L2_SRC_DMIC_L2 (0x1 << 10)
298 #define RT5640_MONO_ADC_L2_SRC_DACMIXL (0x2 << 10)
330 #define RT5640_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
331 #define RT5640_DAC_L2_STO_L_VOL_SFT 11
332 #define RT5640_M_ANC_DAC_L (0x1 << 10)
333 #define RT5640_M_ANC_DAC_L_SFT 10
352 #define RT5640_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
353 #define RT5640_DAC_L2_MONO_L_VOL_SFT 11
354 #define RT5640_M_DAC_R2_MONO_L (0x1 << 10)
355 #define RT5640_M_DAC_R2_MONO_L_SFT 10
380 #define RT5640_M_STO_R_DAC_R (0x1 << 11)
381 #define RT5640_M_STO_R_DAC_R_SFT 11
382 #define RT5640_STO_R_DAC_R_VOL_MASK (0x1 << 10)
383 #define RT5640_STO_R_DAC_R_VOL_SFT 10
411 #define RT5640_IF2_ADC_L_SEL_MASK (0x1 << 11)
412 #define RT5640_IF2_ADC_L_SEL_SFT 11
413 #define RT5640_IF2_ADC_L_SEL_TXDP (0x0 << 11)
414 #define RT5640_IF2_ADC_L_SEL_PASS (0x1 << 11)
415 #define RT5640_IF2_ADC_R_SEL_MASK (0x1 << 10)
416 #define RT5640_IF2_ADC_R_SEL_SFT 10
417 #define RT5640_IF2_ADC_R_SEL_TXDP (0x0 << 10)
418 #define RT5640_IF2_ADC_R_SEL_PASS (0x1 << 10)
457 #define RT5640_IF2_DAC_SEL_MASK (0x3 << 10)
458 #define RT5640_IF2_DAC_SEL_SFT 10
459 #define RT5640_IF2_DAC_SEL_NOR (0x0 << 10)
460 #define RT5640_IF2_DAC_SEL_SWAP (0x1 << 10)
461 #define RT5640_IF2_DAC_SEL_L2R (0x2 << 10)
462 #define RT5640_IF2_DAC_SEL_R2L (0x3 << 10)
485 #define RT5640_G_IN_L_RM_L_MASK (0x7 << 10)
486 #define RT5640_G_IN_L_RM_L_SFT 10
497 #define RT5640_G_OM_L_RM_L_MASK (0x7 << 10)
498 #define RT5640_G_OM_L_RM_L_SFT 10
517 #define RT5640_G_IN_R_RM_R_MASK (0x7 << 10)
518 #define RT5640_G_IN_R_RM_R_SFT 10
529 #define RT5640_G_OM_R_RM_R_MASK (0x7 << 10)
530 #define RT5640_G_OM_R_RM_R_SFT 10
561 #define RT5640_G_DAC_L1_SM_L_MASK (0x3 << 10)
562 #define RT5640_G_DAC_L1_SM_L_SFT 10
583 #define RT5640_G_DAC_R1_SM_R_MASK (0x3 << 10)
584 #define RT5640_G_DAC_R1_SM_R_SFT 10
609 #define RT5640_M_BST1_SPM_L (0x1 << 11)
610 #define RT5640_M_BST1_SPM_L_SFT 11
617 #define RT5640_M_BST1_SPM_R (0x1 << 11)
618 #define RT5640_M_BST1_SPM_R_SFT 11
633 #define RT5640_M_BST1_MM (0x1 << 11)
634 #define RT5640_M_BST1_MM_SFT 11
635 #define RT5640_G_MONOMIX_MASK (0x1 << 10)
636 #define RT5640_G_MONOMIX_SFT 10
641 #define RT5640_G_BST2_OM_L_MASK (0x7 << 10)
642 #define RT5640_G_BST2_OM_L_SFT 10
653 #define RT5640_G_DAC_L2_OM_L_MASK (0x7 << 10)
654 #define RT5640_G_DAC_L2_OM_L_SFT 10
681 #define RT5640_G_BST2_OM_R_MASK (0x7 << 10)
682 #define RT5640_G_BST2_OM_R_SFT 10
693 #define RT5640_G_DAC_R2_OM_R_MASK (0x7 << 10)
694 #define RT5640_G_DAC_R2_OM_R_SFT 10
727 #define RT5640_G_LOUTMIX_MASK (0x1 << 11)
728 #define RT5640_G_LOUTMIX_SFT 11
737 #define RT5640_PWR_DAC_R1 (0x1 << 11)
738 #define RT5640_PWR_DAC_R1_BIT 11
769 #define RT5640_PWR_BG (0x1 << 11)
770 #define RT5640_PWR_BG_BIT 11
771 #define RT5640_PWR_MM (0x1 << 10)
772 #define RT5640_PWR_MM_BIT 10
797 #define RT5640_PWR_MB1 (0x1 << 11)
798 #define RT5640_PWR_MB1_BIT 11
811 #define RT5640_PWR_RM_L (0x1 << 11)
812 #define RT5640_PWR_RM_L_BIT 11
813 #define RT5640_PWR_RM_R (0x1 << 10)
814 #define RT5640_PWR_RM_R_BIT 10
825 #define RT5640_PWR_HV_L (0x1 << 11)
826 #define RT5640_PWR_HV_L_BIT 11
827 #define RT5640_PWR_HV_R (0x1 << 10)
828 #define RT5640_PWR_HV_R_BIT 10
841 #define RT5640_I2S_O_CP_MASK (0x3 << 10)
842 #define RT5640_I2S_O_CP_SFT 10
843 #define RT5640_I2S_O_CP_OFF (0x0 << 10)
844 #define RT5640_I2S_O_CP_U_LAW (0x1 << 10)
845 #define RT5640_I2S_O_CP_A_LAW (0x2 << 10)
889 #define RT5640_I2S_BCLK_MS2_MASK (0x1 << 11)
890 #define RT5640_I2S_BCLK_MS2_SFT 11
891 #define RT5640_I2S_BCLK_MS2_32 (0x0 << 11)
892 #define RT5640_I2S_BCLK_MS2_64 (0x1 << 11)
943 #define RT5640_DAHPF_EN (0x1 << 11)
944 #define RT5640_DAHPF_EN_SFT 11
945 #define RT5640_ADHPF_EN (0x1 << 10)
946 #define RT5640_ADHPF_EN_SFT 10
965 #define RT5640_DMIC_1_DP_MASK (0x1 << 11)
966 #define RT5640_DMIC_1_DP_SFT 11
967 #define RT5640_DMIC_1_DP_GPIO3 (0x0 << 11)
968 #define RT5640_DMIC_1_DP_IN1P (0x1 << 11)
969 #define RT5640_DMIC_2_DP_MASK (0x1 << 10)
970 #define RT5640_DMIC_2_DP_SFT 10
971 #define RT5640_DMIC_2_DP_GPIO4 (0x0 << 10)
972 #define RT5640_DMIC_2_DP_IN1N (0x1 << 10)
1015 #define RT5640_PLL_M_BP (0x1 << 11)
1016 #define RT5640_PLL_M_BP_SFT 11
1061 #define RT5640_ADC_M_MASK (0x1 << 11)
1062 #define RT5640_ADC_M_SFT 11
1063 #define RT5640_ADC_M_NOR (0x0 << 11)
1064 #define RT5640_ADC_M_ASYN (0x1 << 11)
1096 #define RT5640_HP_OVCD_MASK (0x1 << 10)
1097 #define RT5640_HP_OVCD_SFT 10
1098 #define RT5640_HP_OVCD_DIS (0x0 << 10)
1099 #define RT5640_HP_OVCD_EN (0x1 << 10)
1122 #define RT5640_CLSD_OM_MASK (0x1 << 11)
1123 #define RT5640_CLSD_OM_SFT 11
1124 #define RT5640_CLSD_OM_MONO (0x0 << 11)
1125 #define RT5640_CLSD_OM_STO (0x1 << 11)
1126 #define RT5640_CLSD_SCH_MASK (0x1 << 10)
1127 #define RT5640_CLSD_SCH_SFT 10
1128 #define RT5640_CLSD_SCH_L (0x0 << 10)
1129 #define RT5640_CLSD_SCH_S (0x1 << 10)
1186 #define RT5640_BPS_MASK (0x1 << 11)
1187 #define RT5640_BPS_SFT 11
1188 #define RT5640_BPS_DIS (0x0 << 11)
1189 #define RT5640_BPS_EN (0x1 << 11)
1190 #define RT5640_FAST_UPDN_MASK (0x1 << 10)
1191 #define RT5640_FAST_UPDN_SFT 10
1192 #define RT5640_FAST_UPDN_DIS (0x0 << 10)
1193 #define RT5640_FAST_UPDN_EN (0x1 << 10)
1230 #define RT5640_OSW_L_MASK (0x1 << 11)
1231 #define RT5640_OSW_L_SFT 11
1232 #define RT5640_OSW_L_DIS (0x0 << 11)
1233 #define RT5640_OSW_L_EN (0x1 << 11)
1234 #define RT5640_OSW_R_MASK (0x1 << 10)
1235 #define RT5640_OSW_R_SFT 10
1236 #define RT5640_OSW_R_DIS (0x0 << 10)
1237 #define RT5640_OSW_R_EN (0x1 << 10)
1277 #define RT5640_MIC1_OVCD_MASK (0x1 << 11)
1278 #define RT5640_MIC1_OVCD_SFT 11
1279 #define RT5640_MIC1_OVCD_DIS (0x0 << 11)
1280 #define RT5640_MIC1_OVCD_EN (0x1 << 11)
1437 #define RT5640_ANC_SN_MASK (0x1 << 11)
1438 #define RT5640_ANC_SN_SFT 11
1439 #define RT5640_ANC_SN_DIS (0x0 << 11)
1440 #define RT5640_ANC_SN_EN (0x1 << 11)
1441 #define RT5640_ANC_CLK_MASK (0x1 << 10)
1442 #define RT5640_ANC_CLK_SFT 10
1443 #define RT5640_ANC_CLK_ANC (0x0 << 10)
1444 #define RT5640_ANC_CLK_REG (0x1 << 10)
1490 #define RT5640_JD_HP_MASK (0x1 << 11)
1491 #define RT5640_JD_HP_SFT 11
1492 #define RT5640_JD_HP_DIS (0x0 << 11)
1493 #define RT5640_JD_HP_EN (0x1 << 11)
1494 #define RT5640_JD_HP_TRG_MASK (0x1 << 10)
1495 #define RT5640_JD_HP_TRG_SFT 10
1496 #define RT5640_JD_HP_TRG_LO (0x0 << 10)
1497 #define RT5640_JD_HP_TRG_HI (0x1 << 10)
1578 #define RT5640_JD_P_MASK (0x1 << 11)
1579 #define RT5640_JD_P_SFT 11
1580 #define RT5640_JD_P_NOR (0x0 << 11)
1581 #define RT5640_JD_P_INV (0x1 << 11)
1582 #define RT5640_OT_P_MASK (0x1 << 10)
1583 #define RT5640_OT_P_SFT 10
1584 #define RT5640_OT_P_NOR (0x0 << 10)
1585 #define RT5640_OT_P_INV (0x1 << 10)
1596 #define RT5640_MB1_OC_STKY_MASK (0x1 << 11)
1597 #define RT5640_MB1_OC_STKY_SFT 11
1598 #define RT5640_MB1_OC_STKY_DIS (0x0 << 11)
1599 #define RT5640_MB1_OC_STKY_EN (0x1 << 11)
1600 #define RT5640_MB2_OC_STKY_MASK (0x1 << 10)
1601 #define RT5640_MB2_OC_STKY_SFT 10
1602 #define RT5640_MB2_OC_STKY_DIS (0x0 << 10)
1603 #define RT5640_MB2_OC_STKY_EN (0x1 << 10)
1638 #define RT5640_GP4_PIN_MASK (0x1 << 11)
1639 #define RT5640_GP4_PIN_SFT 11
1640 #define RT5640_GP4_PIN_GPIO4 (0x0 << 11)
1641 #define RT5640_GP4_PIN_DMIC2_SDA (0x1 << 11)
1642 #define RT5640_DP_SIG_MASK (0x1 << 10)
1643 #define RT5640_DP_SIG_SFT 10
1644 #define RT5640_DP_SIG_TEST (0x0 << 10)
1645 #define RT5640_DP_SIG_AP (0x1 << 10)
1652 #define RT5640_GP4_PF_MASK (0x1 << 11)
1653 #define RT5640_GP4_PF_SFT 11
1654 #define RT5640_GP4_PF_IN (0x0 << 11)
1655 #define RT5640_GP4_PF_OUT (0x1 << 11)
1656 #define RT5640_GP4_OUT_MASK (0x1 << 10)
1657 #define RT5640_GP4_OUT_SFT 10
1658 #define RT5640_GP4_OUT_LO (0x0 << 10)
1659 #define RT5640_GP4_OUT_HI (0x1 << 10)
1701 /* FM34-500 Register Control 1 (0xc4) */
1704 /* FM34-500 Register Control 2 (0xc5) */
1707 /* FM34-500 Register Control 3 (0xc6) */
1720 #define RT5640_DSP_PD_PIN_MASK (0x1 << 11)
1721 #define RT5640_DSP_PD_PIN_SFT 11
1722 #define RT5640_DSP_PD_PIN_LO (0x0 << 11)
1723 #define RT5640_DSP_PD_PIN_HI (0x1 << 11)
1724 #define RT5640_DSP_RST_PIN_MASK (0x1 << 10)
1725 #define RT5640_DSP_RST_PIN_SFT 10
1726 #define RT5640_DSP_RST_PIN_LO (0x0 << 10)
1727 #define RT5640_DSP_RST_PIN_HI (0x1 << 10)
1742 #define RT5640_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1743 #define RT5640_SEQ1_ST_SFT 11
1744 #define RT5640_SEQ1_ST_RUN (0x0 << 11)
1745 #define RT5640_SEQ1_ST_FIN (0x1 << 11)
1746 #define RT5640_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1747 #define RT5640_SEQ2_ST_SFT 10
1748 #define RT5640_SEQ2_ST_RUN (0x0 << 10)
1749 #define RT5640_SEQ2_ST_FIN (0x1 << 10)
1866 #define RT5640_3D_1F_MIX_MASK (0x3 << 11)
1867 #define RT5640_3D_1F_MIX_SFT 11
1868 #define RT5640_3D_HP_M_MASK (0x1 << 10)
1869 #define RT5640_3D_HP_M_SFT 10
1870 #define RT5640_3D_HP_M_SUR (0x0 << 10)
1871 #define RT5640_3D_HP_M_FRO (0x1 << 10)
1888 #define RT5640_1ST_HPF_MASK (0x1 << 11)
1889 #define RT5640_1ST_HPF_SFT 11
1890 #define RT5640_1ST_HPF_DIS (0x0 << 11)
1891 #define RT5640_1ST_HPF_EN (0x1 << 11)
1904 #define RT5640_SI_DAC_MASK (0x1 << 11)
1905 #define RT5640_SI_DAC_SFT 11
1906 #define RT5640_SI_DAC_AUTO (0x0 << 11)
1907 #define RT5640_SI_DAC_TEST (0x1 << 11)
1908 #define RT5640_DC_CAL_M_MASK (0x1 << 10)
1909 #define RT5640_DC_CAL_M_SFT 10
1910 #define RT5640_DC_CAL_M_CAL (0x0 << 10)
1911 #define RT5640_DC_CAL_M_NOR (0x1 << 10)
1957 #define RT5640_ZCD_DIG_MASK (0x1 << 11)
1958 #define RT5640_ZCD_DIG_SFT 11
1959 #define RT5640_ZCD_DIG_DIS (0x0 << 11)
1960 #define RT5640_ZCD_DIG_EN (0x1 << 11)
1961 #define RT5640_ZCD_MASK (0x1 << 10)
1962 #define RT5640_ZCD_SFT 10
1963 #define RT5640_ZCD_PD (0x0 << 10)
1964 #define RT5640_ZCD_PU (0x1 << 10)
1987 #define RT5640_MCLK_DET (0x1 << 11)
2018 #define RT5640_WND_FC_NW_MASK (0x3f << 10)
2019 #define RT5640_WND_FC_NW_SFT 10
2038 #define RT5640_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2040 #define RT5640_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2051 #define RT5640_DP_SPK_MASK (0x1 << 10)
2052 #define RT5640_DP_SPK_SFT 10
2053 #define RT5640_DP_SPK_DIS (0x0 << 10)
2054 #define RT5640_DP_SPK_EN (0x1 << 10)