Lines Matching +full:8 +full:- +full:12
2 * rt5645.h -- RT5645 ALSA SoC audio driver
22 /* I/O - Output */
27 /* I/O - Input */
35 /* I/O - ADC/DAC/DMIC */
43 /* Mixer - D-D */
52 /* Mixer - PDM */
54 /* Mixer - ADC */
59 /* Mixer - DAC */
97 /* Format - ADC/DAC */
104 /* Format - TDM Control */
110 /* Function - Analog */
126 /* Function - Digital */
230 #define RT5645_L_VOL_MASK (0x3f << 8)
231 #define RT5645_L_VOL_SFT 8
236 #define RT5645_CBJ_BST1_MASK (0xf << 12)
237 #define RT5645_CBJ_BST1_SFT (12)
239 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
247 #define RT5645_CBJ_MN_JD (0x1 << 12)
256 #define RT5645_BST_MASK1 (0xf<<12)
257 #define RT5645_BST_SFT1 12
258 #define RT5645_BST_MASK2 (0xf<<8)
259 #define RT5645_BST_SFT2 8
268 #define RT5645_INL_VOL_MASK (0x1f << 8)
269 #define RT5645_INL_VOL_SFT 8
278 #define RT5645_DAC_L1_VOL_MASK (0xff << 8)
279 #define RT5645_DAC_L1_VOL_SFT 8
284 #define RT5645_DAC_L2_VOL_MASK (0xff << 8)
285 #define RT5645_DAC_L2_VOL_SFT 8
292 #define RT5645_M_DAC_R2_VOL (0x1 << 12)
293 #define RT5645_M_DAC_R2_VOL_SFT 12
300 #define RT5645_ADC_L_VOL_MASK (0x7f << 8)
301 #define RT5645_ADC_L_VOL_SFT 8
306 #define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)
307 #define RT5645_MONO_ADC_L_VOL_SFT 8
314 #define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)
315 #define RT5645_STO1_ADC_R_BST_SFT 12
322 #define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)
323 #define RT5645_MONO_ADC_R_BST_SFT 12
336 #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
337 #define RT5645_ADC_1_SRC_SFT 12
338 #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
339 #define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)
342 #define RT5645_DMIC_SRC_MASK (0x1 << 8)
343 #define RT5645_DMIC_SRC_SFT 8
356 #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
357 #define RT5645_MONO_ADC_L1_SRC_SFT 12
358 #define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)
359 #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
362 #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
363 #define RT5645_MONO_DMIC_L_SRC_SFT 8
388 #define RT5645_DAC1_L_SEL_MASK (0x3 << 8)
389 #define RT5645_DAC1_L_SEL_SFT 8
390 #define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)
391 #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
392 #define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)
393 #define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)
404 #define RT5645_M_DAC_L2 (0x1 << 12)
405 #define RT5645_M_DAC_L2_SFT 12
412 #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
413 #define RT5645_DAC_R1_STO_L_VOL_SFT 8
434 #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
435 #define RT5645_M_DAC_L2_MONO_L_SFT 12
462 #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
463 #define RT5645_DAC_L2_DAC_L_VOL_SFT 12
470 #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
471 #define RT5645_DAC_R2_DAC_R_VOL_SFT 8
490 #define RT5645_IF2_ADC_IN_MASK (0x7 << 12)
491 #define RT5645_IF2_ADC_IN_SFT 12
494 #define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)
495 #define RT5645_IF2_ADC_SEL_SFT 8
510 #define RT5645_M_PDM1_R (0x1 << 12)
511 #define RT5645_M_PDM1_R_SFT 12
518 #define RT5645_M_PDM2_R (0x1 << 8)
519 #define RT5645_M_PDM2_R_SFT 8
609 #define RT5645_IRQ_PSV_MODE (0x1 << 12)
614 #define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)
615 #define RT5645_G_IN_L_SM_L_SFT 12
618 #define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)
619 #define RT5645_G_DAC_L2_SM_L_SFT 8
636 #define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)
637 #define RT5645_G_IN_R_SM_R_SFT 12
640 #define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)
641 #define RT5645_G_DAC_R2_SM_R_SFT 8
662 #define RT5645_M_SV_R_SPM_L (0x1 << 12)
663 #define RT5645_M_SV_R_SPM_L_SFT 12
682 #define RT5645_M_DAC_L2_MA (0x1 << 8)
683 #define RT5645_M_DAC_L2_MA_SFT 8
766 #define RT5645_M_OV_R_LM (0x1 << 12)
767 #define RT5645_M_OV_R_LM_SFT 12
778 #define RT5645_PWR_DAC_L1 (0x1 << 12)
779 #define RT5645_PWR_DAC_L1_BIT 12
784 #define RT5645_PWR_CLS_D_L (0x1 << 8)
785 #define RT5645_PWR_CLS_D_L_BIT 8
804 #define RT5645_PWR_I2S_DSP (0x1 << 12)
805 #define RT5645_PWR_I2S_DSP_BIT 12
828 #define RT5645_PWR_LM (0x1 << 12)
829 #define RT5645_PWR_LM_BIT 12
854 #define RT5645_PWR_BST4 (0x1 << 12)
855 #define RT5645_PWR_BST4_BIT 12
880 #define RT5645_PWR_SM_R (0x1 << 12)
881 #define RT5645_PWR_SM_R_BIT 12
886 #define RT5645_PWR_MM (0x1 << 8)
887 #define RT5645_PWR_MM_BIT 8
906 #define RT5645_PWR_IN_R (0x1 << 8)
907 #define RT5645_PWR_IN_R_BIT 8
921 #define RT5645_I2S_I_CP_MASK (0x3 << 8)
922 #define RT5645_I2S_I_CP_SFT 8
923 #define RT5645_I2S_I_CP_OFF (0x0 << 8)
924 #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
925 #define RT5645_I2S_I_CP_A_LAW (0x2 << 8)
950 #define RT5645_I2S_PD1_MASK (0x7 << 12)
951 #define RT5645_I2S_PD1_SFT 12
952 #define RT5645_I2S_PD1_1 (0x0 << 12)
953 #define RT5645_I2S_PD1_2 (0x1 << 12)
954 #define RT5645_I2S_PD1_3 (0x2 << 12)
955 #define RT5645_I2S_PD1_4 (0x3 << 12)
956 #define RT5645_I2S_PD1_6 (0x4 << 12)
957 #define RT5645_I2S_PD1_8 (0x5 << 12)
958 #define RT5645_I2S_PD1_12 (0x6 << 12)
959 #define RT5645_I2S_PD1_16 (0x7 << 12)
964 #define RT5645_I2S_PD2_MASK (0x7 << 8)
965 #define RT5645_I2S_PD2_SFT 8
966 #define RT5645_I2S_PD2_1 (0x0 << 8)
967 #define RT5645_I2S_PD2_2 (0x1 << 8)
968 #define RT5645_I2S_PD2_3 (0x2 << 8)
969 #define RT5645_I2S_PD2_4 (0x3 << 8)
970 #define RT5645_I2S_PD2_6 (0x4 << 8)
971 #define RT5645_I2S_PD2_8 (0x5 << 8)
972 #define RT5645_I2S_PD2_12 (0x6 << 8)
973 #define RT5645_I2S_PD2_16 (0x7 << 8)
1008 #define RT5645_ADC_R_OSR_MASK (0x3 << 12)
1009 #define RT5645_ADC_R_OSR_SFT 12
1010 #define RT5645_ADC_R_OSR_128 (0x0 << 12)
1011 #define RT5645_ADC_R_OSR_64 (0x1 << 12)
1012 #define RT5645_ADC_R_OSR_32 (0x2 << 12)
1013 #define RT5645_ADC_R_OSR_16 (0x3 << 12)
1032 #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1033 #define RT5645_DMIC_1R_LH_SFT 12
1034 #define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)
1035 #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1046 #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1047 #define RT5645_DMIC_2R_LH_SFT 8
1048 #define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)
1049 #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1063 #define RT5645_IF1_ADC_IN_MASK (0x3 << 8)
1064 #define RT5645_IF1_ADC_IN_SFT 8
1096 #define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)
1097 #define RT5645_PLL_M_SFT 12
1110 #define RT5645_I2S2_F_MASK (0x1 << 12)
1111 #define RT5645_I2S2_F_SFT 12
1112 #define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)
1113 #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1118 #define RT5645_DMIC_2_M_MASK (0x1 << 8)
1119 #define RT5645_DMIC_2_M_SFT 8
1120 #define RT5645_DMIC_2_M_NOR (0x0 << 8)
1121 #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1130 #define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)
1131 #define RT5645_DA_STO_CLK_SEL_SFT 12
1132 #define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)
1133 #define RT5645_DA_MONOL_CLK_SEL_SFT 8
1146 #define RT5645_I2S1_PD_MASK (0x7 << 12)
1147 #define RT5645_I2S1_PD_SFT 12
1148 #define RT5645_I2S2_PD_MASK (0x7 << 8)
1149 #define RT5645_I2S2_PD_SFT 8
1156 #define RT5645_HP_OC_TH_MASK (0x3 << 8)
1157 #define RT5645_HP_OC_TH_SFT 8
1158 #define RT5645_HP_OC_TH_90 (0x0 << 8)
1159 #define RT5645_HP_OC_TH_105 (0x1 << 8)
1160 #define RT5645_HP_OC_TH_120 (0x2 << 8)
1161 #define RT5645_HP_OC_TH_135 (0x3 << 8)
1168 #define RT5645_AUTO_PD_MASK (0x1 << 8)
1169 #define RT5645_AUTO_PD_SFT 8
1170 #define RT5645_AUTO_PD_DIS (0x0 << 8)
1171 #define RT5645_AUTO_PD_EN (0x1 << 8)
1176 #define RT5645_CLSD_RATIO_MASK (0xf << 12)
1177 #define RT5645_CLSD_RATIO_SFT 12
1196 #define RT5645_HP_R_SMT_MASK (0x1 << 8)
1197 #define RT5645_HP_R_SMT_SFT 8
1198 #define RT5645_HP_R_SMT_DIS (0x0 << 8)
1199 #define RT5645_HP_R_SMT_EN (0x1 << 8)
1238 #define RT5645_RAMP_MASK (0x1 << 12)
1239 #define RT5645_RAMP_SFT 12
1240 #define RT5645_RAMP_DIS (0x0 << 12)
1241 #define RT5645_RAMP_EN (0x1 << 12)
1250 #define RT5645_MRES_MASK (0x3 << 8)
1251 #define RT5645_MRES_SFT 8
1252 #define RT5645_MRES_15MO (0x0 << 8)
1253 #define RT5645_MRES_25MO (0x1 << 8)
1254 #define RT5645_MRES_35MO (0x2 << 8)
1255 #define RT5645_MRES_45MO (0x3 << 8)
1268 #define RT5645_CP_SYS_MASK (0x7 << 12)
1269 #define RT5645_CP_SYS_SFT 12
1270 #define RT5645_CP_FQ1_MASK (0x7 << 8)
1271 #define RT5645_CP_FQ1_SFT 8
1308 #define RT5645_MIC2_CLK_MASK (0x1 << 12)
1309 #define RT5645_MIC2_CLK_SFT 12
1310 #define RT5645_MIC2_CLK_DIS (0x0 << 12)
1311 #define RT5645_MIC2_CLK_EN (0x1 << 12)
1321 #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1322 #define RT5645_MIC2_OVCD_SFT 8
1323 #define RT5645_MIC2_OVCD_DIS (0x0 << 8)
1324 #define RT5645_MIC2_OVCD_EN (0x1 << 8)
1346 #define RT5645_VAD_SEL_MASK (0x3 << 8)
1347 #define RT5645_VAD_SEL_SFT 8
1360 #define RT5645_EQ_DITH_MASK (0x3 << 8)
1361 #define RT5645_EQ_DITH_SFT 8
1362 #define RT5645_EQ_DITH_NOR (0x0 << 8)
1363 #define RT5645_EQ_DITH_LSB (0x1 << 8)
1364 #define RT5645_EQ_DITH_LSB_1 (0x2 << 8)
1365 #define RT5645_EQ_DITH_LSB_2 (0x3 << 8)
1368 #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1369 #define RT5645_EQ_HPF1_M_SFT 8
1370 #define RT5645_EQ_HPF1_M_HI (0x0 << 8)
1371 #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1423 #define RT5645_DRC_AGC_AR_MASK (0x1f << 8)
1424 #define RT5645_DRC_AGC_AR_SFT 8
1437 #define RT5645_DRC_AGC_POB_MASK (0x3f << 8)
1438 #define RT5645_DRC_AGC_POB_SFT 8
1453 #define RT5645_DRC_AGC_NGB_MASK (0xf << 12)
1454 #define RT5645_DRC_AGC_NGB_SFT 12
1477 #define RT5645_ANC_MD_MASK (0x3 << 12)
1478 #define RT5645_ANC_MD_SFT 12
1479 #define RT5645_ANC_MD_DIS (0x0 << 12)
1480 #define RT5645_ANC_MD_67MS (0x1 << 12)
1481 #define RT5645_ANC_MD_267MS (0x2 << 12)
1482 #define RT5645_ANC_MD_1067MS (0x3 << 12)
1491 #define RT5645_ANC_ZCD_MASK (0x3 << 8)
1492 #define RT5645_ANC_ZCD_SFT 8
1493 #define RT5645_ANC_ZCD_DIS (0x0 << 8)
1494 #define RT5645_ANC_ZCD_T1 (0x1 << 8)
1495 #define RT5645_ANC_ZCD_T2 (0x2 << 8)
1496 #define RT5645_ANC_ZCD_WT (0x3 << 8)
1509 #define RT5645_ANC_FG_R_MASK (0xf << 12)
1510 #define RT5645_ANC_FG_R_SFT 12
1511 #define RT5645_ANC_FG_L_MASK (0xf << 8)
1512 #define RT5645_ANC_FG_L_SFT 8
1548 #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1549 #define RT5645_JD_SPL_TRG_SFT 8
1550 #define RT5645_JD_SPL_TRG_LO (0x0 << 8)
1551 #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1620 #define RT5645_OT_STKY_MASK (0x1 << 12)
1621 #define RT5645_OT_STKY_SFT 12
1622 #define RT5645_OT_STKY_DIS (0x0 << 12)
1623 #define RT5645_OT_STKY_EN (0x1 << 12)
1651 #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1652 #define RT5645_MB2_OC_STKY_SFT 12
1653 #define RT5645_MB2_OC_STKY_DIS (0x0 << 12)
1654 #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1677 #define RT5645_GP3_PIN_MASK (0x3 << 12)
1678 #define RT5645_GP3_PIN_SFT 12
1679 #define RT5645_GP3_PIN_GPIO3 (0x0 << 12)
1680 #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1681 #define RT5645_GP3_PIN_IRQ (0x2 << 12)
1694 #define RT5645_I2S2_SEL (0x1 << 8)
1695 #define RT5645_I2S2_SEL_SFT 8
1738 #define RT5645_GP3_PF_MASK (0x1 << 8)
1739 #define RT5645_GP3_PF_SFT 8
1740 #define RT5645_GP3_PF_IN (0x0 << 8)
1741 #define RT5645_GP3_PF_OUT (0x1 << 8)
1776 #define RT5645_REG_SEQ_MASK (0xf << 12)
1777 #define RT5645_REG_SEQ_SFT 12
1790 #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1791 #define RT5645_SEQ_2_PT_BIT 8
1800 #define RT5645_SEQ_DLY_MASK (0xff << 8)
1801 #define RT5645_SEQ_DLY_SFT 8
1812 #define RT5645_SEQ1_START_MASK (0xf << 8)
1813 #define RT5645_SEQ1_START_SFT 8
1818 #define RT5645_SEQ2_START_MASK (0xf << 8)
1819 #define RT5645_SEQ2_START_SFT 8
1842 #define RT5645_BB_CT_MASK (0x7 << 12)
1843 #define RT5645_BB_CT_SFT 12
1844 #define RT5645_BB_CT_A (0x0 << 12)
1845 #define RT5645_BB_CT_B (0x1 << 12)
1846 #define RT5645_BB_CT_C (0x2 << 12)
1847 #define RT5645_BB_CT_D (0x3 << 12)
1850 #define RT5645_M_BB_R_MASK (0x1 << 8)
1851 #define RT5645_M_BB_R_SFT 8
1869 #define RT5645_EG_MP3_MASK (0x1f << 8)
1870 #define RT5645_EG_MP3_SFT 8
1885 #define RT5645_OG_MP3_MASK (0x1f << 8)
1886 #define RT5645_OG_MP3_SFT 8
1911 #define RT5645_M_3D_D2H_MASK (0x1 << 8)
1912 #define RT5645_M_3D_D2H_SFT 8
1923 #define RT5645_HPF_CF_L_MASK (0x7 << 12)
1924 #define RT5645_HPF_CF_L_SFT 12
1929 #define RT5645_HPF_CF_R_MASK (0x7 << 8)
1930 #define RT5645_HPF_CF_R_SFT 8
1990 #define RT5645_HP_SV_MASK (0x1 << 12)
1991 #define RT5645_HP_SV_SFT 12
1992 #define RT5645_HP_SV_DIS (0x0 << 12)
1993 #define RT5645_HP_SV_EN (0x1 << 12)
2005 #define RT5645_M_ZCD_RM_R (0x1 << 8)
2031 #define RT5645_3D_SPK_CG_MASK (0x1f << 8)
2032 #define RT5645_3D_SPK_CG_SFT 8
2062 /* Wind Noise Detection Control 8 (0x73) */
2063 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2065 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2066 #define RT5645_WND_STRONG_SFT 12
2090 #define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)
2107 #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2108 #define RT5645_IF1_ADC1_IN1_SFT 12
2132 #define RT5645_JD_PSV_MODE (0x1 << 12)