Lines Matching +full:0 +full:x1
18 #define RT5651_RESET 0x00
19 #define RT5651_VERSION_ID 0xfd
20 #define RT5651_VENDOR_ID 0xfe
21 #define RT5651_DEVICE_ID 0xff
23 #define RT5651_HP_VOL 0x02
24 #define RT5651_LOUT_CTRL1 0x03
25 #define RT5651_LOUT_CTRL2 0x05
27 #define RT5651_IN1_IN2 0x0d
28 #define RT5651_IN3 0x0e
29 #define RT5651_INL1_INR1_VOL 0x0f
30 #define RT5651_INL2_INR2_VOL 0x10
32 #define RT5651_DAC1_DIG_VOL 0x19
33 #define RT5651_DAC2_DIG_VOL 0x1a
34 #define RT5651_DAC2_CTRL 0x1b
35 #define RT5651_ADC_DIG_VOL 0x1c
36 #define RT5651_ADC_DATA 0x1d
37 #define RT5651_ADC_BST_VOL 0x1e
39 #define RT5651_STO1_ADC_MIXER 0x27
40 #define RT5651_STO2_ADC_MIXER 0x28
41 #define RT5651_AD_DA_MIXER 0x29
42 #define RT5651_STO_DAC_MIXER 0x2a
43 #define RT5651_DD_MIXER 0x2b
44 #define RT5651_DIG_INF_DATA 0x2f
46 #define RT5651_PDM_CTL 0x30
47 #define RT5651_PDM_I2C_CTL1 0x31
48 #define RT5651_PDM_I2C_CTL2 0x32
49 #define RT5651_PDM_I2C_DATA_W 0x33
50 #define RT5651_PDM_I2C_DATA_R 0x34
52 #define RT5651_REC_L1_MIXER 0x3b
53 #define RT5651_REC_L2_MIXER 0x3c
54 #define RT5651_REC_R1_MIXER 0x3d
55 #define RT5651_REC_R2_MIXER 0x3e
57 #define RT5651_HPO_MIXER 0x45
58 #define RT5651_OUT_L1_MIXER 0x4d
59 #define RT5651_OUT_L2_MIXER 0x4e
60 #define RT5651_OUT_L3_MIXER 0x4f
61 #define RT5651_OUT_R1_MIXER 0x50
62 #define RT5651_OUT_R2_MIXER 0x51
63 #define RT5651_OUT_R3_MIXER 0x52
64 #define RT5651_LOUT_MIXER 0x53
66 #define RT5651_PWR_DIG1 0x61
67 #define RT5651_PWR_DIG2 0x62
68 #define RT5651_PWR_ANLG1 0x63
69 #define RT5651_PWR_ANLG2 0x64
70 #define RT5651_PWR_MIXER 0x65
71 #define RT5651_PWR_VOL 0x66
73 #define RT5651_PRIV_INDEX 0x6a
74 #define RT5651_PRIV_DATA 0x6c
76 #define RT5651_I2S1_SDP 0x70
77 #define RT5651_I2S2_SDP 0x71
78 #define RT5651_ADDA_CLK1 0x73
79 #define RT5651_ADDA_CLK2 0x74
80 #define RT5651_DMIC 0x75
82 #define RT5651_TDM_CTL_1 0x77
83 #define RT5651_TDM_CTL_2 0x78
84 #define RT5651_TDM_CTL_3 0x79
86 #define RT5651_GLB_CLK 0x80
87 #define RT5651_PLL_CTRL1 0x81
88 #define RT5651_PLL_CTRL2 0x82
89 #define RT5651_PLL_MODE_1 0x83
90 #define RT5651_PLL_MODE_2 0x84
91 #define RT5651_PLL_MODE_3 0x85
92 #define RT5651_PLL_MODE_4 0x86
93 #define RT5651_PLL_MODE_5 0x87
94 #define RT5651_PLL_MODE_6 0x89
95 #define RT5651_PLL_MODE_7 0x8a
96 #define RT5651_DEPOP_M1 0x8e
97 #define RT5651_DEPOP_M2 0x8f
98 #define RT5651_DEPOP_M3 0x90
99 #define RT5651_CHARGE_PUMP 0x91
100 #define RT5651_MICBIAS 0x93
101 #define RT5651_A_JD_CTL1 0x94
103 #define RT5651_EQ_CTRL1 0xb0
104 #define RT5651_EQ_CTRL2 0xb1
105 #define RT5651_ALC_1 0xb4
106 #define RT5651_ALC_2 0xb5
107 #define RT5651_ALC_3 0xb6
108 #define RT5651_JD_CTRL1 0xbb
109 #define RT5651_JD_CTRL2 0xbc
110 #define RT5651_IRQ_CTRL1 0xbd
111 #define RT5651_IRQ_CTRL2 0xbe
112 #define RT5651_INT_IRQ_ST 0xbf
113 #define RT5651_GPIO_CTRL1 0xc0
114 #define RT5651_GPIO_CTRL2 0xc1
115 #define RT5651_GPIO_CTRL3 0xc2
116 #define RT5651_PGM_REG_ARR1 0xc8
117 #define RT5651_PGM_REG_ARR2 0xc9
118 #define RT5651_PGM_REG_ARR3 0xca
119 #define RT5651_PGM_REG_ARR4 0xcb
120 #define RT5651_PGM_REG_ARR5 0xcc
121 #define RT5651_SCB_FUNC 0xcd
122 #define RT5651_SCB_CTRL 0xce
123 #define RT5651_BASE_BACK 0xcf
124 #define RT5651_MP3_PLUS1 0xd0
125 #define RT5651_MP3_PLUS2 0xd1
126 #define RT5651_ADJ_HPF_CTRL1 0xd3
127 #define RT5651_ADJ_HPF_CTRL2 0xd4
128 #define RT5651_HP_CALIB_AMP_DET 0xd6
129 #define RT5651_HP_CALIB2 0xd7
130 #define RT5651_SV_ZCD1 0xd9
131 #define RT5651_SV_ZCD2 0xda
132 #define RT5651_D_MISC 0xfa
134 #define RT5651_DUMMY2 0xfb
135 #define RT5651_DUMMY3 0xfc
139 #define RT5651_BIAS_CUR1 0x12
140 #define RT5651_BIAS_CUR3 0x14
141 #define RT5651_BIAS_CUR4 0x15
142 #define RT5651_CLSD_INT_REG1 0x1c
143 #define RT5651_CHPUMP_INT_REG1 0x24
144 #define RT5651_MAMP_INT_REG2 0x37
145 #define RT5651_CHOP_DAC_ADC 0x3d
146 #define RT5651_3D_SPK 0x63
147 #define RT5651_WND_1 0x6c
148 #define RT5651_WND_2 0x6d
149 #define RT5651_WND_3 0x6e
150 #define RT5651_WND_4 0x6f
151 #define RT5651_WND_5 0x70
152 #define RT5651_WND_8 0x73
153 #define RT5651_DIP_SPK_INF 0x75
154 #define RT5651_HP_DCC_INT1 0x77
155 #define RT5651_EQ_BW_LOP 0xa0
156 #define RT5651_EQ_GN_LOP 0xa1
157 #define RT5651_EQ_FC_BP1 0xa2
158 #define RT5651_EQ_BW_BP1 0xa3
159 #define RT5651_EQ_GN_BP1 0xa4
160 #define RT5651_EQ_FC_BP2 0xa5
161 #define RT5651_EQ_BW_BP2 0xa6
162 #define RT5651_EQ_GN_BP2 0xa7
163 #define RT5651_EQ_FC_BP3 0xa8
164 #define RT5651_EQ_BW_BP3 0xa9
165 #define RT5651_EQ_GN_BP3 0xaa
166 #define RT5651_EQ_FC_BP4 0xab
167 #define RT5651_EQ_BW_BP4 0xac
168 #define RT5651_EQ_GN_BP4 0xad
169 #define RT5651_EQ_FC_HIP1 0xae
170 #define RT5651_EQ_GN_HIP1 0xaf
171 #define RT5651_EQ_FC_HIP2 0xb0
172 #define RT5651_EQ_BW_HIP2 0xb1
173 #define RT5651_EQ_GN_HIP2 0xb2
174 #define RT5651_EQ_PRE_VOL 0xb3
175 #define RT5651_EQ_PST_VOL 0xb4
179 #define RT5651_L_MUTE (0x1 << 15)
181 #define RT5651_VOL_L_MUTE (0x1 << 14)
183 #define RT5651_R_MUTE (0x1 << 7)
185 #define RT5651_VOL_R_MUTE (0x1 << 6)
187 #define RT5651_L_VOL_MASK (0x3f << 8)
189 #define RT5651_R_VOL_MASK (0x3f)
190 #define RT5651_R_VOL_SFT 0
192 /* LOUT Control 2(0x05) */
193 #define RT5651_EN_DFO (0x1 << 15)
195 /* IN1 and IN2 Control (0x0d) */
196 /* IN3 and IN4 Control (0x0e) */
197 #define RT5651_BST_MASK1 (0xf<<12)
199 #define RT5651_BST_MASK2 (0xf<<8)
201 #define RT5651_IN_DF1 (0x1 << 7)
203 #define RT5651_IN_DF2 (0x1 << 6)
206 /* INL1 and INR1 Volume Control (0x0f) */
207 /* INL2 and INR2 Volume Control (0x10) */
208 #define RT5651_INL_SEL_MASK (0x1 << 15)
210 #define RT5651_INL_SEL_IN4P (0x0 << 15)
211 #define RT5651_INL_SEL_MONOP (0x1 << 15)
212 #define RT5651_INL_VOL_MASK (0x1f << 8)
214 #define RT5651_INR_SEL_MASK (0x1 << 7)
216 #define RT5651_INR_SEL_IN4N (0x0 << 7)
217 #define RT5651_INR_SEL_MONON (0x1 << 7)
218 #define RT5651_INR_VOL_MASK (0x1f)
219 #define RT5651_INR_VOL_SFT 0
221 /* DAC1 Digital Volume (0x19) */
222 #define RT5651_DAC_L1_VOL_MASK (0xff << 8)
224 #define RT5651_DAC_R1_VOL_MASK (0xff)
225 #define RT5651_DAC_R1_VOL_SFT 0
227 /* DAC2 Digital Volume (0x1a) */
228 #define RT5651_DAC_L2_VOL_MASK (0xff << 8)
230 #define RT5651_DAC_R2_VOL_MASK (0xff)
231 #define RT5651_DAC_R2_VOL_SFT 0
233 /* DAC2 Control (0x1b) */
234 #define RT5651_M_DAC_L2_VOL (0x1 << 13)
236 #define RT5651_M_DAC_R2_VOL (0x1 << 12)
238 #define RT5651_SEL_DAC_L2 (0x1 << 11)
239 #define RT5651_IF2_DAC_L2 (0x1 << 11)
240 #define RT5651_IF1_DAC_L2 (0x0 << 11)
242 #define RT5651_SEL_DAC_R2 (0x1 << 10)
243 #define RT5651_IF2_DAC_R2 (0x1 << 11)
244 #define RT5651_IF1_DAC_R2 (0x0 << 11)
247 /* ADC Digital Volume Control (0x1c) */
248 #define RT5651_ADC_L_VOL_MASK (0x7f << 8)
250 #define RT5651_ADC_R_VOL_MASK (0x7f)
251 #define RT5651_ADC_R_VOL_SFT 0
253 /* Mono ADC Digital Volume Control (0x1d) */
254 #define RT5651_M_MONO_ADC_L (0x1 << 15)
256 #define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
258 #define RT5651_M_MONO_ADC_R (0x1 << 7)
260 #define RT5651_MONO_ADC_R_VOL_MASK (0x7f)
261 #define RT5651_MONO_ADC_R_VOL_SFT 0
263 /* ADC Boost Volume Control (0x1e) */
264 #define RT5651_ADC_L_BST_MASK (0x3 << 14)
266 #define RT5651_ADC_R_BST_MASK (0x3 << 12)
268 #define RT5651_ADC_COMP_MASK (0x3 << 10)
271 /* Stereo ADC1 Mixer Control (0x27) */
272 #define RT5651_M_STO1_ADC_L1 (0x1 << 14)
274 #define RT5651_M_STO1_ADC_L2 (0x1 << 13)
276 #define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
278 #define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
279 #define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
280 #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
282 #define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
283 #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
284 #define RT5651_M_STO1_ADC_R1 (0x1 << 6)
286 #define RT5651_M_STO1_ADC_R2 (0x1 << 5)
289 /* Stereo ADC2 Mixer Control (0x28) */
290 #define RT5651_M_STO2_ADC_L1 (0x1 << 14)
292 #define RT5651_M_STO2_ADC_L2 (0x1 << 13)
294 #define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
296 #define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
297 #define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
298 #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
300 #define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
301 #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
302 #define RT5651_M_STO2_ADC_R1 (0x1 << 6)
304 #define RT5651_M_STO2_ADC_R2 (0x1 << 5)
306 #define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
308 #define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
309 #define RT5651_STO2_ADC_R1_SRC_DACMIXR (0x0 << 4)
310 #define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
312 #define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
313 #define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
315 /* ADC Mixer to DAC Mixer Control (0x29) */
316 #define RT5651_M_ADCMIX_L (0x1 << 15)
318 #define RT5651_M_IF1_DAC_L (0x1 << 14)
320 #define RT5651_M_ADCMIX_R (0x1 << 7)
322 #define RT5651_M_IF1_DAC_R (0x1 << 6)
325 /* Stereo DAC Mixer Control (0x2a) */
326 #define RT5651_M_DAC_L1_MIXL (0x1 << 14)
328 #define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
330 #define RT5651_M_DAC_L2_MIXL (0x1 << 12)
332 #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
334 #define RT5651_M_DAC_R1_MIXL (0x1 << 9)
336 #define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
338 #define RT5651_M_DAC_R1_MIXR (0x1 << 6)
340 #define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
342 #define RT5651_M_DAC_R2_MIXR (0x1 << 4)
344 #define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
346 #define RT5651_M_DAC_L1_MIXR (0x1 << 1)
348 #define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
349 #define RT5651_DAC_L1_STO_R_VOL_SFT 0
351 /* DD Mixer Control (0x2b) */
352 #define RT5651_M_STO_DD_L1 (0x1 << 14)
354 #define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
356 #define RT5651_M_STO_DD_L2 (0x1 << 12)
358 #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
360 #define RT5651_M_STO_DD_R2_L (0x1 << 10)
362 #define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
364 #define RT5651_M_STO_DD_R1 (0x1 << 6)
366 #define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
368 #define RT5651_M_STO_DD_R2 (0x1 << 4)
370 #define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
372 #define RT5651_M_STO_DD_L2_R (0x1 << 2)
374 #define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
377 /* Digital Mixer Control (0x2c) */
378 #define RT5651_M_STO_L_DAC_L (0x1 << 15)
380 #define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
382 #define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
384 #define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
386 #define RT5651_M_STO_R_DAC_R (0x1 << 11)
388 #define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
390 #define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
392 #define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
395 /* DSP Path Control 1 (0x2d) */
396 #define RT5651_RXDP_SRC_MASK (0x1 << 15)
398 #define RT5651_RXDP_SRC_NOR (0x0 << 15)
399 #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
400 #define RT5651_TXDP_SRC_MASK (0x1 << 14)
402 #define RT5651_TXDP_SRC_NOR (0x0 << 14)
403 #define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
405 /* DSP Path Control 2 (0x2e) */
406 #define RT5651_DAC_L2_SEL_MASK (0x3 << 14)
408 #define RT5651_DAC_L2_SEL_IF2 (0x0 << 14)
409 #define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
410 #define RT5651_DAC_L2_SEL_TXDC (0x2 << 14)
411 #define RT5651_DAC_L2_SEL_BASS (0x3 << 14)
412 #define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
414 #define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
415 #define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
416 #define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
417 #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
419 #define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
420 #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
421 #define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
423 #define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
424 #define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
425 #define RT5651_RXDC_SEL_MASK (0x3 << 8)
427 #define RT5651_RXDC_SEL_NOR (0x0 << 8)
428 #define RT5651_RXDC_SEL_L2R (0x1 << 8)
429 #define RT5651_RXDC_SEL_R2L (0x2 << 8)
430 #define RT5651_RXDC_SEL_SWAP (0x3 << 8)
431 #define RT5651_RXDP_SEL_MASK (0x3 << 6)
433 #define RT5651_RXDP_SEL_NOR (0x0 << 6)
434 #define RT5651_RXDP_SEL_L2R (0x1 << 6)
435 #define RT5651_RXDP_SEL_R2L (0x2 << 6)
436 #define RT5651_RXDP_SEL_SWAP (0x3 << 6)
437 #define RT5651_TXDC_SEL_MASK (0x3 << 4)
439 #define RT5651_TXDC_SEL_NOR (0x0 << 4)
440 #define RT5651_TXDC_SEL_L2R (0x1 << 4)
441 #define RT5651_TXDC_SEL_R2L (0x2 << 4)
442 #define RT5651_TXDC_SEL_SWAP (0x3 << 4)
443 #define RT5651_TXDP_SEL_MASK (0x3 << 2)
445 #define RT5651_TXDP_SEL_NOR (0x0 << 2)
446 #define RT5651_TXDP_SEL_L2R (0x1 << 2)
447 #define RT5651_TXDP_SEL_R2L (0x2 << 2)
448 #define RT5651_TRXDP_SEL_SWAP (0x3 << 2)
450 /* Digital Interface Data Control (0x2f) */
451 #define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
453 #define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
454 #define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
455 #define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
456 #define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
457 #define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
459 #define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
460 #define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
461 #define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
462 #define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
463 #define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
465 #define RT5651_IF1_ADC1 (0x0 << 7)
466 #define RT5651_IF1_ADC2 (0x1 << 7)
468 /* PDM Output Control (0x30) */
469 #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
471 #define RT5651_PDM_L_SEL_DD_L (0x0 << 15)
472 #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
473 #define RT5651_M_PDM_L (0x1 << 14)
475 #define RT5651_PDM_R_SEL_MASK (0x1 << 13)
477 #define RT5651_PDM_R_SEL_DD_L (0x0 << 13)
478 #define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
479 #define RT5651_M_PDM_R (0x1 << 12)
481 #define RT5651_PDM_BUSY (0x1 << 6)
483 #define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
484 #define RT5651_PDM_PATTERN_SEL_64 (0x0 << 5)
485 #define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
486 #define RT5651_PDM_VOL_MASK (0x1 << 4)
488 #define RT5651_PDM_DIV_MASK (0x3)
489 #define RT5651_PDM_DIV_SFT 0
490 #define RT5651_PDM_DIV_1 0
495 /* PDM I2C/Data Control 1 (0x31) */
496 #define RT5651_PDM_I2C_ID_MASK (0xf << 12)
497 #define PT5631_PDM_CMD_EXE (0x1 << 11)
498 #define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
499 #define RT5651_PDM_I2C_CMD_R (0x0 << 10)
500 #define RT5651_PDM_I2C_CMD_W (0x1 << 10)
501 #define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
502 #define RT5651_PDM_I2C_NORMAL (0x0 << 8)
503 #define RT5651_PDM_I2C_BUSY (0x1 << 8)
505 /* PDM I2C/Data Control 2 (0x32) */
506 #define RT5651_PDM_I2C_ADDR (0xff << 8)
507 #define RT5651_PDM_I2C_CMD_PATTERN (0xff)
510 /* REC Left Mixer Control 1 (0x3b) */
511 #define RT5651_G_LN_L2_RM_L_MASK (0x7 << 13)
513 #define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
515 #define RT5651_G_BST3_RM_L_MASK (0x7 << 4)
517 #define RT5651_G_BST2_RM_L_MASK (0x7 << 1)
520 /* REC Left Mixer Control 2 (0x3c) */
521 #define RT5651_G_BST1_RM_L_MASK (0x7 << 13)
523 #define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
525 #define RT5651_M_IN2_L_RM_L (0x1 << 6)
527 #define RT5651_M_IN1_L_RM_L (0x1 << 5)
529 #define RT5651_M_BST3_RM_L (0x1 << 3)
531 #define RT5651_M_BST2_RM_L (0x1 << 2)
533 #define RT5651_M_BST1_RM_L (0x1 << 1)
535 #define RT5651_M_OM_L_RM_L (0x1)
536 #define RT5651_M_OM_L_RM_L_SFT 0
538 /* REC Right Mixer Control 1 (0x3d) */
539 #define RT5651_G_IN2_R_RM_R_MASK (0x7 << 13)
541 #define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
543 #define RT5651_G_BST3_RM_R_MASK (0x7 << 4)
545 #define RT5651_G_BST2_RM_R_MASK (0x7 << 1)
548 /* REC Right Mixer Control 2 (0x3e) */
549 #define RT5651_G_BST1_RM_R_MASK (0x7 << 13)
551 #define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
553 #define RT5651_M_IN2_R_RM_R (0x1 << 6)
555 #define RT5651_M_IN1_R_RM_R (0x1 << 5)
557 #define RT5651_M_BST3_RM_R (0x1 << 3)
559 #define RT5651_M_BST2_RM_R (0x1 << 2)
561 #define RT5651_M_BST1_RM_R (0x1 << 1)
563 #define RT5651_M_OM_R_RM_R (0x1)
564 #define RT5651_M_OM_R_RM_R_SFT 0
566 /* HPMIX Control (0x45) */
567 #define RT5651_M_DAC1_HM (0x1 << 14)
569 #define RT5651_M_HPVOL_HM (0x1 << 13)
571 #define RT5651_G_HPOMIX_MASK (0x1 << 12)
574 /* SPK Left Mixer Control (0x46) */
575 #define RT5651_G_RM_L_SM_L_MASK (0x3 << 14)
577 #define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
579 #define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
581 #define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
583 #define RT5651_G_OM_L_SM_L_MASK (0x3 << 6)
585 #define RT5651_M_RM_L_SM_L (0x1 << 5)
587 #define RT5651_M_IN_L_SM_L (0x1 << 4)
589 #define RT5651_M_DAC_L1_SM_L (0x1 << 3)
591 #define RT5651_M_DAC_L2_SM_L (0x1 << 2)
593 #define RT5651_M_OM_L_SM_L (0x1 << 1)
596 /* SPK Right Mixer Control (0x47) */
597 #define RT5651_G_RM_R_SM_R_MASK (0x3 << 14)
599 #define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
601 #define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
603 #define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
605 #define RT5651_G_OM_R_SM_R_MASK (0x3 << 6)
607 #define RT5651_M_RM_R_SM_R (0x1 << 5)
609 #define RT5651_M_IN_R_SM_R (0x1 << 4)
611 #define RT5651_M_DAC_R1_SM_R (0x1 << 3)
613 #define RT5651_M_DAC_R2_SM_R (0x1 << 2)
615 #define RT5651_M_OM_R_SM_R (0x1 << 1)
618 /* SPOLMIX Control (0x48) */
619 #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
621 #define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
623 #define RT5651_M_SV_R_SPM_L (0x1 << 13)
625 #define RT5651_M_SV_L_SPM_L (0x1 << 12)
627 #define RT5651_M_BST1_SPM_L (0x1 << 11)
630 /* SPORMIX Control (0x49) */
631 #define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
633 #define RT5651_M_SV_R_SPM_R (0x1 << 12)
635 #define RT5651_M_BST1_SPM_R (0x1 << 11)
638 /* SPOLMIX / SPORMIX Ratio Control (0x4a) */
639 #define RT5651_SPO_CLSD_RATIO_MASK (0x7)
640 #define RT5651_SPO_CLSD_RATIO_SFT 0
642 /* Mono Output Mixer Control (0x4c) */
643 #define RT5651_M_DAC_R2_MM (0x1 << 15)
645 #define RT5651_M_DAC_L2_MM (0x1 << 14)
647 #define RT5651_M_OV_R_MM (0x1 << 13)
649 #define RT5651_M_OV_L_MM (0x1 << 12)
651 #define RT5651_M_BST1_MM (0x1 << 11)
653 #define RT5651_G_MONOMIX_MASK (0x1 << 10)
656 /* Output Left Mixer Control 1 (0x4d) */
657 #define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
659 #define RT5651_G_BST1_OM_L_MASK (0x7 << 7)
661 #define RT5651_G_IN1_L_OM_L_MASK (0x7 << 4)
663 #define RT5651_G_RM_L_OM_L_MASK (0x7 << 1)
666 /* Output Left Mixer Control 2 (0x4e) */
667 #define RT5651_G_DAC_L1_OM_L_MASK (0x7 << 7)
669 #define RT5651_G_IN2_L_OM_L_MASK (0x7 << 4)
672 /* Output Left Mixer Control 3 (0x4f) */
673 #define RT5651_M_IN2_L_OM_L (0x1 << 9)
675 #define RT5651_M_BST2_OM_L (0x1 << 6)
677 #define RT5651_M_BST1_OM_L (0x1 << 5)
679 #define RT5651_M_IN1_L_OM_L (0x1 << 4)
681 #define RT5651_M_RM_L_OM_L (0x1 << 3)
683 #define RT5651_M_DAC_L1_OM_L (0x1)
684 #define RT5651_M_DAC_L1_OM_L_SFT 0
686 /* Output Right Mixer Control 1 (0x50) */
687 #define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
689 #define RT5651_G_BST1_OM_R_MASK (0x7 << 7)
691 #define RT5651_G_IN1_R_OM_R_MASK (0x7 << 4)
693 #define RT5651_G_RM_R_OM_R_MASK (0x7 << 1)
696 /* Output Right Mixer Control 2 (0x51) */
697 #define RT5651_G_DAC_R1_OM_R_MASK (0x7 << 7)
699 #define RT5651_G_IN2_R_OM_R_MASK (0x7 << 4)
702 /* Output Right Mixer Control 3 (0x52) */
703 #define RT5651_M_IN2_R_OM_R (0x1 << 9)
705 #define RT5651_M_BST2_OM_R (0x1 << 6)
707 #define RT5651_M_BST1_OM_R (0x1 << 5)
709 #define RT5651_M_IN1_R_OM_R (0x1 << 4)
711 #define RT5651_M_RM_R_OM_R (0x1 << 3)
713 #define RT5651_M_DAC_R1_OM_R (0x1)
714 #define RT5651_M_DAC_R1_OM_R_SFT 0
716 /* LOUT Mixer Control (0x53) */
717 #define RT5651_M_DAC_L1_LM (0x1 << 15)
719 #define RT5651_M_DAC_R1_LM (0x1 << 14)
721 #define RT5651_M_OV_L_LM (0x1 << 13)
723 #define RT5651_M_OV_R_LM (0x1 << 12)
725 #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
728 /* Power Management for Digital 1 (0x61) */
729 #define RT5651_PWR_I2S1 (0x1 << 15)
731 #define RT5651_PWR_I2S2 (0x1 << 14)
733 #define RT5651_PWR_DAC_L1 (0x1 << 12)
735 #define RT5651_PWR_DAC_R1 (0x1 << 11)
737 #define RT5651_PWR_ADC_L (0x1 << 2)
739 #define RT5651_PWR_ADC_R (0x1 << 1)
742 /* Power Management for Digital 2 (0x62) */
743 #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
745 #define RT5651_PWR_ADC_STO2_F (0x1 << 14)
747 #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
749 #define RT5651_PWR_DAC_STO2_F (0x1 << 10)
751 #define RT5651_PWR_PDM (0x1 << 9)
754 /* Power Management for Analog 1 (0x63) */
755 #define RT5651_PWR_VREF1 (0x1 << 15)
757 #define RT5651_PWR_FV1 (0x1 << 14)
759 #define RT5651_PWR_MB (0x1 << 13)
761 #define RT5651_PWR_LM (0x1 << 12)
763 #define RT5651_PWR_BG (0x1 << 11)
765 #define RT5651_PWR_HP_L (0x1 << 7)
767 #define RT5651_PWR_HP_R (0x1 << 6)
769 #define RT5651_PWR_HA (0x1 << 5)
771 #define RT5651_PWR_VREF2 (0x1 << 4)
773 #define RT5651_PWR_FV2 (0x1 << 3)
775 #define RT5651_PWR_LDO (0x1 << 2)
777 #define RT5651_PWR_LDO_DVO_MASK (0x3)
778 #define RT5651_PWR_LDO_DVO_1_0V 0
783 /* Power Management for Analog 2 (0x64) */
784 #define RT5651_PWR_BST1 (0x1 << 15)
786 #define RT5651_PWR_BST2 (0x1 << 14)
788 #define RT5651_PWR_BST3 (0x1 << 13)
790 #define RT5651_PWR_MB1 (0x1 << 11)
792 #define RT5651_PWR_PLL (0x1 << 9)
794 #define RT5651_PWR_BST1_OP2 (0x1 << 5)
796 #define RT5651_PWR_BST2_OP2 (0x1 << 4)
798 #define RT5651_PWR_BST3_OP2 (0x1 << 3)
800 #define RT5651_PWR_JD_M (0x1 << 2)
802 #define RT5651_PWR_JD2 (0x1 << 1)
804 #define RT5651_PWR_JD3 (0x1)
805 #define RT5651_PWM_JD3_BIT 0
807 /* Power Management for Mixer (0x65) */
808 #define RT5651_PWR_OM_L (0x1 << 15)
810 #define RT5651_PWR_OM_R (0x1 << 14)
812 #define RT5651_PWR_RM_L (0x1 << 11)
814 #define RT5651_PWR_RM_R (0x1 << 10)
817 /* Power Management for Volume (0x66) */
818 #define RT5651_PWR_OV_L (0x1 << 13)
820 #define RT5651_PWR_OV_R (0x1 << 12)
822 #define RT5651_PWR_HV_L (0x1 << 11)
824 #define RT5651_PWR_HV_R (0x1 << 10)
826 #define RT5651_PWR_IN1_L (0x1 << 9)
828 #define RT5651_PWR_IN1_R (0x1 << 8)
830 #define RT5651_PWR_IN2_L (0x1 << 7)
832 #define RT5651_PWR_IN2_R (0x1 << 6)
835 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
836 #define RT5651_I2S_MS_MASK (0x1 << 15)
838 #define RT5651_I2S_MS_M (0x0 << 15)
839 #define RT5651_I2S_MS_S (0x1 << 15)
840 #define RT5651_I2S_O_CP_MASK (0x3 << 10)
842 #define RT5651_I2S_O_CP_OFF (0x0 << 10)
843 #define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
844 #define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
845 #define RT5651_I2S_I_CP_MASK (0x3 << 8)
847 #define RT5651_I2S_I_CP_OFF (0x0 << 8)
848 #define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
849 #define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
850 #define RT5651_I2S_BP_MASK (0x1 << 7)
852 #define RT5651_I2S_BP_NOR (0x0 << 7)
853 #define RT5651_I2S_BP_INV (0x1 << 7)
854 #define RT5651_I2S_DL_MASK (0x3 << 2)
856 #define RT5651_I2S_DL_16 (0x0 << 2)
857 #define RT5651_I2S_DL_20 (0x1 << 2)
858 #define RT5651_I2S_DL_24 (0x2 << 2)
859 #define RT5651_I2S_DL_8 (0x3 << 2)
860 #define RT5651_I2S_DF_MASK (0x3)
861 #define RT5651_I2S_DF_SFT 0
862 #define RT5651_I2S_DF_I2S (0x0)
863 #define RT5651_I2S_DF_LEFT (0x1)
864 #define RT5651_I2S_DF_PCM_A (0x2)
865 #define RT5651_I2S_DF_PCM_B (0x3)
867 /* ADC/DAC Clock Control 1 (0x73) */
868 #define RT5651_I2S_PD1_MASK (0x7 << 12)
870 #define RT5651_I2S_PD1_1 (0x0 << 12)
871 #define RT5651_I2S_PD1_2 (0x1 << 12)
872 #define RT5651_I2S_PD1_3 (0x2 << 12)
873 #define RT5651_I2S_PD1_4 (0x3 << 12)
874 #define RT5651_I2S_PD1_6 (0x4 << 12)
875 #define RT5651_I2S_PD1_8 (0x5 << 12)
876 #define RT5651_I2S_PD1_12 (0x6 << 12)
877 #define RT5651_I2S_PD1_16 (0x7 << 12)
878 #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
880 #define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
881 #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
882 #define RT5651_I2S_PD2_MASK (0x7 << 8)
884 #define RT5651_I2S_PD2_1 (0x0 << 8)
885 #define RT5651_I2S_PD2_2 (0x1 << 8)
886 #define RT5651_I2S_PD2_3 (0x2 << 8)
887 #define RT5651_I2S_PD2_4 (0x3 << 8)
888 #define RT5651_I2S_PD2_6 (0x4 << 8)
889 #define RT5651_I2S_PD2_8 (0x5 << 8)
890 #define RT5651_I2S_PD2_12 (0x6 << 8)
891 #define RT5651_I2S_PD2_16 (0x7 << 8)
892 #define RT5651_DAC_OSR_MASK (0x3 << 2)
894 #define RT5651_DAC_OSR_128 (0x0 << 2)
895 #define RT5651_DAC_OSR_64 (0x1 << 2)
896 #define RT5651_DAC_OSR_32 (0x2 << 2)
897 #define RT5651_DAC_OSR_128_3 (0x3 << 2)
898 #define RT5651_ADC_OSR_MASK (0x3)
899 #define RT5651_ADC_OSR_SFT 0
900 #define RT5651_ADC_OSR_128 (0x0)
901 #define RT5651_ADC_OSR_64 (0x1)
902 #define RT5651_ADC_OSR_32 (0x2)
903 #define RT5651_ADC_OSR_128_3 (0x3)
905 /* ADC/DAC Clock Control 2 (0x74) */
906 #define RT5651_DAHPF_EN (0x1 << 11)
908 #define RT5651_ADHPF_EN (0x1 << 10)
911 /* Digital Microphone Control (0x75) */
912 #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
914 #define RT5651_DMIC_1_DIS (0x0 << 15)
915 #define RT5651_DMIC_1_EN (0x1 << 15)
916 #define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
918 #define RT5651_DMIC_1L_LH_FALLING (0x0 << 13)
919 #define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
920 #define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
922 #define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
923 #define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
924 #define RT5651_DMIC_1_DP_MASK (0x3 << 10)
926 #define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
927 #define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
928 #define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
929 #define RT5651_DMIC_CLK_MASK (0x7 << 5)
932 /* TDM Control 1 (0x77) */
933 #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
935 #define RT5651_TDM_INTEL_SEL_64 (0x0 << 15)
936 #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
937 #define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
939 #define RT5651_TDM_MODE_SEL_NOR (0x0 << 14)
940 #define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
941 #define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
943 #define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
944 #define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
945 #define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
946 #define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
947 #define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
949 #define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
950 #define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
951 #define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
952 #define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
953 #define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
955 #define RT5651_TDM_ADC_SEL_NOR (0x0 << 9)
956 #define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
957 #define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
959 #define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
960 #define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
961 #define RT5651_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
963 #define RT5651_TDM_I2S_CH2_SEL_LR (0x0 << 6)
964 #define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
965 #define RT5651_TDM_I2S_CH2_SEL_LL (0x2 << 6)
966 #define RT5651_TDM_I2S_CH2_SEL_RR (0x3 << 6)
967 #define RT5651_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
969 #define RT5651_TDM_I2S_CH4_SEL_LR (0x0 << 4)
970 #define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
971 #define RT5651_TDM_I2S_CH4_SEL_LL (0x2 << 4)
972 #define RT5651_TDM_I2S_CH4_SEL_RR (0x3 << 4)
973 #define RT5651_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
975 #define RT5651_TDM_I2S_CH6_SEL_LR (0x0 << 2)
976 #define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
977 #define RT5651_TDM_I2S_CH6_SEL_LL (0x2 << 2)
978 #define RT5651_TDM_I2S_CH6_SEL_RR (0x3 << 2)
979 #define RT5651_TDM_I2S_CH8_SEL_MASK (0x3)
980 #define RT5651_TDM_I2S_CH8_SEL_SFT 0
981 #define RT5651_TDM_I2S_CH8_SEL_LR (0x0)
982 #define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
983 #define RT5651_TDM_I2S_CH8_SEL_LL (0x2)
984 #define RT5651_TDM_I2S_CH8_SEL_RR (0x3)
986 /* TDM Control 2 (0x78) */
987 #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
989 #define RT5651_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
990 #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
991 #define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
993 #define RT5651_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
994 #define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
995 #define RT5651_TDM_CH_VAL_EN (0x1 << 13)
997 #define RT5651_TDM_LPBK_EN (0x1 << 12)
999 #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
1001 #define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
1002 #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1003 #define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1005 #define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1006 #define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1007 #define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1009 #define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1011 #define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1012 #define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1013 #define RT5651_M_TDM2_L (0x1 << 7)
1015 #define RT5651_M_TDM2_R (0x1 << 6)
1017 #define RT5651_M_TDM4_L (0x1 << 5)
1019 #define RT5651_M_TDM4_R (0x1 << 4)
1022 /* TDM Control 3 (0x79) */
1023 #define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1025 #define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1026 #define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1027 #define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1028 #define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1029 #define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1030 #define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1031 #define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1032 #define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1033 #define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1035 #define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1036 #define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1037 #define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1038 #define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1039 #define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1040 #define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1041 #define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1042 #define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1043 #define RT5651_CH4_L_SEL_MASK (0x7 << 4)
1045 #define RT5651_CH4_L_SEL_SL0 (0x0 << 4)
1046 #define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1047 #define RT5651_CH4_L_SEL_SL2 (0x2 << 4)
1048 #define RT5651_CH4_L_SEL_SL3 (0x3 << 4)
1049 #define RT5651_CH4_L_SEL_SL4 (0x4 << 4)
1050 #define RT5651_CH4_L_SEL_SL5 (0x5 << 4)
1051 #define RT5651_CH4_L_SEL_SL6 (0x6 << 4)
1052 #define RT5651_CH4_L_SEL_SL7 (0x7 << 4)
1053 #define RT5651_CH4_R_SEL_MASK (0x7)
1054 #define RT5651_CH4_R_SEL_SFT 0
1055 #define RT5651_CH4_R_SEL_SL0 (0x0)
1056 #define RT5651_CH4_R_SEL_SL1 (0x1)
1057 #define RT5651_CH4_R_SEL_SL2 (0x2)
1058 #define RT5651_CH4_R_SEL_SL3 (0x3)
1059 #define RT5651_CH4_R_SEL_SL4 (0x4)
1060 #define RT5651_CH4_R_SEL_SL5 (0x5)
1061 #define RT5651_CH4_R_SEL_SL6 (0x6)
1062 #define RT5651_CH4_R_SEL_SL7 (0x7)
1064 /* Global Clock Control (0x80) */
1065 #define RT5651_SCLK_SRC_MASK (0x3 << 14)
1067 #define RT5651_SCLK_SRC_MCLK (0x0 << 14)
1068 #define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1069 #define RT5651_SCLK_SRC_RCCLK (0x2 << 14)
1070 #define RT5651_PLL1_SRC_MASK (0x3 << 12)
1072 #define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1073 #define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1074 #define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1075 #define RT5651_PLL1_PD_MASK (0x1 << 3)
1077 #define RT5651_PLL1_PD_1 (0x0 << 3)
1078 #define RT5651_PLL1_PD_2 (0x1 << 3)
1082 /* PLL M/N/K Code Control 1 (0x81) */
1083 #define RT5651_PLL_N_MAX 0x1ff
1086 #define RT5651_PLL_K_MAX 0x1f
1088 #define RT5651_PLL_K_SFT 0
1090 /* PLL M/N/K Code Control 2 (0x82) */
1091 #define RT5651_PLL_M_MAX 0xf
1094 #define RT5651_PLL_M_BP (0x1 << 11)
1097 /* PLL tracking mode 1 (0x83) */
1098 #define RT5651_STO1_T_MASK (0x1 << 15)
1100 #define RT5651_STO1_T_SCLK (0x0 << 15)
1101 #define RT5651_STO1_T_LRCK1 (0x1 << 15)
1102 #define RT5651_STO2_T_MASK (0x1 << 12)
1104 #define RT5651_STO2_T_I2S2 (0x0 << 12)
1105 #define RT5651_STO2_T_LRCK2 (0x1 << 12)
1106 #define RT5651_ASRC2_REF_MASK (0x1 << 11)
1108 #define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1109 #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1110 #define RT5651_DMIC_1_M_MASK (0x1 << 9)
1112 #define RT5651_DMIC_1_M_NOR (0x0 << 9)
1113 #define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1115 /* PLL tracking mode 2 (0x84) */
1116 #define RT5651_STO1_ASRC_EN (0x1 << 15)
1118 #define RT5651_STO2_ASRC_EN (0x1 << 14)
1120 #define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1122 #define RT5651_STO1_DAC_M_NOR (0x0 << 13)
1123 #define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1124 #define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1126 #define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1127 #define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1128 #define RT5651_ADC_M_MASK (0x1 << 11)
1130 #define RT5651_ADC_M_NOR (0x0 << 11)
1131 #define RT5651_ADC_M_ASRC (0x1 << 11)
1132 #define RT5651_I2S1_R_D_MASK (0x1 << 4)
1134 #define RT5651_I2S1_R_D_DIS (0x0 << 4)
1135 #define RT5651_I2S1_R_D_EN (0x1 << 4)
1136 #define RT5651_I2S2_R_D_MASK (0x1 << 3)
1138 #define RT5651_I2S2_R_D_DIS (0x0 << 3)
1139 #define RT5651_I2S2_R_D_EN (0x1 << 3)
1140 #define RT5651_PRE_SCLK_MASK (0x3)
1141 #define RT5651_PRE_SCLK_SFT 0
1142 #define RT5651_PRE_SCLK_512 (0x0)
1143 #define RT5651_PRE_SCLK_1024 (0x1)
1144 #define RT5651_PRE_SCLK_2048 (0x2)
1146 /* PLL tracking mode 3 (0x85) */
1147 #define RT5651_I2S1_RATE_MASK (0xf << 12)
1149 #define RT5651_I2S2_RATE_MASK (0xf << 8)
1151 #define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1153 #define RT5651_ASRC_LP_F_M (0x1 << 2)
1155 #define RT5651_ASRC_LP_F_NOR (0x0 << 2)
1156 #define RT5651_ASRC_LP_F_SB (0x1 << 2)
1157 #define RT5651_FTK_PH_DET_MASK (0x3)
1158 #define RT5651_FTK_PH_DET_SFT 0
1159 #define RT5651_FTK_PH_DET_DIV1 (0x0)
1160 #define RT5651_FTK_PH_DET_DIV2 (0x1)
1161 #define RT5651_FTK_PH_DET_DIV4 (0x2)
1162 #define RT5651_FTK_PH_DET_DIV8 (0x3)
1164 /*PLL tracking mode 6 (0x89) */
1165 #define RT5651_I2S1_PD_MASK (0x7 << 12)
1167 #define RT5651_I2S2_PD_MASK (0x7 << 8)
1170 /*PLL tracking mode 7 (0x8a) */
1171 #define RT5651_FSI1_RATE_MASK (0xf << 12)
1173 #define RT5651_FSI2_RATE_MASK (0xf << 8)
1176 /* HPOUT Over Current Detection (0x8b) */
1177 #define RT5651_HP_OVCD_MASK (0x1 << 10)
1179 #define RT5651_HP_OVCD_DIS (0x0 << 10)
1180 #define RT5651_HP_OVCD_EN (0x1 << 10)
1181 #define RT5651_HP_OC_TH_MASK (0x3 << 8)
1183 #define RT5651_HP_OC_TH_90 (0x0 << 8)
1184 #define RT5651_HP_OC_TH_105 (0x1 << 8)
1185 #define RT5651_HP_OC_TH_120 (0x2 << 8)
1186 #define RT5651_HP_OC_TH_135 (0x3 << 8)
1188 /* Depop Mode Control 1 (0x8e) */
1189 #define RT5651_SMT_TRIG_MASK (0x1 << 15)
1191 #define RT5651_SMT_TRIG_DIS (0x0 << 15)
1192 #define RT5651_SMT_TRIG_EN (0x1 << 15)
1193 #define RT5651_HP_L_SMT_MASK (0x1 << 9)
1195 #define RT5651_HP_L_SMT_DIS (0x0 << 9)
1196 #define RT5651_HP_L_SMT_EN (0x1 << 9)
1197 #define RT5651_HP_R_SMT_MASK (0x1 << 8)
1199 #define RT5651_HP_R_SMT_DIS (0x0 << 8)
1200 #define RT5651_HP_R_SMT_EN (0x1 << 8)
1201 #define RT5651_HP_CD_PD_MASK (0x1 << 7)
1203 #define RT5651_HP_CD_PD_DIS (0x0 << 7)
1204 #define RT5651_HP_CD_PD_EN (0x1 << 7)
1205 #define RT5651_RSTN_MASK (0x1 << 6)
1207 #define RT5651_RSTN_DIS (0x0 << 6)
1208 #define RT5651_RSTN_EN (0x1 << 6)
1209 #define RT5651_RSTP_MASK (0x1 << 5)
1211 #define RT5651_RSTP_DIS (0x0 << 5)
1212 #define RT5651_RSTP_EN (0x1 << 5)
1213 #define RT5651_HP_CO_MASK (0x1 << 4)
1215 #define RT5651_HP_CO_DIS (0x0 << 4)
1216 #define RT5651_HP_CO_EN (0x1 << 4)
1217 #define RT5651_HP_CP_MASK (0x1 << 3)
1219 #define RT5651_HP_CP_PD (0x0 << 3)
1220 #define RT5651_HP_CP_PU (0x1 << 3)
1221 #define RT5651_HP_SG_MASK (0x1 << 2)
1223 #define RT5651_HP_SG_DIS (0x0 << 2)
1224 #define RT5651_HP_SG_EN (0x1 << 2)
1225 #define RT5651_HP_DP_MASK (0x1 << 1)
1227 #define RT5651_HP_DP_PD (0x0 << 1)
1228 #define RT5651_HP_DP_PU (0x1 << 1)
1229 #define RT5651_HP_CB_MASK (0x1)
1230 #define RT5651_HP_CB_SFT 0
1231 #define RT5651_HP_CB_PD (0x0)
1232 #define RT5651_HP_CB_PU (0x1)
1234 /* Depop Mode Control 2 (0x8f) */
1235 #define RT5651_DEPOP_MASK (0x1 << 13)
1237 #define RT5651_DEPOP_AUTO (0x0 << 13)
1238 #define RT5651_DEPOP_MAN (0x1 << 13)
1239 #define RT5651_RAMP_MASK (0x1 << 12)
1241 #define RT5651_RAMP_DIS (0x0 << 12)
1242 #define RT5651_RAMP_EN (0x1 << 12)
1243 #define RT5651_BPS_MASK (0x1 << 11)
1245 #define RT5651_BPS_DIS (0x0 << 11)
1246 #define RT5651_BPS_EN (0x1 << 11)
1247 #define RT5651_FAST_UPDN_MASK (0x1 << 10)
1249 #define RT5651_FAST_UPDN_DIS (0x0 << 10)
1250 #define RT5651_FAST_UPDN_EN (0x1 << 10)
1251 #define RT5651_MRES_MASK (0x3 << 8)
1253 #define RT5651_MRES_15MO (0x0 << 8)
1254 #define RT5651_MRES_25MO (0x1 << 8)
1255 #define RT5651_MRES_35MO (0x2 << 8)
1256 #define RT5651_MRES_45MO (0x3 << 8)
1257 #define RT5651_VLO_MASK (0x1 << 7)
1259 #define RT5651_VLO_3V (0x0 << 7)
1260 #define RT5651_VLO_32V (0x1 << 7)
1261 #define RT5651_DIG_DP_MASK (0x1 << 6)
1263 #define RT5651_DIG_DP_DIS (0x0 << 6)
1264 #define RT5651_DIG_DP_EN (0x1 << 6)
1265 #define RT5651_DP_TH_MASK (0x3 << 4)
1268 /* Depop Mode Control 3 (0x90) */
1269 #define RT5651_CP_SYS_MASK (0x7 << 12)
1271 #define RT5651_CP_FQ1_MASK (0x7 << 8)
1273 #define RT5651_CP_FQ2_MASK (0x7 << 4)
1275 #define RT5651_CP_FQ3_MASK (0x7)
1276 #define RT5651_CP_FQ3_SFT 0
1277 #define RT5651_CP_FQ_1_5_KHZ 0
1286 /* HPOUT charge pump (0x91) */
1287 #define RT5651_OSW_L_MASK (0x1 << 11)
1289 #define RT5651_OSW_L_DIS (0x0 << 11)
1290 #define RT5651_OSW_L_EN (0x1 << 11)
1291 #define RT5651_OSW_R_MASK (0x1 << 10)
1293 #define RT5651_OSW_R_DIS (0x0 << 10)
1294 #define RT5651_OSW_R_EN (0x1 << 10)
1295 #define RT5651_PM_HP_MASK (0x3 << 8)
1297 #define RT5651_PM_HP_LV (0x0 << 8)
1298 #define RT5651_PM_HP_MV (0x1 << 8)
1299 #define RT5651_PM_HP_HV (0x2 << 8)
1300 #define RT5651_IB_HP_MASK (0x3 << 6)
1302 #define RT5651_IB_HP_125IL (0x0 << 6)
1303 #define RT5651_IB_HP_25IL (0x1 << 6)
1304 #define RT5651_IB_HP_5IL (0x2 << 6)
1305 #define RT5651_IB_HP_1IL (0x3 << 6)
1307 /* Micbias Control (0x93) */
1308 #define RT5651_MIC1_BS_MASK (0x1 << 15)
1310 #define RT5651_MIC1_BS_9AV (0x0 << 15)
1311 #define RT5651_MIC1_BS_75AV (0x1 << 15)
1312 #define RT5651_MIC1_CLK_MASK (0x1 << 13)
1314 #define RT5651_MIC1_CLK_DIS (0x0 << 13)
1315 #define RT5651_MIC1_CLK_EN (0x1 << 13)
1316 #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1318 #define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1319 #define RT5651_MIC1_OVCD_EN (0x1 << 11)
1320 #define RT5651_MIC1_OVTH_MASK (0x3 << 9)
1322 #define RT5651_MIC1_OVTH_600UA (0x0 << 9)
1323 #define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1324 #define RT5651_MIC1_OVTH_2000UA (0x2 << 9)
1325 #define RT5651_PWR_MB_MASK (0x1 << 5)
1327 #define RT5651_PWR_MB_PD (0x0 << 5)
1328 #define RT5651_PWR_MB_PU (0x1 << 5)
1329 #define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1331 #define RT5651_PWR_CLK12M_PD (0x0 << 4)
1332 #define RT5651_PWR_CLK12M_PU (0x1 << 4)
1334 /* Analog JD Control 1 (0x94) */
1335 #define RT5651_JD2_CMP_MASK (0x7 << 12)
1337 #define RT5651_JD_PU (0x1 << 11)
1339 #define RT5651_JD_PD (0x1 << 10)
1341 #define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1343 #define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1344 #define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1345 #define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1346 #define RT5651_JD_M_CMP (0x7 << 4)
1348 #define RT5651_JD_M_PU (0x1 << 3)
1350 #define RT5651_JD_M_PD (0x1 << 2)
1352 #define RT5651_JD_M_MODE_SEL_MASK (0x3)
1353 #define RT5651_JD_M_MODE_SEL_SFT 0
1354 #define RT5651_JD_M_MODE_SEL_M0 (0x0)
1355 #define RT5651_JD_M_MODE_SEL_M1 (0x1)
1356 #define RT5651_JD_M_MODE_SEL_M2 (0x2)
1358 /* Analog JD Control 2 (0x95) */
1359 #define RT5651_JD3_CMP_MASK (0x7 << 12)
1362 /* EQ Control 1 (0xb0) */
1363 #define RT5651_EQ_SRC_MASK (0x1 << 15)
1365 #define RT5651_EQ_SRC_DAC (0x0 << 15)
1366 #define RT5651_EQ_SRC_ADC (0x1 << 15)
1367 #define RT5651_EQ_UPD (0x1 << 14)
1369 #define RT5651_EQ_CD_MASK (0x1 << 13)
1371 #define RT5651_EQ_CD_DIS (0x0 << 13)
1372 #define RT5651_EQ_CD_EN (0x1 << 13)
1373 #define RT5651_EQ_DITH_MASK (0x3 << 8)
1375 #define RT5651_EQ_DITH_NOR (0x0 << 8)
1376 #define RT5651_EQ_DITH_LSB (0x1 << 8)
1377 #define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1378 #define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1379 #define RT5651_EQ_CD_F (0x1 << 7)
1381 #define RT5651_EQ_STA_HP2 (0x1 << 6)
1383 #define RT5651_EQ_STA_HP1 (0x1 << 5)
1385 #define RT5651_EQ_STA_BP4 (0x1 << 4)
1387 #define RT5651_EQ_STA_BP3 (0x1 << 3)
1389 #define RT5651_EQ_STA_BP2 (0x1 << 2)
1391 #define RT5651_EQ_STA_BP1 (0x1 << 1)
1393 #define RT5651_EQ_STA_LP (0x1)
1394 #define RT5651_EQ_STA_LP_BIT 0
1396 /* EQ Control 2 (0xb1) */
1397 #define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1399 #define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1400 #define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1401 #define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1403 #define RT5651_EQ_LPF1_M_LO (0x0 << 7)
1404 #define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1405 #define RT5651_EQ_HPF2_MASK (0x1 << 6)
1407 #define RT5651_EQ_HPF2_DIS (0x0 << 6)
1408 #define RT5651_EQ_HPF2_EN (0x1 << 6)
1409 #define RT5651_EQ_HPF1_MASK (0x1 << 5)
1411 #define RT5651_EQ_HPF1_DIS (0x0 << 5)
1412 #define RT5651_EQ_HPF1_EN (0x1 << 5)
1413 #define RT5651_EQ_BPF4_MASK (0x1 << 4)
1415 #define RT5651_EQ_BPF4_DIS (0x0 << 4)
1416 #define RT5651_EQ_BPF4_EN (0x1 << 4)
1417 #define RT5651_EQ_BPF3_MASK (0x1 << 3)
1419 #define RT5651_EQ_BPF3_DIS (0x0 << 3)
1420 #define RT5651_EQ_BPF3_EN (0x1 << 3)
1421 #define RT5651_EQ_BPF2_MASK (0x1 << 2)
1423 #define RT5651_EQ_BPF2_DIS (0x0 << 2)
1424 #define RT5651_EQ_BPF2_EN (0x1 << 2)
1425 #define RT5651_EQ_BPF1_MASK (0x1 << 1)
1427 #define RT5651_EQ_BPF1_DIS (0x0 << 1)
1428 #define RT5651_EQ_BPF1_EN (0x1 << 1)
1429 #define RT5651_EQ_LPF_MASK (0x1)
1430 #define RT5651_EQ_LPF_SFT 0
1431 #define RT5651_EQ_LPF_DIS (0x0)
1432 #define RT5651_EQ_LPF_EN (0x1)
1433 #define RT5651_EQ_CTRL_MASK (0x7f)
1435 /* Memory Test (0xb2) */
1436 #define RT5651_MT_MASK (0x1 << 15)
1438 #define RT5651_MT_DIS (0x0 << 15)
1439 #define RT5651_MT_EN (0x1 << 15)
1441 /* ALC Control 1 (0xb4) */
1442 #define RT5651_ALC_P_MASK (0x1 << 15)
1444 #define RT5651_ALC_P_DAC (0x0 << 15)
1445 #define RT5651_ALC_P_ADC (0x1 << 15)
1446 #define RT5651_ALC_MASK (0x1 << 14)
1448 #define RT5651_ALC_DIS (0x0 << 14)
1449 #define RT5651_ALC_EN (0x1 << 14)
1450 #define RT5651_ALC_UPD (0x1 << 13)
1452 #define RT5651_ALC_AR_MASK (0x1f << 8)
1454 #define RT5651_ALC_R_MASK (0x7 << 5)
1456 #define RT5651_ALC_R_48K (0x1 << 5)
1457 #define RT5651_ALC_R_96K (0x2 << 5)
1458 #define RT5651_ALC_R_192K (0x3 << 5)
1459 #define RT5651_ALC_R_441K (0x5 << 5)
1460 #define RT5651_ALC_R_882K (0x6 << 5)
1461 #define RT5651_ALC_R_1764K (0x7 << 5)
1462 #define RT5651_ALC_RC_MASK (0x1f)
1463 #define RT5651_ALC_RC_SFT 0
1465 /* ALC Control 2 (0xb5) */
1466 #define RT5651_ALC_POB_MASK (0x3f << 8)
1468 #define RT5651_ALC_DRC_MASK (0x1 << 7)
1470 #define RT5651_ALC_DRC_DIS (0x0 << 7)
1471 #define RT5651_ALC_DRC_EN (0x1 << 7)
1472 #define RT5651_ALC_CPR_MASK (0x3 << 5)
1474 #define RT5651_ALC_CPR_1_1 (0x0 << 5)
1475 #define RT5651_ALC_CPR_1_2 (0x1 << 5)
1476 #define RT5651_ALC_CPR_1_4 (0x2 << 5)
1477 #define RT5651_ALC_CPR_1_8 (0x3 << 5)
1478 #define RT5651_ALC_PRB_MASK (0x1f)
1479 #define RT5651_ALC_PRB_SFT 0
1481 /* ALC Control 3 (0xb6) */
1482 #define RT5651_ALC_NGB_MASK (0xf << 12)
1484 #define RT5651_ALC_TAR_MASK (0x1f << 7)
1486 #define RT5651_ALC_NG_MASK (0x1 << 6)
1488 #define RT5651_ALC_NG_DIS (0x0 << 6)
1489 #define RT5651_ALC_NG_EN (0x1 << 6)
1490 #define RT5651_ALC_NGH_MASK (0x1 << 5)
1492 #define RT5651_ALC_NGH_DIS (0x0 << 5)
1493 #define RT5651_ALC_NGH_EN (0x1 << 5)
1494 #define RT5651_ALC_NGT_MASK (0x1f)
1495 #define RT5651_ALC_NGT_SFT 0
1497 /* Jack Detect Control 1 (0xbb) */
1498 #define RT5651_JD_MASK (0x7 << 13)
1500 #define RT5651_JD_DIS (0x0 << 13)
1501 #define RT5651_JD_GPIO1 (0x1 << 13)
1502 #define RT5651_JD_GPIO2 (0x2 << 13)
1503 #define RT5651_JD_GPIO3 (0x3 << 13)
1504 #define RT5651_JD_GPIO4 (0x4 << 13)
1505 #define RT5651_JD_GPIO5 (0x5 << 13)
1506 #define RT5651_JD_GPIO6 (0x6 << 13)
1507 #define RT5651_JD_HP_MASK (0x1 << 11)
1509 #define RT5651_JD_HP_DIS (0x0 << 11)
1510 #define RT5651_JD_HP_EN (0x1 << 11)
1511 #define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1513 #define RT5651_JD_HP_TRG_LO (0x0 << 10)
1514 #define RT5651_JD_HP_TRG_HI (0x1 << 10)
1515 #define RT5651_JD_SPL_MASK (0x1 << 9)
1517 #define RT5651_JD_SPL_DIS (0x0 << 9)
1518 #define RT5651_JD_SPL_EN (0x1 << 9)
1519 #define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1521 #define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1522 #define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1523 #define RT5651_JD_SPR_MASK (0x1 << 7)
1525 #define RT5651_JD_SPR_DIS (0x0 << 7)
1526 #define RT5651_JD_SPR_EN (0x1 << 7)
1527 #define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1529 #define RT5651_JD_SPR_TRG_LO (0x0 << 6)
1530 #define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1531 #define RT5651_JD_LO_MASK (0x1 << 3)
1533 #define RT5651_JD_LO_DIS (0x0 << 3)
1534 #define RT5651_JD_LO_EN (0x1 << 3)
1535 #define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1537 #define RT5651_JD_LO_TRG_LO (0x0 << 2)
1538 #define RT5651_JD_LO_TRG_HI (0x1 << 2)
1540 /* Jack Detect Control 2 (0xbc) */
1541 #define RT5651_JD_TRG_SEL_MASK (0x7 << 9)
1543 #define RT5651_JD_TRG_SEL_GPIO (0x0 << 9)
1544 #define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1545 #define RT5651_JD_TRG_SEL_JD1_2 (0x2 << 9)
1546 #define RT5651_JD_TRG_SEL_JD2 (0x3 << 9)
1547 #define RT5651_JD_TRG_SEL_JD3 (0x4 << 9)
1548 #define RT5651_JD3_IRQ_EN (0x1 << 8)
1550 #define RT5651_JD3_EN_STKY (0x1 << 7)
1552 #define RT5651_JD3_INV (0x1 << 6)
1555 /* IRQ Control 1 (0xbd) */
1556 #define RT5651_IRQ_JD_MASK (0x1 << 15)
1558 #define RT5651_IRQ_JD_BP (0x0 << 15)
1559 #define RT5651_IRQ_JD_NOR (0x1 << 15)
1560 #define RT5651_JD_STKY_MASK (0x1 << 13)
1562 #define RT5651_JD_STKY_DIS (0x0 << 13)
1563 #define RT5651_JD_STKY_EN (0x1 << 13)
1564 #define RT5651_JD_P_MASK (0x1 << 11)
1566 #define RT5651_JD_P_NOR (0x0 << 11)
1567 #define RT5651_JD_P_INV (0x1 << 11)
1568 #define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1570 #define RT5651_JD1_1_EN_STKY (0x1 << 8)
1572 #define RT5651_JD1_1_INV (0x1 << 7)
1574 #define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1576 #define RT5651_JD1_2_EN_STKY (0x1 << 5)
1578 #define RT5651_JD1_2_INV (0x1 << 4)
1580 #define RT5651_JD2_IRQ_EN (0x1 << 3)
1582 #define RT5651_JD2_EN_STKY (0x1 << 2)
1584 #define RT5651_JD2_INV (0x1 << 1)
1587 /* IRQ Control 2 (0xbe) */
1588 #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1590 #define RT5651_IRQ_MB1_OC_BP (0x0 << 15)
1591 #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1592 #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1594 #define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1595 #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1596 #define RT5651_MB1_OC_P_MASK (0x1 << 7)
1598 #define RT5651_MB1_OC_P_NOR (0x0 << 7)
1599 #define RT5651_MB1_OC_P_INV (0x1 << 7)
1600 #define RT5651_MB2_OC_P_MASK (0x1 << 6)
1601 #define RT5651_MB1_OC_CLR (0x1 << 3)
1603 #define RT5651_STA_GPIO8 (0x1)
1604 #define RT5651_STA_GPIO8_BIT 0
1606 /* Internal Status and GPIO status (0xbf) */
1607 #define RT5651_STA_JD3 (0x1 << 15)
1609 #define RT5651_STA_JD2 (0x1 << 14)
1611 #define RT5651_STA_JD1_2 (0x1 << 13)
1613 #define RT5651_STA_JD1_1 (0x1 << 12)
1615 #define RT5651_STA_GP7 (0x1 << 11)
1617 #define RT5651_STA_GP6 (0x1 << 10)
1619 #define RT5651_STA_GP5 (0x1 << 9)
1621 #define RT5651_STA_GP1 (0x1 << 8)
1623 #define RT5651_STA_GP2 (0x1 << 7)
1625 #define RT5651_STA_GP3 (0x1 << 6)
1627 #define RT5651_STA_GP4 (0x1 << 5)
1629 #define RT5651_STA_GP_JD (0x1 << 4)
1632 /* GPIO Control 1 (0xc0) */
1633 #define RT5651_GP1_PIN_MASK (0x1 << 15)
1635 #define RT5651_GP1_PIN_GPIO1 (0x0 << 15)
1636 #define RT5651_GP1_PIN_IRQ (0x1 << 15)
1637 #define RT5651_GP2_PIN_MASK (0x1 << 14)
1639 #define RT5651_GP2_PIN_GPIO2 (0x0 << 14)
1640 #define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1641 #define RT5651_GPIO_M_MASK (0x1 << 9)
1643 #define RT5651_GPIO_M_FLT (0x0 << 9)
1644 #define RT5651_GPIO_M_PH (0x1 << 9)
1645 #define RT5651_I2S2_SEL_MASK (0x1 << 8)
1647 #define RT5651_I2S2_SEL_I2S (0x0 << 8)
1648 #define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1649 #define RT5651_GP5_PIN_MASK (0x1 << 7)
1651 #define RT5651_GP5_PIN_GPIO5 (0x0 << 7)
1652 #define RT5651_GP5_PIN_IRQ (0x1 << 7)
1653 #define RT5651_GP6_PIN_MASK (0x1 << 6)
1655 #define RT5651_GP6_PIN_GPIO6 (0x0 << 6)
1656 #define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1657 #define RT5651_GP7_PIN_MASK (0x1 << 5)
1659 #define RT5651_GP7_PIN_GPIO7 (0x0 << 5)
1660 #define RT5651_GP7_PIN_IRQ (0x1 << 5)
1661 #define RT5651_GP8_PIN_MASK (0x1 << 4)
1663 #define RT5651_GP8_PIN_GPIO8 (0x0 << 4)
1664 #define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1665 #define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1667 #define RT5651_GPIO_PDM_SEL_GPIO (0x0 << 3)
1668 #define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1670 /* GPIO Control 2 (0xc1) */
1671 #define RT5651_GP5_DR_MASK (0x1 << 14)
1673 #define RT5651_GP5_DR_IN (0x0 << 14)
1674 #define RT5651_GP5_DR_OUT (0x1 << 14)
1675 #define RT5651_GP5_OUT_MASK (0x1 << 13)
1677 #define RT5651_GP5_OUT_LO (0x0 << 13)
1678 #define RT5651_GP5_OUT_HI (0x1 << 13)
1679 #define RT5651_GP5_P_MASK (0x1 << 12)
1681 #define RT5651_GP5_P_NOR (0x0 << 12)
1682 #define RT5651_GP5_P_INV (0x1 << 12)
1683 #define RT5651_GP4_DR_MASK (0x1 << 11)
1685 #define RT5651_GP4_DR_IN (0x0 << 11)
1686 #define RT5651_GP4_DR_OUT (0x1 << 11)
1687 #define RT5651_GP4_OUT_MASK (0x1 << 10)
1689 #define RT5651_GP4_OUT_LO (0x0 << 10)
1690 #define RT5651_GP4_OUT_HI (0x1 << 10)
1691 #define RT5651_GP4_P_MASK (0x1 << 9)
1693 #define RT5651_GP4_P_NOR (0x0 << 9)
1694 #define RT5651_GP4_P_INV (0x1 << 9)
1695 #define RT5651_GP3_DR_MASK (0x1 << 8)
1697 #define RT5651_GP3_DR_IN (0x0 << 8)
1698 #define RT5651_GP3_DR_OUT (0x1 << 8)
1699 #define RT5651_GP3_OUT_MASK (0x1 << 7)
1701 #define RT5651_GP3_OUT_LO (0x0 << 7)
1702 #define RT5651_GP3_OUT_HI (0x1 << 7)
1703 #define RT5651_GP3_P_MASK (0x1 << 6)
1705 #define RT5651_GP3_P_NOR (0x0 << 6)
1706 #define RT5651_GP3_P_INV (0x1 << 6)
1707 #define RT5651_GP2_DR_MASK (0x1 << 5)
1709 #define RT5651_GP2_DR_IN (0x0 << 5)
1710 #define RT5651_GP2_DR_OUT (0x1 << 5)
1711 #define RT5651_GP2_OUT_MASK (0x1 << 4)
1713 #define RT5651_GP2_OUT_LO (0x0 << 4)
1714 #define RT5651_GP2_OUT_HI (0x1 << 4)
1715 #define RT5651_GP2_P_MASK (0x1 << 3)
1717 #define RT5651_GP2_P_NOR (0x0 << 3)
1718 #define RT5651_GP2_P_INV (0x1 << 3)
1719 #define RT5651_GP1_DR_MASK (0x1 << 2)
1721 #define RT5651_GP1_DR_IN (0x0 << 2)
1722 #define RT5651_GP1_DR_OUT (0x1 << 2)
1723 #define RT5651_GP1_OUT_MASK (0x1 << 1)
1725 #define RT5651_GP1_OUT_LO (0x0 << 1)
1726 #define RT5651_GP1_OUT_HI (0x1 << 1)
1727 #define RT5651_GP1_P_MASK (0x1)
1728 #define RT5651_GP1_P_SFT 0
1729 #define RT5651_GP1_P_NOR (0x0)
1730 #define RT5651_GP1_P_INV (0x1)
1732 /* GPIO Control 3 (0xc2) */
1733 #define RT5651_GP8_DR_MASK (0x1 << 8)
1735 #define RT5651_GP8_DR_IN (0x0 << 8)
1736 #define RT5651_GP8_DR_OUT (0x1 << 8)
1737 #define RT5651_GP8_OUT_MASK (0x1 << 7)
1739 #define RT5651_GP8_OUT_LO (0x0 << 7)
1740 #define RT5651_GP8_OUT_HI (0x1 << 7)
1741 #define RT5651_GP8_P_MASK (0x1 << 6)
1743 #define RT5651_GP8_P_NOR (0x0 << 6)
1744 #define RT5651_GP8_P_INV (0x1 << 6)
1745 #define RT5651_GP7_DR_MASK (0x1 << 5)
1747 #define RT5651_GP7_DR_IN (0x0 << 5)
1748 #define RT5651_GP7_DR_OUT (0x1 << 5)
1749 #define RT5651_GP7_OUT_MASK (0x1 << 4)
1751 #define RT5651_GP7_OUT_LO (0x0 << 4)
1752 #define RT5651_GP7_OUT_HI (0x1 << 4)
1753 #define RT5651_GP7_P_MASK (0x1 << 3)
1755 #define RT5651_GP7_P_NOR (0x0 << 3)
1756 #define RT5651_GP7_P_INV (0x1 << 3)
1757 #define RT5651_GP6_DR_MASK (0x1 << 2)
1759 #define RT5651_GP6_DR_IN (0x0 << 2)
1760 #define RT5651_GP6_DR_OUT (0x1 << 2)
1761 #define RT5651_GP6_OUT_MASK (0x1 << 1)
1763 #define RT5651_GP6_OUT_LO (0x0 << 1)
1764 #define RT5651_GP6_OUT_HI (0x1 << 1)
1765 #define RT5651_GP6_P_MASK (0x1)
1766 #define RT5651_GP6_P_SFT 0
1767 #define RT5651_GP6_P_NOR (0x0)
1768 #define RT5651_GP6_P_INV (0x1)
1770 /* Scramble Control (0xce) */
1771 #define RT5651_SCB_SWAP_MASK (0x1 << 15)
1773 #define RT5651_SCB_SWAP_DIS (0x0 << 15)
1774 #define RT5651_SCB_SWAP_EN (0x1 << 15)
1775 #define RT5651_SCB_MASK (0x1 << 14)
1777 #define RT5651_SCB_DIS (0x0 << 14)
1778 #define RT5651_SCB_EN (0x1 << 14)
1780 /* Baseback Control (0xcf) */
1781 #define RT5651_BB_MASK (0x1 << 15)
1783 #define RT5651_BB_DIS (0x0 << 15)
1784 #define RT5651_BB_EN (0x1 << 15)
1785 #define RT5651_BB_CT_MASK (0x7 << 12)
1787 #define RT5651_BB_CT_A (0x0 << 12)
1788 #define RT5651_BB_CT_B (0x1 << 12)
1789 #define RT5651_BB_CT_C (0x2 << 12)
1790 #define RT5651_BB_CT_D (0x3 << 12)
1791 #define RT5651_M_BB_L_MASK (0x1 << 9)
1793 #define RT5651_M_BB_R_MASK (0x1 << 8)
1795 #define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1797 #define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1799 #define RT5651_G_BB_BST_MASK (0x3f)
1800 #define RT5651_G_BB_BST_SFT 0
1802 /* MP3 Plus Control 1 (0xd0) */
1803 #define RT5651_M_MP3_L_MASK (0x1 << 15)
1805 #define RT5651_M_MP3_R_MASK (0x1 << 14)
1807 #define RT5651_M_MP3_MASK (0x1 << 13)
1809 #define RT5651_M_MP3_DIS (0x0 << 13)
1810 #define RT5651_M_MP3_EN (0x1 << 13)
1811 #define RT5651_EG_MP3_MASK (0x1f << 8)
1813 #define RT5651_MP3_HLP_MASK (0x1 << 7)
1815 #define RT5651_MP3_HLP_DIS (0x0 << 7)
1816 #define RT5651_MP3_HLP_EN (0x1 << 7)
1817 #define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1819 #define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1822 /* MP3 Plus Control 2 (0xd1) */
1823 #define RT5651_MP3_WT_MASK (0x1 << 13)
1825 #define RT5651_MP3_WT_1_4 (0x0 << 13)
1826 #define RT5651_MP3_WT_1_2 (0x1 << 13)
1827 #define RT5651_OG_MP3_MASK (0x1f << 8)
1829 #define RT5651_HG_MP3_MASK (0x3f)
1830 #define RT5651_HG_MP3_SFT 0
1832 /* 3D HP Control 1 (0xd2) */
1833 #define RT5651_3D_CF_MASK (0x1 << 15)
1835 #define RT5651_3D_CF_DIS (0x0 << 15)
1836 #define RT5651_3D_CF_EN (0x1 << 15)
1837 #define RT5651_3D_HP_MASK (0x1 << 14)
1839 #define RT5651_3D_HP_DIS (0x0 << 14)
1840 #define RT5651_3D_HP_EN (0x1 << 14)
1841 #define RT5651_3D_BT_MASK (0x1 << 13)
1843 #define RT5651_3D_BT_DIS (0x0 << 13)
1844 #define RT5651_3D_BT_EN (0x1 << 13)
1845 #define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1847 #define RT5651_3D_HP_M_MASK (0x1 << 10)
1849 #define RT5651_3D_HP_M_SUR (0x0 << 10)
1850 #define RT5651_3D_HP_M_FRO (0x1 << 10)
1851 #define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1853 #define RT5651_M_3D_D2H_MASK (0x1 << 8)
1855 #define RT5651_M_3D_D2R_MASK (0x1 << 7)
1857 #define RT5651_M_3D_REVB_MASK (0x1 << 6)
1860 /* Adjustable high pass filter control 1 (0xd3) */
1861 #define RT5651_2ND_HPF_MASK (0x1 << 15)
1863 #define RT5651_2ND_HPF_DIS (0x0 << 15)
1864 #define RT5651_2ND_HPF_EN (0x1 << 15)
1865 #define RT5651_HPF_CF_L_MASK (0x7 << 12)
1867 #define RT5651_HPF_CF_R_MASK (0x7 << 8)
1869 #define RT5651_ZD_T_MASK (0x3 << 6)
1871 #define RT5651_ZD_F_MASK (0x3 << 4)
1873 #define RT5651_ZD_F_IM (0x0 << 4)
1874 #define RT5651_ZD_F_ZC_IM (0x1 << 4)
1875 #define RT5651_ZD_F_ZC_IOD (0x2 << 4)
1876 #define RT5651_ZD_F_UN (0x3 << 4)
1878 /* Adjustable high pass filter control 2 (0xd4) */
1879 #define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1881 #define RT5651_HPF_CF_R_NUM_MASK (0x3f)
1882 #define RT5651_HPF_CF_R_NUM_SFT 0
1884 /* HP calibration control and Amp detection (0xd6) */
1885 #define RT5651_SI_DAC_MASK (0x1 << 11)
1887 #define RT5651_SI_DAC_AUTO (0x0 << 11)
1888 #define RT5651_SI_DAC_TEST (0x1 << 11)
1889 #define RT5651_DC_CAL_M_MASK (0x1 << 10)
1891 #define RT5651_DC_CAL_M_NOR (0x0 << 10)
1892 #define RT5651_DC_CAL_M_CAL (0x1 << 10)
1893 #define RT5651_DC_CAL_MASK (0x1 << 9)
1895 #define RT5651_DC_CAL_DIS (0x0 << 9)
1896 #define RT5651_DC_CAL_EN (0x1 << 9)
1897 #define RT5651_HPD_RCV_MASK (0x7 << 6)
1899 #define RT5651_HPD_PS_MASK (0x1 << 5)
1901 #define RT5651_HPD_PS_DIS (0x0 << 5)
1902 #define RT5651_HPD_PS_EN (0x1 << 5)
1903 #define RT5651_CAL_M_MASK (0x1 << 4)
1905 #define RT5651_CAL_M_DEP (0x0 << 4)
1906 #define RT5651_CAL_M_CAL (0x1 << 4)
1907 #define RT5651_CAL_MASK (0x1 << 3)
1909 #define RT5651_CAL_DIS (0x0 << 3)
1910 #define RT5651_CAL_EN (0x1 << 3)
1911 #define RT5651_CAL_TEST_MASK (0x1 << 2)
1913 #define RT5651_CAL_TEST_DIS (0x0 << 2)
1914 #define RT5651_CAL_TEST_EN (0x1 << 2)
1915 #define RT5651_CAL_P_MASK (0x3)
1916 #define RT5651_CAL_P_SFT 0
1917 #define RT5651_CAL_P_NONE (0x0)
1918 #define RT5651_CAL_P_CAL (0x1)
1919 #define RT5651_CAL_P_DAC_CAL (0x2)
1921 /* Soft volume and zero cross control 1 (0xd9) */
1922 #define RT5651_SV_MASK (0x1 << 15)
1924 #define RT5651_SV_DIS (0x0 << 15)
1925 #define RT5651_SV_EN (0x1 << 15)
1926 #define RT5651_OUT_SV_MASK (0x1 << 13)
1928 #define RT5651_OUT_SV_DIS (0x0 << 13)
1929 #define RT5651_OUT_SV_EN (0x1 << 13)
1930 #define RT5651_HP_SV_MASK (0x1 << 12)
1932 #define RT5651_HP_SV_DIS (0x0 << 12)
1933 #define RT5651_HP_SV_EN (0x1 << 12)
1934 #define RT5651_ZCD_DIG_MASK (0x1 << 11)
1936 #define RT5651_ZCD_DIG_DIS (0x0 << 11)
1937 #define RT5651_ZCD_DIG_EN (0x1 << 11)
1938 #define RT5651_ZCD_MASK (0x1 << 10)
1940 #define RT5651_ZCD_PD (0x0 << 10)
1941 #define RT5651_ZCD_PU (0x1 << 10)
1942 #define RT5651_M_ZCD_MASK (0x3f << 4)
1944 #define RT5651_M_ZCD_OM_L (0x1 << 7)
1945 #define RT5651_M_ZCD_OM_R (0x1 << 6)
1946 #define RT5651_M_ZCD_RM_L (0x1 << 5)
1947 #define RT5651_M_ZCD_RM_R (0x1 << 4)
1948 #define RT5651_SV_DLY_MASK (0xf)
1949 #define RT5651_SV_DLY_SFT 0
1951 /* Soft volume and zero cross control 2 (0xda) */
1952 #define RT5651_ZCD_HP_MASK (0x1 << 15)
1954 #define RT5651_ZCD_HP_DIS (0x0 << 15)
1955 #define RT5651_ZCD_HP_EN (0x1 << 15)
1957 /* Digital Misc Control (0xfa) */
1958 #define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1960 #define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1961 #define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1962 #define RT5651_CLK_DET_EN (0x1 << 3)
1964 #define RT5651_AMP_DET_EN (0x1 << 1)
1966 #define RT5651_D_GATE_EN (0x1)
1967 #define RT5651_D_GATE_EN_SFT 0
1971 /* MIC Over current threshold scale factor (0x15) */
1972 #define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
1974 #define RT5651_MIC_OVCD_SF_0P5 (0x0 << 8)
1975 #define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1976 #define RT5651_MIC_OVCD_SF_1P0 (0x2 << 8)
1977 #define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
1979 /* 3D Speaker Control (0x63) */
1980 #define RT5651_3D_SPK_MASK (0x1 << 15)
1982 #define RT5651_3D_SPK_DIS (0x0 << 15)
1983 #define RT5651_3D_SPK_EN (0x1 << 15)
1984 #define RT5651_3D_SPK_M_MASK (0x3 << 13)
1986 #define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1988 #define RT5651_3D_SPK_SG_MASK (0x1f)
1989 #define RT5651_3D_SPK_SG_SFT 0
1991 /* Wind Noise Detection Control 1 (0x6c) */
1992 #define RT5651_WND_MASK (0x1 << 15)
1994 #define RT5651_WND_DIS (0x0 << 15)
1995 #define RT5651_WND_EN (0x1 << 15)
1997 /* Wind Noise Detection Control 2 (0x6d) */
1998 #define RT5651_WND_FC_NW_MASK (0x3f << 10)
2000 #define RT5651_WND_FC_WK_MASK (0x3f << 4)
2003 /* Wind Noise Detection Control 3 (0x6e) */
2004 #define RT5651_HPF_FC_MASK (0x3f << 6)
2006 #define RT5651_WND_FC_ST_MASK (0x3f)
2007 #define RT5651_WND_FC_ST_SFT 0
2009 /* Wind Noise Detection Control 4 (0x6f) */
2010 #define RT5651_WND_TH_LO_MASK (0x3ff)
2011 #define RT5651_WND_TH_LO_SFT 0
2013 /* Wind Noise Detection Control 5 (0x70) */
2014 #define RT5651_WND_TH_HI_MASK (0x3ff)
2015 #define RT5651_WND_TH_HI_SFT 0
2017 /* Wind Noise Detection Control 8 (0x73) */
2018 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2020 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2028 /* Dipole Speaker Interface (0x75) */
2029 #define RT5651_DP_ATT_MASK (0x3 << 14)
2031 #define RT5651_DP_SPK_MASK (0x1 << 10)
2033 #define RT5651_DP_SPK_DIS (0x0 << 10)
2034 #define RT5651_DP_SPK_EN (0x1 << 10)
2036 /* EQ Pre Volume Control (0xb3) */
2037 #define RT5651_EQ_PRE_VOL_MASK (0xffff)
2038 #define RT5651_EQ_PRE_VOL_SFT 0
2040 /* EQ Post Volume Control (0xb4) */
2041 #define RT5651_EQ_PST_VOL_MASK (0xffff)
2042 #define RT5651_EQ_PST_VOL_SFT 0