Lines Matching +full:10 +full:- +full:11
2 * rt5651.h -- RT5651 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5651.h>
22 /* I/O - Output */
26 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
51 /* Mixer - ADC */
56 /* Mixer - DAC */
75 /* Format - ADC/DAC */
85 /* Function - Analog */
102 /* Function - Digital */
238 #define RT5651_SEL_DAC_L2 (0x1 << 11)
239 #define RT5651_IF2_DAC_L2 (0x1 << 11)
240 #define RT5651_IF1_DAC_L2 (0x0 << 11)
241 #define RT5651_SEL_DAC_L2_SFT 11
242 #define RT5651_SEL_DAC_R2 (0x1 << 10)
243 #define RT5651_IF2_DAC_R2 (0x1 << 11)
244 #define RT5651_IF1_DAC_R2 (0x0 << 11)
245 #define RT5651_SEL_DAC_R2_SFT 10
268 #define RT5651_ADC_COMP_MASK (0x3 << 10)
269 #define RT5651_ADC_COMP_SFT 10
280 #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
281 #define RT5651_STO1_ADC_2_SRC_SFT 11
282 #define RT5651_STO1_ADC_2_SRC_DMIC (0x0 << 11)
283 #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
298 #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
299 #define RT5651_STO2_ADC_L2_SRC_SFT 11
300 #define RT5651_STO2_ADC_L2_SRC_DMIC (0x0 << 11)
301 #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
332 #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
333 #define RT5651_DAC_L2_STO_L_VOL_SFT 11
358 #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
359 #define RT5651_STO_DD_L2_VOL_SFT 11
360 #define RT5651_M_STO_DD_R2_L (0x1 << 10)
361 #define RT5651_M_STO_DD_R2_L_SFT 10
386 #define RT5651_M_STO_R_DAC_R (0x1 << 11)
387 #define RT5651_M_STO_R_DAC_R_SFT 11
388 #define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
389 #define RT5651_STO_R_DAC_R_VOL_SFT 10
417 #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
418 #define RT5651_IF2_ADC_L_SEL_SFT 11
419 #define RT5651_IF2_ADC_L_SEL_TXDP (0x0 << 11)
420 #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
421 #define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
422 #define RT5651_IF2_ADC_R_SEL_SFT 10
423 #define RT5651_IF2_ADC_R_SEL_TXDP (0x0 << 10)
424 #define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
451 #define RT5651_IF2_DAC_SEL_MASK (0x3 << 10)
452 #define RT5651_IF2_DAC_SEL_SFT 10
453 #define RT5651_IF2_DAC_SEL_NOR (0x0 << 10)
454 #define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
455 #define RT5651_IF2_DAC_SEL_L2R (0x2 << 10)
456 #define RT5651_IF2_DAC_SEL_R2L (0x3 << 10)
497 #define PT5631_PDM_CMD_EXE (0x1 << 11)
498 #define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
499 #define RT5651_PDM_I2C_CMD_R (0x0 << 10)
500 #define RT5651_PDM_I2C_CMD_W (0x1 << 10)
513 #define RT5651_G_LN_L1_RM_L_MASK (0x7 << 10)
514 #define RT5651_G_IN_L1_RM_L_SFT 10
523 #define RT5651_G_OM_L_RM_L_MASK (0x7 << 10)
524 #define RT5651_G_OM_L_RM_L_SFT 10
541 #define RT5651_G_IN1_R_RM_R_MASK (0x7 << 10)
542 #define RT5651_G_IN1_R_RM_R_SFT 10
551 #define RT5651_G_OM_R_RM_R_MASK (0x7 << 10)
552 #define RT5651_G_OM_R_RM_R_SFT 10
579 #define RT5651_G_DAC_L1_SM_L_MASK (0x3 << 10)
580 #define RT5651_G_DAC_L1_SM_L_SFT 10
601 #define RT5651_G_DAC_R1_SM_R_MASK (0x3 << 10)
602 #define RT5651_G_DAC_R1_SM_R_SFT 10
627 #define RT5651_M_BST1_SPM_L (0x1 << 11)
628 #define RT5651_M_BST1_SPM_L_SFT 11
635 #define RT5651_M_BST1_SPM_R (0x1 << 11)
636 #define RT5651_M_BST1_SPM_R_SFT 11
651 #define RT5651_M_BST1_MM (0x1 << 11)
652 #define RT5651_M_BST1_MM_SFT 11
653 #define RT5651_G_MONOMIX_MASK (0x1 << 10)
654 #define RT5651_G_MONOMIX_SFT 10
657 #define RT5651_G_BST2_OM_L_MASK (0x7 << 10)
658 #define RT5651_G_BST2_OM_L_SFT 10
687 #define RT5651_G_BST2_OM_R_MASK (0x7 << 10)
688 #define RT5651_G_BST2_OM_R_SFT 10
725 #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
726 #define RT5651_G_LOUTMIX_SFT 11
735 #define RT5651_PWR_DAC_R1 (0x1 << 11)
736 #define RT5651_PWR_DAC_R1_BIT 11
747 #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
748 #define RT5651_PWR_DAC_STO1_F_BIT 11
749 #define RT5651_PWR_DAC_STO2_F (0x1 << 10)
750 #define RT5651_PWR_DAC_STO2_F_BIT 10
763 #define RT5651_PWR_BG (0x1 << 11)
764 #define RT5651_PWR_BG_BIT 11
790 #define RT5651_PWR_MB1 (0x1 << 11)
791 #define RT5651_PWR_MB1_BIT 11
812 #define RT5651_PWR_RM_L (0x1 << 11)
813 #define RT5651_PWR_RM_L_BIT 11
814 #define RT5651_PWR_RM_R (0x1 << 10)
815 #define RT5651_PWR_RM_R_BIT 10
822 #define RT5651_PWR_HV_L (0x1 << 11)
823 #define RT5651_PWR_HV_L_BIT 11
824 #define RT5651_PWR_HV_R (0x1 << 10)
825 #define RT5651_PWR_HV_R_BIT 10
840 #define RT5651_I2S_O_CP_MASK (0x3 << 10)
841 #define RT5651_I2S_O_CP_SFT 10
842 #define RT5651_I2S_O_CP_OFF (0x0 << 10)
843 #define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
844 #define RT5651_I2S_O_CP_A_LAW (0x2 << 10)
878 #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
879 #define RT5651_I2S_BCLK_MS2_SFT 11
880 #define RT5651_I2S_BCLK_MS2_32 (0x0 << 11)
881 #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
906 #define RT5651_DAHPF_EN (0x1 << 11)
907 #define RT5651_DAHPF_EN_SFT 11
908 #define RT5651_ADHPF_EN (0x1 << 10)
909 #define RT5651_ADHPF_EN_SFT 10
924 #define RT5651_DMIC_1_DP_MASK (0x3 << 10)
925 #define RT5651_DMIC_1_DP_SFT 10
926 #define RT5651_DMIC_1_DP_GPIO6 (0x0 << 10)
927 #define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
928 #define RT5651_DMIC_2_DP_GPIO8 (0x2 << 10)
947 #define RT5651_TDM_CH_LEN_SEL_MASK (0x3 << 10)
948 #define RT5651_TDM_CH_LEN_SEL_SFT 10
949 #define RT5651_TDM_CH_LEN_SEL_16 (0x0 << 10)
950 #define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
951 #define RT5651_TDM_CH_LEN_SEL_24 (0x2 << 10)
952 #define RT5651_TDM_CH_LEN_SEL_32 (0x3 << 10)
999 #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
1000 #define RT5651_TDM_LRCK_PULSE_SEL_SFT 11
1001 #define RT5651_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
1002 #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1003 #define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1004 #define RT5651_TDM_END_EDGE_SEL_SFT 10
1005 #define RT5651_TDM_END_EDGE_SEL_POS (0x0 << 10)
1006 #define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1094 #define RT5651_PLL_M_BP (0x1 << 11)
1095 #define RT5651_PLL_M_BP_SFT 11
1106 #define RT5651_ASRC2_REF_MASK (0x1 << 11)
1107 #define RT5651_ASRC2_REF_SFT 11
1108 #define RT5651_ASRC2_REF_LRCK2 (0x0 << 11)
1109 #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1128 #define RT5651_ADC_M_MASK (0x1 << 11)
1129 #define RT5651_ADC_M_SFT 11
1130 #define RT5651_ADC_M_NOR (0x0 << 11)
1131 #define RT5651_ADC_M_ASRC (0x1 << 11)
1177 #define RT5651_HP_OVCD_MASK (0x1 << 10)
1178 #define RT5651_HP_OVCD_SFT 10
1179 #define RT5651_HP_OVCD_DIS (0x0 << 10)
1180 #define RT5651_HP_OVCD_EN (0x1 << 10)
1243 #define RT5651_BPS_MASK (0x1 << 11)
1244 #define RT5651_BPS_SFT 11
1245 #define RT5651_BPS_DIS (0x0 << 11)
1246 #define RT5651_BPS_EN (0x1 << 11)
1247 #define RT5651_FAST_UPDN_MASK (0x1 << 10)
1248 #define RT5651_FAST_UPDN_SFT 10
1249 #define RT5651_FAST_UPDN_DIS (0x0 << 10)
1250 #define RT5651_FAST_UPDN_EN (0x1 << 10)
1287 #define RT5651_OSW_L_MASK (0x1 << 11)
1288 #define RT5651_OSW_L_SFT 11
1289 #define RT5651_OSW_L_DIS (0x0 << 11)
1290 #define RT5651_OSW_L_EN (0x1 << 11)
1291 #define RT5651_OSW_R_MASK (0x1 << 10)
1292 #define RT5651_OSW_R_SFT 10
1293 #define RT5651_OSW_R_DIS (0x0 << 10)
1294 #define RT5651_OSW_R_EN (0x1 << 10)
1316 #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1317 #define RT5651_MIC1_OVCD_SFT 11
1318 #define RT5651_MIC1_OVCD_DIS (0x0 << 11)
1319 #define RT5651_MIC1_OVCD_EN (0x1 << 11)
1337 #define RT5651_JD_PU (0x1 << 11)
1338 #define RT5651_JD_PU_SFT 11
1339 #define RT5651_JD_PD (0x1 << 10)
1340 #define RT5651_JD_PD_SFT 10
1507 #define RT5651_JD_HP_MASK (0x1 << 11)
1508 #define RT5651_JD_HP_SFT 11
1509 #define RT5651_JD_HP_DIS (0x0 << 11)
1510 #define RT5651_JD_HP_EN (0x1 << 11)
1511 #define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1512 #define RT5651_JD_HP_TRG_SFT 10
1513 #define RT5651_JD_HP_TRG_LO (0x0 << 10)
1514 #define RT5651_JD_HP_TRG_HI (0x1 << 10)
1564 #define RT5651_JD_P_MASK (0x1 << 11)
1565 #define RT5651_JD_P_SFT 11
1566 #define RT5651_JD_P_NOR (0x0 << 11)
1567 #define RT5651_JD_P_INV (0x1 << 11)
1592 #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1593 #define RT5651_MB1_OC_STKY_SFT 11
1594 #define RT5651_MB1_OC_STKY_DIS (0x0 << 11)
1595 #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1615 #define RT5651_STA_GP7 (0x1 << 11)
1616 #define RT5651_STA_GP7_BIT 11
1617 #define RT5651_STA_GP6 (0x1 << 10)
1618 #define RT5651_STA_GP6_BIT 10
1683 #define RT5651_GP4_DR_MASK (0x1 << 11)
1684 #define RT5651_GP4_DR_SFT 11
1685 #define RT5651_GP4_DR_IN (0x0 << 11)
1686 #define RT5651_GP4_DR_OUT (0x1 << 11)
1687 #define RT5651_GP4_OUT_MASK (0x1 << 10)
1688 #define RT5651_GP4_OUT_SFT 10
1689 #define RT5651_GP4_OUT_LO (0x0 << 10)
1690 #define RT5651_GP4_OUT_HI (0x1 << 10)
1845 #define RT5651_3D_1F_MIX_MASK (0x3 << 11)
1846 #define RT5651_3D_1F_MIX_SFT 11
1847 #define RT5651_3D_HP_M_MASK (0x1 << 10)
1848 #define RT5651_3D_HP_M_SFT 10
1849 #define RT5651_3D_HP_M_SUR (0x0 << 10)
1850 #define RT5651_3D_HP_M_FRO (0x1 << 10)
1885 #define RT5651_SI_DAC_MASK (0x1 << 11)
1886 #define RT5651_SI_DAC_SFT 11
1887 #define RT5651_SI_DAC_AUTO (0x0 << 11)
1888 #define RT5651_SI_DAC_TEST (0x1 << 11)
1889 #define RT5651_DC_CAL_M_MASK (0x1 << 10)
1890 #define RT5651_DC_CAL_M_SFT 10
1891 #define RT5651_DC_CAL_M_NOR (0x0 << 10)
1892 #define RT5651_DC_CAL_M_CAL (0x1 << 10)
1934 #define RT5651_ZCD_DIG_MASK (0x1 << 11)
1935 #define RT5651_ZCD_DIG_SFT 11
1936 #define RT5651_ZCD_DIG_DIS (0x0 << 11)
1937 #define RT5651_ZCD_DIG_EN (0x1 << 11)
1938 #define RT5651_ZCD_MASK (0x1 << 10)
1939 #define RT5651_ZCD_SFT 10
1940 #define RT5651_ZCD_PD (0x0 << 10)
1941 #define RT5651_ZCD_PU (0x1 << 10)
1998 #define RT5651_WND_FC_NW_MASK (0x3f << 10)
1999 #define RT5651_WND_FC_NW_SFT 10
2018 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2020 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2031 #define RT5651_DP_SPK_MASK (0x1 << 10)
2032 #define RT5651_DP_SPK_SFT 10
2033 #define RT5651_DP_SPK_DIS (0x0 << 10)
2034 #define RT5651_DP_SPK_EN (0x1 << 10)