Lines Matching +full:8 +full:- +full:12
2 * rt5651.h -- RT5651 ALSA SoC audio driver
15 #include <dt-bindings/sound/rt5651.h>
22 /* I/O - Output */
26 /* I/O - Input */
31 /* I/O - ADC/DAC/DMIC */
38 /* Mixer - D-D */
51 /* Mixer - ADC */
56 /* Mixer - DAC */
75 /* Format - ADC/DAC */
85 /* Function - Analog */
102 /* Function - Digital */
187 #define RT5651_L_VOL_MASK (0x3f << 8)
188 #define RT5651_L_VOL_SFT 8
197 #define RT5651_BST_MASK1 (0xf<<12)
198 #define RT5651_BST_SFT1 12
199 #define RT5651_BST_MASK2 (0xf<<8)
200 #define RT5651_BST_SFT2 8
212 #define RT5651_INL_VOL_MASK (0x1f << 8)
213 #define RT5651_INL_VOL_SFT 8
222 #define RT5651_DAC_L1_VOL_MASK (0xff << 8)
223 #define RT5651_DAC_L1_VOL_SFT 8
228 #define RT5651_DAC_L2_VOL_MASK (0xff << 8)
229 #define RT5651_DAC_L2_VOL_SFT 8
236 #define RT5651_M_DAC_R2_VOL (0x1 << 12)
237 #define RT5651_M_DAC_R2_VOL_SFT 12
248 #define RT5651_ADC_L_VOL_MASK (0x7f << 8)
249 #define RT5651_ADC_L_VOL_SFT 8
256 #define RT5651_MONO_ADC_L_VOL_MASK (0x7f << 8)
257 #define RT5651_MONO_ADC_L_VOL_SFT 8
266 #define RT5651_ADC_R_BST_MASK (0x3 << 12)
267 #define RT5651_ADC_R_BST_SFT 12
276 #define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
277 #define RT5651_STO1_ADC_1_SRC_SFT 12
278 #define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
279 #define RT5651_STO1_ADC_1_SRC_DACMIX (0x0 << 12)
294 #define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
295 #define RT5651_STO2_ADC_L1_SRC_SFT 12
296 #define RT5651_STO2_ADC_L1_SRC_DACMIXL (0x0 << 12)
297 #define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
330 #define RT5651_M_DAC_L2_MIXL (0x1 << 12)
331 #define RT5651_M_DAC_L2_MIXL_SFT 12
336 #define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
337 #define RT5651_DAC_R1_STO_L_VOL_SFT 8
356 #define RT5651_M_STO_DD_L2 (0x1 << 12)
357 #define RT5651_M_STO_DD_L2_SFT 12
384 #define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
385 #define RT5651_DAC_L2_DAC_L_VOL_SFT 12
392 #define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
393 #define RT5651_DAC_R2_DAC_R_VOL_SFT 8
412 #define RT5651_DAC_R2_SEL_MASK (0x3 << 12)
413 #define RT5651_DAC_R2_SEL_SFT 12
414 #define RT5651_DAC_R2_SEL_IF2 (0x0 << 12)
415 #define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
416 #define RT5651_DAC_R2_SEL_TXDC (0x2 << 12)
425 #define RT5651_RXDC_SEL_MASK (0x3 << 8)
426 #define RT5651_RXDC_SEL_SFT 8
427 #define RT5651_RXDC_SEL_NOR (0x0 << 8)
428 #define RT5651_RXDC_SEL_L2R (0x1 << 8)
429 #define RT5651_RXDC_SEL_R2L (0x2 << 8)
430 #define RT5651_RXDC_SEL_SWAP (0x3 << 8)
457 #define RT5651_IF2_ADC_SEL_MASK (0x3 << 8)
458 #define RT5651_IF2_ADC_SEL_SFT 8
459 #define RT5651_IF2_ADC_SEL_NOR (0x0 << 8)
460 #define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
461 #define RT5651_IF2_ADC_SEL_L2R (0x2 << 8)
462 #define RT5651_IF2_ADC_SEL_R2L (0x3 << 8)
479 #define RT5651_M_PDM_R (0x1 << 12)
480 #define RT5651_M_PDM_R_SFT 12
496 #define RT5651_PDM_I2C_ID_MASK (0xf << 12)
502 #define RT5651_PDM_I2C_NORMAL (0x0 << 8)
503 #define RT5651_PDM_I2C_BUSY (0x1 << 8)
506 #define RT5651_PDM_I2C_ADDR (0xff << 8)
571 #define RT5651_G_HPOMIX_MASK (0x1 << 12)
572 #define RT5651_G_HPOMIX_SFT 12
577 #define RT5651_G_IN_L_SM_L_MASK (0x3 << 12)
578 #define RT5651_G_IN_L_SM_L_SFT 12
581 #define RT5651_G_DAC_L2_SM_L_MASK (0x3 << 8)
582 #define RT5651_G_DAC_L2_SM_L_SFT 8
599 #define RT5651_G_IN_R_SM_R_MASK (0x3 << 12)
600 #define RT5651_G_IN_R_SM_R_SFT 12
603 #define RT5651_G_DAC_R2_SM_R_MASK (0x3 << 8)
604 #define RT5651_G_DAC_R2_SM_R_SFT 8
625 #define RT5651_M_SV_L_SPM_L (0x1 << 12)
626 #define RT5651_M_SV_L_SPM_L_SFT 12
633 #define RT5651_M_SV_R_SPM_R (0x1 << 12)
634 #define RT5651_M_SV_R_SPM_R_SFT 12
649 #define RT5651_M_OV_L_MM (0x1 << 12)
650 #define RT5651_M_OV_L_MM_SFT 12
723 #define RT5651_M_OV_R_LM (0x1 << 12)
724 #define RT5651_M_OV_R_LM_SFT 12
733 #define RT5651_PWR_DAC_L1 (0x1 << 12)
734 #define RT5651_PWR_DAC_L1_BIT 12
761 #define RT5651_PWR_LM (0x1 << 12)
762 #define RT5651_PWR_LM_BIT 12
820 #define RT5651_PWR_OV_R (0x1 << 12)
821 #define RT5651_PWR_OV_R_BIT 12
828 #define RT5651_PWR_IN1_R (0x1 << 8)
829 #define RT5651_PWR_IN1_R_BIT 8
845 #define RT5651_I2S_I_CP_MASK (0x3 << 8)
846 #define RT5651_I2S_I_CP_SFT 8
847 #define RT5651_I2S_I_CP_OFF (0x0 << 8)
848 #define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
849 #define RT5651_I2S_I_CP_A_LAW (0x2 << 8)
868 #define RT5651_I2S_PD1_MASK (0x7 << 12)
869 #define RT5651_I2S_PD1_SFT 12
870 #define RT5651_I2S_PD1_1 (0x0 << 12)
871 #define RT5651_I2S_PD1_2 (0x1 << 12)
872 #define RT5651_I2S_PD1_3 (0x2 << 12)
873 #define RT5651_I2S_PD1_4 (0x3 << 12)
874 #define RT5651_I2S_PD1_6 (0x4 << 12)
875 #define RT5651_I2S_PD1_8 (0x5 << 12)
876 #define RT5651_I2S_PD1_12 (0x6 << 12)
877 #define RT5651_I2S_PD1_16 (0x7 << 12)
882 #define RT5651_I2S_PD2_MASK (0x7 << 8)
883 #define RT5651_I2S_PD2_SFT 8
884 #define RT5651_I2S_PD2_1 (0x0 << 8)
885 #define RT5651_I2S_PD2_2 (0x1 << 8)
886 #define RT5651_I2S_PD2_3 (0x2 << 8)
887 #define RT5651_I2S_PD2_4 (0x3 << 8)
888 #define RT5651_I2S_PD2_6 (0x4 << 8)
889 #define RT5651_I2S_PD2_8 (0x5 << 8)
890 #define RT5651_I2S_PD2_12 (0x6 << 8)
891 #define RT5651_I2S_PD2_16 (0x7 << 8)
920 #define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
921 #define RT5651_DMIC_1R_LH_SFT 12
922 #define RT5651_DMIC_1R_LH_FALLING (0x0 << 12)
923 #define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
941 #define RT5651_TDM_CH_NUM_SEL_MASK (0x3 << 12)
942 #define RT5651_TDM_CH_NUM_SEL_SFT 12
943 #define RT5651_TDM_CH_NUM_SEL_2 (0x0 << 12)
944 #define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
945 #define RT5651_TDM_CH_NUM_SEL_6 (0x2 << 12)
946 #define RT5651_TDM_CH_NUM_SEL_8 (0x3 << 12)
957 #define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
958 #define RT5651_TDM_ADC_START_SEL_SFT 8
959 #define RT5651_TDM_ADC_START_SEL_SL0 (0x0 << 8)
960 #define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
997 #define RT5651_TDM_LPBK_EN (0x1 << 12)
998 #define RT5651_TDM_LPBK_SFT 12
1009 #define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1010 #define RT5651_TDM_TRAN_EDGE_SEL_SFT 8
1011 #define RT5651_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
1012 #define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1023 #define RT5651_CH2_L_SEL_MASK (0x7 << 12)
1024 #define RT5651_CH2_L_SEL_SFT 12
1025 #define RT5651_CH2_L_SEL_SL0 (0x0 << 12)
1026 #define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1027 #define RT5651_CH2_L_SEL_SL2 (0x2 << 12)
1028 #define RT5651_CH2_L_SEL_SL3 (0x3 << 12)
1029 #define RT5651_CH2_L_SEL_SL4 (0x4 << 12)
1030 #define RT5651_CH2_L_SEL_SL5 (0x5 << 12)
1031 #define RT5651_CH2_L_SEL_SL6 (0x6 << 12)
1032 #define RT5651_CH2_L_SEL_SL7 (0x7 << 12)
1033 #define RT5651_CH2_R_SEL_MASK (0x7 << 8)
1034 #define RT5651_CH2_R_SEL_SFT 8
1035 #define RT5651_CH2_R_SEL_SL0 (0x0 << 8)
1036 #define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1037 #define RT5651_CH2_R_SEL_SL2 (0x2 << 8)
1038 #define RT5651_CH2_R_SEL_SL3 (0x3 << 8)
1039 #define RT5651_CH2_R_SEL_SL4 (0x4 << 8)
1040 #define RT5651_CH2_R_SEL_SL5 (0x5 << 8)
1041 #define RT5651_CH2_R_SEL_SL6 (0x6 << 8)
1042 #define RT5651_CH2_R_SEL_SL7 (0x7 << 8)
1070 #define RT5651_PLL1_SRC_MASK (0x3 << 12)
1071 #define RT5651_PLL1_SRC_SFT 12
1072 #define RT5651_PLL1_SRC_MCLK (0x0 << 12)
1073 #define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1074 #define RT5651_PLL1_SRC_BCLK2 (0x2 << 12)
1092 #define RT5651_PLL_M_MASK (RT5651_PLL_M_MAX << 12)
1093 #define RT5651_PLL_M_SFT 12
1102 #define RT5651_STO2_T_MASK (0x1 << 12)
1103 #define RT5651_STO2_T_SFT 12
1104 #define RT5651_STO2_T_I2S2 (0x0 << 12)
1105 #define RT5651_STO2_T_LRCK2 (0x1 << 12)
1124 #define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1125 #define RT5651_STO2_DAC_M_SFT 12
1126 #define RT5651_STO2_DAC_M_NOR (0x0 << 12)
1127 #define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1147 #define RT5651_I2S1_RATE_MASK (0xf << 12)
1148 #define RT5651_I2S1_RATE_SFT 12
1149 #define RT5651_I2S2_RATE_MASK (0xf << 8)
1150 #define RT5651_I2S2_RATE_SFT 8
1165 #define RT5651_I2S1_PD_MASK (0x7 << 12)
1166 #define RT5651_I2S1_PD_SFT 12
1167 #define RT5651_I2S2_PD_MASK (0x7 << 8)
1168 #define RT5651_I2S2_PD_SFT 8
1171 #define RT5651_FSI1_RATE_MASK (0xf << 12)
1172 #define RT5651_FSI1_RATE_SFT 12
1173 #define RT5651_FSI2_RATE_MASK (0xf << 8)
1174 #define RT5651_FSI2_RATE_SFT 8
1181 #define RT5651_HP_OC_TH_MASK (0x3 << 8)
1182 #define RT5651_HP_OC_TH_SFT 8
1183 #define RT5651_HP_OC_TH_90 (0x0 << 8)
1184 #define RT5651_HP_OC_TH_105 (0x1 << 8)
1185 #define RT5651_HP_OC_TH_120 (0x2 << 8)
1186 #define RT5651_HP_OC_TH_135 (0x3 << 8)
1197 #define RT5651_HP_R_SMT_MASK (0x1 << 8)
1198 #define RT5651_HP_R_SMT_SFT 8
1199 #define RT5651_HP_R_SMT_DIS (0x0 << 8)
1200 #define RT5651_HP_R_SMT_EN (0x1 << 8)
1239 #define RT5651_RAMP_MASK (0x1 << 12)
1240 #define RT5651_RAMP_SFT 12
1241 #define RT5651_RAMP_DIS (0x0 << 12)
1242 #define RT5651_RAMP_EN (0x1 << 12)
1251 #define RT5651_MRES_MASK (0x3 << 8)
1252 #define RT5651_MRES_SFT 8
1253 #define RT5651_MRES_15MO (0x0 << 8)
1254 #define RT5651_MRES_25MO (0x1 << 8)
1255 #define RT5651_MRES_35MO (0x2 << 8)
1256 #define RT5651_MRES_45MO (0x3 << 8)
1269 #define RT5651_CP_SYS_MASK (0x7 << 12)
1270 #define RT5651_CP_SYS_SFT 12
1271 #define RT5651_CP_FQ1_MASK (0x7 << 8)
1272 #define RT5651_CP_FQ1_SFT 8
1295 #define RT5651_PM_HP_MASK (0x3 << 8)
1296 #define RT5651_PM_HP_SFT 8
1297 #define RT5651_PM_HP_LV (0x0 << 8)
1298 #define RT5651_PM_HP_MV (0x1 << 8)
1299 #define RT5651_PM_HP_HV (0x2 << 8)
1335 #define RT5651_JD2_CMP_MASK (0x7 << 12)
1336 #define RT5651_JD2_CMP_SFT 12
1341 #define RT5651_JD_MODE_SEL_MASK (0x3 << 8)
1342 #define RT5651_JD_MODE_SEL_SFT 8
1343 #define RT5651_JD_MODE_SEL_M0 (0x0 << 8)
1344 #define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1345 #define RT5651_JD_MODE_SEL_M2 (0x2 << 8)
1359 #define RT5651_JD3_CMP_MASK (0x7 << 12)
1360 #define RT5651_JD3_CMP_SFT 12
1373 #define RT5651_EQ_DITH_MASK (0x3 << 8)
1374 #define RT5651_EQ_DITH_SFT 8
1375 #define RT5651_EQ_DITH_NOR (0x0 << 8)
1376 #define RT5651_EQ_DITH_LSB (0x1 << 8)
1377 #define RT5651_EQ_DITH_LSB_1 (0x2 << 8)
1378 #define RT5651_EQ_DITH_LSB_2 (0x3 << 8)
1397 #define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1398 #define RT5651_EQ_HPF1_M_SFT 8
1399 #define RT5651_EQ_HPF1_M_HI (0x0 << 8)
1400 #define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1452 #define RT5651_ALC_AR_MASK (0x1f << 8)
1453 #define RT5651_ALC_AR_SFT 8
1466 #define RT5651_ALC_POB_MASK (0x3f << 8)
1467 #define RT5651_ALC_POB_SFT 8
1482 #define RT5651_ALC_NGB_MASK (0xf << 12)
1483 #define RT5651_ALC_NGB_SFT 12
1519 #define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1520 #define RT5651_JD_SPL_TRG_SFT 8
1521 #define RT5651_JD_SPL_TRG_LO (0x0 << 8)
1522 #define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1548 #define RT5651_JD3_IRQ_EN (0x1 << 8)
1549 #define RT5651_JD3_IRQ_EN_SFT 8
1570 #define RT5651_JD1_1_EN_STKY (0x1 << 8)
1571 #define RT5651_JD1_1_EN_STKY_SFT 8
1613 #define RT5651_STA_JD1_1 (0x1 << 12)
1614 #define RT5651_STA_JD1_1_BIT 12
1621 #define RT5651_STA_GP1 (0x1 << 8)
1622 #define RT5651_STA_GP1_BIT 8
1645 #define RT5651_I2S2_SEL_MASK (0x1 << 8)
1646 #define RT5651_I2S2_SEL_SFT 8
1647 #define RT5651_I2S2_SEL_I2S (0x0 << 8)
1648 #define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1679 #define RT5651_GP5_P_MASK (0x1 << 12)
1680 #define RT5651_GP5_P_SFT 12
1681 #define RT5651_GP5_P_NOR (0x0 << 12)
1682 #define RT5651_GP5_P_INV (0x1 << 12)
1695 #define RT5651_GP3_DR_MASK (0x1 << 8)
1696 #define RT5651_GP3_DR_SFT 8
1697 #define RT5651_GP3_DR_IN (0x0 << 8)
1698 #define RT5651_GP3_DR_OUT (0x1 << 8)
1733 #define RT5651_GP8_DR_MASK (0x1 << 8)
1734 #define RT5651_GP8_DR_SFT 8
1735 #define RT5651_GP8_DR_IN (0x0 << 8)
1736 #define RT5651_GP8_DR_OUT (0x1 << 8)
1785 #define RT5651_BB_CT_MASK (0x7 << 12)
1786 #define RT5651_BB_CT_SFT 12
1787 #define RT5651_BB_CT_A (0x0 << 12)
1788 #define RT5651_BB_CT_B (0x1 << 12)
1789 #define RT5651_BB_CT_C (0x2 << 12)
1790 #define RT5651_BB_CT_D (0x3 << 12)
1793 #define RT5651_M_BB_R_MASK (0x1 << 8)
1794 #define RT5651_M_BB_R_SFT 8
1811 #define RT5651_EG_MP3_MASK (0x1f << 8)
1812 #define RT5651_EG_MP3_SFT 8
1827 #define RT5651_OG_MP3_MASK (0x1f << 8)
1828 #define RT5651_OG_MP3_SFT 8
1853 #define RT5651_M_3D_D2H_MASK (0x1 << 8)
1854 #define RT5651_M_3D_D2H_SFT 8
1865 #define RT5651_HPF_CF_L_MASK (0x7 << 12)
1866 #define RT5651_HPF_CF_L_SFT 12
1867 #define RT5651_HPF_CF_R_MASK (0x7 << 8)
1868 #define RT5651_HPF_CF_R_SFT 8
1879 #define RT5651_HPF_CF_L_NUM_MASK (0x3f << 8)
1880 #define RT5651_HPF_CF_L_NUM_SFT 8
1930 #define RT5651_HP_SV_MASK (0x1 << 12)
1931 #define RT5651_HP_SV_SFT 12
1932 #define RT5651_HP_SV_DIS (0x0 << 12)
1933 #define RT5651_HP_SV_EN (0x1 << 12)
1958 #define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1959 #define RT5651_I2S2_MS_SP_SEL 8
1960 #define RT5651_I2S2_MS_SP_64 (0x0 << 8)
1961 #define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1972 #define RT5651_MIC_OVCD_SF_MASK (0x3 << 8)
1973 #define RT5651_MIC_OVCD_SF_SFT 8
1974 #define RT5651_MIC_OVCD_SF_0P5 (0x0 << 8)
1975 #define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1976 #define RT5651_MIC_OVCD_SF_1P0 (0x2 << 8)
1977 #define RT5651_MIC_OVCD_SF_1P5 (0x3 << 8)
1986 #define RT5651_3D_SPK_CG_MASK (0x1f << 8)
1987 #define RT5651_3D_SPK_CG_SFT 8
2017 /* Wind Noise Detection Control 8 (0x73) */
2018 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2020 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2021 #define RT5651_WND_STRONG_SFT 12