Lines Matching full:x1
179 #define RT5651_L_MUTE (0x1 << 15)
181 #define RT5651_VOL_L_MUTE (0x1 << 14)
183 #define RT5651_R_MUTE (0x1 << 7)
185 #define RT5651_VOL_R_MUTE (0x1 << 6)
193 #define RT5651_EN_DFO (0x1 << 15)
201 #define RT5651_IN_DF1 (0x1 << 7)
203 #define RT5651_IN_DF2 (0x1 << 6)
208 #define RT5651_INL_SEL_MASK (0x1 << 15)
211 #define RT5651_INL_SEL_MONOP (0x1 << 15)
214 #define RT5651_INR_SEL_MASK (0x1 << 7)
217 #define RT5651_INR_SEL_MONON (0x1 << 7)
234 #define RT5651_M_DAC_L2_VOL (0x1 << 13)
236 #define RT5651_M_DAC_R2_VOL (0x1 << 12)
238 #define RT5651_SEL_DAC_L2 (0x1 << 11)
239 #define RT5651_IF2_DAC_L2 (0x1 << 11)
242 #define RT5651_SEL_DAC_R2 (0x1 << 10)
243 #define RT5651_IF2_DAC_R2 (0x1 << 11)
254 #define RT5651_M_MONO_ADC_L (0x1 << 15)
258 #define RT5651_M_MONO_ADC_R (0x1 << 7)
272 #define RT5651_M_STO1_ADC_L1 (0x1 << 14)
274 #define RT5651_M_STO1_ADC_L2 (0x1 << 13)
276 #define RT5651_STO1_ADC_1_SRC_MASK (0x1 << 12)
278 #define RT5651_STO1_ADC_1_SRC_ADC (0x1 << 12)
280 #define RT5651_STO1_ADC_2_SRC_MASK (0x1 << 11)
283 #define RT5651_STO1_ADC_2_SRC_DACMIXR (0x1 << 11)
284 #define RT5651_M_STO1_ADC_R1 (0x1 << 6)
286 #define RT5651_M_STO1_ADC_R2 (0x1 << 5)
290 #define RT5651_M_STO2_ADC_L1 (0x1 << 14)
292 #define RT5651_M_STO2_ADC_L2 (0x1 << 13)
294 #define RT5651_STO2_ADC_L1_SRC_MASK (0x1 << 12)
297 #define RT5651_STO2_ADC_L1_SRC_ADCL (0x1 << 12)
298 #define RT5651_STO2_ADC_L2_SRC_MASK (0x1 << 11)
301 #define RT5651_STO2_ADC_L2_SRC_DACMIXR (0x1 << 11)
302 #define RT5651_M_STO2_ADC_R1 (0x1 << 6)
304 #define RT5651_M_STO2_ADC_R2 (0x1 << 5)
306 #define RT5651_STO2_ADC_R1_SRC_MASK (0x1 << 4)
308 #define RT5651_STO2_ADC_R1_SRC_ADCR (0x1 << 4)
310 #define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
313 #define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
316 #define RT5651_M_ADCMIX_L (0x1 << 15)
318 #define RT5651_M_IF1_DAC_L (0x1 << 14)
320 #define RT5651_M_ADCMIX_R (0x1 << 7)
322 #define RT5651_M_IF1_DAC_R (0x1 << 6)
326 #define RT5651_M_DAC_L1_MIXL (0x1 << 14)
328 #define RT5651_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
330 #define RT5651_M_DAC_L2_MIXL (0x1 << 12)
332 #define RT5651_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
334 #define RT5651_M_DAC_R1_MIXL (0x1 << 9)
336 #define RT5651_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
338 #define RT5651_M_DAC_R1_MIXR (0x1 << 6)
340 #define RT5651_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
342 #define RT5651_M_DAC_R2_MIXR (0x1 << 4)
344 #define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
346 #define RT5651_M_DAC_L1_MIXR (0x1 << 1)
348 #define RT5651_DAC_L1_STO_R_VOL_MASK (0x1)
352 #define RT5651_M_STO_DD_L1 (0x1 << 14)
354 #define RT5651_STO_DD_L1_VOL_MASK (0x1 << 13)
356 #define RT5651_M_STO_DD_L2 (0x1 << 12)
358 #define RT5651_STO_DD_L2_VOL_MASK (0x1 << 11)
360 #define RT5651_M_STO_DD_R2_L (0x1 << 10)
362 #define RT5651_STO_DD_R2_L_VOL_MASK (0x1 << 9)
364 #define RT5651_M_STO_DD_R1 (0x1 << 6)
366 #define RT5651_STO_DD_R1_VOL_MASK (0x1 << 5)
368 #define RT5651_M_STO_DD_R2 (0x1 << 4)
370 #define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
372 #define RT5651_M_STO_DD_L2_R (0x1 << 2)
374 #define RT5651_STO_DD_L2_R_VOL_MASK (0x1 << 1)
378 #define RT5651_M_STO_L_DAC_L (0x1 << 15)
380 #define RT5651_STO_L_DAC_L_VOL_MASK (0x1 << 14)
382 #define RT5651_M_DAC_L2_DAC_L (0x1 << 13)
384 #define RT5651_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
386 #define RT5651_M_STO_R_DAC_R (0x1 << 11)
388 #define RT5651_STO_R_DAC_R_VOL_MASK (0x1 << 10)
390 #define RT5651_M_DAC_R2_DAC_R (0x1 << 9)
392 #define RT5651_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
396 #define RT5651_RXDP_SRC_MASK (0x1 << 15)
399 #define RT5651_RXDP_SRC_DIV3 (0x1 << 15)
400 #define RT5651_TXDP_SRC_MASK (0x1 << 14)
403 #define RT5651_TXDP_SRC_DIV3 (0x1 << 14)
409 #define RT5651_DAC_L2_SEL_IF3 (0x1 << 14)
415 #define RT5651_DAC_R2_SEL_IF3 (0x1 << 12)
417 #define RT5651_IF2_ADC_L_SEL_MASK (0x1 << 11)
420 #define RT5651_IF2_ADC_L_SEL_PASS (0x1 << 11)
421 #define RT5651_IF2_ADC_R_SEL_MASK (0x1 << 10)
424 #define RT5651_IF2_ADC_R_SEL_PASS (0x1 << 10)
428 #define RT5651_RXDC_SEL_L2R (0x1 << 8)
434 #define RT5651_RXDP_SEL_L2R (0x1 << 6)
440 #define RT5651_TXDC_SEL_L2R (0x1 << 4)
446 #define RT5651_TXDP_SEL_L2R (0x1 << 2)
454 #define RT5651_IF2_DAC_SEL_SWAP (0x1 << 10)
460 #define RT5651_IF2_ADC_SEL_SWAP (0x1 << 8)
463 #define RT5651_IF2_ADC_SRC_MASK (0x1 << 7)
466 #define RT5651_IF1_ADC2 (0x1 << 7)
469 #define RT5651_PDM_L_SEL_MASK (0x1 << 15)
472 #define RT5651_PDM_L_SEL_STO_L (0x1 << 15)
473 #define RT5651_M_PDM_L (0x1 << 14)
475 #define RT5651_PDM_R_SEL_MASK (0x1 << 13)
478 #define RT5651_PDM_R_SEL_STO_L (0x1 << 13)
479 #define RT5651_M_PDM_R (0x1 << 12)
481 #define RT5651_PDM_BUSY (0x1 << 6)
483 #define RT5651_PDM_PATTERN_SEL_MASK (0x1 << 5)
485 #define RT5651_PDM_PATTERN_SEL_128 (0x1 << 5)
486 #define RT5651_PDM_VOL_MASK (0x1 << 4)
497 #define PT5631_PDM_CMD_EXE (0x1 << 11)
498 #define RT5651_PDM_I2C_CMD_MASK (0x1 << 10)
500 #define RT5651_PDM_I2C_CMD_W (0x1 << 10)
501 #define RT5651_PDM_I2C_CMD_EXE (0x1 << 9)
503 #define RT5651_PDM_I2C_BUSY (0x1 << 8)
525 #define RT5651_M_IN2_L_RM_L (0x1 << 6)
527 #define RT5651_M_IN1_L_RM_L (0x1 << 5)
529 #define RT5651_M_BST3_RM_L (0x1 << 3)
531 #define RT5651_M_BST2_RM_L (0x1 << 2)
533 #define RT5651_M_BST1_RM_L (0x1 << 1)
535 #define RT5651_M_OM_L_RM_L (0x1)
553 #define RT5651_M_IN2_R_RM_R (0x1 << 6)
555 #define RT5651_M_IN1_R_RM_R (0x1 << 5)
557 #define RT5651_M_BST3_RM_R (0x1 << 3)
559 #define RT5651_M_BST2_RM_R (0x1 << 2)
561 #define RT5651_M_BST1_RM_R (0x1 << 1)
563 #define RT5651_M_OM_R_RM_R (0x1)
567 #define RT5651_M_DAC1_HM (0x1 << 14)
569 #define RT5651_M_HPVOL_HM (0x1 << 13)
571 #define RT5651_G_HPOMIX_MASK (0x1 << 12)
585 #define RT5651_M_RM_L_SM_L (0x1 << 5)
587 #define RT5651_M_IN_L_SM_L (0x1 << 4)
589 #define RT5651_M_DAC_L1_SM_L (0x1 << 3)
591 #define RT5651_M_DAC_L2_SM_L (0x1 << 2)
593 #define RT5651_M_OM_L_SM_L (0x1 << 1)
607 #define RT5651_M_RM_R_SM_R (0x1 << 5)
609 #define RT5651_M_IN_R_SM_R (0x1 << 4)
611 #define RT5651_M_DAC_R1_SM_R (0x1 << 3)
613 #define RT5651_M_DAC_R2_SM_R (0x1 << 2)
615 #define RT5651_M_OM_R_SM_R (0x1 << 1)
619 #define RT5651_M_DAC_R1_SPM_L (0x1 << 15)
621 #define RT5651_M_DAC_L1_SPM_L (0x1 << 14)
623 #define RT5651_M_SV_R_SPM_L (0x1 << 13)
625 #define RT5651_M_SV_L_SPM_L (0x1 << 12)
627 #define RT5651_M_BST1_SPM_L (0x1 << 11)
631 #define RT5651_M_DAC_R1_SPM_R (0x1 << 13)
633 #define RT5651_M_SV_R_SPM_R (0x1 << 12)
635 #define RT5651_M_BST1_SPM_R (0x1 << 11)
643 #define RT5651_M_DAC_R2_MM (0x1 << 15)
645 #define RT5651_M_DAC_L2_MM (0x1 << 14)
647 #define RT5651_M_OV_R_MM (0x1 << 13)
649 #define RT5651_M_OV_L_MM (0x1 << 12)
651 #define RT5651_M_BST1_MM (0x1 << 11)
653 #define RT5651_G_MONOMIX_MASK (0x1 << 10)
673 #define RT5651_M_IN2_L_OM_L (0x1 << 9)
675 #define RT5651_M_BST2_OM_L (0x1 << 6)
677 #define RT5651_M_BST1_OM_L (0x1 << 5)
679 #define RT5651_M_IN1_L_OM_L (0x1 << 4)
681 #define RT5651_M_RM_L_OM_L (0x1 << 3)
683 #define RT5651_M_DAC_L1_OM_L (0x1)
703 #define RT5651_M_IN2_R_OM_R (0x1 << 9)
705 #define RT5651_M_BST2_OM_R (0x1 << 6)
707 #define RT5651_M_BST1_OM_R (0x1 << 5)
709 #define RT5651_M_IN1_R_OM_R (0x1 << 4)
711 #define RT5651_M_RM_R_OM_R (0x1 << 3)
713 #define RT5651_M_DAC_R1_OM_R (0x1)
717 #define RT5651_M_DAC_L1_LM (0x1 << 15)
719 #define RT5651_M_DAC_R1_LM (0x1 << 14)
721 #define RT5651_M_OV_L_LM (0x1 << 13)
723 #define RT5651_M_OV_R_LM (0x1 << 12)
725 #define RT5651_G_LOUTMIX_MASK (0x1 << 11)
729 #define RT5651_PWR_I2S1 (0x1 << 15)
731 #define RT5651_PWR_I2S2 (0x1 << 14)
733 #define RT5651_PWR_DAC_L1 (0x1 << 12)
735 #define RT5651_PWR_DAC_R1 (0x1 << 11)
737 #define RT5651_PWR_ADC_L (0x1 << 2)
739 #define RT5651_PWR_ADC_R (0x1 << 1)
743 #define RT5651_PWR_ADC_STO1_F (0x1 << 15)
745 #define RT5651_PWR_ADC_STO2_F (0x1 << 14)
747 #define RT5651_PWR_DAC_STO1_F (0x1 << 11)
749 #define RT5651_PWR_DAC_STO2_F (0x1 << 10)
751 #define RT5651_PWR_PDM (0x1 << 9)
755 #define RT5651_PWR_VREF1 (0x1 << 15)
757 #define RT5651_PWR_FV1 (0x1 << 14)
759 #define RT5651_PWR_MB (0x1 << 13)
761 #define RT5651_PWR_LM (0x1 << 12)
763 #define RT5651_PWR_BG (0x1 << 11)
765 #define RT5651_PWR_HP_L (0x1 << 7)
767 #define RT5651_PWR_HP_R (0x1 << 6)
769 #define RT5651_PWR_HA (0x1 << 5)
771 #define RT5651_PWR_VREF2 (0x1 << 4)
773 #define RT5651_PWR_FV2 (0x1 << 3)
775 #define RT5651_PWR_LDO (0x1 << 2)
784 #define RT5651_PWR_BST1 (0x1 << 15)
786 #define RT5651_PWR_BST2 (0x1 << 14)
788 #define RT5651_PWR_BST3 (0x1 << 13)
790 #define RT5651_PWR_MB1 (0x1 << 11)
792 #define RT5651_PWR_PLL (0x1 << 9)
794 #define RT5651_PWR_BST1_OP2 (0x1 << 5)
796 #define RT5651_PWR_BST2_OP2 (0x1 << 4)
798 #define RT5651_PWR_BST3_OP2 (0x1 << 3)
800 #define RT5651_PWR_JD_M (0x1 << 2)
802 #define RT5651_PWR_JD2 (0x1 << 1)
804 #define RT5651_PWR_JD3 (0x1)
808 #define RT5651_PWR_OM_L (0x1 << 15)
810 #define RT5651_PWR_OM_R (0x1 << 14)
812 #define RT5651_PWR_RM_L (0x1 << 11)
814 #define RT5651_PWR_RM_R (0x1 << 10)
818 #define RT5651_PWR_OV_L (0x1 << 13)
820 #define RT5651_PWR_OV_R (0x1 << 12)
822 #define RT5651_PWR_HV_L (0x1 << 11)
824 #define RT5651_PWR_HV_R (0x1 << 10)
826 #define RT5651_PWR_IN1_L (0x1 << 9)
828 #define RT5651_PWR_IN1_R (0x1 << 8)
830 #define RT5651_PWR_IN2_L (0x1 << 7)
832 #define RT5651_PWR_IN2_R (0x1 << 6)
836 #define RT5651_I2S_MS_MASK (0x1 << 15)
839 #define RT5651_I2S_MS_S (0x1 << 15)
843 #define RT5651_I2S_O_CP_U_LAW (0x1 << 10)
848 #define RT5651_I2S_I_CP_U_LAW (0x1 << 8)
850 #define RT5651_I2S_BP_MASK (0x1 << 7)
853 #define RT5651_I2S_BP_INV (0x1 << 7)
857 #define RT5651_I2S_DL_20 (0x1 << 2)
863 #define RT5651_I2S_DF_LEFT (0x1)
871 #define RT5651_I2S_PD1_2 (0x1 << 12)
878 #define RT5651_I2S_BCLK_MS2_MASK (0x1 << 11)
881 #define RT5651_I2S_BCLK_MS2_64 (0x1 << 11)
885 #define RT5651_I2S_PD2_2 (0x1 << 8)
895 #define RT5651_DAC_OSR_64 (0x1 << 2)
901 #define RT5651_ADC_OSR_64 (0x1)
906 #define RT5651_DAHPF_EN (0x1 << 11)
908 #define RT5651_ADHPF_EN (0x1 << 10)
912 #define RT5651_DMIC_1_EN_MASK (0x1 << 15)
915 #define RT5651_DMIC_1_EN (0x1 << 15)
916 #define RT5651_DMIC_1L_LH_MASK (0x1 << 13)
919 #define RT5651_DMIC_1L_LH_RISING (0x1 << 13)
920 #define RT5651_DMIC_1R_LH_MASK (0x1 << 12)
923 #define RT5651_DMIC_1R_LH_RISING (0x1 << 12)
927 #define RT5651_DMIC_1_DP_IN1P (0x1 << 10)
933 #define RT5651_TDM_INTEL_SEL_MASK (0x1 << 15)
936 #define RT5651_TDM_INTEL_SEL_50 (0x1 << 15)
937 #define RT5651_TDM_MODE_SEL_MASK (0x1 << 14)
940 #define RT5651_TDM_MODE_SEL_TDM (0x1 << 14)
944 #define RT5651_TDM_CH_NUM_SEL_4 (0x1 << 12)
950 #define RT5651_TDM_CH_LEN_SEL_20 (0x1 << 10)
953 #define RT5651_TDM_ADC_SEL_MASK (0x1 << 9)
956 #define RT5651_TDM_ADC_SEL_SWAP (0x1 << 9)
957 #define RT5651_TDM_ADC_START_SEL_MASK (0x1 << 8)
960 #define RT5651_TDM_ADC_START_SEL_SL4 (0x1 << 8)
964 #define RT5651_TDM_I2S_CH2_SEL_RL (0x1 << 6)
970 #define RT5651_TDM_I2S_CH4_SEL_RL (0x1 << 4)
976 #define RT5651_TDM_I2S_CH6_SEL_RL (0x1 << 2)
982 #define RT5651_TDM_I2S_CH8_SEL_RL (0x1)
987 #define RT5651_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
990 #define RT5651_TDM_LRCK_POL_SEL_INV (0x1 << 15)
991 #define RT5651_TDM_CH_VAL_SEL_MASK (0x1 << 14)
994 #define RT5651_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
995 #define RT5651_TDM_CH_VAL_EN (0x1 << 13)
997 #define RT5651_TDM_LPBK_EN (0x1 << 12)
999 #define RT5651_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
1002 #define RT5651_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
1003 #define RT5651_TDM_END_EDGE_SEL_MASK (0x1 << 10)
1006 #define RT5651_TDM_END_EDGE_SEL_NEG (0x1 << 10)
1007 #define RT5651_TDM_END_EDGE_EN (0x1 << 9)
1009 #define RT5651_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
1012 #define RT5651_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
1013 #define RT5651_M_TDM2_L (0x1 << 7)
1015 #define RT5651_M_TDM2_R (0x1 << 6)
1017 #define RT5651_M_TDM4_L (0x1 << 5)
1019 #define RT5651_M_TDM4_R (0x1 << 4)
1026 #define RT5651_CH2_L_SEL_SL1 (0x1 << 12)
1036 #define RT5651_CH2_R_SEL_SL1 (0x1 << 8)
1046 #define RT5651_CH4_L_SEL_SL1 (0x1 << 4)
1056 #define RT5651_CH4_R_SEL_SL1 (0x1)
1068 #define RT5651_SCLK_SRC_PLL1 (0x1 << 14)
1073 #define RT5651_PLL1_SRC_BCLK1 (0x1 << 12)
1075 #define RT5651_PLL1_PD_MASK (0x1 << 3)
1078 #define RT5651_PLL1_PD_2 (0x1 << 3)
1094 #define RT5651_PLL_M_BP (0x1 << 11)
1098 #define RT5651_STO1_T_MASK (0x1 << 15)
1101 #define RT5651_STO1_T_LRCK1 (0x1 << 15)
1102 #define RT5651_STO2_T_MASK (0x1 << 12)
1105 #define RT5651_STO2_T_LRCK2 (0x1 << 12)
1106 #define RT5651_ASRC2_REF_MASK (0x1 << 11)
1109 #define RT5651_ASRC2_REF_LRCK1 (0x1 << 11)
1110 #define RT5651_DMIC_1_M_MASK (0x1 << 9)
1113 #define RT5651_DMIC_1_M_ASYN (0x1 << 9)
1116 #define RT5651_STO1_ASRC_EN (0x1 << 15)
1118 #define RT5651_STO2_ASRC_EN (0x1 << 14)
1120 #define RT5651_STO1_DAC_M_MASK (0x1 << 13)
1123 #define RT5651_STO1_DAC_M_ASRC (0x1 << 13)
1124 #define RT5651_STO2_DAC_M_MASK (0x1 << 12)
1127 #define RT5651_STO2_DAC_M_ASRC (0x1 << 12)
1128 #define RT5651_ADC_M_MASK (0x1 << 11)
1131 #define RT5651_ADC_M_ASRC (0x1 << 11)
1132 #define RT5651_I2S1_R_D_MASK (0x1 << 4)
1135 #define RT5651_I2S1_R_D_EN (0x1 << 4)
1136 #define RT5651_I2S2_R_D_MASK (0x1 << 3)
1139 #define RT5651_I2S2_R_D_EN (0x1 << 3)
1143 #define RT5651_PRE_SCLK_1024 (0x1)
1151 #define RT5651_G_ASRC_LP_MASK (0x1 << 3)
1153 #define RT5651_ASRC_LP_F_M (0x1 << 2)
1156 #define RT5651_ASRC_LP_F_SB (0x1 << 2)
1160 #define RT5651_FTK_PH_DET_DIV2 (0x1)
1177 #define RT5651_HP_OVCD_MASK (0x1 << 10)
1180 #define RT5651_HP_OVCD_EN (0x1 << 10)
1184 #define RT5651_HP_OC_TH_105 (0x1 << 8)
1189 #define RT5651_SMT_TRIG_MASK (0x1 << 15)
1192 #define RT5651_SMT_TRIG_EN (0x1 << 15)
1193 #define RT5651_HP_L_SMT_MASK (0x1 << 9)
1196 #define RT5651_HP_L_SMT_EN (0x1 << 9)
1197 #define RT5651_HP_R_SMT_MASK (0x1 << 8)
1200 #define RT5651_HP_R_SMT_EN (0x1 << 8)
1201 #define RT5651_HP_CD_PD_MASK (0x1 << 7)
1204 #define RT5651_HP_CD_PD_EN (0x1 << 7)
1205 #define RT5651_RSTN_MASK (0x1 << 6)
1208 #define RT5651_RSTN_EN (0x1 << 6)
1209 #define RT5651_RSTP_MASK (0x1 << 5)
1212 #define RT5651_RSTP_EN (0x1 << 5)
1213 #define RT5651_HP_CO_MASK (0x1 << 4)
1216 #define RT5651_HP_CO_EN (0x1 << 4)
1217 #define RT5651_HP_CP_MASK (0x1 << 3)
1220 #define RT5651_HP_CP_PU (0x1 << 3)
1221 #define RT5651_HP_SG_MASK (0x1 << 2)
1224 #define RT5651_HP_SG_EN (0x1 << 2)
1225 #define RT5651_HP_DP_MASK (0x1 << 1)
1228 #define RT5651_HP_DP_PU (0x1 << 1)
1229 #define RT5651_HP_CB_MASK (0x1)
1232 #define RT5651_HP_CB_PU (0x1)
1235 #define RT5651_DEPOP_MASK (0x1 << 13)
1238 #define RT5651_DEPOP_MAN (0x1 << 13)
1239 #define RT5651_RAMP_MASK (0x1 << 12)
1242 #define RT5651_RAMP_EN (0x1 << 12)
1243 #define RT5651_BPS_MASK (0x1 << 11)
1246 #define RT5651_BPS_EN (0x1 << 11)
1247 #define RT5651_FAST_UPDN_MASK (0x1 << 10)
1250 #define RT5651_FAST_UPDN_EN (0x1 << 10)
1254 #define RT5651_MRES_25MO (0x1 << 8)
1257 #define RT5651_VLO_MASK (0x1 << 7)
1260 #define RT5651_VLO_32V (0x1 << 7)
1261 #define RT5651_DIG_DP_MASK (0x1 << 6)
1264 #define RT5651_DIG_DP_EN (0x1 << 6)
1287 #define RT5651_OSW_L_MASK (0x1 << 11)
1290 #define RT5651_OSW_L_EN (0x1 << 11)
1291 #define RT5651_OSW_R_MASK (0x1 << 10)
1294 #define RT5651_OSW_R_EN (0x1 << 10)
1298 #define RT5651_PM_HP_MV (0x1 << 8)
1303 #define RT5651_IB_HP_25IL (0x1 << 6)
1308 #define RT5651_MIC1_BS_MASK (0x1 << 15)
1311 #define RT5651_MIC1_BS_75AV (0x1 << 15)
1312 #define RT5651_MIC1_CLK_MASK (0x1 << 13)
1315 #define RT5651_MIC1_CLK_EN (0x1 << 13)
1316 #define RT5651_MIC1_OVCD_MASK (0x1 << 11)
1319 #define RT5651_MIC1_OVCD_EN (0x1 << 11)
1323 #define RT5651_MIC1_OVTH_1500UA (0x1 << 9)
1325 #define RT5651_PWR_MB_MASK (0x1 << 5)
1328 #define RT5651_PWR_MB_PU (0x1 << 5)
1329 #define RT5651_PWR_CLK12M_MASK (0x1 << 4)
1332 #define RT5651_PWR_CLK12M_PU (0x1 << 4)
1337 #define RT5651_JD_PU (0x1 << 11)
1339 #define RT5651_JD_PD (0x1 << 10)
1344 #define RT5651_JD_MODE_SEL_M1 (0x1 << 8)
1348 #define RT5651_JD_M_PU (0x1 << 3)
1350 #define RT5651_JD_M_PD (0x1 << 2)
1355 #define RT5651_JD_M_MODE_SEL_M1 (0x1)
1363 #define RT5651_EQ_SRC_MASK (0x1 << 15)
1366 #define RT5651_EQ_SRC_ADC (0x1 << 15)
1367 #define RT5651_EQ_UPD (0x1 << 14)
1369 #define RT5651_EQ_CD_MASK (0x1 << 13)
1372 #define RT5651_EQ_CD_EN (0x1 << 13)
1376 #define RT5651_EQ_DITH_LSB (0x1 << 8)
1379 #define RT5651_EQ_CD_F (0x1 << 7)
1381 #define RT5651_EQ_STA_HP2 (0x1 << 6)
1383 #define RT5651_EQ_STA_HP1 (0x1 << 5)
1385 #define RT5651_EQ_STA_BP4 (0x1 << 4)
1387 #define RT5651_EQ_STA_BP3 (0x1 << 3)
1389 #define RT5651_EQ_STA_BP2 (0x1 << 2)
1391 #define RT5651_EQ_STA_BP1 (0x1 << 1)
1393 #define RT5651_EQ_STA_LP (0x1)
1397 #define RT5651_EQ_HPF1_M_MASK (0x1 << 8)
1400 #define RT5651_EQ_HPF1_M_1ST (0x1 << 8)
1401 #define RT5651_EQ_LPF1_M_MASK (0x1 << 7)
1404 #define RT5651_EQ_LPF1_M_1ST (0x1 << 7)
1405 #define RT5651_EQ_HPF2_MASK (0x1 << 6)
1408 #define RT5651_EQ_HPF2_EN (0x1 << 6)
1409 #define RT5651_EQ_HPF1_MASK (0x1 << 5)
1412 #define RT5651_EQ_HPF1_EN (0x1 << 5)
1413 #define RT5651_EQ_BPF4_MASK (0x1 << 4)
1416 #define RT5651_EQ_BPF4_EN (0x1 << 4)
1417 #define RT5651_EQ_BPF3_MASK (0x1 << 3)
1420 #define RT5651_EQ_BPF3_EN (0x1 << 3)
1421 #define RT5651_EQ_BPF2_MASK (0x1 << 2)
1424 #define RT5651_EQ_BPF2_EN (0x1 << 2)
1425 #define RT5651_EQ_BPF1_MASK (0x1 << 1)
1428 #define RT5651_EQ_BPF1_EN (0x1 << 1)
1429 #define RT5651_EQ_LPF_MASK (0x1)
1432 #define RT5651_EQ_LPF_EN (0x1)
1436 #define RT5651_MT_MASK (0x1 << 15)
1439 #define RT5651_MT_EN (0x1 << 15)
1442 #define RT5651_ALC_P_MASK (0x1 << 15)
1445 #define RT5651_ALC_P_ADC (0x1 << 15)
1446 #define RT5651_ALC_MASK (0x1 << 14)
1449 #define RT5651_ALC_EN (0x1 << 14)
1450 #define RT5651_ALC_UPD (0x1 << 13)
1456 #define RT5651_ALC_R_48K (0x1 << 5)
1468 #define RT5651_ALC_DRC_MASK (0x1 << 7)
1471 #define RT5651_ALC_DRC_EN (0x1 << 7)
1475 #define RT5651_ALC_CPR_1_2 (0x1 << 5)
1486 #define RT5651_ALC_NG_MASK (0x1 << 6)
1489 #define RT5651_ALC_NG_EN (0x1 << 6)
1490 #define RT5651_ALC_NGH_MASK (0x1 << 5)
1493 #define RT5651_ALC_NGH_EN (0x1 << 5)
1501 #define RT5651_JD_GPIO1 (0x1 << 13)
1507 #define RT5651_JD_HP_MASK (0x1 << 11)
1510 #define RT5651_JD_HP_EN (0x1 << 11)
1511 #define RT5651_JD_HP_TRG_MASK (0x1 << 10)
1514 #define RT5651_JD_HP_TRG_HI (0x1 << 10)
1515 #define RT5651_JD_SPL_MASK (0x1 << 9)
1518 #define RT5651_JD_SPL_EN (0x1 << 9)
1519 #define RT5651_JD_SPL_TRG_MASK (0x1 << 8)
1522 #define RT5651_JD_SPL_TRG_HI (0x1 << 8)
1523 #define RT5651_JD_SPR_MASK (0x1 << 7)
1526 #define RT5651_JD_SPR_EN (0x1 << 7)
1527 #define RT5651_JD_SPR_TRG_MASK (0x1 << 6)
1530 #define RT5651_JD_SPR_TRG_HI (0x1 << 6)
1531 #define RT5651_JD_LO_MASK (0x1 << 3)
1534 #define RT5651_JD_LO_EN (0x1 << 3)
1535 #define RT5651_JD_LO_TRG_MASK (0x1 << 2)
1538 #define RT5651_JD_LO_TRG_HI (0x1 << 2)
1544 #define RT5651_JD_TRG_SEL_JD1_1 (0x1 << 9)
1548 #define RT5651_JD3_IRQ_EN (0x1 << 8)
1550 #define RT5651_JD3_EN_STKY (0x1 << 7)
1552 #define RT5651_JD3_INV (0x1 << 6)
1556 #define RT5651_IRQ_JD_MASK (0x1 << 15)
1559 #define RT5651_IRQ_JD_NOR (0x1 << 15)
1560 #define RT5651_JD_STKY_MASK (0x1 << 13)
1563 #define RT5651_JD_STKY_EN (0x1 << 13)
1564 #define RT5651_JD_P_MASK (0x1 << 11)
1567 #define RT5651_JD_P_INV (0x1 << 11)
1568 #define RT5651_JD1_1_IRQ_EN (0x1 << 9)
1570 #define RT5651_JD1_1_EN_STKY (0x1 << 8)
1572 #define RT5651_JD1_1_INV (0x1 << 7)
1574 #define RT5651_JD1_2_IRQ_EN (0x1 << 6)
1576 #define RT5651_JD1_2_EN_STKY (0x1 << 5)
1578 #define RT5651_JD1_2_INV (0x1 << 4)
1580 #define RT5651_JD2_IRQ_EN (0x1 << 3)
1582 #define RT5651_JD2_EN_STKY (0x1 << 2)
1584 #define RT5651_JD2_INV (0x1 << 1)
1588 #define RT5651_IRQ_MB1_OC_MASK (0x1 << 15)
1591 #define RT5651_IRQ_MB1_OC_NOR (0x1 << 15)
1592 #define RT5651_MB1_OC_STKY_MASK (0x1 << 11)
1595 #define RT5651_MB1_OC_STKY_EN (0x1 << 11)
1596 #define RT5651_MB1_OC_P_MASK (0x1 << 7)
1599 #define RT5651_MB1_OC_P_INV (0x1 << 7)
1600 #define RT5651_MB2_OC_P_MASK (0x1 << 6)
1601 #define RT5651_MB1_OC_CLR (0x1 << 3)
1603 #define RT5651_STA_GPIO8 (0x1)
1607 #define RT5651_STA_JD3 (0x1 << 15)
1609 #define RT5651_STA_JD2 (0x1 << 14)
1611 #define RT5651_STA_JD1_2 (0x1 << 13)
1613 #define RT5651_STA_JD1_1 (0x1 << 12)
1615 #define RT5651_STA_GP7 (0x1 << 11)
1617 #define RT5651_STA_GP6 (0x1 << 10)
1619 #define RT5651_STA_GP5 (0x1 << 9)
1621 #define RT5651_STA_GP1 (0x1 << 8)
1623 #define RT5651_STA_GP2 (0x1 << 7)
1625 #define RT5651_STA_GP3 (0x1 << 6)
1627 #define RT5651_STA_GP4 (0x1 << 5)
1629 #define RT5651_STA_GP_JD (0x1 << 4)
1633 #define RT5651_GP1_PIN_MASK (0x1 << 15)
1636 #define RT5651_GP1_PIN_IRQ (0x1 << 15)
1637 #define RT5651_GP2_PIN_MASK (0x1 << 14)
1640 #define RT5651_GP2_PIN_DMIC1_SCL (0x1 << 14)
1641 #define RT5651_GPIO_M_MASK (0x1 << 9)
1644 #define RT5651_GPIO_M_PH (0x1 << 9)
1645 #define RT5651_I2S2_SEL_MASK (0x1 << 8)
1648 #define RT5651_I2S2_SEL_GPIO (0x1 << 8)
1649 #define RT5651_GP5_PIN_MASK (0x1 << 7)
1652 #define RT5651_GP5_PIN_IRQ (0x1 << 7)
1653 #define RT5651_GP6_PIN_MASK (0x1 << 6)
1656 #define RT5651_GP6_PIN_DMIC_SDA (0x1 << 6)
1657 #define RT5651_GP7_PIN_MASK (0x1 << 5)
1660 #define RT5651_GP7_PIN_IRQ (0x1 << 5)
1661 #define RT5651_GP8_PIN_MASK (0x1 << 4)
1664 #define RT5651_GP8_PIN_DMIC_SDA (0x1 << 4)
1665 #define RT5651_GPIO_PDM_SEL_MASK (0x1 << 3)
1668 #define RT5651_GPIO_PDM_SEL_PDM (0x1 << 3)
1671 #define RT5651_GP5_DR_MASK (0x1 << 14)
1674 #define RT5651_GP5_DR_OUT (0x1 << 14)
1675 #define RT5651_GP5_OUT_MASK (0x1 << 13)
1678 #define RT5651_GP5_OUT_HI (0x1 << 13)
1679 #define RT5651_GP5_P_MASK (0x1 << 12)
1682 #define RT5651_GP5_P_INV (0x1 << 12)
1683 #define RT5651_GP4_DR_MASK (0x1 << 11)
1686 #define RT5651_GP4_DR_OUT (0x1 << 11)
1687 #define RT5651_GP4_OUT_MASK (0x1 << 10)
1690 #define RT5651_GP4_OUT_HI (0x1 << 10)
1691 #define RT5651_GP4_P_MASK (0x1 << 9)
1694 #define RT5651_GP4_P_INV (0x1 << 9)
1695 #define RT5651_GP3_DR_MASK (0x1 << 8)
1698 #define RT5651_GP3_DR_OUT (0x1 << 8)
1699 #define RT5651_GP3_OUT_MASK (0x1 << 7)
1702 #define RT5651_GP3_OUT_HI (0x1 << 7)
1703 #define RT5651_GP3_P_MASK (0x1 << 6)
1706 #define RT5651_GP3_P_INV (0x1 << 6)
1707 #define RT5651_GP2_DR_MASK (0x1 << 5)
1710 #define RT5651_GP2_DR_OUT (0x1 << 5)
1711 #define RT5651_GP2_OUT_MASK (0x1 << 4)
1714 #define RT5651_GP2_OUT_HI (0x1 << 4)
1715 #define RT5651_GP2_P_MASK (0x1 << 3)
1718 #define RT5651_GP2_P_INV (0x1 << 3)
1719 #define RT5651_GP1_DR_MASK (0x1 << 2)
1722 #define RT5651_GP1_DR_OUT (0x1 << 2)
1723 #define RT5651_GP1_OUT_MASK (0x1 << 1)
1726 #define RT5651_GP1_OUT_HI (0x1 << 1)
1727 #define RT5651_GP1_P_MASK (0x1)
1730 #define RT5651_GP1_P_INV (0x1)
1733 #define RT5651_GP8_DR_MASK (0x1 << 8)
1736 #define RT5651_GP8_DR_OUT (0x1 << 8)
1737 #define RT5651_GP8_OUT_MASK (0x1 << 7)
1740 #define RT5651_GP8_OUT_HI (0x1 << 7)
1741 #define RT5651_GP8_P_MASK (0x1 << 6)
1744 #define RT5651_GP8_P_INV (0x1 << 6)
1745 #define RT5651_GP7_DR_MASK (0x1 << 5)
1748 #define RT5651_GP7_DR_OUT (0x1 << 5)
1749 #define RT5651_GP7_OUT_MASK (0x1 << 4)
1752 #define RT5651_GP7_OUT_HI (0x1 << 4)
1753 #define RT5651_GP7_P_MASK (0x1 << 3)
1756 #define RT5651_GP7_P_INV (0x1 << 3)
1757 #define RT5651_GP6_DR_MASK (0x1 << 2)
1760 #define RT5651_GP6_DR_OUT (0x1 << 2)
1761 #define RT5651_GP6_OUT_MASK (0x1 << 1)
1764 #define RT5651_GP6_OUT_HI (0x1 << 1)
1765 #define RT5651_GP6_P_MASK (0x1)
1768 #define RT5651_GP6_P_INV (0x1)
1771 #define RT5651_SCB_SWAP_MASK (0x1 << 15)
1774 #define RT5651_SCB_SWAP_EN (0x1 << 15)
1775 #define RT5651_SCB_MASK (0x1 << 14)
1778 #define RT5651_SCB_EN (0x1 << 14)
1781 #define RT5651_BB_MASK (0x1 << 15)
1784 #define RT5651_BB_EN (0x1 << 15)
1788 #define RT5651_BB_CT_B (0x1 << 12)
1791 #define RT5651_M_BB_L_MASK (0x1 << 9)
1793 #define RT5651_M_BB_R_MASK (0x1 << 8)
1795 #define RT5651_M_BB_HPF_L_MASK (0x1 << 7)
1797 #define RT5651_M_BB_HPF_R_MASK (0x1 << 6)
1803 #define RT5651_M_MP3_L_MASK (0x1 << 15)
1805 #define RT5651_M_MP3_R_MASK (0x1 << 14)
1807 #define RT5651_M_MP3_MASK (0x1 << 13)
1810 #define RT5651_M_MP3_EN (0x1 << 13)
1813 #define RT5651_MP3_HLP_MASK (0x1 << 7)
1816 #define RT5651_MP3_HLP_EN (0x1 << 7)
1817 #define RT5651_M_MP3_ORG_L_MASK (0x1 << 6)
1819 #define RT5651_M_MP3_ORG_R_MASK (0x1 << 5)
1823 #define RT5651_MP3_WT_MASK (0x1 << 13)
1826 #define RT5651_MP3_WT_1_2 (0x1 << 13)
1833 #define RT5651_3D_CF_MASK (0x1 << 15)
1836 #define RT5651_3D_CF_EN (0x1 << 15)
1837 #define RT5651_3D_HP_MASK (0x1 << 14)
1840 #define RT5651_3D_HP_EN (0x1 << 14)
1841 #define RT5651_3D_BT_MASK (0x1 << 13)
1844 #define RT5651_3D_BT_EN (0x1 << 13)
1847 #define RT5651_3D_HP_M_MASK (0x1 << 10)
1850 #define RT5651_3D_HP_M_FRO (0x1 << 10)
1851 #define RT5651_M_3D_HRTF_MASK (0x1 << 9)
1853 #define RT5651_M_3D_D2H_MASK (0x1 << 8)
1855 #define RT5651_M_3D_D2R_MASK (0x1 << 7)
1857 #define RT5651_M_3D_REVB_MASK (0x1 << 6)
1861 #define RT5651_2ND_HPF_MASK (0x1 << 15)
1864 #define RT5651_2ND_HPF_EN (0x1 << 15)
1874 #define RT5651_ZD_F_ZC_IM (0x1 << 4)
1885 #define RT5651_SI_DAC_MASK (0x1 << 11)
1888 #define RT5651_SI_DAC_TEST (0x1 << 11)
1889 #define RT5651_DC_CAL_M_MASK (0x1 << 10)
1892 #define RT5651_DC_CAL_M_CAL (0x1 << 10)
1893 #define RT5651_DC_CAL_MASK (0x1 << 9)
1896 #define RT5651_DC_CAL_EN (0x1 << 9)
1899 #define RT5651_HPD_PS_MASK (0x1 << 5)
1902 #define RT5651_HPD_PS_EN (0x1 << 5)
1903 #define RT5651_CAL_M_MASK (0x1 << 4)
1906 #define RT5651_CAL_M_CAL (0x1 << 4)
1907 #define RT5651_CAL_MASK (0x1 << 3)
1910 #define RT5651_CAL_EN (0x1 << 3)
1911 #define RT5651_CAL_TEST_MASK (0x1 << 2)
1914 #define RT5651_CAL_TEST_EN (0x1 << 2)
1918 #define RT5651_CAL_P_CAL (0x1)
1922 #define RT5651_SV_MASK (0x1 << 15)
1925 #define RT5651_SV_EN (0x1 << 15)
1926 #define RT5651_OUT_SV_MASK (0x1 << 13)
1929 #define RT5651_OUT_SV_EN (0x1 << 13)
1930 #define RT5651_HP_SV_MASK (0x1 << 12)
1933 #define RT5651_HP_SV_EN (0x1 << 12)
1934 #define RT5651_ZCD_DIG_MASK (0x1 << 11)
1937 #define RT5651_ZCD_DIG_EN (0x1 << 11)
1938 #define RT5651_ZCD_MASK (0x1 << 10)
1941 #define RT5651_ZCD_PU (0x1 << 10)
1944 #define RT5651_M_ZCD_OM_L (0x1 << 7)
1945 #define RT5651_M_ZCD_OM_R (0x1 << 6)
1946 #define RT5651_M_ZCD_RM_L (0x1 << 5)
1947 #define RT5651_M_ZCD_RM_R (0x1 << 4)
1952 #define RT5651_ZCD_HP_MASK (0x1 << 15)
1955 #define RT5651_ZCD_HP_EN (0x1 << 15)
1958 #define RT5651_I2S2_MS_SP_MASK (0x1 << 8)
1961 #define RT5651_I2S2_MS_SP_50 (0x1 << 8)
1962 #define RT5651_CLK_DET_EN (0x1 << 3)
1964 #define RT5651_AMP_DET_EN (0x1 << 1)
1966 #define RT5651_D_GATE_EN (0x1)
1975 #define RT5651_MIC_OVCD_SF_0P75 (0x1 << 8)
1980 #define RT5651_3D_SPK_MASK (0x1 << 15)
1983 #define RT5651_3D_SPK_EN (0x1 << 15)
1992 #define RT5651_WND_MASK (0x1 << 15)
1995 #define RT5651_WND_EN (0x1 << 15)
2018 #define RT5651_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2020 #define RT5651_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2031 #define RT5651_DP_SPK_MASK (0x1 << 10)
2034 #define RT5651_DP_SPK_EN (0x1 << 10)