Lines Matching +full:8 +full:- +full:12
2 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver
24 /* I/O - Output */
33 /* I/O - Input */
39 /* I/O - Speaker */
47 /* I/O - ADC/DAC/DMIC */
61 /* Mixer - D-D */
73 /* Mixer - PDM */
79 /* Mixer - ADC */
91 /* Mixer - DAC */
115 /* Format - ADC/DAC */
123 /* Format - TDM Control */
132 /* Function - Analog */
161 /* Function - Digital */
442 #define RT5665_L_VOL_MASK (0x3f << 8)
443 #define RT5665_L_VOL_SFT 8
448 #define RT5665_G_HP (0xf << 8)
449 #define RT5665_G_HP_SFT 8
454 #define RT5665_BST_CBJ_MASK (0xf << 8)
455 #define RT5665_BST_CBJ_SFT 8
460 #define RT5665_BST1_MASK (0x7f << 8)
461 #define RT5665_BST1_SFT 8
470 #define RT5665_BST3_MASK (0x7f << 8)
471 #define RT5665_BST3_SFT 8
478 #define RT5665_INL_VOL_MASK (0x1f << 8)
479 #define RT5665_INL_VOL_SFT 8
492 #define RT5665_POL_FAST_OFF_MASK (0x1 << 8)
493 #define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)
494 #define RT5665_POL_FAST_OFF_LOW (0x0 << 8)
520 #define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)
521 #define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)
522 #define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)
535 #define RT5665_M_DAC2_R_VOL (0x1 << 12)
536 #define RT5665_M_DAC2_R_VOL_SFT 12
549 #define RT5665_DAC_L1_VOL_MASK (0xff << 8)
550 #define RT5665_DAC_L1_VOL_SFT 8
555 #define RT5665_DAC_L2_VOL_MASK (0xff << 8)
556 #define RT5665_DAC_L2_VOL_SFT 8
563 #define RT5665_M_DAC3_R_VOL (0x1 << 12)
564 #define RT5665_M_DAC3_R_VOL_SFT 12
571 #define RT5665_ADC_L_VOL_MASK (0x7f << 8)
572 #define RT5665_ADC_L_VOL_SFT 8
577 #define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)
578 #define RT5665_MONO_ADC_L_VOL_SFT 8
585 #define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)
586 #define RT5665_STO1_ADC_R_BST_SFT 12
591 #define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)
592 #define RT5665_MONO_ADC_R_BST_SFT 12
597 #define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)
598 #define RT5665_STO2_ADC_R_BST_SFT 12
609 #define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)
610 #define RT5665_STO1_ADC2L_SRC_SFT 12
615 #define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)
616 #define RT5665_STO1_DMIC_SRC_SFT 8
617 #define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
618 #define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
640 #define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)
641 #define RT5665_MONO_ADC_L2_SRC_SFT 12
646 #define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)
647 #define RT5665_MONO_DMIC_L_SRC_SFT 8
673 #define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)
674 #define RT5665_STO2_ADC2L_SRC_SFT 12
679 #define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)
680 #define RT5665_STO2_DMIC_SRC_SFT 8
681 #define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)
682 #define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)
704 #define RT5665_DAC1_L_SEL_MASK (0x3 << 8)
705 #define RT5665_DAC1_L_SEL_SFT 8
718 #define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)
719 #define RT5665_G_DAC_R1_STO_L_SFT 12
726 #define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)
727 #define RT5665_G_DAC_R2_STO_L_SFT 8
752 #define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)
753 #define RT5665_G_DAC_R1_MONO_L_SFT 12
760 #define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)
761 #define RT5665_G_DAC_R2_MONO_L_SFT 8
786 #define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)
787 #define RT5665_G_DAC_L2_STO2_L_SFT 12
794 #define RT5665_M_ST_DAC_R1 (0x1 << 8)
795 #define RT5665_M_ST_DAC_R1_SFT 8
810 #define RT5665_DAC_MIX_L_MASK (0x3 << 12)
811 #define RT5665_DAC_MIX_L_SFT 12
812 #define RT5665_DAC_MIX_R_MASK (0x3 << 8)
813 #define RT5665_DAC_MIX_R_SFT 8
826 #define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)
827 #define RT5665_IF2_1_ADC_IN_SFT 12
830 #define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)
831 #define RT5665_IF2_1_ADC_SEL_SFT 8
850 #define RT5665_M_PDM1_R (0x1 << 12)
851 #define RT5665_M_PDM1_R_SFT 12
854 #define RT5665_PDM1_R_MASK (0x3 << 8)
855 #define RT5665_PDM1_R_SFT 8
957 #define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)
958 #define RT5665_M_SPKVOLL_SPKOMIX_SFT 12
961 #define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)
962 #define RT5665_M_SPKVOLR_SPKOMIX_SFT 8
969 #define RT5665_M_DAC_L2_MA (0x1 << 8)
970 #define RT5665_M_DAC_L2_MA_SFT 8
983 #define RT5665_G_BST3_OM_L_MASK (0x7 << 12)
984 #define RT5665_G_BST3_OM_L_SFT 12
1025 #define RT5665_M_OV_R_LM (0x1 << 12)
1026 #define RT5665_M_OV_R_LM_SFT 12
1038 #define RT5665_PWR_I2S2_2 (0x1 << 12)
1039 #define RT5665_PWR_I2S2_2_BIT 12
1046 #define RT5665_PWR_LDO (0x1 << 8)
1047 #define RT5665_PWR_LDO_BIT 8
1068 #define RT5665_PWR_ADC_MF_R (0x1 << 12)
1069 #define RT5665_PWR_ADC_MF_R_BIT 12
1076 #define RT5665_PWR_DAC_MF_R (0x1 << 8)
1077 #define RT5665_PWR_DAC_MF_R_BIT 8
1088 #define RT5665_PWR_FV2 (0x1 << 12)
1089 #define RT5665_PWR_FV2_BIT 12
1096 #define RT5665_PWR_LM (0x1 << 8)
1097 #define RT5665_PWR_LM_BIT 8
1123 #define RT5665_PWR_BST4 (0x1 << 12)
1124 #define RT5665_PWR_BST4_BIT 12
1153 #define RT5665_PWR_BST_L (0x1 << 8)
1154 #define RT5665_PWR_BST_L_BIT 8
1171 #define RT5665_PWR_OM_R (0x1 << 12)
1172 #define RT5665_PWR_OM_R_BIT 12
1193 #define RT5665_PWR_OV_R (0x1 << 12)
1194 #define RT5665_PWR_OV_R_BIT 12
1197 #define RT5665_PWR_IN_R (0x1 << 8)
1198 #define RT5665_PWR_IN_R_BIT 8
1208 #define RT5665_LOUT_CLK_DET 12
1259 #define RT5665_I2S_BP_MASK (0x1 << 8)
1260 #define RT5665_I2S_BP_SFT 8
1261 #define RT5665_I2S_BP_NOR (0x0 << 8)
1262 #define RT5665_I2S_BP_INV (0x1 << 8)
1279 #define RT5665_I2S_PD1_MASK (0x7 << 12)
1280 #define RT5665_I2S_PD1_SFT 12
1281 #define RT5665_I2S_PD1_1 (0x0 << 12)
1282 #define RT5665_I2S_PD1_2 (0x1 << 12)
1283 #define RT5665_I2S_PD1_3 (0x2 << 12)
1284 #define RT5665_I2S_PD1_4 (0x3 << 12)
1285 #define RT5665_I2S_PD1_6 (0x4 << 12)
1286 #define RT5665_I2S_PD1_8 (0x5 << 12)
1287 #define RT5665_I2S_PD1_12 (0x6 << 12)
1288 #define RT5665_I2S_PD1_16 (0x7 << 12)
1289 #define RT5665_I2S_M_PD2_MASK (0x7 << 8)
1290 #define RT5665_I2S_M_PD2_SFT 8
1291 #define RT5665_I2S_M_PD2_1 (0x0 << 8)
1292 #define RT5665_I2S_M_PD2_2 (0x1 << 8)
1293 #define RT5665_I2S_M_PD2_3 (0x2 << 8)
1294 #define RT5665_I2S_M_PD2_4 (0x3 << 8)
1295 #define RT5665_I2S_M_PD2_6 (0x4 << 8)
1296 #define RT5665_I2S_M_PD2_8 (0x5 << 8)
1297 #define RT5665_I2S_M_PD2_12 (0x6 << 8)
1298 #define RT5665_I2S_M_PD2_16 (0x7 << 8)
1320 #define RT5665_I2S_PD2_MASK (0x7 << 12)
1321 #define RT5665_I2S_PD2_SFT 12
1322 #define RT5665_I2S_PD2_1 (0x0 << 12)
1323 #define RT5665_I2S_PD2_2 (0x1 << 12)
1324 #define RT5665_I2S_PD2_3 (0x2 << 12)
1325 #define RT5665_I2S_PD2_4 (0x3 << 12)
1326 #define RT5665_I2S_PD2_6 (0x4 << 12)
1327 #define RT5665_I2S_PD2_8 (0x5 << 12)
1328 #define RT5665_I2S_PD2_12 (0x6 << 12)
1329 #define RT5665_I2S_PD2_16 (0x7 << 12)
1334 #define RT5665_I2S_PD3_MASK (0x7 << 8)
1335 #define RT5665_I2S_PD3_SFT 8
1336 #define RT5665_I2S_PD3_1 (0x0 << 8)
1337 #define RT5665_I2S_PD3_2 (0x1 << 8)
1338 #define RT5665_I2S_PD3_3 (0x2 << 8)
1339 #define RT5665_I2S_PD3_4 (0x3 << 8)
1340 #define RT5665_I2S_PD3_6 (0x4 << 8)
1341 #define RT5665_I2S_PD3_8 (0x5 << 8)
1342 #define RT5665_I2S_PD3_12 (0x6 << 8)
1343 #define RT5665_I2S_PD3_16 (0x7 << 8)
1364 #define RT5665_TDM_OUT_CH_MASK (0x3 << 8)
1365 #define RT5665_TDM_OUT_CH_2 (0x0 << 8)
1366 #define RT5665_TDM_OUT_CH_4 (0x1 << 8)
1367 #define RT5665_TDM_OUT_CH_6 (0x2 << 8)
1368 #define RT5665_TDM_OUT_CH_8 (0x3 << 8)
1383 #define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 12
1385 #define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 8
1394 #define RT5665_IF1_ADC3_SEL_SFT 8
1406 #define RT5665_PLL1_SRC_MASK (0x7 << 8)
1407 #define RT5665_PLL1_SRC_SFT 8
1408 #define RT5665_PLL1_SRC_MCLK (0x0 << 8)
1409 #define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)
1410 #define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)
1411 #define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)
1428 #define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)
1429 #define RT5665_PLL_M_SFT 12
1442 #define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)
1443 #define RT5665_DAC_STO1_ASRC_SFT 12
1450 #define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)
1451 #define RT5665_DMIC_STO1_ASRC_SFT 8
1468 #define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)
1469 #define RT5665_DA_STO1_CLK_SEL_SFT 12
1470 #define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)
1471 #define RT5665_DA_STO2_CLK_SEL_SFT 8
1478 #define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)
1479 #define RT5665_AD_STO1_CLK_SEL_SFT 12
1480 #define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)
1481 #define RT5665_AD_STO2_CLK_SEL_SFT 8
1488 #define RT5665_I2S1_RATE_MASK (0xf << 12)
1489 #define RT5665_I2S1_RATE_SFT 12
1490 #define RT5665_I2S2_RATE_MASK (0xf << 8)
1491 #define RT5665_I2S2_RATE_SFT 8
1503 #define RT5665_RAMP_MASK (0x1 << 12)
1504 #define RT5665_RAMP_SFT 12
1505 #define RT5665_RAMP_DIS (0x0 << 12)
1506 #define RT5665_RAMP_EN (0x1 << 12)
1515 #define RT5665_MRES_MASK (0x3 << 8)
1516 #define RT5665_MRES_SFT 8
1517 #define RT5665_MRES_15MO (0x0 << 8)
1518 #define RT5665_MRES_25MO (0x1 << 8)
1519 #define RT5665_MRES_35MO (0x2 << 8)
1520 #define RT5665_MRES_45MO (0x3 << 8)
1533 #define RT5665_CP_SYS_MASK (0x7 << 12)
1534 #define RT5665_CP_SYS_SFT 12
1535 #define RT5665_CP_FQ1_MASK (0x7 << 8)
1536 #define RT5665_CP_FQ1_SFT 8
1559 #define RT5665_PM_HP_MASK (0x3 << 8)
1560 #define RT5665_PM_HP_SFT 8
1561 #define RT5665_PM_HP_LV (0x0 << 8)
1562 #define RT5665_PM_HP_MV (0x1 << 8)
1563 #define RT5665_PM_HP_HV (0x2 << 8)
1594 #define RT5665_MIC2_CLK_MASK (0x1 << 12)
1595 #define RT5665_MIC2_CLK_SFT 12
1596 #define RT5665_MIC2_CLK_DIS (0x0 << 12)
1597 #define RT5665_MIC2_CLK_EN (0x1 << 12)
1607 #define RT5665_MIC2_OVCD_MASK (0x1 << 8)
1608 #define RT5665_MIC2_OVCD_SFT 8
1609 #define RT5665_MIC2_OVCD_DIS (0x0 << 8)
1610 #define RT5665_MIC2_OVCD_EN (0x1 << 8)
1626 #define RT5665_PWR_CLK1M_MASK (0x1 << 8)
1627 #define RT5665_PWR_CLK1M_SFT 8
1628 #define RT5665_PWR_CLK1M_PD (0x0 << 8)
1629 #define RT5665_PWR_CLK1M_PU (0x1 << 8)
1643 #define RT5665_I2S2_SRC_MASK (0x3 << 12)
1644 #define RT5665_I2S2_SRC_SFT 12
1645 #define RT5665_I2S2_M_PD_MASK (0x7 << 8)
1646 #define RT5665_I2S2_M_PD_SFT 8
1662 #define RT5665_EQ_DITH_MASK (0x3 << 8)
1663 #define RT5665_EQ_DITH_SFT 8
1664 #define RT5665_EQ_DITH_NOR (0x0 << 8)
1665 #define RT5665_EQ_DITH_LSB (0x1 << 8)
1666 #define RT5665_EQ_DITH_LSB_1 (0x2 << 8)
1667 #define RT5665_EQ_DITH_LSB_2 (0x3 << 8)
1674 #define RT5665_JD1_2_EN_MASK (0x1 << 12)
1675 #define RT5665_JD1_2_EN_SFT 12
1676 #define RT5665_JD1_2_DIS (0x0 << 12)
1677 #define RT5665_JD1_2_EN (0x1 << 12)
1738 #define RT5665_GP10_PIN_MASK (0x3 << 12)
1739 #define RT5665_GP10_PIN_SFT 12
1740 #define RT5665_GP10_PIN_GPIO10 (0x0 << 12)
1741 #define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)
1742 #define RT5665_GP10_PIN_LPD (0x2 << 12)
1752 #define RT5665_GP2_OUT_MASK (0x1 << 8)
1753 #define RT5665_GP2_OUT_H (0x0 << 8)
1754 #define RT5665_GP2_OUT_L (0x1 << 8)
1791 #define RT5665_GP8_OUT_MASK (0x1 << 12)
1792 #define RT5665_GP8_OUT_H (0x0 << 12)
1793 #define RT5665_GP8_OUT_L (0x1 << 12)
1803 #define RT5665_GP10_OUT_MASK (0x1 << 8)
1804 #define RT5665_GP10_OUT_H (0x0 << 8)
1805 #define RT5665_GP10_OUT_L (0x1 << 8)
1822 #define RT5665_HP_SV_MASK (0x1 << 12)
1823 #define RT5665_HP_SV_SFT 12
1824 #define RT5665_HP_SV_DIS (0x0 << 12)
1825 #define RT5665_HP_SV_EN (0x1 << 12)
1876 #define RT5665_M_RF_DIG_MASK (0x1 << 12)
1877 #define RT5665_M_RF_DIG_SFT 12
1883 #define RT5665_CKGEN_DAC1_MASK (0x1 << 12)
1884 #define RT5665_CKGEN_DAC1_SFT 12
1893 #define RT5665_CKGEN_ADC1_MASK (0x1 << 12)
1894 #define RT5665_CKGEN_ADC1_SFT 12
1928 #define RT5665_SAR_POW_MASK (0x1 << 12)
1929 #define RT5665_SAR_POW_EN (0x1 << 12)
1930 #define RT5665_SAR_POW_DIS (0x0 << 12)
1940 #define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)
1941 #define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)
1942 #define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)