Lines Matching +full:aif3 +full:- +full:pins
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
30 #include <sound/soc-dapm.h>
36 #include "rt5677-spi.h"
547 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
558 struct snd_soc_component *component = rt5677->component; in rt5677_dsp_mode_i2c_write_addr()
561 mutex_lock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_write_addr()
563 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, in rt5677_dsp_mode_i2c_write_addr()
566 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
570 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, in rt5677_dsp_mode_i2c_write_addr()
573 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
577 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, in rt5677_dsp_mode_i2c_write_addr()
580 dev_err(component->dev, "Failed to set data msb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
584 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, in rt5677_dsp_mode_i2c_write_addr()
587 dev_err(component->dev, "Failed to set data lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
591 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, in rt5677_dsp_mode_i2c_write_addr()
594 dev_err(component->dev, "Failed to set op code value: %d\n", ret); in rt5677_dsp_mode_i2c_write_addr()
599 mutex_unlock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_write_addr()
605 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
616 struct snd_soc_component *component = rt5677->component; in rt5677_dsp_mode_i2c_read_addr()
620 mutex_lock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_read_addr()
622 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB, in rt5677_dsp_mode_i2c_read_addr()
625 dev_err(component->dev, "Failed to set addr msb value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
629 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB, in rt5677_dsp_mode_i2c_read_addr()
632 dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
636 ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE, in rt5677_dsp_mode_i2c_read_addr()
639 dev_err(component->dev, "Failed to set op code value: %d\n", ret); in rt5677_dsp_mode_i2c_read_addr()
643 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb); in rt5677_dsp_mode_i2c_read_addr()
644 regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb); in rt5677_dsp_mode_i2c_read_addr()
648 mutex_unlock(&rt5677->dsp_cmd_lock); in rt5677_dsp_mode_i2c_read_addr()
654 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
670 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
694 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x2); in rt5677_set_dsp_mode()
695 rt5677->is_dsp_mode = true; in rt5677_set_dsp_mode()
697 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x2, 0x0); in rt5677_set_dsp_mode()
698 rt5677->is_dsp_mode = false; in rt5677_set_dsp_mode()
709 return -ENXIO; in rt5677_set_dsp_vad()
714 regcache_cache_only(rt5677->regmap, false); in rt5677_set_dsp_vad()
715 regcache_cache_bypass(rt5677->regmap, true); in rt5677_set_dsp_vad()
717 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x1); in rt5677_set_dsp_vad()
718 regmap_update_bits(rt5677->regmap, in rt5677_set_dsp_vad()
720 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_dsp_vad()
722 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_dsp_vad()
724 switch (rt5677->type) { in rt5677_set_dsp_vad()
726 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dsp_vad()
728 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, in rt5677_set_dsp_vad()
735 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK2, in rt5677_set_dsp_vad()
742 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x07ff); in rt5677_set_dsp_vad()
743 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x07fd); in rt5677_set_dsp_vad()
746 ret = request_firmware(&rt5677->fw1, RT5677_FIRMWARE1, in rt5677_set_dsp_vad()
747 component->dev); in rt5677_set_dsp_vad()
749 rt5677_spi_write_firmware(0x50000000, rt5677->fw1); in rt5677_set_dsp_vad()
750 release_firmware(rt5677->fw1); in rt5677_set_dsp_vad()
753 ret = request_firmware(&rt5677->fw2, RT5677_FIRMWARE2, in rt5677_set_dsp_vad()
754 component->dev); in rt5677_set_dsp_vad()
756 rt5677_spi_write_firmware(0x60000000, rt5677->fw2); in rt5677_set_dsp_vad()
757 release_firmware(rt5677->fw2); in rt5677_set_dsp_vad()
760 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x0); in rt5677_set_dsp_vad()
762 regcache_cache_bypass(rt5677->regmap, false); in rt5677_set_dsp_vad()
763 regcache_cache_only(rt5677->regmap, true); in rt5677_set_dsp_vad()
767 regcache_cache_only(rt5677->regmap, false); in rt5677_set_dsp_vad()
768 regcache_cache_bypass(rt5677->regmap, true); in rt5677_set_dsp_vad()
770 regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1, 0x1, 0x1); in rt5677_set_dsp_vad()
772 regmap_write(rt5677->regmap, RT5677_PWR_DSP1, 0x0001); in rt5677_set_dsp_vad()
774 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_set_dsp_vad()
776 regcache_cache_bypass(rt5677->regmap, false); in rt5677_set_dsp_vad()
777 regcache_mark_dirty(rt5677->regmap); in rt5677_set_dsp_vad()
778 regcache_sync(rt5677->regmap); in rt5677_set_dsp_vad()
784 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
785 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
787 static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);
806 ucontrol->value.integer.value[0] = rt5677->dsp_vad_en; in rt5677_dsp_vad_get()
817 rt5677->dsp_vad_en = !!ucontrol->value.integer.value[0]; in rt5677_dsp_vad_put()
820 rt5677_set_dsp_vad(component, rt5677->dsp_vad_en); in rt5677_dsp_vad_put()
902 * set_dmic_clk - Set parameter of dmic.
914 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in set_dmic_clk()
918 rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap, in set_dmic_clk()
922 dev_err(component->dev, "Failed to set DMIC clock\n"); in set_dmic_clk()
924 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1, in set_dmic_clk()
932 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in is_sys_clk_from_pll()
936 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val); in is_sys_clk_from_pll()
947 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in is_using_asrc()
951 if (source->reg == RT5677_ASRC_1) { in is_using_asrc()
952 switch (source->shift) { in is_using_asrc()
973 switch (source->shift) { in is_using_asrc()
1015 regmap_read(rt5677->regmap, reg, &val); in is_using_asrc()
1030 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in can_use_asrc()
1033 if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384) in can_use_asrc()
1040 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
1081 return -EINVAL; in rt5677_sel_asrc_clk_src()
1104 regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask, in rt5677_sel_asrc_clk_src()
1133 regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask, in rt5677_sel_asrc_clk_src()
1162 regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask, in rt5677_sel_asrc_clk_src()
1179 regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask, in rt5677_sel_asrc_clk_src()
1196 regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask, in rt5677_sel_asrc_clk_src()
1203 | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1209 | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1215 | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1221 | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT); in rt5677_sel_asrc_clk_src()
1225 regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask, in rt5677_sel_asrc_clk_src()
1235 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); in rt5677_dmic_use_asrc()
1239 switch (source->shift) { in rt5677_dmic_use_asrc()
1241 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1247 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1253 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1259 regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting); in rt5677_dmic_use_asrc()
1265 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); in rt5677_dmic_use_asrc()
1271 regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting); in rt5677_dmic_use_asrc()
1564 /* DAC1 L/R Source */ /* MX-29 [10:8] */
1577 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
1590 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
1615 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
1640 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1665 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1705 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1731 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1778 /* Stereo2 ADC Source */ /* MX-26 [0] */
1790 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1816 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1828 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1840 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1852 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1864 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1877 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1889 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1902 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1915 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1928 /* InBound6 Source */ /* MX-A3 [2:0] */
1941 /* InBound7 Source */ /* MX-A4 [14:12] */
1954 /* InBound8 Source */ /* MX-A4 [10:8] */
1967 /* InBound9 Source */ /* MX-A4 [6:4] */
1980 /* VAD Source */ /* MX-9F [6:4] */
1993 /* Sidetone Source */ /* MX-13 [11:9] */
2005 /* DAC1/2 Source */ /* MX-15 [1:0] */
2017 /* DAC3 Source */ /* MX-15 [5:4] */
2029 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
2062 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0] */
2088 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
2114 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
2140 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
2166 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4] */
2186 /* TDM IF1/2 ADC Data Selection */ /* MX-3B MX-40 [7:6][5:4][3:2][1:0] */
2247 /* TDM IF1 ADC Data Selection */ /* MX-3C [2:0] */
2260 /* TDM IF2 ADC Data Selection */ /* MX-41[2:0] */
2273 /* TDM IF1/2 DAC Data Selection */ /* MX-3E[14:12][10:8][6:4][2:0]
2274 MX-3F[14:12][10:8][6:4][2:0]
2275 MX-43[14:12][10:8][6:4][2:0]
2276 MX-44[14:12][10:8][6:4][2:0] */
2396 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_bst1_event()
2401 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2406 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst1_event()
2420 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_bst2_event()
2425 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2430 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_bst2_event()
2444 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_pll1_event()
2449 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2); in rt5677_set_pll1_event()
2453 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0); in rt5677_set_pll1_event()
2466 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_pll2_event()
2471 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2); in rt5677_set_pll2_event()
2475 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0); in rt5677_set_pll2_event()
2488 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_set_micbias1_event()
2493 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2500 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_micbias1_event()
2515 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_if1_adc_tdm_event()
2521 regmap_read(rt5677->regmap, RT5677_TDM1_CTRL2, &value); in rt5677_if1_adc_tdm_event()
2523 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, in rt5677_if1_adc_tdm_event()
2538 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_if2_adc_tdm_event()
2544 regmap_read(rt5677->regmap, RT5677_TDM2_CTRL2, &value); in rt5677_if2_adc_tdm_event()
2546 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, in rt5677_if2_adc_tdm_event()
2561 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rt5677_vref_event()
2567 !rt5677->is_vref_slow) { in rt5677_vref_event()
2569 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_vref_event()
2572 rt5677->is_vref_slow = true; in rt5677_vref_event()
3004 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
3005 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
4101 struct snd_soc_component *component = dai->component; in rt5677_hw_params()
4106 rt5677->lrck[dai->id] = params_rate(params); in rt5677_hw_params()
4107 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]); in rt5677_hw_params()
4109 dev_err(component->dev, "Unsupported clock setting: sysclk=%dHz lrck=%dHz\n", in rt5677_hw_params()
4110 rt5677->sysclk, rt5677->lrck[dai->id]); in rt5677_hw_params()
4111 return -EINVAL; in rt5677_hw_params()
4115 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size); in rt5677_hw_params()
4116 return -EINVAL; in rt5677_hw_params()
4119 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms); in rt5677_hw_params()
4121 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", in rt5677_hw_params()
4122 rt5677->bclk[dai->id], rt5677->lrck[dai->id]); in rt5677_hw_params()
4123 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", in rt5677_hw_params()
4124 bclk_ms, pre_div, dai->id); in rt5677_hw_params()
4139 return -EINVAL; in rt5677_hw_params()
4142 switch (dai->id) { in rt5677_hw_params()
4146 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, in rt5677_hw_params()
4148 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4154 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, in rt5677_hw_params()
4156 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4163 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, in rt5677_hw_params()
4165 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4172 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, in rt5677_hw_params()
4174 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1, in rt5677_hw_params()
4186 struct snd_soc_component *component = dai->component; in rt5677_set_dai_fmt()
4192 rt5677->master[dai->id] = 1; in rt5677_set_dai_fmt()
4196 rt5677->master[dai->id] = 0; in rt5677_set_dai_fmt()
4199 return -EINVAL; in rt5677_set_dai_fmt()
4209 return -EINVAL; in rt5677_set_dai_fmt()
4225 return -EINVAL; in rt5677_set_dai_fmt()
4228 switch (dai->id) { in rt5677_set_dai_fmt()
4230 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP, in rt5677_set_dai_fmt()
4235 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP, in rt5677_set_dai_fmt()
4240 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP, in rt5677_set_dai_fmt()
4245 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP, in rt5677_set_dai_fmt()
4260 struct snd_soc_component *component = dai->component; in rt5677_set_dai_sysclk()
4264 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src) in rt5677_set_dai_sysclk()
4278 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id); in rt5677_set_dai_sysclk()
4279 return -EINVAL; in rt5677_set_dai_sysclk()
4281 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_sysclk()
4283 rt5677->sysclk = freq; in rt5677_set_dai_sysclk()
4284 rt5677->sysclk_src = clk_id; in rt5677_set_dai_sysclk()
4286 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); in rt5677_set_dai_sysclk()
4292 * rt5677_pll_calc - Calcualte PLL M/N/K code.
4305 return -EINVAL; in rt5677_pll_calc()
4313 struct snd_soc_component *component = dai->component; in rt5677_set_dai_pll()
4318 if (source == rt5677->pll_src && freq_in == rt5677->pll_in && in rt5677_set_dai_pll()
4319 freq_out == rt5677->pll_out) in rt5677_set_dai_pll()
4323 dev_dbg(component->dev, "PLL disabled\n"); in rt5677_set_dai_pll()
4325 rt5677->pll_in = 0; in rt5677_set_dai_pll()
4326 rt5677->pll_out = 0; in rt5677_set_dai_pll()
4327 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4334 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4341 switch (dai->id) { in rt5677_set_dai_pll()
4343 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4347 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4351 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4355 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1, in rt5677_set_dai_pll()
4363 dev_err(component->dev, "Unknown PLL source %d\n", source); in rt5677_set_dai_pll()
4364 return -EINVAL; in rt5677_set_dai_pll()
4369 dev_err(component->dev, "Unsupport input clock %d\n", freq_in); in rt5677_set_dai_pll()
4373 dev_dbg(component->dev, "m_bypass=%d m=%d n=%d k=%d\n", in rt5677_set_dai_pll()
4377 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1, in rt5677_set_dai_pll()
4379 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2, in rt5677_set_dai_pll()
4383 rt5677->pll_in = freq_in; in rt5677_set_dai_pll()
4384 rt5677->pll_out = freq_out; in rt5677_set_dai_pll()
4385 rt5677->pll_src = source; in rt5677_set_dai_pll()
4393 struct snd_soc_component *component = dai->component; in rt5677_set_tdm_slot()
4433 switch (dai->id) { in rt5677_set_tdm_slot()
4435 regmap_update_bits(rt5677->regmap, RT5677_TDM1_CTRL1, 0x1f00, in rt5677_set_tdm_slot()
4437 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x8000, in rt5677_set_tdm_slot()
4441 regmap_update_bits(rt5677->regmap, RT5677_TDM2_CTRL1, 0x1f00, in rt5677_set_tdm_slot()
4443 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x80, in rt5677_set_tdm_slot()
4466 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4469 regmap_update_bits(rt5677->regmap, in rt5677_set_bias_level()
4472 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1, in rt5677_set_bias_level()
4478 rt5677->is_vref_slow = false; in rt5677_set_bias_level()
4479 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2, in rt5677_set_bias_level()
4481 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, in rt5677_set_bias_level()
4490 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0); in rt5677_set_bias_level()
4491 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000); in rt5677_set_bias_level()
4492 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000); in rt5677_set_bias_level()
4493 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022); in rt5677_set_bias_level()
4494 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000); in rt5677_set_bias_level()
4495 regmap_update_bits(rt5677->regmap, in rt5677_set_bias_level()
4498 if (rt5677->dsp_vad_en) in rt5677_set_bias_level()
4516 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_gpio_set()
4521 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, in rt5677_gpio_set()
4537 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_gpio_direction_out()
4543 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, in rt5677_gpio_direction_out()
4560 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value); in rt5677_gpio_get()
4573 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_gpio_direction_in()
4578 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3, in rt5677_gpio_direction_in()
4590 * 0 - floating
4591 * 1 - pull down
4592 * 2 - pull up
4601 shift = 2 * (1 - offset); in rt5677_gpio_config()
4602 regmap_update_bits(rt5677->regmap, in rt5677_gpio_config()
4609 shift = 2 * (9 - offset); in rt5677_gpio_config()
4610 regmap_update_bits(rt5677->regmap, in rt5677_gpio_config()
4624 struct regmap_irq_chip_data *data = rt5677->irq_data; in rt5677_to_irq()
4627 if ((rt5677->pdata.jd1_gpio == 1 && offset == RT5677_GPIO1) || in rt5677_to_irq()
4628 (rt5677->pdata.jd1_gpio == 2 && in rt5677_to_irq()
4630 (rt5677->pdata.jd1_gpio == 3 && in rt5677_to_irq()
4633 } else if ((rt5677->pdata.jd2_gpio == 1 && offset == RT5677_GPIO4) || in rt5677_to_irq()
4634 (rt5677->pdata.jd2_gpio == 2 && in rt5677_to_irq()
4636 (rt5677->pdata.jd2_gpio == 3 && in rt5677_to_irq()
4639 } else if ((rt5677->pdata.jd3_gpio == 1 && in rt5677_to_irq()
4641 (rt5677->pdata.jd3_gpio == 2 && in rt5677_to_irq()
4643 (rt5677->pdata.jd3_gpio == 3 && in rt5677_to_irq()
4647 return -ENXIO; in rt5677_to_irq()
4669 rt5677->gpio_chip = rt5677_template_chip; in rt5677_init_gpio()
4670 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM; in rt5677_init_gpio()
4671 rt5677->gpio_chip.parent = &i2c->dev; in rt5677_init_gpio()
4672 rt5677->gpio_chip.base = -1; in rt5677_init_gpio()
4674 ret = gpiochip_add_data(&rt5677->gpio_chip, rt5677); in rt5677_init_gpio()
4676 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret); in rt5677_init_gpio()
4683 gpiochip_remove(&rt5677->gpio_chip); in rt5677_free_gpio()
4706 rt5677->component = component; in rt5677_probe()
4708 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { in rt5677_probe()
4720 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020); in rt5677_probe()
4721 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00); in rt5677_probe()
4724 rt5677_gpio_config(rt5677, i, rt5677->pdata.gpio_config[i]); in rt5677_probe()
4726 if (rt5677->irq_data) { in rt5677_probe()
4727 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1, 0x8000, in rt5677_probe()
4729 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x0018, in rt5677_probe()
4732 if (rt5677->pdata.jd1_gpio) in rt5677_probe()
4733 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, in rt5677_probe()
4735 rt5677->pdata.jd1_gpio << in rt5677_probe()
4738 if (rt5677->pdata.jd2_gpio) in rt5677_probe()
4739 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, in rt5677_probe()
4741 rt5677->pdata.jd2_gpio << in rt5677_probe()
4744 if (rt5677->pdata.jd3_gpio) in rt5677_probe()
4745 regmap_update_bits(rt5677->regmap, RT5677_JD_CTRL1, in rt5677_probe()
4747 rt5677->pdata.jd3_gpio << in rt5677_probe()
4751 mutex_init(&rt5677->dsp_cmd_lock); in rt5677_probe()
4752 mutex_init(&rt5677->dsp_pri_lock); in rt5677_probe()
4761 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_remove()
4762 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); in rt5677_remove()
4763 gpiod_set_value_cansleep(rt5677->reset_pin, 1); in rt5677_remove()
4771 if (!rt5677->dsp_vad_en) { in rt5677_suspend()
4772 regcache_cache_only(rt5677->regmap, true); in rt5677_suspend()
4773 regcache_mark_dirty(rt5677->regmap); in rt5677_suspend()
4775 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); in rt5677_suspend()
4776 gpiod_set_value_cansleep(rt5677->reset_pin, 1); in rt5677_suspend()
4786 if (!rt5677->dsp_vad_en) { in rt5677_resume()
4787 rt5677->pll_src = 0; in rt5677_resume()
4788 rt5677->pll_in = 0; in rt5677_resume()
4789 rt5677->pll_out = 0; in rt5677_resume()
4790 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); in rt5677_resume()
4791 gpiod_set_value_cansleep(rt5677->reset_pin, 0); in rt5677_resume()
4792 if (rt5677->pow_ldo2 || rt5677->reset_pin) in rt5677_resume()
4795 regcache_cache_only(rt5677->regmap, false); in rt5677_resume()
4796 regcache_sync(rt5677->regmap); in rt5677_resume()
4811 if (rt5677->is_dsp_mode) { in rt5677_read()
4813 mutex_lock(&rt5677->dsp_pri_lock); in rt5677_read()
4817 mutex_unlock(&rt5677->dsp_pri_lock); in rt5677_read()
4822 regmap_read(rt5677->regmap_physical, reg, val); in rt5677_read()
4833 if (rt5677->is_dsp_mode) { in rt5677_write()
4835 mutex_lock(&rt5677->dsp_pri_lock); in rt5677_write()
4840 mutex_unlock(&rt5677->dsp_pri_lock); in rt5677_write()
4845 regmap_write(rt5677->regmap_physical, reg, val); in rt5677_write()
4865 .name = "rt5677-aif1",
4884 .name = "rt5677-aif2",
4903 .name = "rt5677-aif3",
4906 .stream_name = "AIF3 Playback",
4913 .stream_name = "AIF3 Capture",
4922 .name = "rt5677-aif4",
4941 .name = "rt5677-slimbus",
5029 rt5677->pdata.dmic2_clk_pin = val; in rt5677_read_acpi_properties()
5031 rt5677->pdata.in1_diff = device_property_read_bool(dev, "IN1"); in rt5677_read_acpi_properties()
5032 rt5677->pdata.in2_diff = device_property_read_bool(dev, "IN2"); in rt5677_read_acpi_properties()
5033 rt5677->pdata.lout1_diff = device_property_read_bool(dev, "OUT1"); in rt5677_read_acpi_properties()
5034 rt5677->pdata.lout2_diff = device_property_read_bool(dev, "OUT2"); in rt5677_read_acpi_properties()
5035 rt5677->pdata.lout3_diff = device_property_read_bool(dev, "OUT3"); in rt5677_read_acpi_properties()
5037 device_property_read_u32(dev, "JD1", &rt5677->pdata.jd1_gpio); in rt5677_read_acpi_properties()
5038 device_property_read_u32(dev, "JD2", &rt5677->pdata.jd2_gpio); in rt5677_read_acpi_properties()
5039 device_property_read_u32(dev, "JD3", &rt5677->pdata.jd3_gpio); in rt5677_read_acpi_properties()
5045 rt5677->pdata.in1_diff = device_property_read_bool(dev, in rt5677_read_device_properties()
5046 "realtek,in1-differential"); in rt5677_read_device_properties()
5047 rt5677->pdata.in2_diff = device_property_read_bool(dev, in rt5677_read_device_properties()
5048 "realtek,in2-differential"); in rt5677_read_device_properties()
5049 rt5677->pdata.lout1_diff = device_property_read_bool(dev, in rt5677_read_device_properties()
5050 "realtek,lout1-differential"); in rt5677_read_device_properties()
5051 rt5677->pdata.lout2_diff = device_property_read_bool(dev, in rt5677_read_device_properties()
5052 "realtek,lout2-differential"); in rt5677_read_device_properties()
5053 rt5677->pdata.lout3_diff = device_property_read_bool(dev, in rt5677_read_device_properties()
5054 "realtek,lout3-differential"); in rt5677_read_device_properties()
5056 device_property_read_u8_array(dev, "realtek,gpio-config", in rt5677_read_device_properties()
5057 rt5677->pdata.gpio_config, RT5677_GPIO_NUM); in rt5677_read_device_properties()
5059 device_property_read_u32(dev, "realtek,jd1-gpio", in rt5677_read_device_properties()
5060 &rt5677->pdata.jd1_gpio); in rt5677_read_device_properties()
5061 device_property_read_u32(dev, "realtek,jd2-gpio", in rt5677_read_device_properties()
5062 &rt5677->pdata.jd2_gpio); in rt5677_read_device_properties()
5063 device_property_read_u32(dev, "realtek,jd3-gpio", in rt5677_read_device_properties()
5064 &rt5677->pdata.jd3_gpio); in rt5677_read_device_properties()
5098 if (!rt5677->pdata.jd1_gpio && in rt5677_init_irq()
5099 !rt5677->pdata.jd2_gpio && in rt5677_init_irq()
5100 !rt5677->pdata.jd3_gpio) in rt5677_init_irq()
5103 if (!i2c->irq) { in rt5677_init_irq()
5104 dev_err(&i2c->dev, "No interrupt specified\n"); in rt5677_init_irq()
5105 return -EINVAL; in rt5677_init_irq()
5108 ret = regmap_add_irq_chip(rt5677->regmap, i2c->irq, in rt5677_init_irq()
5110 &rt5677_irq_chip, &rt5677->irq_data); in rt5677_init_irq()
5113 dev_err(&i2c->dev, "Failed to register IRQ chip: %d\n", ret); in rt5677_init_irq()
5124 if (rt5677->irq_data) in rt5677_free_irq()
5125 regmap_del_irq_chip(i2c->irq, rt5677->irq_data); in rt5677_free_irq()
5134 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv), in rt5677_i2c_probe()
5137 return -ENOMEM; in rt5677_i2c_probe()
5141 if (i2c->dev.of_node) { in rt5677_i2c_probe()
5144 match_id = of_match_device(rt5677_of_match, &i2c->dev); in rt5677_i2c_probe()
5146 rt5677->type = (enum rt5677_type)match_id->data; in rt5677_i2c_probe()
5148 rt5677_read_device_properties(rt5677, &i2c->dev); in rt5677_i2c_probe()
5149 } else if (ACPI_HANDLE(&i2c->dev)) { in rt5677_i2c_probe()
5152 acpi_id = acpi_match_device(rt5677_acpi_match, &i2c->dev); in rt5677_i2c_probe()
5154 rt5677->type = (enum rt5677_type)acpi_id->driver_data; in rt5677_i2c_probe()
5156 rt5677_read_acpi_properties(rt5677, &i2c->dev); in rt5677_i2c_probe()
5158 return -EINVAL; in rt5677_i2c_probe()
5161 /* pow-ldo2 and reset are optional. The codec pins may be statically in rt5677_i2c_probe()
5165 rt5677->pow_ldo2 = devm_gpiod_get_optional(&i2c->dev, in rt5677_i2c_probe()
5166 "realtek,pow-ldo2", GPIOD_OUT_HIGH); in rt5677_i2c_probe()
5167 if (IS_ERR(rt5677->pow_ldo2)) { in rt5677_i2c_probe()
5168 ret = PTR_ERR(rt5677->pow_ldo2); in rt5677_i2c_probe()
5169 dev_err(&i2c->dev, "Failed to request POW_LDO2: %d\n", ret); in rt5677_i2c_probe()
5172 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, in rt5677_i2c_probe()
5174 if (IS_ERR(rt5677->reset_pin)) { in rt5677_i2c_probe()
5175 ret = PTR_ERR(rt5677->reset_pin); in rt5677_i2c_probe()
5176 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); in rt5677_i2c_probe()
5180 if (rt5677->pow_ldo2 || rt5677->reset_pin) { in rt5677_i2c_probe()
5188 rt5677->regmap_physical = devm_regmap_init_i2c(i2c, in rt5677_i2c_probe()
5190 if (IS_ERR(rt5677->regmap_physical)) { in rt5677_i2c_probe()
5191 ret = PTR_ERR(rt5677->regmap_physical); in rt5677_i2c_probe()
5192 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5677_i2c_probe()
5197 rt5677->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5677_regmap); in rt5677_i2c_probe()
5198 if (IS_ERR(rt5677->regmap)) { in rt5677_i2c_probe()
5199 ret = PTR_ERR(rt5677->regmap); in rt5677_i2c_probe()
5200 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", in rt5677_i2c_probe()
5205 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val); in rt5677_i2c_probe()
5207 dev_err(&i2c->dev, in rt5677_i2c_probe()
5209 return -ENODEV; in rt5677_i2c_probe()
5212 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); in rt5677_i2c_probe()
5214 ret = regmap_register_patch(rt5677->regmap, init_list, in rt5677_i2c_probe()
5217 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); in rt5677_i2c_probe()
5219 if (rt5677->pdata.in1_diff) in rt5677_i2c_probe()
5220 regmap_update_bits(rt5677->regmap, RT5677_IN1, in rt5677_i2c_probe()
5223 if (rt5677->pdata.in2_diff) in rt5677_i2c_probe()
5224 regmap_update_bits(rt5677->regmap, RT5677_IN1, in rt5677_i2c_probe()
5227 if (rt5677->pdata.lout1_diff) in rt5677_i2c_probe()
5228 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5231 if (rt5677->pdata.lout2_diff) in rt5677_i2c_probe()
5232 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5235 if (rt5677->pdata.lout3_diff) in rt5677_i2c_probe()
5236 regmap_update_bits(rt5677->regmap, RT5677_LOUT1, in rt5677_i2c_probe()
5239 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) { in rt5677_i2c_probe()
5240 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2, in rt5677_i2c_probe()
5243 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2, in rt5677_i2c_probe()
5248 if (rt5677->pdata.micbias1_vdd_3v3) in rt5677_i2c_probe()
5249 regmap_update_bits(rt5677->regmap, RT5677_MICBIAS, in rt5677_i2c_probe()
5256 return devm_snd_soc_register_component(&i2c->dev, in rt5677_i2c_probe()