Lines Matching +full:8 +full:- +full:12
2 * rt5677.h -- RT5677 ALSA SoC audio driver
23 /* I/O - Output */
25 /* I/O - Input */
28 /* I/O - SLIMBus */
34 /* I/O - ADC/DAC */
46 /* Mixer - D-D */
63 /* Mixer - PDM */
119 /* Format - ADC/DAC */
127 /* Function - Analog */
162 /* Function - Digital */
321 #define RT5677_LOUT2_L_DF (0x1 << 12)
322 #define RT5677_LOUT2_L_DF_SFT (12)
329 #define RT5677_LOUT2_ENH_DRV (0x1 << 8)
330 #define RT5677_LOUT2_ENH_DRV_SFT (8)
335 #define RT5677_BST_MASK1 (0xf << 12)
336 #define RT5677_BST_SFT1 12
337 #define RT5677_BST_MASK2 (0xf << 8)
338 #define RT5677_BST_SFT2 8
380 #define RT5677_ST_HPF_PATH (0x1 << 12)
381 #define RT5677_ST_HPF_PATH_SFT 12
400 #define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
401 #define RT5677_SEL_DAC4_L_SRC_SFT 12
404 #define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
405 #define RT5677_SEL_DAC4_R_SRC_SFT 8
416 #define RT5677_DAC4_L_VOL_MASK (0xff << 8)
417 #define RT5677_DAC4_L_VOL_SFT 8
422 #define RT5677_DAC3_L_VOL_MASK (0xff << 8)
423 #define RT5677_DAC3_L_VOL_SFT 8
428 #define RT5677_DAC1_L_VOL_MASK (0xff << 8)
429 #define RT5677_DAC1_L_VOL_SFT 8
434 #define RT5677_DAC2_L_VOL_MASK (0xff << 8)
435 #define RT5677_DAC2_L_VOL_SFT 8
464 #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
465 #define RT5677_STO1_ADC_R_BST_SFT 12
468 #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
469 #define RT5677_STO2_ADC_L_BST_SFT 8
476 #define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
477 #define RT5677_STO2_ADC_L_VOL_SFT 8
484 #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
485 #define RT5677_MONO_ADC_R_BST_SFT 12
492 #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
493 #define RT5677_STO3_ADC_R_BST_SFT 12
496 #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
497 #define RT5677_STO4_ADC_L_BST_SFT 8
504 #define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
505 #define RT5677_STO3_ADC_L_VOL_SFT 8
510 #define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
511 #define RT5677_STO4_ADC_L_VOL_SFT 8
520 #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
521 #define RT5677_SEL_STO4_ADC1_SFT 12
524 #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
525 #define RT5677_SEL_STO4_DMIC_SFT 8
536 #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
537 #define RT5677_SEL_STO3_ADC1_SFT 12
540 #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
541 #define RT5677_SEL_STO3_DMIC_SFT 8
552 #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
553 #define RT5677_SEL_STO2_ADC1_SFT 12
556 #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
557 #define RT5677_SEL_STO2_DMIC_SFT 8
572 #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
573 #define RT5677_SEL_STO1_ADC1_SFT 12
576 #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
577 #define RT5677_SEL_STO1_DMIC_SFT 8
588 #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
589 #define RT5677_SEL_MONO_ADC_L1_SFT 12
592 #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
593 #define RT5677_SEL_MONO_DMIC_L_SFT 8
610 #define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
611 #define RT5677_DAC1_L_SEL_SFT 8
624 #define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
625 #define RT5677_DAC1_L_STO_L_VOL_SFT 12
632 #define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
633 #define RT5677_DAC1_R_STO_L_VOL_SFT 8
654 #define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
655 #define RT5677_DAC2_L_MONO_L_VOL_SFT 12
662 #define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
663 #define RT5677_DAC1_L_MONO_L_VOL_SFT 8
686 #define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
687 #define RT5677_MONO_L_DD1_L_VOL_SFT 12
694 #define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
695 #define RT5677_DAC3_R_DD1_L_VOL_SFT 8
720 #define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
721 #define RT5677_MONO_L_DD2_L_VOL_SFT 12
728 #define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
729 #define RT5677_DAC4_R_DD2_L_VOL_SFT 8
766 #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
767 #define RT5677_SEL_PDM1_L_SFT 12
770 #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
771 #define RT5677_SEL_PDM1_R_SFT 8
791 #define RT5677_PDM1_I2C_ID (0xf << 12)
795 #define RT5677_PDM1_I2C_BUSY (0x1 << 8)
803 #define RT5677_IF1_ADC_MODE_MASK (0x1 << 12)
804 #define RT5677_IF1_ADC_MODE_SFT 12
805 #define RT5677_IF1_ADC_MODE_I2S (0x0 << 12)
806 #define RT5677_IF1_ADC_MODE_TDM (0x1 << 12)
819 #define RT5677_IF1_ADC3_MASK (0x3 << 8)
820 #define RT5677_IF1_ADC3_SFT 8
829 #define RT5677_IF1_DAC0_MASK (0x7 << 12)
830 #define RT5677_IF1_DAC0_SFT 12
831 #define RT5677_IF1_DAC1_MASK (0x7 << 8)
832 #define RT5677_IF1_DAC1_SFT 8
839 #define RT5677_IF1_DAC4_MASK (0x7 << 12)
840 #define RT5677_IF1_DAC4_SFT 12
841 #define RT5677_IF1_DAC5_MASK (0x7 << 8)
842 #define RT5677_IF1_DAC5_SFT 8
849 #define RT5677_IF2_ADC_MODE_MASK (0x1 << 12)
850 #define RT5677_IF2_ADC_MODE_SFT 12
851 #define RT5677_IF2_ADC_MODE_I2S (0x0 << 12)
852 #define RT5677_IF2_ADC_MODE_TDM (0x1 << 12)
865 #define RT5677_IF2_ADC3_MASK (0x3 << 8)
866 #define RT5677_IF2_ADC3_SFT 8
875 #define RT5677_IF2_DAC0_MASK (0x7 << 12)
876 #define RT5677_IF2_DAC0_SFT 12
877 #define RT5677_IF2_DAC1_MASK (0x7 << 8)
878 #define RT5677_IF2_DAC1_SFT 8
885 #define RT5677_IF2_DAC4_MASK (0x7 << 12)
886 #define RT5677_IF2_DAC4_SFT 12
887 #define RT5677_IF2_DAC5_MASK (0x7 << 8)
888 #define RT5677_IF2_DAC5_SFT 8
907 #define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
908 #define RT5677_DMIC_R_STO1_LH_SFT 12
909 #define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
910 #define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
923 #define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
924 #define RT5677_DMIC_R_STO2_LH_SFT 8
925 #define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
926 #define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
991 #define RT5677_PWR_DAC1 (0x1 << 12)
992 #define RT5677_PWR_DAC1_BIT 12
1019 #define RT5677_PWR_DAC_S1F (0x1 << 12)
1020 #define RT5677_PWR_DAC_S1F_BIT 12
1027 #define RT5677_PWR_DAC_M3F_R (0x1 << 8)
1028 #define RT5677_PWR_DAC_M3F_R_BIT 8
1051 #define RT5677_PWR_LO1 (0x1 << 12)
1052 #define RT5677_PWR_LO1_BIT 12
1059 #define RT5677_PWR_VREF2 (0x1 << 8)
1060 #define RT5677_PWR_VREF2_BIT 8
1075 #define RT5677_PWR_SLIM (0x1 << 12)
1076 #define RT5677_PWR_SLIM_BIT 12
1083 #define RT5677_PWR_PLL2 (0x1 << 8)
1084 #define RT5677_PWR_PLL2_BIT 8
1105 #define RT5677_PWR_SR5 (0x1 << 8)
1106 #define RT5677_PWR_SR5_BIT 8
1127 #define RT5677_PWR_SR6_RDY (0x1 << 8)
1128 #define RT5677_PWR_SR6_RDY_BIT 8
1153 #define RT5677_PWR_SR7_ISO (0x1 << 8)
1154 #define RT5677_PWR_SR7_ISO_BIT 8
1182 #define RT5677_I2S_I_CP_MASK (0x3 << 8)
1183 #define RT5677_I2S_I_CP_SFT 8
1184 #define RT5677_I2S_I_CP_OFF (0x0 << 8)
1185 #define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1186 #define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
1205 #define RT5677_I2S_PD1_MASK (0x7 << 12)
1206 #define RT5677_I2S_PD1_SFT 12
1207 #define RT5677_I2S_PD1_1 (0x0 << 12)
1208 #define RT5677_I2S_PD1_2 (0x1 << 12)
1209 #define RT5677_I2S_PD1_3 (0x2 << 12)
1210 #define RT5677_I2S_PD1_4 (0x3 << 12)
1211 #define RT5677_I2S_PD1_6 (0x4 << 12)
1212 #define RT5677_I2S_PD1_8 (0x5 << 12)
1213 #define RT5677_I2S_PD1_12 (0x6 << 12)
1214 #define RT5677_I2S_PD1_16 (0x7 << 12)
1219 #define RT5677_I2S_PD2_MASK (0x7 << 8)
1220 #define RT5677_I2S_PD2_SFT 8
1221 #define RT5677_I2S_PD2_1 (0x0 << 8)
1222 #define RT5677_I2S_PD2_2 (0x1 << 8)
1223 #define RT5677_I2S_PD2_3 (0x2 << 8)
1224 #define RT5677_I2S_PD2_4 (0x3 << 8)
1225 #define RT5677_I2S_PD2_6 (0x4 << 8)
1226 #define RT5677_I2S_PD2_8 (0x5 << 8)
1227 #define RT5677_I2S_PD2_12 (0x6 << 8)
1228 #define RT5677_I2S_PD2_16 (0x7 << 8)
1259 #define RT5677_I2S_PD5_MASK (0x7 << 12)
1260 #define RT5677_I2S_PD5_SFT 12
1261 #define RT5677_I2S_PD5_1 (0x0 << 12)
1262 #define RT5677_I2S_PD5_2 (0x1 << 12)
1263 #define RT5677_I2S_PD5_3 (0x2 << 12)
1264 #define RT5677_I2S_PD5_4 (0x3 << 12)
1265 #define RT5677_I2S_PD5_6 (0x4 << 12)
1266 #define RT5677_I2S_PD5_8 (0x5 << 12)
1267 #define RT5677_I2S_PD5_12 (0x6 << 12)
1268 #define RT5677_I2S_PD5_16 (0x7 << 12)
1269 #define RT5677_I2S_PD6_MASK (0x7 << 8)
1270 #define RT5677_I2S_PD6_SFT 8
1271 #define RT5677_I2S_PD6_1 (0x0 << 8)
1272 #define RT5677_I2S_PD6_2 (0x1 << 8)
1273 #define RT5677_I2S_PD6_3 (0x2 << 8)
1274 #define RT5677_I2S_PD6_4 (0x3 << 8)
1275 #define RT5677_I2S_PD6_6 (0x4 << 8)
1276 #define RT5677_I2S_PD6_8 (0x5 << 8)
1277 #define RT5677_I2S_PD6_12 (0x6 << 8)
1278 #define RT5677_I2S_PD6_16 (0x7 << 8)
1338 #define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
1339 #define RT5677_PLL_M_SFT 12
1363 #define RT5677_PLL1_PD_MASK (0x1 << 8)
1364 #define RT5677_PLL1_PD_SFT 8
1365 #define RT5677_PLL1_PD_1 (0x0 << 8)
1366 #define RT5677_PLL1_PD_2 (0x1 << 8)
1383 #define RT5677_PLL2_SRC_MASK (0x7 << 12)
1384 #define RT5677_PLL2_SRC_SFT 12
1385 #define RT5677_PLL2_SRC_MCLK (0x0 << 12)
1386 #define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1387 #define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
1388 #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1389 #define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
1390 #define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
1391 #define RT5677_PLL2_SRC_SLIM (0x6 << 12)
1398 #define RT5677_DSP_ASRC_I_SRC (0x3 << 8)
1399 #define RT5677_DSP_ASRC_I_SRC_SFT 8
1400 #define RT5677_DSP_ASRC_I_MCLK (0x0 << 8)
1401 #define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8)
1402 #define RT5677_DSP_ASRC_I_SLIM (0x2 << 8)
1403 #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8)
1410 #define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12)
1411 #define RT5677_DA_STO_CLK_SEL_SFT 12
1418 #define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12)
1419 #define RT5677_DA_MONO3L_CLK_SEL_SFT 12
1420 #define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8)
1421 #define RT5677_DA_MONO3R_CLK_SEL_SFT 8
1428 #define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12)
1429 #define RT5677_AD_STO1_CLK_SEL_SFT 12
1430 #define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8)
1431 #define RT5677_AD_STO2_CLK_SEL_SFT 8
1438 #define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12)
1439 #define RT5677_AD_MONOL_CLK_SEL_SFT 12
1440 #define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8)
1441 #define RT5677_AD_MONOR_CLK_SEL_SFT 8
1444 #define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12)
1445 #define RT5677_DSP_OB_0_3_CLK_SEL_SFT 12
1446 #define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)
1447 #define RT5677_DSP_OB_4_7_CLK_SEL_SFT 8
1449 /* ASRC Control 8 (0x8a) */
1450 #define RT5677_I2S1_CLK_SEL_MASK (0xf << 12)
1451 #define RT5677_I2S1_CLK_SEL_SFT 12
1452 #define RT5677_I2S2_CLK_SEL_MASK (0xf << 8)
1453 #define RT5677_I2S2_CLK_SEL_SFT 8
1460 #define RT5677_VAD_SRC_MASK (0x7 << 8)
1461 #define RT5677_VAD_SRC_SFT 8
1464 #define RT5677_IB01_SRC_MASK (0x7 << 12)
1465 #define RT5677_IB01_SRC_SFT 12
1466 #define RT5677_IB23_SRC_MASK (0x7 << 8)
1467 #define RT5677_IB23_SRC_SFT 8
1474 #define RT5677_IB7_SRC_MASK (0x7 << 12)
1475 #define RT5677_IB7_SRC_SFT 12
1476 #define RT5677_IB8_SRC_MASK (0x7 << 8)
1477 #define RT5677_IB8_SRC_SFT 8
1496 #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)
1497 #define RT5677_SEL_GPIO_JD2_SFT 12
1508 #define RT5677_INV_GPIO_JD1 (0x1 << 12)
1509 #define RT5677_INV_GPIO_JD1_SFT 12
1516 #define RT5677_INV_GPIO_JD2 (0x1 << 8)
1517 #define RT5677_INV_GPIO_JD2_SFT 8
1572 #define RT5677_GPIO5_P_MASK (0x1 << 12)
1573 #define RT5677_GPIO5_P_SFT 12
1574 #define RT5677_GPIO5_P_NOR (0x0 << 12)
1575 #define RT5677_GPIO5_P_INV (0x1 << 12)
1588 #define RT5677_GPIO3_DIR_MASK (0x1 << 8)
1589 #define RT5677_GPIO3_DIR_SFT 8
1590 #define RT5677_GPIO3_DIR_IN (0x0 << 8)
1591 #define RT5677_GPIO3_DIR_OUT (0x1 << 8)
1646 #define RT5677_DSP_IB_6_H (0x1 << 12)
1647 #define RT5677_DSP_IB_6_H_SFT 12
1750 RT5677_AD_STEREO2_FILTER = (0x1 << 8),
1754 RT5677_AD_MONO_R_FILTER = (0x1 << 12),
1778 /* configures GPIO, 0 - floating, 1 - pulldown, 2 - pullup */