Lines Matching +full:4 +full:- +full:channel
17 * - implement DAPM and input muxing
18 * - implement modulation limit
19 * - implement non-default PWM start
22 * because the registers are of unequal size, and multi-byte registers
27 * it doesn't matter because the entire map can be accessed as 8-bit
30 * routines have to be open-coded.
80 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
98 * Default TAS5086 power-up configuration
139 return 4; in tas5086_register_size()
182 size = tas5086_register_size(&client->dev, reg); in tas5086_reg_write()
184 return -EINVAL; in tas5086_reg_write()
188 for (i = size; i >= 1; --i) { in tas5086_reg_write()
199 return -EIO; in tas5086_reg_write()
206 uint8_t send_buf, recv_buf[4]; in tas5086_reg_read()
212 size = tas5086_register_size(&client->dev, reg); in tas5086_reg_read()
214 return -EINVAL; in tas5086_reg_read()
218 msgs[0].addr = client->addr; in tas5086_reg_read()
223 msgs[1].addr = client->addr; in tas5086_reg_read()
228 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); in tas5086_reg_read()
232 return -EIO; in tas5086_reg_read()
255 /* Current sample rate for de-emphasis control */
269 if (priv->deemph) { in tas5086_set_deemph()
271 if (tas5086_deemph[i] == priv->rate) { in tas5086_set_deemph()
278 return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1, in tas5086_set_deemph()
288 ucontrol->value.integer.value[0] = priv->deemph; in tas5086_get_deemph()
299 priv->deemph = ucontrol->value.integer.value[0]; in tas5086_put_deemph()
308 struct snd_soc_component *component = codec_dai->component; in tas5086_set_dai_sysclk()
313 priv->mclk = freq; in tas5086_set_dai_sysclk()
316 priv->sclk = freq; in tas5086_set_dai_sysclk()
326 struct snd_soc_component *component = codec_dai->component; in tas5086_set_dai_fmt()
331 dev_err(component->dev, "Invalid clocking mode\n"); in tas5086_set_dai_fmt()
332 return -EINVAL; in tas5086_set_dai_fmt()
336 priv->format = format; in tas5086_set_dai_fmt()
357 return -ENOENT; in index_in_array()
364 struct snd_soc_component *component = dai->component; in tas5086_hw_params()
369 priv->rate = params_rate(params); in tas5086_hw_params()
373 ARRAY_SIZE(tas5086_sample_rates), priv->rate); in tas5086_hw_params()
376 dev_err(component->dev, "Invalid sample rate\n"); in tas5086_hw_params()
377 return -EINVAL; in tas5086_hw_params()
380 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
388 priv->mclk / priv->rate); in tas5086_hw_params()
390 dev_err(component->dev, "Invalid MCLK / Fs ratio\n"); in tas5086_hw_params()
391 return -EINVAL; in tas5086_hw_params()
394 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
401 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
403 (priv->sclk == 48 * priv->rate) ? in tas5086_hw_params()
411 * a logical bit-boundary. Hence, we have to refer to the format passed in tas5086_hw_params()
416 switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) { in tas5086_hw_params()
427 dev_err(component->dev, "Invalid DAI format\n"); in tas5086_hw_params()
428 return -EINVAL; in tas5086_hw_params()
443 dev_err(component->dev, "Invalid bit width\n"); in tas5086_hw_params()
444 return -EINVAL; in tas5086_hw_params()
447 ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); in tas5086_hw_params()
452 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, in tas5086_hw_params()
462 struct snd_soc_component *component = dai->component; in tas5086_mute_stream()
469 return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); in tas5086_mute_stream()
474 if (gpio_is_valid(priv->gpio_nreset)) { in tas5086_reset()
475 /* Reset codec - minimum assertion time is 400ns */ in tas5086_reset()
476 gpio_direction_output(priv->gpio_nreset, 0); in tas5086_reset()
478 gpio_set_value(priv->gpio_nreset, 1); in tas5086_reset()
497 * If any of the channels is configured to start in Mid-Z mode, in tas5086_init()
498 * configure 'part 1' of the PWM starts to use Mid-Z, and tell in tas5086_init()
499 * all configured mid-z channels to start start under 'part 1'. in tas5086_init()
501 if (priv->pwm_start_mid_z) in tas5086_init()
502 regmap_write(priv->regmap, TAS5086_PWM_START, in tas5086_init()
504 priv->pwm_start_mid_z); in tas5086_init()
506 /* lookup and set split-capacitor charge period */ in tas5086_init()
507 if (priv->charge_period == 0) { in tas5086_init()
508 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0); in tas5086_init()
512 priv->charge_period); in tas5086_init()
514 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, in tas5086_init()
518 "Invalid split-cap charge period of %d ns.\n", in tas5086_init()
519 priv->charge_period); in tas5086_init()
523 ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00); in tas5086_init()
528 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20); in tas5086_init()
533 ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE, in tas5086_init()
542 static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1);
547 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
550 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
553 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
554 TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5),
556 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0,
563 "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R",
564 "SDIN3-L", "SDIN3-R", "Ground (0)", "nc"
572 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts),
577 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
578 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
579 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
580 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
581 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
582 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
587 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
588 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
595 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts),
604 SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]),
609 SND_SOC_DAPM_INPUT("SDIN1-L"),
610 SND_SOC_DAPM_INPUT("SDIN1-R"),
611 SND_SOC_DAPM_INPUT("SDIN2-L"),
612 SND_SOC_DAPM_INPUT("SDIN2-R"),
613 SND_SOC_DAPM_INPUT("SDIN3-L"),
614 SND_SOC_DAPM_INPUT("SDIN3-R"),
615 SND_SOC_DAPM_INPUT("SDIN4-L"),
616 SND_SOC_DAPM_INPUT("SDIN4-R"),
625 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
627 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
629 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
631 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
633 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
634 &tas5086_dapm_input_mux_controls[4]),
635 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
647 &tas5086_dapm_output_mux_controls[4]),
653 /* SDIN inputs -> channel muxes */
654 { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" },
655 { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" },
656 { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" },
657 { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" },
658 { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" },
659 { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" },
661 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
662 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
663 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
664 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
665 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
666 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
668 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" },
669 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" },
670 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" },
671 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" },
672 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" },
673 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" },
675 { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" },
676 { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" },
677 { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" },
678 { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" },
679 { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" },
680 { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" },
682 { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" },
683 { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" },
684 { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" },
685 { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" },
686 { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" },
687 { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" },
689 { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" },
690 { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" },
691 { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" },
692 { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" },
693 { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" },
694 { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" },
696 { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" },
697 { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" },
698 { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" },
699 { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" },
700 { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" },
701 { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" },
703 /* Channel muxes -> PWM muxes */
704 { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" },
705 { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" },
706 { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" },
707 { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" },
708 { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" },
709 { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" },
711 { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" },
712 { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" },
713 { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" },
714 { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" },
715 { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" },
716 { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" },
718 { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" },
719 { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" },
720 { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" },
721 { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" },
722 { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" },
723 { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" },
725 { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" },
726 { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" },
727 { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" },
728 { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" },
729 { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" },
730 { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" },
732 { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" },
733 { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" },
734 { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" },
735 { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" },
736 { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" },
737 { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" },
739 { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" },
740 { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" },
741 { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" },
742 { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" },
743 { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" },
744 { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" },
764 .name = "tas5086-hifi",
782 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60); in tas5086_soc_suspend()
786 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_soc_suspend()
796 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_soc_resume()
801 regcache_mark_dirty(priv->regmap); in tas5086_soc_resume()
803 ret = tas5086_init(component->dev, priv); in tas5086_soc_resume()
807 ret = regcache_sync(priv->regmap); in tas5086_soc_resume()
831 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_probe()
833 dev_err(component->dev, "Failed to enable regulators: %d\n", ret); in tas5086_probe()
837 priv->pwm_start_mid_z = 0; in tas5086_probe()
838 priv->charge_period = 1300000; /* hardware default is 1300 ms */ in tas5086_probe()
840 if (of_match_device(of_match_ptr(tas5086_dt_ids), component->dev)) { in tas5086_probe()
841 struct device_node *of_node = component->dev->of_node; in tas5086_probe()
843 of_property_read_u32(of_node, "ti,charge-period", in tas5086_probe()
844 &priv->charge_period); in tas5086_probe()
850 "ti,mid-z-channel-%d", i + 1); in tas5086_probe()
853 priv->pwm_start_mid_z |= 1 << i; in tas5086_probe()
858 ret = tas5086_init(component->dev, priv); in tas5086_probe()
863 ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30); in tas5086_probe()
870 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_probe()
879 if (gpio_is_valid(priv->gpio_nreset)) in tas5086_remove()
881 gpio_set_value(priv->gpio_nreset, 0); in tas5086_remove()
883 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_remove()
927 struct device *dev = &i2c->dev; in tas5086_i2c_probe()
928 int gpio_nreset = -EINVAL; in tas5086_i2c_probe()
933 return -ENOMEM; in tas5086_i2c_probe()
936 priv->supplies[i].supply = supply_names[i]; in tas5086_i2c_probe()
938 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), in tas5086_i2c_probe()
939 priv->supplies); in tas5086_i2c_probe()
945 priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap); in tas5086_i2c_probe()
946 if (IS_ERR(priv->regmap)) { in tas5086_i2c_probe()
947 ret = PTR_ERR(priv->regmap); in tas5086_i2c_probe()
948 dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); in tas5086_i2c_probe()
955 struct device_node *of_node = dev->of_node; in tas5086_i2c_probe()
956 gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0); in tas5086_i2c_probe()
961 gpio_nreset = -EINVAL; in tas5086_i2c_probe()
963 priv->gpio_nreset = gpio_nreset; in tas5086_i2c_probe()
965 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_i2c_probe()
974 ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i); in tas5086_i2c_probe()
978 ret = -ENODEV; in tas5086_i2c_probe()
985 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); in tas5086_i2c_probe()
988 ret = devm_snd_soc_register_component(&i2c->dev, in tas5086_i2c_probe()