Lines Matching +full:1 +full:- +full:6

2  * wm2200.h - WM2200 audio codec interface
16 #define WM2200_CLK_SYSCLK 1
19 #define WM2200_CLKSRC_MCLK2  1
24 #define WM2200_FLL_SRC_MCLK2 1
533  * R0 (0x00) - software reset
535 #define WM2200_SW_RESET_CHIP_ID1_MASK           0xFFFF  /* SW_RESET_CHIP_ID1 - [15:0] */
536 #define WM2200_SW_RESET_CHIP_ID1_SHIFT               0  /* SW_RESET_CHIP_ID1 - [15:0] */
537 #define WM2200_SW_RESET_CHIP_ID1_WIDTH              16  /* SW_RESET_CHIP_ID1 - [15:0] */
540  * R1 (0x01) - Device Revision
542 #define WM2200_DEVICE_REVISION_MASK             0x000F  /* DEVICE_REVISION - [3:0] */
543 #define WM2200_DEVICE_REVISION_SHIFT                 0  /* DEVICE_REVISION - [3:0] */
544 #define WM2200_DEVICE_REVISION_WIDTH                 4  /* DEVICE_REVISION - [3:0] */
547  * R11 (0x0B) - Tone Generator 1
552 #define WM2200_TONE_ENA_WIDTH                        1  /* TONE_ENA */
555  * R258 (0x102) - Clocking 3
557 #define WM2200_SYSCLK_FREQ_MASK                 0x0700  /* SYSCLK_FREQ - [10:8] */
558 #define WM2200_SYSCLK_FREQ_SHIFT                     8  /* SYSCLK_FREQ - [10:8] */
559 #define WM2200_SYSCLK_FREQ_WIDTH                     3  /* SYSCLK_FREQ - [10:8] */
562 #define WM2200_SYSCLK_ENA_SHIFT                      6  /* SYSCLK_ENA */
563 #define WM2200_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
564 #define WM2200_SYSCLK_SRC_MASK                  0x000F  /* SYSCLK_SRC - [3:0] */
565 #define WM2200_SYSCLK_SRC_SHIFT                      0  /* SYSCLK_SRC - [3:0] */
566 #define WM2200_SYSCLK_SRC_WIDTH                      4  /* SYSCLK_SRC - [3:0] */
569  * R259 (0x103) - Clocking 4
571 #define WM2200_SAMPLE_RATE_1_MASK               0x001F  /* SAMPLE_RATE_1 - [4:0] */
572 #define WM2200_SAMPLE_RATE_1_SHIFT                   0  /* SAMPLE_RATE_1 - [4:0] */
573 #define WM2200_SAMPLE_RATE_1_WIDTH                   5  /* SAMPLE_RATE_1 - [4:0] */
576  * R273 (0x111) - FLL Control 1
581 #define WM2200_FLL_ENA_WIDTH                         1  /* FLL_ENA */
584  * R274 (0x112) - FLL Control 2
586 #define WM2200_FLL_OUTDIV_MASK                  0x3F00  /* FLL_OUTDIV - [13:8] */
587 #define WM2200_FLL_OUTDIV_SHIFT                      8  /* FLL_OUTDIV - [13:8] */
588 #define WM2200_FLL_OUTDIV_WIDTH                      6  /* FLL_OUTDIV - [13:8] */
589 #define WM2200_FLL_FRATIO_MASK                  0x0007  /* FLL_FRATIO - [2:0] */
590 #define WM2200_FLL_FRATIO_SHIFT                      0  /* FLL_FRATIO - [2:0] */
591 #define WM2200_FLL_FRATIO_WIDTH                      3  /* FLL_FRATIO - [2:0] */
594  * R275 (0x113) - FLL Control 3
599 #define WM2200_FLL_FRACN_ENA_WIDTH                   1  /* FLL_FRACN_ENA */
602  * R276 (0x114) - FLL Control 4
604 #define WM2200_FLL_THETA_MASK                   0xFFFF  /* FLL_THETA - [15:0] */
605 #define WM2200_FLL_THETA_SHIFT                       0  /* FLL_THETA - [15:0] */
606 #define WM2200_FLL_THETA_WIDTH                      16  /* FLL_THETA - [15:0] */
609  * R278 (0x116) - FLL Control 6
611 #define WM2200_FLL_N_MASK                       0x03FF  /* FLL_N - [9:0] */
612 #define WM2200_FLL_N_SHIFT                           0  /* FLL_N - [9:0] */
613 #define WM2200_FLL_N_WIDTH                          10  /* FLL_N - [9:0] */
616  * R279 (0x117) - FLL Control 7
618 #define WM2200_FLL_CLK_REF_DIV_MASK             0x0030  /* FLL_CLK_REF_DIV - [5:4] */
619 #define WM2200_FLL_CLK_REF_DIV_SHIFT                 4  /* FLL_CLK_REF_DIV - [5:4] */
620 #define WM2200_FLL_CLK_REF_DIV_WIDTH                 2  /* FLL_CLK_REF_DIV - [5:4] */
621 #define WM2200_FLL_CLK_REF_SRC_MASK             0x0003  /* FLL_CLK_REF_SRC - [1:0] */
622 #define WM2200_FLL_CLK_REF_SRC_SHIFT                 0  /* FLL_CLK_REF_SRC - [1:0] */
623 #define WM2200_FLL_CLK_REF_SRC_WIDTH                 2  /* FLL_CLK_REF_SRC - [1:0] */
626  * R281 (0x119) - FLL EFS 1
628 #define WM2200_FLL_LAMBDA_MASK                  0xFFFF  /* FLL_LAMBDA - [15:0] */
629 #define WM2200_FLL_LAMBDA_SHIFT                      0  /* FLL_LAMBDA - [15:0] */
630 #define WM2200_FLL_LAMBDA_WIDTH                     16  /* FLL_LAMBDA - [15:0] */
633  * R282 (0x11A) - FLL EFS 2
638 #define WM2200_FLL_EFS_ENA_WIDTH                     1  /* FLL_EFS_ENA */
641  * R512 (0x200) - Mic Charge Pump 1
646 #define WM2200_CPMIC_BYPASS_MODE_WIDTH               1  /* CPMIC_BYPASS_MODE */
650 #define WM2200_CPMIC_ENA_WIDTH                       1  /* CPMIC_ENA */
653  * R513 (0x201) - Mic Charge Pump 2
655 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK     0xF800  /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
656 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT        11  /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
657 #define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH         5  /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
660  * R514 (0x202) - DM Charge Pump 1
665 #define WM2200_CPDM_ENA_WIDTH                        1  /* CPDM_ENA */
668  * R524 (0x20C) - Mic Bias Ctrl 1
672 #define WM2200_MICB1_DISCH_SHIFT                     6  /* MICB1_DISCH */
673 #define WM2200_MICB1_DISCH_WIDTH                     1  /* MICB1_DISCH */
677 #define WM2200_MICB1_RATE_WIDTH                      1  /* MICB1_RATE */
678 #define WM2200_MICB1_LVL_MASK                   0x001C  /* MICB1_LVL - [4:2] */
679 #define WM2200_MICB1_LVL_SHIFT                       2  /* MICB1_LVL - [4:2] */
680 #define WM2200_MICB1_LVL_WIDTH                       3  /* MICB1_LVL - [4:2] */
683 #define WM2200_MICB1_MODE_SHIFT                      1  /* MICB1_MODE */
684 #define WM2200_MICB1_MODE_WIDTH                      1  /* MICB1_MODE */
688 #define WM2200_MICB1_ENA_WIDTH                       1  /* MICB1_ENA */
691  * R525 (0x20D) - Mic Bias Ctrl 2
695 #define WM2200_MICB2_DISCH_SHIFT                     6  /* MICB2_DISCH */
696 #define WM2200_MICB2_DISCH_WIDTH                     1  /* MICB2_DISCH */
700 #define WM2200_MICB2_RATE_WIDTH                      1  /* MICB2_RATE */
701 #define WM2200_MICB2_LVL_MASK                   0x001C  /* MICB2_LVL - [4:2] */
702 #define WM2200_MICB2_LVL_SHIFT                       2  /* MICB2_LVL - [4:2] */
703 #define WM2200_MICB2_LVL_WIDTH                       3  /* MICB2_LVL - [4:2] */
706 #define WM2200_MICB2_MODE_SHIFT                      1  /* MICB2_MODE */
707 #define WM2200_MICB2_MODE_WIDTH                      1  /* MICB2_MODE */
711 #define WM2200_MICB2_ENA_WIDTH                       1  /* MICB2_ENA */
714  * R527 (0x20F) - Ear Piece Ctrl 1
719 #define WM2200_EPD_LP_ENA_WIDTH                      1  /* EPD_LP_ENA */
723 #define WM2200_EPD_OUTP_LP_ENA_WIDTH                 1  /* EPD_OUTP_LP_ENA */
727 #define WM2200_EPD_RMV_SHRT_LP_WIDTH                 1  /* EPD_RMV_SHRT_LP */
731 #define WM2200_EPD_LN_ENA_WIDTH                      1  /* EPD_LN_ENA */
735 #define WM2200_EPD_OUTP_LN_ENA_WIDTH                 1  /* EPD_OUTP_LN_ENA */
739 #define WM2200_EPD_RMV_SHRT_LN_WIDTH                 1  /* EPD_RMV_SHRT_LN */
742  * R528 (0x210) - Ear Piece Ctrl 2
747 #define WM2200_EPD_RP_ENA_WIDTH                      1  /* EPD_RP_ENA */
751 #define WM2200_EPD_OUTP_RP_ENA_WIDTH                 1  /* EPD_OUTP_RP_ENA */
755 #define WM2200_EPD_RMV_SHRT_RP_WIDTH                 1  /* EPD_RMV_SHRT_RP */
759 #define WM2200_EPD_RN_ENA_WIDTH                      1  /* EPD_RN_ENA */
763 #define WM2200_EPD_OUTP_RN_ENA_WIDTH                 1  /* EPD_OUTP_RN_ENA */
767 #define WM2200_EPD_RMV_SHRT_RN_WIDTH                 1  /* EPD_RMV_SHRT_RN */
770  * R769 (0x301) - Input Enables
775 #define WM2200_IN3L_ENA_WIDTH                        1  /* IN3L_ENA */
779 #define WM2200_IN3R_ENA_WIDTH                        1  /* IN3R_ENA */
783 #define WM2200_IN2L_ENA_WIDTH                        1  /* IN2L_ENA */
787 #define WM2200_IN2R_ENA_WIDTH                        1  /* IN2R_ENA */
790 #define WM2200_IN1L_ENA_SHIFT                        1  /* IN1L_ENA */
791 #define WM2200_IN1L_ENA_WIDTH                        1  /* IN1L_ENA */
795 #define WM2200_IN1R_ENA_WIDTH                        1  /* IN1R_ENA */
798  * R770 (0x302) - IN1L Control
803 #define WM2200_IN1_OSR_WIDTH                         1  /* IN1_OSR */
804 #define WM2200_IN1_DMIC_SUP_MASK                0x1800  /* IN1_DMIC_SUP - [12:11] */
805 #define WM2200_IN1_DMIC_SUP_SHIFT                   11  /* IN1_DMIC_SUP - [12:11] */
806 #define WM2200_IN1_DMIC_SUP_WIDTH                    2  /* IN1_DMIC_SUP - [12:11] */
807 #define WM2200_IN1_MODE_MASK                    0x0600  /* IN1_MODE - [10:9] */
808 #define WM2200_IN1_MODE_SHIFT                        9  /* IN1_MODE - [10:9] */
809 #define WM2200_IN1_MODE_WIDTH                        2  /* IN1_MODE - [10:9] */
810 #define WM2200_IN1L_PGA_VOL_MASK                0x00FE  /* IN1L_PGA_VOL - [7:1] */
811 #define WM2200_IN1L_PGA_VOL_SHIFT                    1  /* IN1L_PGA_VOL - [7:1] */
812 #define WM2200_IN1L_PGA_VOL_WIDTH                    7  /* IN1L_PGA_VOL - [7:1] */
815  * R771 (0x303) - IN1R Control
817 #define WM2200_IN1R_PGA_VOL_MASK                0x00FE  /* IN1R_PGA_VOL - [7:1] */
818 #define WM2200_IN1R_PGA_VOL_SHIFT                    1  /* IN1R_PGA_VOL - [7:1] */
819 #define WM2200_IN1R_PGA_VOL_WIDTH                    7  /* IN1R_PGA_VOL - [7:1] */
822  * R772 (0x304) - IN2L Control
827 #define WM2200_IN2_OSR_WIDTH                         1  /* IN2_OSR */
828 #define WM2200_IN2_DMIC_SUP_MASK                0x1800  /* IN2_DMIC_SUP - [12:11] */
829 #define WM2200_IN2_DMIC_SUP_SHIFT                   11  /* IN2_DMIC_SUP - [12:11] */
830 #define WM2200_IN2_DMIC_SUP_WIDTH                    2  /* IN2_DMIC_SUP - [12:11] */
831 #define WM2200_IN2_MODE_MASK                    0x0600  /* IN2_MODE - [10:9] */
832 #define WM2200_IN2_MODE_SHIFT                        9  /* IN2_MODE - [10:9] */
833 #define WM2200_IN2_MODE_WIDTH                        2  /* IN2_MODE - [10:9] */
834 #define WM2200_IN2L_PGA_VOL_MASK                0x00FE  /* IN2L_PGA_VOL - [7:1] */
835 #define WM2200_IN2L_PGA_VOL_SHIFT                    1  /* IN2L_PGA_VOL - [7:1] */
836 #define WM2200_IN2L_PGA_VOL_WIDTH                    7  /* IN2L_PGA_VOL - [7:1] */
839  * R773 (0x305) - IN2R Control
841 #define WM2200_IN2R_PGA_VOL_MASK                0x00FE  /* IN2R_PGA_VOL - [7:1] */
842 #define WM2200_IN2R_PGA_VOL_SHIFT                    1  /* IN2R_PGA_VOL - [7:1] */
843 #define WM2200_IN2R_PGA_VOL_WIDTH                    7  /* IN2R_PGA_VOL - [7:1] */
846  * R774 (0x306) - IN3L Control
851 #define WM2200_IN3_OSR_WIDTH                         1  /* IN3_OSR */
852 #define WM2200_IN3_DMIC_SUP_MASK                0x1800  /* IN3_DMIC_SUP - [12:11] */
853 #define WM2200_IN3_DMIC_SUP_SHIFT                   11  /* IN3_DMIC_SUP - [12:11] */
854 #define WM2200_IN3_DMIC_SUP_WIDTH                    2  /* IN3_DMIC_SUP - [12:11] */
855 #define WM2200_IN3_MODE_MASK                    0x0600  /* IN3_MODE - [10:9] */
856 #define WM2200_IN3_MODE_SHIFT                        9  /* IN3_MODE - [10:9] */
857 #define WM2200_IN3_MODE_WIDTH                        2  /* IN3_MODE - [10:9] */
858 #define WM2200_IN3L_PGA_VOL_MASK                0x00FE  /* IN3L_PGA_VOL - [7:1] */
859 #define WM2200_IN3L_PGA_VOL_SHIFT                    1  /* IN3L_PGA_VOL - [7:1] */
860 #define WM2200_IN3L_PGA_VOL_WIDTH                    7  /* IN3L_PGA_VOL - [7:1] */
863  * R775 (0x307) - IN3R Control
865 #define WM2200_IN3R_PGA_VOL_MASK                0x00FE  /* IN3R_PGA_VOL - [7:1] */
866 #define WM2200_IN3R_PGA_VOL_SHIFT                    1  /* IN3R_PGA_VOL - [7:1] */
867 #define WM2200_IN3R_PGA_VOL_WIDTH                    7  /* IN3R_PGA_VOL - [7:1] */
870  * R778 (0x30A) - RXANC_SRC
872 #define WM2200_IN_RXANC_SEL_MASK                0x0007  /* IN_RXANC_SEL - [2:0] */
873 #define WM2200_IN_RXANC_SEL_SHIFT                    0  /* IN_RXANC_SEL - [2:0] */
874 #define WM2200_IN_RXANC_SEL_WIDTH                    3  /* IN_RXANC_SEL - [2:0] */
877  * R779 (0x30B) - Input Volume Ramp
879 #define WM2200_IN_VD_RAMP_MASK                  0x0070  /* IN_VD_RAMP - [6:4] */
880 #define WM2200_IN_VD_RAMP_SHIFT                      4  /* IN_VD_RAMP - [6:4] */
881 #define WM2200_IN_VD_RAMP_WIDTH                      3  /* IN_VD_RAMP - [6:4] */
882 #define WM2200_IN_VI_RAMP_MASK                  0x0007  /* IN_VI_RAMP - [2:0] */
883 #define WM2200_IN_VI_RAMP_SHIFT                      0  /* IN_VI_RAMP - [2:0] */
884 #define WM2200_IN_VI_RAMP_WIDTH                      3  /* IN_VI_RAMP - [2:0] */
887  * R780 (0x30C) - ADC Digital Volume 1L
892 #define WM2200_IN_VU_WIDTH                           1  /* IN_VU */
896 #define WM2200_IN1L_MUTE_WIDTH                       1  /* IN1L_MUTE */
897 #define WM2200_IN1L_DIG_VOL_MASK                0x00FF  /* IN1L_DIG_VOL - [7:0] */
898 #define WM2200_IN1L_DIG_VOL_SHIFT                    0  /* IN1L_DIG_VOL - [7:0] */
899 #define WM2200_IN1L_DIG_VOL_WIDTH                    8  /* IN1L_DIG_VOL - [7:0] */
902  * R781 (0x30D) - ADC Digital Volume 1R
907 #define WM2200_IN_VU_WIDTH                           1  /* IN_VU */
911 #define WM2200_IN1R_MUTE_WIDTH                       1  /* IN1R_MUTE */
912 #define WM2200_IN1R_DIG_VOL_MASK                0x00FF  /* IN1R_DIG_VOL - [7:0] */
913 #define WM2200_IN1R_DIG_VOL_SHIFT                    0  /* IN1R_DIG_VOL - [7:0] */
914 #define WM2200_IN1R_DIG_VOL_WIDTH                    8  /* IN1R_DIG_VOL - [7:0] */
917  * R782 (0x30E) - ADC Digital Volume 2L
922 #define WM2200_IN_VU_WIDTH                           1  /* IN_VU */
926 #define WM2200_IN2L_MUTE_WIDTH                       1  /* IN2L_MUTE */
927 #define WM2200_IN2L_DIG_VOL_MASK                0x00FF  /* IN2L_DIG_VOL - [7:0] */
928 #define WM2200_IN2L_DIG_VOL_SHIFT                    0  /* IN2L_DIG_VOL - [7:0] */
929 #define WM2200_IN2L_DIG_VOL_WIDTH                    8  /* IN2L_DIG_VOL - [7:0] */
932  * R783 (0x30F) - ADC Digital Volume 2R
937 #define WM2200_IN_VU_WIDTH                           1  /* IN_VU */
941 #define WM2200_IN2R_MUTE_WIDTH                       1  /* IN2R_MUTE */
942 #define WM2200_IN2R_DIG_VOL_MASK                0x00FF  /* IN2R_DIG_VOL - [7:0] */
943 #define WM2200_IN2R_DIG_VOL_SHIFT                    0  /* IN2R_DIG_VOL - [7:0] */
944 #define WM2200_IN2R_DIG_VOL_WIDTH                    8  /* IN2R_DIG_VOL - [7:0] */
947  * R784 (0x310) - ADC Digital Volume 3L
952 #define WM2200_IN_VU_WIDTH                           1  /* IN_VU */
956 #define WM2200_IN3L_MUTE_WIDTH                       1  /* IN3L_MUTE */
957 #define WM2200_IN3L_DIG_VOL_MASK                0x00FF  /* IN3L_DIG_VOL - [7:0] */
958 #define WM2200_IN3L_DIG_VOL_SHIFT                    0  /* IN3L_DIG_VOL - [7:0] */
959 #define WM2200_IN3L_DIG_VOL_WIDTH                    8  /* IN3L_DIG_VOL - [7:0] */
962  * R785 (0x311) - ADC Digital Volume 3R
967 #define WM2200_IN_VU_WIDTH                           1  /* IN_VU */
971 #define WM2200_IN3R_MUTE_WIDTH                       1  /* IN3R_MUTE */
972 #define WM2200_IN3R_DIG_VOL_MASK                0x00FF  /* IN3R_DIG_VOL - [7:0] */
973 #define WM2200_IN3R_DIG_VOL_SHIFT                    0  /* IN3R_DIG_VOL - [7:0] */
974 #define WM2200_IN3R_DIG_VOL_WIDTH                    8  /* IN3R_DIG_VOL - [7:0] */
977  * R1024 (0x400) - Output Enables
982 #define WM2200_OUT2L_ENA_WIDTH                       1  /* OUT2L_ENA */
986 #define WM2200_OUT2R_ENA_WIDTH                       1  /* OUT2R_ENA */
989 #define WM2200_OUT1L_ENA_SHIFT                       1  /* OUT1L_ENA */
990 #define WM2200_OUT1L_ENA_WIDTH                       1  /* OUT1L_ENA */
994 #define WM2200_OUT1R_ENA_WIDTH                       1  /* OUT1R_ENA */
997  * R1025 (0x401) - DAC Volume Limit 1L
1002 #define WM2200_OUT1_OSR_WIDTH                        1  /* OUT1_OSR */
1006 #define WM2200_OUT1L_ANC_SRC_WIDTH                   1  /* OUT1L_ANC_SRC */
1007 #define WM2200_OUT1L_PGA_VOL_MASK               0x00FE  /* OUT1L_PGA_VOL - [7:1] */
1008 #define WM2200_OUT1L_PGA_VOL_SHIFT                   1  /* OUT1L_PGA_VOL - [7:1] */
1009 #define WM2200_OUT1L_PGA_VOL_WIDTH                   7  /* OUT1L_PGA_VOL - [7:1] */
1012  * R1026 (0x402) - DAC Volume Limit 1R
1017 #define WM2200_OUT1R_ANC_SRC_WIDTH                   1  /* OUT1R_ANC_SRC */
1018 #define WM2200_OUT1R_PGA_VOL_MASK               0x00FE  /* OUT1R_PGA_VOL - [7:1] */
1019 #define WM2200_OUT1R_PGA_VOL_SHIFT                   1  /* OUT1R_PGA_VOL - [7:1] */
1020 #define WM2200_OUT1R_PGA_VOL_WIDTH                   7  /* OUT1R_PGA_VOL - [7:1] */
1023  * R1027 (0x403) - DAC Volume Limit 2L
1028 #define WM2200_OUT2_OSR_WIDTH                        1  /* OUT2_OSR */
1032 #define WM2200_OUT2L_ANC_SRC_WIDTH                   1  /* OUT2L_ANC_SRC */
1035  * R1028 (0x404) - DAC Volume Limit 2R
1040 #define WM2200_OUT2R_ANC_SRC_WIDTH                   1  /* OUT2R_ANC_SRC */
1043  * R1033 (0x409) - DAC AEC Control 1
1048 #define WM2200_AEC_LOOPBACK_ENA_WIDTH                1  /* AEC_LOOPBACK_ENA */
1049 #define WM2200_AEC_LOOPBACK_SRC_MASK            0x0003  /* AEC_LOOPBACK_SRC - [1:0] */
1050 #define WM2200_AEC_LOOPBACK_SRC_SHIFT                0  /* AEC_LOOPBACK_SRC - [1:0] */
1051 #define WM2200_AEC_LOOPBACK_SRC_WIDTH                2  /* AEC_LOOPBACK_SRC - [1:0] */
1054  * R1034 (0x40A) - Output Volume Ramp
1056 #define WM2200_OUT_VD_RAMP_MASK                 0x0070  /* OUT_VD_RAMP - [6:4] */
1057 #define WM2200_OUT_VD_RAMP_SHIFT                     4  /* OUT_VD_RAMP - [6:4] */
1058 #define WM2200_OUT_VD_RAMP_WIDTH                     3  /* OUT_VD_RAMP - [6:4] */
1059 #define WM2200_OUT_VI_RAMP_MASK                 0x0007  /* OUT_VI_RAMP - [2:0] */
1060 #define WM2200_OUT_VI_RAMP_SHIFT                     0  /* OUT_VI_RAMP - [2:0] */
1061 #define WM2200_OUT_VI_RAMP_WIDTH                     3  /* OUT_VI_RAMP - [2:0] */
1064  * R1035 (0x40B) - DAC Digital Volume 1L
1069 #define WM2200_OUT_VU_WIDTH                          1  /* OUT_VU */
1073 #define WM2200_OUT1L_MUTE_WIDTH                      1  /* OUT1L_MUTE */
1074 #define WM2200_OUT1L_VOL_MASK                   0x00FF  /* OUT1L_VOL - [7:0] */
1075 #define WM2200_OUT1L_VOL_SHIFT                       0  /* OUT1L_VOL - [7:0] */
1076 #define WM2200_OUT1L_VOL_WIDTH                       8  /* OUT1L_VOL - [7:0] */
1079  * R1036 (0x40C) - DAC Digital Volume 1R
1084 #define WM2200_OUT_VU_WIDTH                          1  /* OUT_VU */
1088 #define WM2200_OUT1R_MUTE_WIDTH                      1  /* OUT1R_MUTE */
1089 #define WM2200_OUT1R_VOL_MASK                   0x00FF  /* OUT1R_VOL - [7:0] */
1090 #define WM2200_OUT1R_VOL_SHIFT                       0  /* OUT1R_VOL - [7:0] */
1091 #define WM2200_OUT1R_VOL_WIDTH                       8  /* OUT1R_VOL - [7:0] */
1094  * R1037 (0x40D) - DAC Digital Volume 2L
1099 #define WM2200_OUT_VU_WIDTH                          1  /* OUT_VU */
1103 #define WM2200_OUT2L_MUTE_WIDTH                      1  /* OUT2L_MUTE */
1104 #define WM2200_OUT2L_VOL_MASK                   0x00FF  /* OUT2L_VOL - [7:0] */
1105 #define WM2200_OUT2L_VOL_SHIFT                       0  /* OUT2L_VOL - [7:0] */
1106 #define WM2200_OUT2L_VOL_WIDTH                       8  /* OUT2L_VOL - [7:0] */
1109  * R1038 (0x40E) - DAC Digital Volume 2R
1114 #define WM2200_OUT_VU_WIDTH                          1  /* OUT_VU */
1118 #define WM2200_OUT2R_MUTE_WIDTH                      1  /* OUT2R_MUTE */
1119 #define WM2200_OUT2R_VOL_MASK                   0x00FF  /* OUT2R_VOL - [7:0] */
1120 #define WM2200_OUT2R_VOL_SHIFT                       0  /* OUT2R_VOL - [7:0] */
1121 #define WM2200_OUT2R_VOL_WIDTH                       8  /* OUT2R_VOL - [7:0] */
1124  * R1047 (0x417) - PDM 1
1129 #define WM2200_SPK1R_MUTE_WIDTH                      1  /* SPK1R_MUTE */
1133 #define WM2200_SPK1L_MUTE_WIDTH                      1  /* SPK1L_MUTE */
1137 #define WM2200_SPK1_MUTE_ENDIAN_WIDTH                1  /* SPK1_MUTE_ENDIAN */
1138 #define WM2200_SPK1_MUTE_SEQL_MASK              0x00FF  /* SPK1_MUTE_SEQL - [7:0] */
1139 #define WM2200_SPK1_MUTE_SEQL_SHIFT                  0  /* SPK1_MUTE_SEQL - [7:0] */
1140 #define WM2200_SPK1_MUTE_SEQL_WIDTH                  8  /* SPK1_MUTE_SEQL - [7:0] */
1143  * R1048 (0x418) - PDM 2
1148 #define WM2200_SPK1_FMT_WIDTH                        1  /* SPK1_FMT */
1151  * R1280 (0x500) - Audio IF 1_1
1155 #define WM2200_AIF1_BCLK_INV_SHIFT                   6  /* AIF1_BCLK_INV */
1156 #define WM2200_AIF1_BCLK_INV_WIDTH                   1  /* AIF1_BCLK_INV */
1160 #define WM2200_AIF1_BCLK_FRC_WIDTH                   1  /* AIF1_BCLK_FRC */
1164 #define WM2200_AIF1_BCLK_MSTR_WIDTH                  1  /* AIF1_BCLK_MSTR */
1165 #define WM2200_AIF1_BCLK_DIV_MASK               0x000F  /* AIF1_BCLK_DIV - [3:0] */
1166 #define WM2200_AIF1_BCLK_DIV_SHIFT                   0  /* AIF1_BCLK_DIV - [3:0] */
1167 #define WM2200_AIF1_BCLK_DIV_WIDTH                   4  /* AIF1_BCLK_DIV - [3:0] */
1170  * R1281 (0x501) - Audio IF 1_2
1175 #define WM2200_AIF1TX_DAT_TRI_WIDTH                  1  /* AIF1TX_DAT_TRI */
1179 #define WM2200_AIF1TX_LRCLK_SRC_WIDTH                1  /* AIF1TX_LRCLK_SRC */
1183 #define WM2200_AIF1TX_LRCLK_INV_WIDTH                1  /* AIF1TX_LRCLK_INV */
1186 #define WM2200_AIF1TX_LRCLK_FRC_SHIFT                1  /* AIF1TX_LRCLK_FRC */
1187 #define WM2200_AIF1TX_LRCLK_FRC_WIDTH                1  /* AIF1TX_LRCLK_FRC */
1191 #define WM2200_AIF1TX_LRCLK_MSTR_WIDTH               1  /* AIF1TX_LRCLK_MSTR */
1194  * R1282 (0x502) - Audio IF 1_3
1199 #define WM2200_AIF1RX_LRCLK_INV_WIDTH                1  /* AIF1RX_LRCLK_INV */
1202 #define WM2200_AIF1RX_LRCLK_FRC_SHIFT                1  /* AIF1RX_LRCLK_FRC */
1203 #define WM2200_AIF1RX_LRCLK_FRC_WIDTH                1  /* AIF1RX_LRCLK_FRC */
1207 #define WM2200_AIF1RX_LRCLK_MSTR_WIDTH               1  /* AIF1RX_LRCLK_MSTR */
1210  * R1283 (0x503) - Audio IF 1_4
1214 #define WM2200_AIF1_TRI_SHIFT                        6  /* AIF1_TRI */
1215 #define WM2200_AIF1_TRI_WIDTH                        1  /* AIF1_TRI */
1218  * R1284 (0x504) - Audio IF 1_5
1220 #define WM2200_AIF1_FMT_MASK                    0x0007  /* AIF1_FMT - [2:0] */
1221 #define WM2200_AIF1_FMT_SHIFT                        0  /* AIF1_FMT - [2:0] */
1222 #define WM2200_AIF1_FMT_WIDTH                        3  /* AIF1_FMT - [2:0] */
1225  * R1285 (0x505) - Audio IF 1_6
1227 #define WM2200_AIF1TX_BCPF_MASK                 0x07FF  /* AIF1TX_BCPF - [10:0] */
1228 #define WM2200_AIF1TX_BCPF_SHIFT                     0  /* AIF1TX_BCPF - [10:0] */
1229 #define WM2200_AIF1TX_BCPF_WIDTH                    11  /* AIF1TX_BCPF - [10:0] */
1232  * R1286 (0x506) - Audio IF 1_7
1234 #define WM2200_AIF1RX_BCPF_MASK                 0x07FF  /* AIF1RX_BCPF - [10:0] */
1235 #define WM2200_AIF1RX_BCPF_SHIFT                     0  /* AIF1RX_BCPF - [10:0] */
1236 #define WM2200_AIF1RX_BCPF_WIDTH                    11  /* AIF1RX_BCPF - [10:0] */
1239  * R1287 (0x507) - Audio IF 1_8
1241 #define WM2200_AIF1TX_WL_MASK                   0x3F00  /* AIF1TX_WL - [13:8] */
1242 #define WM2200_AIF1TX_WL_SHIFT                       8  /* AIF1TX_WL - [13:8] */
1243 #define WM2200_AIF1TX_WL_WIDTH                       6  /* AIF1TX_WL - [13:8] */
1244 #define WM2200_AIF1TX_SLOT_LEN_MASK             0x00FF  /* AIF1TX_SLOT_LEN - [7:0] */
1245 #define WM2200_AIF1TX_SLOT_LEN_SHIFT                 0  /* AIF1TX_SLOT_LEN - [7:0] */
1246 #define WM2200_AIF1TX_SLOT_LEN_WIDTH                 8  /* AIF1TX_SLOT_LEN - [7:0] */
1249  * R1288 (0x508) - Audio IF 1_9
1251 #define WM2200_AIF1RX_WL_MASK                   0x3F00  /* AIF1RX_WL - [13:8] */
1252 #define WM2200_AIF1RX_WL_SHIFT                       8  /* AIF1RX_WL - [13:8] */
1253 #define WM2200_AIF1RX_WL_WIDTH                       6  /* AIF1RX_WL - [13:8] */
1254 #define WM2200_AIF1RX_SLOT_LEN_MASK             0x00FF  /* AIF1RX_SLOT_LEN - [7:0] */
1255 #define WM2200_AIF1RX_SLOT_LEN_SHIFT                 0  /* AIF1RX_SLOT_LEN - [7:0] */
1256 #define WM2200_AIF1RX_SLOT_LEN_WIDTH                 8  /* AIF1RX_SLOT_LEN - [7:0] */
1259  * R1289 (0x509) - Audio IF 1_10
1261 #define WM2200_AIF1TX1_SLOT_MASK                0x003F  /* AIF1TX1_SLOT - [5:0] */
1262 #define WM2200_AIF1TX1_SLOT_SHIFT                    0  /* AIF1TX1_SLOT - [5:0] */
1263 #define WM2200_AIF1TX1_SLOT_WIDTH                    6  /* AIF1TX1_SLOT - [5:0] */
1266  * R1290 (0x50A) - Audio IF 1_11
1268 #define WM2200_AIF1TX2_SLOT_MASK                0x003F  /* AIF1TX2_SLOT - [5:0] */
1269 #define WM2200_AIF1TX2_SLOT_SHIFT                    0  /* AIF1TX2_SLOT - [5:0] */
1270 #define WM2200_AIF1TX2_SLOT_WIDTH                    6  /* AIF1TX2_SLOT - [5:0] */
1273  * R1291 (0x50B) - Audio IF 1_12
1275 #define WM2200_AIF1TX3_SLOT_MASK                0x003F  /* AIF1TX3_SLOT - [5:0] */
1276 #define WM2200_AIF1TX3_SLOT_SHIFT                    0  /* AIF1TX3_SLOT - [5:0] */
1277 #define WM2200_AIF1TX3_SLOT_WIDTH                    6  /* AIF1TX3_SLOT - [5:0] */
1280  * R1292 (0x50C) - Audio IF 1_13
1282 #define WM2200_AIF1TX4_SLOT_MASK                0x003F  /* AIF1TX4_SLOT - [5:0] */
1283 #define WM2200_AIF1TX4_SLOT_SHIFT                    0  /* AIF1TX4_SLOT - [5:0] */
1284 #define WM2200_AIF1TX4_SLOT_WIDTH                    6  /* AIF1TX4_SLOT - [5:0] */
1287  * R1293 (0x50D) - Audio IF 1_14
1289 #define WM2200_AIF1TX5_SLOT_MASK                0x003F  /* AIF1TX5_SLOT - [5:0] */
1290 #define WM2200_AIF1TX5_SLOT_SHIFT                    0  /* AIF1TX5_SLOT - [5:0] */
1291 #define WM2200_AIF1TX5_SLOT_WIDTH                    6  /* AIF1TX5_SLOT - [5:0] */
1294  * R1294 (0x50E) - Audio IF 1_15
1296 #define WM2200_AIF1TX6_SLOT_MASK                0x003F  /* AIF1TX6_SLOT - [5:0] */
1297 #define WM2200_AIF1TX6_SLOT_SHIFT                    0  /* AIF1TX6_SLOT - [5:0] */
1298 #define WM2200_AIF1TX6_SLOT_WIDTH                    6  /* AIF1TX6_SLOT - [5:0] */
1301  * R1295 (0x50F) - Audio IF 1_16
1303 #define WM2200_AIF1RX1_SLOT_MASK                0x003F  /* AIF1RX1_SLOT - [5:0] */
1304 #define WM2200_AIF1RX1_SLOT_SHIFT                    0  /* AIF1RX1_SLOT - [5:0] */
1305 #define WM2200_AIF1RX1_SLOT_WIDTH                    6  /* AIF1RX1_SLOT - [5:0] */
1308  * R1296 (0x510) - Audio IF 1_17
1310 #define WM2200_AIF1RX2_SLOT_MASK                0x003F  /* AIF1RX2_SLOT - [5:0] */
1311 #define WM2200_AIF1RX2_SLOT_SHIFT                    0  /* AIF1RX2_SLOT - [5:0] */
1312 #define WM2200_AIF1RX2_SLOT_WIDTH                    6  /* AIF1RX2_SLOT - [5:0] */
1315  * R1297 (0x511) - Audio IF 1_18
1317 #define WM2200_AIF1RX3_SLOT_MASK                0x003F  /* AIF1RX3_SLOT - [5:0] */
1318 #define WM2200_AIF1RX3_SLOT_SHIFT                    0  /* AIF1RX3_SLOT - [5:0] */
1319 #define WM2200_AIF1RX3_SLOT_WIDTH                    6  /* AIF1RX3_SLOT - [5:0] */
1322  * R1298 (0x512) - Audio IF 1_19
1324 #define WM2200_AIF1RX4_SLOT_MASK                0x003F  /* AIF1RX4_SLOT - [5:0] */
1325 #define WM2200_AIF1RX4_SLOT_SHIFT                    0  /* AIF1RX4_SLOT - [5:0] */
1326 #define WM2200_AIF1RX4_SLOT_WIDTH                    6  /* AIF1RX4_SLOT - [5:0] */
1329  * R1299 (0x513) - Audio IF 1_20
1331 #define WM2200_AIF1RX5_SLOT_MASK                0x003F  /* AIF1RX5_SLOT - [5:0] */
1332 #define WM2200_AIF1RX5_SLOT_SHIFT                    0  /* AIF1RX5_SLOT - [5:0] */
1333 #define WM2200_AIF1RX5_SLOT_WIDTH                    6  /* AIF1RX5_SLOT - [5:0] */
1336  * R1300 (0x514) - Audio IF 1_21
1338 #define WM2200_AIF1RX6_SLOT_MASK                0x003F  /* AIF1RX6_SLOT - [5:0] */
1339 #define WM2200_AIF1RX6_SLOT_SHIFT                    0  /* AIF1RX6_SLOT - [5:0] */
1340 #define WM2200_AIF1RX6_SLOT_WIDTH                    6  /* AIF1RX6_SLOT - [5:0] */
1343  * R1301 (0x515) - Audio IF 1_22
1348 #define WM2200_AIF1RX6_ENA_WIDTH                     1  /* AIF1RX6_ENA */
1352 #define WM2200_AIF1RX5_ENA_WIDTH                     1  /* AIF1RX5_ENA */
1356 #define WM2200_AIF1RX4_ENA_WIDTH                     1  /* AIF1RX4_ENA */
1360 #define WM2200_AIF1RX3_ENA_WIDTH                     1  /* AIF1RX3_ENA */
1364 #define WM2200_AIF1RX2_ENA_WIDTH                     1  /* AIF1RX2_ENA */
1367 #define WM2200_AIF1RX1_ENA_SHIFT                     6  /* AIF1RX1_ENA */
1368 #define WM2200_AIF1RX1_ENA_WIDTH                     1  /* AIF1RX1_ENA */
1372 #define WM2200_AIF1TX6_ENA_WIDTH                     1  /* AIF1TX6_ENA */
1376 #define WM2200_AIF1TX5_ENA_WIDTH                     1  /* AIF1TX5_ENA */
1380 #define WM2200_AIF1TX4_ENA_WIDTH                     1  /* AIF1TX4_ENA */
1384 #define WM2200_AIF1TX3_ENA_WIDTH                     1  /* AIF1TX3_ENA */
1387 #define WM2200_AIF1TX2_ENA_SHIFT                     1  /* AIF1TX2_ENA */
1388 #define WM2200_AIF1TX2_ENA_WIDTH                     1  /* AIF1TX2_ENA */
1392 #define WM2200_AIF1TX1_ENA_WIDTH                     1  /* AIF1TX1_ENA */
1395  * R1536 (0x600) - OUT1LMIX Input 1 Source
1397 #define WM2200_OUT1LMIX_SRC1_MASK               0x007F  /* OUT1LMIX_SRC1 - [6:0] */
1398 #define WM2200_OUT1LMIX_SRC1_SHIFT                   0  /* OUT1LMIX_SRC1 - [6:0] */
1399 #define WM2200_OUT1LMIX_SRC1_WIDTH                   7  /* OUT1LMIX_SRC1 - [6:0] */
1402  * R1537 (0x601) - OUT1LMIX Input 1 Volume
1404 #define WM2200_OUT1LMIX_VOL1_MASK               0x00FE  /* OUT1LMIX_VOL1 - [7:1] */
1405 #define WM2200_OUT1LMIX_VOL1_SHIFT                   1  /* OUT1LMIX_VOL1 - [7:1] */
1406 #define WM2200_OUT1LMIX_VOL1_WIDTH                   7  /* OUT1LMIX_VOL1 - [7:1] */
1409  * R1538 (0x602) - OUT1LMIX Input 2 Source
1411 #define WM2200_OUT1LMIX_SRC2_MASK               0x007F  /* OUT1LMIX_SRC2 - [6:0] */
1412 #define WM2200_OUT1LMIX_SRC2_SHIFT                   0  /* OUT1LMIX_SRC2 - [6:0] */
1413 #define WM2200_OUT1LMIX_SRC2_WIDTH                   7  /* OUT1LMIX_SRC2 - [6:0] */
1416  * R1539 (0x603) - OUT1LMIX Input 2 Volume
1418 #define WM2200_OUT1LMIX_VOL2_MASK               0x00FE  /* OUT1LMIX_VOL2 - [7:1] */
1419 #define WM2200_OUT1LMIX_VOL2_SHIFT                   1  /* OUT1LMIX_VOL2 - [7:1] */
1420 #define WM2200_OUT1LMIX_VOL2_WIDTH                   7  /* OUT1LMIX_VOL2 - [7:1] */
1423  * R1540 (0x604) - OUT1LMIX Input 3 Source
1425 #define WM2200_OUT1LMIX_SRC3_MASK               0x007F  /* OUT1LMIX_SRC3 - [6:0] */
1426 #define WM2200_OUT1LMIX_SRC3_SHIFT                   0  /* OUT1LMIX_SRC3 - [6:0] */
1427 #define WM2200_OUT1LMIX_SRC3_WIDTH                   7  /* OUT1LMIX_SRC3 - [6:0] */
1430  * R1541 (0x605) - OUT1LMIX Input 3 Volume
1432 #define WM2200_OUT1LMIX_VOL3_MASK               0x00FE  /* OUT1LMIX_VOL3 - [7:1] */
1433 #define WM2200_OUT1LMIX_VOL3_SHIFT                   1  /* OUT1LMIX_VOL3 - [7:1] */
1434 #define WM2200_OUT1LMIX_VOL3_WIDTH                   7  /* OUT1LMIX_VOL3 - [7:1] */
1437  * R1542 (0x606) - OUT1LMIX Input 4 Source
1439 #define WM2200_OUT1LMIX_SRC4_MASK               0x007F  /* OUT1LMIX_SRC4 - [6:0] */
1440 #define WM2200_OUT1LMIX_SRC4_SHIFT                   0  /* OUT1LMIX_SRC4 - [6:0] */
1441 #define WM2200_OUT1LMIX_SRC4_WIDTH                   7  /* OUT1LMIX_SRC4 - [6:0] */
1444  * R1543 (0x607) - OUT1LMIX Input 4 Volume
1446 #define WM2200_OUT1LMIX_VOL4_MASK               0x00FE  /* OUT1LMIX_VOL4 - [7:1] */
1447 #define WM2200_OUT1LMIX_VOL4_SHIFT                   1  /* OUT1LMIX_VOL4 - [7:1] */
1448 #define WM2200_OUT1LMIX_VOL4_WIDTH                   7  /* OUT1LMIX_VOL4 - [7:1] */
1451  * R1544 (0x608) - OUT1RMIX Input 1 Source
1453 #define WM2200_OUT1RMIX_SRC1_MASK               0x007F  /* OUT1RMIX_SRC1 - [6:0] */
1454 #define WM2200_OUT1RMIX_SRC1_SHIFT                   0  /* OUT1RMIX_SRC1 - [6:0] */
1455 #define WM2200_OUT1RMIX_SRC1_WIDTH                   7  /* OUT1RMIX_SRC1 - [6:0] */
1458  * R1545 (0x609) - OUT1RMIX Input 1 Volume
1460 #define WM2200_OUT1RMIX_VOL1_MASK               0x00FE  /* OUT1RMIX_VOL1 - [7:1] */
1461 #define WM2200_OUT1RMIX_VOL1_SHIFT                   1  /* OUT1RMIX_VOL1 - [7:1] */
1462 #define WM2200_OUT1RMIX_VOL1_WIDTH                   7  /* OUT1RMIX_VOL1 - [7:1] */
1465  * R1546 (0x60A) - OUT1RMIX Input 2 Source
1467 #define WM2200_OUT1RMIX_SRC2_MASK               0x007F  /* OUT1RMIX_SRC2 - [6:0] */
1468 #define WM2200_OUT1RMIX_SRC2_SHIFT                   0  /* OUT1RMIX_SRC2 - [6:0] */
1469 #define WM2200_OUT1RMIX_SRC2_WIDTH                   7  /* OUT1RMIX_SRC2 - [6:0] */
1472  * R1547 (0x60B) - OUT1RMIX Input 2 Volume
1474 #define WM2200_OUT1RMIX_VOL2_MASK               0x00FE  /* OUT1RMIX_VOL2 - [7:1] */
1475 #define WM2200_OUT1RMIX_VOL2_SHIFT                   1  /* OUT1RMIX_VOL2 - [7:1] */
1476 #define WM2200_OUT1RMIX_VOL2_WIDTH                   7  /* OUT1RMIX_VOL2 - [7:1] */
1479  * R1548 (0x60C) - OUT1RMIX Input 3 Source
1481 #define WM2200_OUT1RMIX_SRC3_MASK               0x007F  /* OUT1RMIX_SRC3 - [6:0] */
1482 #define WM2200_OUT1RMIX_SRC3_SHIFT                   0  /* OUT1RMIX_SRC3 - [6:0] */
1483 #define WM2200_OUT1RMIX_SRC3_WIDTH                   7  /* OUT1RMIX_SRC3 - [6:0] */
1486  * R1549 (0x60D) - OUT1RMIX Input 3 Volume
1488 #define WM2200_OUT1RMIX_VOL3_MASK               0x00FE  /* OUT1RMIX_VOL3 - [7:1] */
1489 #define WM2200_OUT1RMIX_VOL3_SHIFT                   1  /* OUT1RMIX_VOL3 - [7:1] */
1490 #define WM2200_OUT1RMIX_VOL3_WIDTH                   7  /* OUT1RMIX_VOL3 - [7:1] */
1493  * R1550 (0x60E) - OUT1RMIX Input 4 Source
1495 #define WM2200_OUT1RMIX_SRC4_MASK               0x007F  /* OUT1RMIX_SRC4 - [6:0] */
1496 #define WM2200_OUT1RMIX_SRC4_SHIFT                   0  /* OUT1RMIX_SRC4 - [6:0] */
1497 #define WM2200_OUT1RMIX_SRC4_WIDTH                   7  /* OUT1RMIX_SRC4 - [6:0] */
1500  * R1551 (0x60F) - OUT1RMIX Input 4 Volume
1502 #define WM2200_OUT1RMIX_VOL4_MASK               0x00FE  /* OUT1RMIX_VOL4 - [7:1] */
1503 #define WM2200_OUT1RMIX_VOL4_SHIFT                   1  /* OUT1RMIX_VOL4 - [7:1] */
1504 #define WM2200_OUT1RMIX_VOL4_WIDTH                   7  /* OUT1RMIX_VOL4 - [7:1] */
1507  * R1552 (0x610) - OUT2LMIX Input 1 Source
1509 #define WM2200_OUT2LMIX_SRC1_MASK               0x007F  /* OUT2LMIX_SRC1 - [6:0] */
1510 #define WM2200_OUT2LMIX_SRC1_SHIFT                   0  /* OUT2LMIX_SRC1 - [6:0] */
1511 #define WM2200_OUT2LMIX_SRC1_WIDTH                   7  /* OUT2LMIX_SRC1 - [6:0] */
1514  * R1553 (0x611) - OUT2LMIX Input 1 Volume
1516 #define WM2200_OUT2LMIX_VOL1_MASK               0x00FE  /* OUT2LMIX_VOL1 - [7:1] */
1517 #define WM2200_OUT2LMIX_VOL1_SHIFT                   1  /* OUT2LMIX_VOL1 - [7:1] */
1518 #define WM2200_OUT2LMIX_VOL1_WIDTH                   7  /* OUT2LMIX_VOL1 - [7:1] */
1521  * R1554 (0x612) - OUT2LMIX Input 2 Source
1523 #define WM2200_OUT2LMIX_SRC2_MASK               0x007F  /* OUT2LMIX_SRC2 - [6:0] */
1524 #define WM2200_OUT2LMIX_SRC2_SHIFT                   0  /* OUT2LMIX_SRC2 - [6:0] */
1525 #define WM2200_OUT2LMIX_SRC2_WIDTH                   7  /* OUT2LMIX_SRC2 - [6:0] */
1528  * R1555 (0x613) - OUT2LMIX Input 2 Volume
1530 #define WM2200_OUT2LMIX_VOL2_MASK               0x00FE  /* OUT2LMIX_VOL2 - [7:1] */
1531 #define WM2200_OUT2LMIX_VOL2_SHIFT                   1  /* OUT2LMIX_VOL2 - [7:1] */
1532 #define WM2200_OUT2LMIX_VOL2_WIDTH                   7  /* OUT2LMIX_VOL2 - [7:1] */
1535  * R1556 (0x614) - OUT2LMIX Input 3 Source
1537 #define WM2200_OUT2LMIX_SRC3_MASK               0x007F  /* OUT2LMIX_SRC3 - [6:0] */
1538 #define WM2200_OUT2LMIX_SRC3_SHIFT                   0  /* OUT2LMIX_SRC3 - [6:0] */
1539 #define WM2200_OUT2LMIX_SRC3_WIDTH                   7  /* OUT2LMIX_SRC3 - [6:0] */
1542  * R1557 (0x615) - OUT2LMIX Input 3 Volume
1544 #define WM2200_OUT2LMIX_VOL3_MASK               0x00FE  /* OUT2LMIX_VOL3 - [7:1] */
1545 #define WM2200_OUT2LMIX_VOL3_SHIFT                   1  /* OUT2LMIX_VOL3 - [7:1] */
1546 #define WM2200_OUT2LMIX_VOL3_WIDTH                   7  /* OUT2LMIX_VOL3 - [7:1] */
1549  * R1558 (0x616) - OUT2LMIX Input 4 Source
1551 #define WM2200_OUT2LMIX_SRC4_MASK               0x007F  /* OUT2LMIX_SRC4 - [6:0] */
1552 #define WM2200_OUT2LMIX_SRC4_SHIFT                   0  /* OUT2LMIX_SRC4 - [6:0] */
1553 #define WM2200_OUT2LMIX_SRC4_WIDTH                   7  /* OUT2LMIX_SRC4 - [6:0] */
1556  * R1559 (0x617) - OUT2LMIX Input 4 Volume
1558 #define WM2200_OUT2LMIX_VOL4_MASK               0x00FE  /* OUT2LMIX_VOL4 - [7:1] */
1559 #define WM2200_OUT2LMIX_VOL4_SHIFT                   1  /* OUT2LMIX_VOL4 - [7:1] */
1560 #define WM2200_OUT2LMIX_VOL4_WIDTH                   7  /* OUT2LMIX_VOL4 - [7:1] */
1563  * R1560 (0x618) - OUT2RMIX Input 1 Source
1565 #define WM2200_OUT2RMIX_SRC1_MASK               0x007F  /* OUT2RMIX_SRC1 - [6:0] */
1566 #define WM2200_OUT2RMIX_SRC1_SHIFT                   0  /* OUT2RMIX_SRC1 - [6:0] */
1567 #define WM2200_OUT2RMIX_SRC1_WIDTH                   7  /* OUT2RMIX_SRC1 - [6:0] */
1570  * R1561 (0x619) - OUT2RMIX Input 1 Volume
1572 #define WM2200_OUT2RMIX_VOL1_MASK               0x00FE  /* OUT2RMIX_VOL1 - [7:1] */
1573 #define WM2200_OUT2RMIX_VOL1_SHIFT                   1  /* OUT2RMIX_VOL1 - [7:1] */
1574 #define WM2200_OUT2RMIX_VOL1_WIDTH                   7  /* OUT2RMIX_VOL1 - [7:1] */
1577  * R1562 (0x61A) - OUT2RMIX Input 2 Source
1579 #define WM2200_OUT2RMIX_SRC2_MASK               0x007F  /* OUT2RMIX_SRC2 - [6:0] */
1580 #define WM2200_OUT2RMIX_SRC2_SHIFT                   0  /* OUT2RMIX_SRC2 - [6:0] */
1581 #define WM2200_OUT2RMIX_SRC2_WIDTH                   7  /* OUT2RMIX_SRC2 - [6:0] */
1584  * R1563 (0x61B) - OUT2RMIX Input 2 Volume
1586 #define WM2200_OUT2RMIX_VOL2_MASK               0x00FE  /* OUT2RMIX_VOL2 - [7:1] */
1587 #define WM2200_OUT2RMIX_VOL2_SHIFT                   1  /* OUT2RMIX_VOL2 - [7:1] */
1588 #define WM2200_OUT2RMIX_VOL2_WIDTH                   7  /* OUT2RMIX_VOL2 - [7:1] */
1591  * R1564 (0x61C) - OUT2RMIX Input 3 Source
1593 #define WM2200_OUT2RMIX_SRC3_MASK               0x007F  /* OUT2RMIX_SRC3 - [6:0] */
1594 #define WM2200_OUT2RMIX_SRC3_SHIFT                   0  /* OUT2RMIX_SRC3 - [6:0] */
1595 #define WM2200_OUT2RMIX_SRC3_WIDTH                   7  /* OUT2RMIX_SRC3 - [6:0] */
1598  * R1565 (0x61D) - OUT2RMIX Input 3 Volume
1600 #define WM2200_OUT2RMIX_VOL3_MASK               0x00FE  /* OUT2RMIX_VOL3 - [7:1] */
1601 #define WM2200_OUT2RMIX_VOL3_SHIFT                   1  /* OUT2RMIX_VOL3 - [7:1] */
1602 #define WM2200_OUT2RMIX_VOL3_WIDTH                   7  /* OUT2RMIX_VOL3 - [7:1] */
1605  * R1566 (0x61E) - OUT2RMIX Input 4 Source
1607 #define WM2200_OUT2RMIX_SRC4_MASK               0x007F  /* OUT2RMIX_SRC4 - [6:0] */
1608 #define WM2200_OUT2RMIX_SRC4_SHIFT                   0  /* OUT2RMIX_SRC4 - [6:0] */
1609 #define WM2200_OUT2RMIX_SRC4_WIDTH                   7  /* OUT2RMIX_SRC4 - [6:0] */
1612  * R1567 (0x61F) - OUT2RMIX Input 4 Volume
1614 #define WM2200_OUT2RMIX_VOL4_MASK               0x00FE  /* OUT2RMIX_VOL4 - [7:1] */
1615 #define WM2200_OUT2RMIX_VOL4_SHIFT                   1  /* OUT2RMIX_VOL4 - [7:1] */
1616 #define WM2200_OUT2RMIX_VOL4_WIDTH                   7  /* OUT2RMIX_VOL4 - [7:1] */
1619  * R1568 (0x620) - AIF1TX1MIX Input 1 Source
1621 #define WM2200_AIF1TX1MIX_SRC1_MASK             0x007F  /* AIF1TX1MIX_SRC1 - [6:0] */
1622 #define WM2200_AIF1TX1MIX_SRC1_SHIFT                 0  /* AIF1TX1MIX_SRC1 - [6:0] */
1623 #define WM2200_AIF1TX1MIX_SRC1_WIDTH                 7  /* AIF1TX1MIX_SRC1 - [6:0] */
1626  * R1569 (0x621) - AIF1TX1MIX Input 1 Volume
1628 #define WM2200_AIF1TX1MIX_VOL1_MASK             0x00FE  /* AIF1TX1MIX_VOL1 - [7:1] */
1629 #define WM2200_AIF1TX1MIX_VOL1_SHIFT                 1  /* AIF1TX1MIX_VOL1 - [7:1] */
1630 #define WM2200_AIF1TX1MIX_VOL1_WIDTH                 7  /* AIF1TX1MIX_VOL1 - [7:1] */
1633  * R1570 (0x622) - AIF1TX1MIX Input 2 Source
1635 #define WM2200_AIF1TX1MIX_SRC2_MASK             0x007F  /* AIF1TX1MIX_SRC2 - [6:0] */
1636 #define WM2200_AIF1TX1MIX_SRC2_SHIFT                 0  /* AIF1TX1MIX_SRC2 - [6:0] */
1637 #define WM2200_AIF1TX1MIX_SRC2_WIDTH                 7  /* AIF1TX1MIX_SRC2 - [6:0] */
1640  * R1571 (0x623) - AIF1TX1MIX Input 2 Volume
1642 #define WM2200_AIF1TX1MIX_VOL2_MASK             0x00FE  /* AIF1TX1MIX_VOL2 - [7:1] */
1643 #define WM2200_AIF1TX1MIX_VOL2_SHIFT                 1  /* AIF1TX1MIX_VOL2 - [7:1] */
1644 #define WM2200_AIF1TX1MIX_VOL2_WIDTH                 7  /* AIF1TX1MIX_VOL2 - [7:1] */
1647  * R1572 (0x624) - AIF1TX1MIX Input 3 Source
1649 #define WM2200_AIF1TX1MIX_SRC3_MASK             0x007F  /* AIF1TX1MIX_SRC3 - [6:0] */
1650 #define WM2200_AIF1TX1MIX_SRC3_SHIFT                 0  /* AIF1TX1MIX_SRC3 - [6:0] */
1651 #define WM2200_AIF1TX1MIX_SRC3_WIDTH                 7  /* AIF1TX1MIX_SRC3 - [6:0] */
1654  * R1573 (0x625) - AIF1TX1MIX Input 3 Volume
1656 #define WM2200_AIF1TX1MIX_VOL3_MASK             0x00FE  /* AIF1TX1MIX_VOL3 - [7:1] */
1657 #define WM2200_AIF1TX1MIX_VOL3_SHIFT                 1  /* AIF1TX1MIX_VOL3 - [7:1] */
1658 #define WM2200_AIF1TX1MIX_VOL3_WIDTH                 7  /* AIF1TX1MIX_VOL3 - [7:1] */
1661  * R1574 (0x626) - AIF1TX1MIX Input 4 Source
1663 #define WM2200_AIF1TX1MIX_SRC4_MASK             0x007F  /* AIF1TX1MIX_SRC4 - [6:0] */
1664 #define WM2200_AIF1TX1MIX_SRC4_SHIFT                 0  /* AIF1TX1MIX_SRC4 - [6:0] */
1665 #define WM2200_AIF1TX1MIX_SRC4_WIDTH                 7  /* AIF1TX1MIX_SRC4 - [6:0] */
1668  * R1575 (0x627) - AIF1TX1MIX Input 4 Volume
1670 #define WM2200_AIF1TX1MIX_VOL4_MASK             0x00FE  /* AIF1TX1MIX_VOL4 - [7:1] */
1671 #define WM2200_AIF1TX1MIX_VOL4_SHIFT                 1  /* AIF1TX1MIX_VOL4 - [7:1] */
1672 #define WM2200_AIF1TX1MIX_VOL4_WIDTH                 7  /* AIF1TX1MIX_VOL4 - [7:1] */
1675  * R1576 (0x628) - AIF1TX2MIX Input 1 Source
1677 #define WM2200_AIF1TX2MIX_SRC1_MASK             0x007F  /* AIF1TX2MIX_SRC1 - [6:0] */
1678 #define WM2200_AIF1TX2MIX_SRC1_SHIFT                 0  /* AIF1TX2MIX_SRC1 - [6:0] */
1679 #define WM2200_AIF1TX2MIX_SRC1_WIDTH                 7  /* AIF1TX2MIX_SRC1 - [6:0] */
1682  * R1577 (0x629) - AIF1TX2MIX Input 1 Volume
1684 #define WM2200_AIF1TX2MIX_VOL1_MASK             0x00FE  /* AIF1TX2MIX_VOL1 - [7:1] */
1685 #define WM2200_AIF1TX2MIX_VOL1_SHIFT                 1  /* AIF1TX2MIX_VOL1 - [7:1] */
1686 #define WM2200_AIF1TX2MIX_VOL1_WIDTH                 7  /* AIF1TX2MIX_VOL1 - [7:1] */
1689  * R1578 (0x62A) - AIF1TX2MIX Input 2 Source
1691 #define WM2200_AIF1TX2MIX_SRC2_MASK             0x007F  /* AIF1TX2MIX_SRC2 - [6:0] */
1692 #define WM2200_AIF1TX2MIX_SRC2_SHIFT                 0  /* AIF1TX2MIX_SRC2 - [6:0] */
1693 #define WM2200_AIF1TX2MIX_SRC2_WIDTH                 7  /* AIF1TX2MIX_SRC2 - [6:0] */
1696  * R1579 (0x62B) - AIF1TX2MIX Input 2 Volume
1698 #define WM2200_AIF1TX2MIX_VOL2_MASK             0x00FE  /* AIF1TX2MIX_VOL2 - [7:1] */
1699 #define WM2200_AIF1TX2MIX_VOL2_SHIFT                 1  /* AIF1TX2MIX_VOL2 - [7:1] */
1700 #define WM2200_AIF1TX2MIX_VOL2_WIDTH                 7  /* AIF1TX2MIX_VOL2 - [7:1] */
1703  * R1580 (0x62C) - AIF1TX2MIX Input 3 Source
1705 #define WM2200_AIF1TX2MIX_SRC3_MASK             0x007F  /* AIF1TX2MIX_SRC3 - [6:0] */
1706 #define WM2200_AIF1TX2MIX_SRC3_SHIFT                 0  /* AIF1TX2MIX_SRC3 - [6:0] */
1707 #define WM2200_AIF1TX2MIX_SRC3_WIDTH                 7  /* AIF1TX2MIX_SRC3 - [6:0] */
1710  * R1581 (0x62D) - AIF1TX2MIX Input 3 Volume
1712 #define WM2200_AIF1TX2MIX_VOL3_MASK             0x00FE  /* AIF1TX2MIX_VOL3 - [7:1] */
1713 #define WM2200_AIF1TX2MIX_VOL3_SHIFT                 1  /* AIF1TX2MIX_VOL3 - [7:1] */
1714 #define WM2200_AIF1TX2MIX_VOL3_WIDTH                 7  /* AIF1TX2MIX_VOL3 - [7:1] */
1717  * R1582 (0x62E) - AIF1TX2MIX Input 4 Source
1719 #define WM2200_AIF1TX2MIX_SRC4_MASK             0x007F  /* AIF1TX2MIX_SRC4 - [6:0] */
1720 #define WM2200_AIF1TX2MIX_SRC4_SHIFT                 0  /* AIF1TX2MIX_SRC4 - [6:0] */
1721 #define WM2200_AIF1TX2MIX_SRC4_WIDTH                 7  /* AIF1TX2MIX_SRC4 - [6:0] */
1724  * R1583 (0x62F) - AIF1TX2MIX Input 4 Volume
1726 #define WM2200_AIF1TX2MIX_VOL4_MASK             0x00FE  /* AIF1TX2MIX_VOL4 - [7:1] */
1727 #define WM2200_AIF1TX2MIX_VOL4_SHIFT                 1  /* AIF1TX2MIX_VOL4 - [7:1] */
1728 #define WM2200_AIF1TX2MIX_VOL4_WIDTH                 7  /* AIF1TX2MIX_VOL4 - [7:1] */
1731  * R1584 (0x630) - AIF1TX3MIX Input 1 Source
1733 #define WM2200_AIF1TX3MIX_SRC1_MASK             0x007F  /* AIF1TX3MIX_SRC1 - [6:0] */
1734 #define WM2200_AIF1TX3MIX_SRC1_SHIFT                 0  /* AIF1TX3MIX_SRC1 - [6:0] */
1735 #define WM2200_AIF1TX3MIX_SRC1_WIDTH                 7  /* AIF1TX3MIX_SRC1 - [6:0] */
1738  * R1585 (0x631) - AIF1TX3MIX Input 1 Volume
1740 #define WM2200_AIF1TX3MIX_VOL1_MASK             0x00FE  /* AIF1TX3MIX_VOL1 - [7:1] */
1741 #define WM2200_AIF1TX3MIX_VOL1_SHIFT                 1  /* AIF1TX3MIX_VOL1 - [7:1] */
1742 #define WM2200_AIF1TX3MIX_VOL1_WIDTH                 7  /* AIF1TX3MIX_VOL1 - [7:1] */
1745  * R1586 (0x632) - AIF1TX3MIX Input 2 Source
1747 #define WM2200_AIF1TX3MIX_SRC2_MASK             0x007F  /* AIF1TX3MIX_SRC2 - [6:0] */
1748 #define WM2200_AIF1TX3MIX_SRC2_SHIFT                 0  /* AIF1TX3MIX_SRC2 - [6:0] */
1749 #define WM2200_AIF1TX3MIX_SRC2_WIDTH                 7  /* AIF1TX3MIX_SRC2 - [6:0] */
1752  * R1587 (0x633) - AIF1TX3MIX Input 2 Volume
1754 #define WM2200_AIF1TX3MIX_VOL2_MASK             0x00FE  /* AIF1TX3MIX_VOL2 - [7:1] */
1755 #define WM2200_AIF1TX3MIX_VOL2_SHIFT                 1  /* AIF1TX3MIX_VOL2 - [7:1] */
1756 #define WM2200_AIF1TX3MIX_VOL2_WIDTH                 7  /* AIF1TX3MIX_VOL2 - [7:1] */
1759  * R1588 (0x634) - AIF1TX3MIX Input 3 Source
1761 #define WM2200_AIF1TX3MIX_SRC3_MASK             0x007F  /* AIF1TX3MIX_SRC3 - [6:0] */
1762 #define WM2200_AIF1TX3MIX_SRC3_SHIFT                 0  /* AIF1TX3MIX_SRC3 - [6:0] */
1763 #define WM2200_AIF1TX3MIX_SRC3_WIDTH                 7  /* AIF1TX3MIX_SRC3 - [6:0] */
1766  * R1589 (0x635) - AIF1TX3MIX Input 3 Volume
1768 #define WM2200_AIF1TX3MIX_VOL3_MASK             0x00FE  /* AIF1TX3MIX_VOL3 - [7:1] */
1769 #define WM2200_AIF1TX3MIX_VOL3_SHIFT                 1  /* AIF1TX3MIX_VOL3 - [7:1] */
1770 #define WM2200_AIF1TX3MIX_VOL3_WIDTH                 7  /* AIF1TX3MIX_VOL3 - [7:1] */
1773  * R1590 (0x636) - AIF1TX3MIX Input 4 Source
1775 #define WM2200_AIF1TX3MIX_SRC4_MASK             0x007F  /* AIF1TX3MIX_SRC4 - [6:0] */
1776 #define WM2200_AIF1TX3MIX_SRC4_SHIFT                 0  /* AIF1TX3MIX_SRC4 - [6:0] */
1777 #define WM2200_AIF1TX3MIX_SRC4_WIDTH                 7  /* AIF1TX3MIX_SRC4 - [6:0] */
1780  * R1591 (0x637) - AIF1TX3MIX Input 4 Volume
1782 #define WM2200_AIF1TX3MIX_VOL4_MASK             0x00FE  /* AIF1TX3MIX_VOL4 - [7:1] */
1783 #define WM2200_AIF1TX3MIX_VOL4_SHIFT                 1  /* AIF1TX3MIX_VOL4 - [7:1] */
1784 #define WM2200_AIF1TX3MIX_VOL4_WIDTH                 7  /* AIF1TX3MIX_VOL4 - [7:1] */
1787  * R1592 (0x638) - AIF1TX4MIX Input 1 Source
1789 #define WM2200_AIF1TX4MIX_SRC1_MASK             0x007F  /* AIF1TX4MIX_SRC1 - [6:0] */
1790 #define WM2200_AIF1TX4MIX_SRC1_SHIFT                 0  /* AIF1TX4MIX_SRC1 - [6:0] */
1791 #define WM2200_AIF1TX4MIX_SRC1_WIDTH                 7  /* AIF1TX4MIX_SRC1 - [6:0] */
1794  * R1593 (0x639) - AIF1TX4MIX Input 1 Volume
1796 #define WM2200_AIF1TX4MIX_VOL1_MASK             0x00FE  /* AIF1TX4MIX_VOL1 - [7:1] */
1797 #define WM2200_AIF1TX4MIX_VOL1_SHIFT                 1  /* AIF1TX4MIX_VOL1 - [7:1] */
1798 #define WM2200_AIF1TX4MIX_VOL1_WIDTH                 7  /* AIF1TX4MIX_VOL1 - [7:1] */
1801  * R1594 (0x63A) - AIF1TX4MIX Input 2 Source
1803 #define WM2200_AIF1TX4MIX_SRC2_MASK             0x007F  /* AIF1TX4MIX_SRC2 - [6:0] */
1804 #define WM2200_AIF1TX4MIX_SRC2_SHIFT                 0  /* AIF1TX4MIX_SRC2 - [6:0] */
1805 #define WM2200_AIF1TX4MIX_SRC2_WIDTH                 7  /* AIF1TX4MIX_SRC2 - [6:0] */
1808  * R1595 (0x63B) - AIF1TX4MIX Input 2 Volume
1810 #define WM2200_AIF1TX4MIX_VOL2_MASK             0x00FE  /* AIF1TX4MIX_VOL2 - [7:1] */
1811 #define WM2200_AIF1TX4MIX_VOL2_SHIFT                 1  /* AIF1TX4MIX_VOL2 - [7:1] */
1812 #define WM2200_AIF1TX4MIX_VOL2_WIDTH                 7  /* AIF1TX4MIX_VOL2 - [7:1] */
1815  * R1596 (0x63C) - AIF1TX4MIX Input 3 Source
1817 #define WM2200_AIF1TX4MIX_SRC3_MASK             0x007F  /* AIF1TX4MIX_SRC3 - [6:0] */
1818 #define WM2200_AIF1TX4MIX_SRC3_SHIFT                 0  /* AIF1TX4MIX_SRC3 - [6:0] */
1819 #define WM2200_AIF1TX4MIX_SRC3_WIDTH                 7  /* AIF1TX4MIX_SRC3 - [6:0] */
1822  * R1597 (0x63D) - AIF1TX4MIX Input 3 Volume
1824 #define WM2200_AIF1TX4MIX_VOL3_MASK             0x00FE  /* AIF1TX4MIX_VOL3 - [7:1] */
1825 #define WM2200_AIF1TX4MIX_VOL3_SHIFT                 1  /* AIF1TX4MIX_VOL3 - [7:1] */
1826 #define WM2200_AIF1TX4MIX_VOL3_WIDTH                 7  /* AIF1TX4MIX_VOL3 - [7:1] */
1829  * R1598 (0x63E) - AIF1TX4MIX Input 4 Source
1831 #define WM2200_AIF1TX4MIX_SRC4_MASK             0x007F  /* AIF1TX4MIX_SRC4 - [6:0] */
1832 #define WM2200_AIF1TX4MIX_SRC4_SHIFT                 0  /* AIF1TX4MIX_SRC4 - [6:0] */
1833 #define WM2200_AIF1TX4MIX_SRC4_WIDTH                 7  /* AIF1TX4MIX_SRC4 - [6:0] */
1836  * R1599 (0x63F) - AIF1TX4MIX Input 4 Volume
1838 #define WM2200_AIF1TX4MIX_VOL4_MASK             0x00FE  /* AIF1TX4MIX_VOL4 - [7:1] */
1839 #define WM2200_AIF1TX4MIX_VOL4_SHIFT                 1  /* AIF1TX4MIX_VOL4 - [7:1] */
1840 #define WM2200_AIF1TX4MIX_VOL4_WIDTH                 7  /* AIF1TX4MIX_VOL4 - [7:1] */
1843  * R1600 (0x640) - AIF1TX5MIX Input 1 Source
1845 #define WM2200_AIF1TX5MIX_SRC1_MASK             0x007F  /* AIF1TX5MIX_SRC1 - [6:0] */
1846 #define WM2200_AIF1TX5MIX_SRC1_SHIFT                 0  /* AIF1TX5MIX_SRC1 - [6:0] */
1847 #define WM2200_AIF1TX5MIX_SRC1_WIDTH                 7  /* AIF1TX5MIX_SRC1 - [6:0] */
1850  * R1601 (0x641) - AIF1TX5MIX Input 1 Volume
1852 #define WM2200_AIF1TX5MIX_VOL1_MASK             0x00FE  /* AIF1TX5MIX_VOL1 - [7:1] */
1853 #define WM2200_AIF1TX5MIX_VOL1_SHIFT                 1  /* AIF1TX5MIX_VOL1 - [7:1] */
1854 #define WM2200_AIF1TX5MIX_VOL1_WIDTH                 7  /* AIF1TX5MIX_VOL1 - [7:1] */
1857  * R1602 (0x642) - AIF1TX5MIX Input 2 Source
1859 #define WM2200_AIF1TX5MIX_SRC2_MASK             0x007F  /* AIF1TX5MIX_SRC2 - [6:0] */
1860 #define WM2200_AIF1TX5MIX_SRC2_SHIFT                 0  /* AIF1TX5MIX_SRC2 - [6:0] */
1861 #define WM2200_AIF1TX5MIX_SRC2_WIDTH                 7  /* AIF1TX5MIX_SRC2 - [6:0] */
1864  * R1603 (0x643) - AIF1TX5MIX Input 2 Volume
1866 #define WM2200_AIF1TX5MIX_VOL2_MASK             0x00FE  /* AIF1TX5MIX_VOL2 - [7:1] */
1867 #define WM2200_AIF1TX5MIX_VOL2_SHIFT                 1  /* AIF1TX5MIX_VOL2 - [7:1] */
1868 #define WM2200_AIF1TX5MIX_VOL2_WIDTH                 7  /* AIF1TX5MIX_VOL2 - [7:1] */
1871  * R1604 (0x644) - AIF1TX5MIX Input 3 Source
1873 #define WM2200_AIF1TX5MIX_SRC3_MASK             0x007F  /* AIF1TX5MIX_SRC3 - [6:0] */
1874 #define WM2200_AIF1TX5MIX_SRC3_SHIFT                 0  /* AIF1TX5MIX_SRC3 - [6:0] */
1875 #define WM2200_AIF1TX5MIX_SRC3_WIDTH                 7  /* AIF1TX5MIX_SRC3 - [6:0] */
1878  * R1605 (0x645) - AIF1TX5MIX Input 3 Volume
1880 #define WM2200_AIF1TX5MIX_VOL3_MASK             0x00FE  /* AIF1TX5MIX_VOL3 - [7:1] */
1881 #define WM2200_AIF1TX5MIX_VOL3_SHIFT                 1  /* AIF1TX5MIX_VOL3 - [7:1] */
1882 #define WM2200_AIF1TX5MIX_VOL3_WIDTH                 7  /* AIF1TX5MIX_VOL3 - [7:1] */
1885  * R1606 (0x646) - AIF1TX5MIX Input 4 Source
1887 #define WM2200_AIF1TX5MIX_SRC4_MASK             0x007F  /* AIF1TX5MIX_SRC4 - [6:0] */
1888 #define WM2200_AIF1TX5MIX_SRC4_SHIFT                 0  /* AIF1TX5MIX_SRC4 - [6:0] */
1889 #define WM2200_AIF1TX5MIX_SRC4_WIDTH                 7  /* AIF1TX5MIX_SRC4 - [6:0] */
1892  * R1607 (0x647) - AIF1TX5MIX Input 4 Volume
1894 #define WM2200_AIF1TX5MIX_VOL4_MASK             0x00FE  /* AIF1TX5MIX_VOL4 - [7:1] */
1895 #define WM2200_AIF1TX5MIX_VOL4_SHIFT                 1  /* AIF1TX5MIX_VOL4 - [7:1] */
1896 #define WM2200_AIF1TX5MIX_VOL4_WIDTH                 7  /* AIF1TX5MIX_VOL4 - [7:1] */
1899  * R1608 (0x648) - AIF1TX6MIX Input 1 Source
1901 #define WM2200_AIF1TX6MIX_SRC1_MASK             0x007F  /* AIF1TX6MIX_SRC1 - [6:0] */
1902 #define WM2200_AIF1TX6MIX_SRC1_SHIFT                 0  /* AIF1TX6MIX_SRC1 - [6:0] */
1903 #define WM2200_AIF1TX6MIX_SRC1_WIDTH                 7  /* AIF1TX6MIX_SRC1 - [6:0] */
1906  * R1609 (0x649) - AIF1TX6MIX Input 1 Volume
1908 #define WM2200_AIF1TX6MIX_VOL1_MASK             0x00FE  /* AIF1TX6MIX_VOL1 - [7:1] */
1909 #define WM2200_AIF1TX6MIX_VOL1_SHIFT                 1  /* AIF1TX6MIX_VOL1 - [7:1] */
1910 #define WM2200_AIF1TX6MIX_VOL1_WIDTH                 7  /* AIF1TX6MIX_VOL1 - [7:1] */
1913  * R1610 (0x64A) - AIF1TX6MIX Input 2 Source
1915 #define WM2200_AIF1TX6MIX_SRC2_MASK             0x007F  /* AIF1TX6MIX_SRC2 - [6:0] */
1916 #define WM2200_AIF1TX6MIX_SRC2_SHIFT                 0  /* AIF1TX6MIX_SRC2 - [6:0] */
1917 #define WM2200_AIF1TX6MIX_SRC2_WIDTH                 7  /* AIF1TX6MIX_SRC2 - [6:0] */
1920  * R1611 (0x64B) - AIF1TX6MIX Input 2 Volume
1922 #define WM2200_AIF1TX6MIX_VOL2_MASK             0x00FE  /* AIF1TX6MIX_VOL2 - [7:1] */
1923 #define WM2200_AIF1TX6MIX_VOL2_SHIFT                 1  /* AIF1TX6MIX_VOL2 - [7:1] */
1924 #define WM2200_AIF1TX6MIX_VOL2_WIDTH                 7  /* AIF1TX6MIX_VOL2 - [7:1] */
1927  * R1612 (0x64C) - AIF1TX6MIX Input 3 Source
1929 #define WM2200_AIF1TX6MIX_SRC3_MASK             0x007F  /* AIF1TX6MIX_SRC3 - [6:0] */
1930 #define WM2200_AIF1TX6MIX_SRC3_SHIFT                 0  /* AIF1TX6MIX_SRC3 - [6:0] */
1931 #define WM2200_AIF1TX6MIX_SRC3_WIDTH                 7  /* AIF1TX6MIX_SRC3 - [6:0] */
1934  * R1613 (0x64D) - AIF1TX6MIX Input 3 Volume
1936 #define WM2200_AIF1TX6MIX_VOL3_MASK             0x00FE  /* AIF1TX6MIX_VOL3 - [7:1] */
1937 #define WM2200_AIF1TX6MIX_VOL3_SHIFT                 1  /* AIF1TX6MIX_VOL3 - [7:1] */
1938 #define WM2200_AIF1TX6MIX_VOL3_WIDTH                 7  /* AIF1TX6MIX_VOL3 - [7:1] */
1941  * R1614 (0x64E) - AIF1TX6MIX Input 4 Source
1943 #define WM2200_AIF1TX6MIX_SRC4_MASK             0x007F  /* AIF1TX6MIX_SRC4 - [6:0] */
1944 #define WM2200_AIF1TX6MIX_SRC4_SHIFT                 0  /* AIF1TX6MIX_SRC4 - [6:0] */
1945 #define WM2200_AIF1TX6MIX_SRC4_WIDTH                 7  /* AIF1TX6MIX_SRC4 - [6:0] */
1948  * R1615 (0x64F) - AIF1TX6MIX Input 4 Volume
1950 #define WM2200_AIF1TX6MIX_VOL4_MASK             0x00FE  /* AIF1TX6MIX_VOL4 - [7:1] */
1951 #define WM2200_AIF1TX6MIX_VOL4_SHIFT                 1  /* AIF1TX6MIX_VOL4 - [7:1] */
1952 #define WM2200_AIF1TX6MIX_VOL4_WIDTH                 7  /* AIF1TX6MIX_VOL4 - [7:1] */
1955  * R1616 (0x650) - EQLMIX Input 1 Source
1957 #define WM2200_EQLMIX_SRC1_MASK                 0x007F  /* EQLMIX_SRC1 - [6:0] */
1958 #define WM2200_EQLMIX_SRC1_SHIFT                     0  /* EQLMIX_SRC1 - [6:0] */
1959 #define WM2200_EQLMIX_SRC1_WIDTH                     7  /* EQLMIX_SRC1 - [6:0] */
1962  * R1617 (0x651) - EQLMIX Input 1 Volume
1964 #define WM2200_EQLMIX_VOL1_MASK                 0x00FE  /* EQLMIX_VOL1 - [7:1] */
1965 #define WM2200_EQLMIX_VOL1_SHIFT                     1  /* EQLMIX_VOL1 - [7:1] */
1966 #define WM2200_EQLMIX_VOL1_WIDTH                     7  /* EQLMIX_VOL1 - [7:1] */
1969  * R1618 (0x652) - EQLMIX Input 2 Source
1971 #define WM2200_EQLMIX_SRC2_MASK                 0x007F  /* EQLMIX_SRC2 - [6:0] */
1972 #define WM2200_EQLMIX_SRC2_SHIFT                     0  /* EQLMIX_SRC2 - [6:0] */
1973 #define WM2200_EQLMIX_SRC2_WIDTH                     7  /* EQLMIX_SRC2 - [6:0] */
1976  * R1619 (0x653) - EQLMIX Input 2 Volume
1978 #define WM2200_EQLMIX_VOL2_MASK                 0x00FE  /* EQLMIX_VOL2 - [7:1] */
1979 #define WM2200_EQLMIX_VOL2_SHIFT                     1  /* EQLMIX_VOL2 - [7:1] */
1980 #define WM2200_EQLMIX_VOL2_WIDTH                     7  /* EQLMIX_VOL2 - [7:1] */
1983  * R1620 (0x654) - EQLMIX Input 3 Source
1985 #define WM2200_EQLMIX_SRC3_MASK                 0x007F  /* EQLMIX_SRC3 - [6:0] */
1986 #define WM2200_EQLMIX_SRC3_SHIFT                     0  /* EQLMIX_SRC3 - [6:0] */
1987 #define WM2200_EQLMIX_SRC3_WIDTH                     7  /* EQLMIX_SRC3 - [6:0] */
1990  * R1621 (0x655) - EQLMIX Input 3 Volume
1992 #define WM2200_EQLMIX_VOL3_MASK                 0x00FE  /* EQLMIX_VOL3 - [7:1] */
1993 #define WM2200_EQLMIX_VOL3_SHIFT                     1  /* EQLMIX_VOL3 - [7:1] */
1994 #define WM2200_EQLMIX_VOL3_WIDTH                     7  /* EQLMIX_VOL3 - [7:1] */
1997  * R1622 (0x656) - EQLMIX Input 4 Source
1999 #define WM2200_EQLMIX_SRC4_MASK                 0x007F  /* EQLMIX_SRC4 - [6:0] */
2000 #define WM2200_EQLMIX_SRC4_SHIFT                     0  /* EQLMIX_SRC4 - [6:0] */
2001 #define WM2200_EQLMIX_SRC4_WIDTH                     7  /* EQLMIX_SRC4 - [6:0] */
2004  * R1623 (0x657) - EQLMIX Input 4 Volume
2006 #define WM2200_EQLMIX_VOL4_MASK                 0x00FE  /* EQLMIX_VOL4 - [7:1] */
2007 #define WM2200_EQLMIX_VOL4_SHIFT                     1  /* EQLMIX_VOL4 - [7:1] */
2008 #define WM2200_EQLMIX_VOL4_WIDTH                     7  /* EQLMIX_VOL4 - [7:1] */
2011  * R1624 (0x658) - EQRMIX Input 1 Source
2013 #define WM2200_EQRMIX_SRC1_MASK                 0x007F  /* EQRMIX_SRC1 - [6:0] */
2014 #define WM2200_EQRMIX_SRC1_SHIFT                     0  /* EQRMIX_SRC1 - [6:0] */
2015 #define WM2200_EQRMIX_SRC1_WIDTH                     7  /* EQRMIX_SRC1 - [6:0] */
2018  * R1625 (0x659) - EQRMIX Input 1 Volume
2020 #define WM2200_EQRMIX_VOL1_MASK                 0x00FE  /* EQRMIX_VOL1 - [7:1] */
2021 #define WM2200_EQRMIX_VOL1_SHIFT                     1  /* EQRMIX_VOL1 - [7:1] */
2022 #define WM2200_EQRMIX_VOL1_WIDTH                     7  /* EQRMIX_VOL1 - [7:1] */
2025  * R1626 (0x65A) - EQRMIX Input 2 Source
2027 #define WM2200_EQRMIX_SRC2_MASK                 0x007F  /* EQRMIX_SRC2 - [6:0] */
2028 #define WM2200_EQRMIX_SRC2_SHIFT                     0  /* EQRMIX_SRC2 - [6:0] */
2029 #define WM2200_EQRMIX_SRC2_WIDTH                     7  /* EQRMIX_SRC2 - [6:0] */
2032  * R1627 (0x65B) - EQRMIX Input 2 Volume
2034 #define WM2200_EQRMIX_VOL2_MASK                 0x00FE  /* EQRMIX_VOL2 - [7:1] */
2035 #define WM2200_EQRMIX_VOL2_SHIFT                     1  /* EQRMIX_VOL2 - [7:1] */
2036 #define WM2200_EQRMIX_VOL2_WIDTH                     7  /* EQRMIX_VOL2 - [7:1] */
2039  * R1628 (0x65C) - EQRMIX Input 3 Source
2041 #define WM2200_EQRMIX_SRC3_MASK                 0x007F  /* EQRMIX_SRC3 - [6:0] */
2042 #define WM2200_EQRMIX_SRC3_SHIFT                     0  /* EQRMIX_SRC3 - [6:0] */
2043 #define WM2200_EQRMIX_SRC3_WIDTH                     7  /* EQRMIX_SRC3 - [6:0] */
2046  * R1629 (0x65D) - EQRMIX Input 3 Volume
2048 #define WM2200_EQRMIX_VOL3_MASK                 0x00FE  /* EQRMIX_VOL3 - [7:1] */
2049 #define WM2200_EQRMIX_VOL3_SHIFT                     1  /* EQRMIX_VOL3 - [7:1] */
2050 #define WM2200_EQRMIX_VOL3_WIDTH                     7  /* EQRMIX_VOL3 - [7:1] */
2053  * R1630 (0x65E) - EQRMIX Input 4 Source
2055 #define WM2200_EQRMIX_SRC4_MASK                 0x007F  /* EQRMIX_SRC4 - [6:0] */
2056 #define WM2200_EQRMIX_SRC4_SHIFT                     0  /* EQRMIX_SRC4 - [6:0] */
2057 #define WM2200_EQRMIX_SRC4_WIDTH                     7  /* EQRMIX_SRC4 - [6:0] */
2060  * R1631 (0x65F) - EQRMIX Input 4 Volume
2062 #define WM2200_EQRMIX_VOL4_MASK                 0x00FE  /* EQRMIX_VOL4 - [7:1] */
2063 #define WM2200_EQRMIX_VOL4_SHIFT                     1  /* EQRMIX_VOL4 - [7:1] */
2064 #define WM2200_EQRMIX_VOL4_WIDTH                     7  /* EQRMIX_VOL4 - [7:1] */
2067  * R1632 (0x660) - LHPF1MIX Input 1 Source
2069 #define WM2200_LHPF1MIX_SRC1_MASK               0x007F  /* LHPF1MIX_SRC1 - [6:0] */
2070 #define WM2200_LHPF1MIX_SRC1_SHIFT                   0  /* LHPF1MIX_SRC1 - [6:0] */
2071 #define WM2200_LHPF1MIX_SRC1_WIDTH                   7  /* LHPF1MIX_SRC1 - [6:0] */
2074  * R1633 (0x661) - LHPF1MIX Input 1 Volume
2076 #define WM2200_LHPF1MIX_VOL1_MASK               0x00FE  /* LHPF1MIX_VOL1 - [7:1] */
2077 #define WM2200_LHPF1MIX_VOL1_SHIFT                   1  /* LHPF1MIX_VOL1 - [7:1] */
2078 #define WM2200_LHPF1MIX_VOL1_WIDTH                   7  /* LHPF1MIX_VOL1 - [7:1] */
2081  * R1634 (0x662) - LHPF1MIX Input 2 Source
2083 #define WM2200_LHPF1MIX_SRC2_MASK               0x007F  /* LHPF1MIX_SRC2 - [6:0] */
2084 #define WM2200_LHPF1MIX_SRC2_SHIFT                   0  /* LHPF1MIX_SRC2 - [6:0] */
2085 #define WM2200_LHPF1MIX_SRC2_WIDTH                   7  /* LHPF1MIX_SRC2 - [6:0] */
2088  * R1635 (0x663) - LHPF1MIX Input 2 Volume
2090 #define WM2200_LHPF1MIX_VOL2_MASK               0x00FE  /* LHPF1MIX_VOL2 - [7:1] */
2091 #define WM2200_LHPF1MIX_VOL2_SHIFT                   1  /* LHPF1MIX_VOL2 - [7:1] */
2092 #define WM2200_LHPF1MIX_VOL2_WIDTH                   7  /* LHPF1MIX_VOL2 - [7:1] */
2095  * R1636 (0x664) - LHPF1MIX Input 3 Source
2097 #define WM2200_LHPF1MIX_SRC3_MASK               0x007F  /* LHPF1MIX_SRC3 - [6:0] */
2098 #define WM2200_LHPF1MIX_SRC3_SHIFT                   0  /* LHPF1MIX_SRC3 - [6:0] */
2099 #define WM2200_LHPF1MIX_SRC3_WIDTH                   7  /* LHPF1MIX_SRC3 - [6:0] */
2102  * R1637 (0x665) - LHPF1MIX Input 3 Volume
2104 #define WM2200_LHPF1MIX_VOL3_MASK               0x00FE  /* LHPF1MIX_VOL3 - [7:1] */
2105 #define WM2200_LHPF1MIX_VOL3_SHIFT                   1  /* LHPF1MIX_VOL3 - [7:1] */
2106 #define WM2200_LHPF1MIX_VOL3_WIDTH                   7  /* LHPF1MIX_VOL3 - [7:1] */
2109  * R1638 (0x666) - LHPF1MIX Input 4 Source
2111 #define WM2200_LHPF1MIX_SRC4_MASK               0x007F  /* LHPF1MIX_SRC4 - [6:0] */
2112 #define WM2200_LHPF1MIX_SRC4_SHIFT                   0  /* LHPF1MIX_SRC4 - [6:0] */
2113 #define WM2200_LHPF1MIX_SRC4_WIDTH                   7  /* LHPF1MIX_SRC4 - [6:0] */
2116  * R1639 (0x667) - LHPF1MIX Input 4 Volume
2118 #define WM2200_LHPF1MIX_VOL4_MASK               0x00FE  /* LHPF1MIX_VOL4 - [7:1] */
2119 #define WM2200_LHPF1MIX_VOL4_SHIFT                   1  /* LHPF1MIX_VOL4 - [7:1] */
2120 #define WM2200_LHPF1MIX_VOL4_WIDTH                   7  /* LHPF1MIX_VOL4 - [7:1] */
2123  * R1640 (0x668) - LHPF2MIX Input 1 Source
2125 #define WM2200_LHPF2MIX_SRC1_MASK               0x007F  /* LHPF2MIX_SRC1 - [6:0] */
2126 #define WM2200_LHPF2MIX_SRC1_SHIFT                   0  /* LHPF2MIX_SRC1 - [6:0] */
2127 #define WM2200_LHPF2MIX_SRC1_WIDTH                   7  /* LHPF2MIX_SRC1 - [6:0] */
2130  * R1641 (0x669) - LHPF2MIX Input 1 Volume
2132 #define WM2200_LHPF2MIX_VOL1_MASK               0x00FE  /* LHPF2MIX_VOL1 - [7:1] */
2133 #define WM2200_LHPF2MIX_VOL1_SHIFT                   1  /* LHPF2MIX_VOL1 - [7:1] */
2134 #define WM2200_LHPF2MIX_VOL1_WIDTH                   7  /* LHPF2MIX_VOL1 - [7:1] */
2137  * R1642 (0x66A) - LHPF2MIX Input 2 Source
2139 #define WM2200_LHPF2MIX_SRC2_MASK               0x007F  /* LHPF2MIX_SRC2 - [6:0] */
2140 #define WM2200_LHPF2MIX_SRC2_SHIFT                   0  /* LHPF2MIX_SRC2 - [6:0] */
2141 #define WM2200_LHPF2MIX_SRC2_WIDTH                   7  /* LHPF2MIX_SRC2 - [6:0] */
2144  * R1643 (0x66B) - LHPF2MIX Input 2 Volume
2146 #define WM2200_LHPF2MIX_VOL2_MASK               0x00FE  /* LHPF2MIX_VOL2 - [7:1] */
2147 #define WM2200_LHPF2MIX_VOL2_SHIFT                   1  /* LHPF2MIX_VOL2 - [7:1] */
2148 #define WM2200_LHPF2MIX_VOL2_WIDTH                   7  /* LHPF2MIX_VOL2 - [7:1] */
2151  * R1644 (0x66C) - LHPF2MIX Input 3 Source
2153 #define WM2200_LHPF2MIX_SRC3_MASK               0x007F  /* LHPF2MIX_SRC3 - [6:0] */
2154 #define WM2200_LHPF2MIX_SRC3_SHIFT                   0  /* LHPF2MIX_SRC3 - [6:0] */
2155 #define WM2200_LHPF2MIX_SRC3_WIDTH                   7  /* LHPF2MIX_SRC3 - [6:0] */
2158  * R1645 (0x66D) - LHPF2MIX Input 3 Volume
2160 #define WM2200_LHPF2MIX_VOL3_MASK               0x00FE  /* LHPF2MIX_VOL3 - [7:1] */
2161 #define WM2200_LHPF2MIX_VOL3_SHIFT                   1  /* LHPF2MIX_VOL3 - [7:1] */
2162 #define WM2200_LHPF2MIX_VOL3_WIDTH                   7  /* LHPF2MIX_VOL3 - [7:1] */
2165  * R1646 (0x66E) - LHPF2MIX Input 4 Source
2167 #define WM2200_LHPF2MIX_SRC4_MASK               0x007F  /* LHPF2MIX_SRC4 - [6:0] */
2168 #define WM2200_LHPF2MIX_SRC4_SHIFT                   0  /* LHPF2MIX_SRC4 - [6:0] */
2169 #define WM2200_LHPF2MIX_SRC4_WIDTH                   7  /* LHPF2MIX_SRC4 - [6:0] */
2172  * R1647 (0x66F) - LHPF2MIX Input 4 Volume
2174 #define WM2200_LHPF2MIX_VOL4_MASK               0x00FE  /* LHPF2MIX_VOL4 - [7:1] */
2175 #define WM2200_LHPF2MIX_VOL4_SHIFT                   1  /* LHPF2MIX_VOL4 - [7:1] */
2176 #define WM2200_LHPF2MIX_VOL4_WIDTH                   7  /* LHPF2MIX_VOL4 - [7:1] */
2179  * R1648 (0x670) - DSP1LMIX Input 1 Source
2181 #define WM2200_DSP1LMIX_SRC1_MASK               0x007F  /* DSP1LMIX_SRC1 - [6:0] */
2182 #define WM2200_DSP1LMIX_SRC1_SHIFT                   0  /* DSP1LMIX_SRC1 - [6:0] */
2183 #define WM2200_DSP1LMIX_SRC1_WIDTH                   7  /* DSP1LMIX_SRC1 - [6:0] */
2186  * R1649 (0x671) - DSP1LMIX Input 1 Volume
2188 #define WM2200_DSP1LMIX_VOL1_MASK               0x00FE  /* DSP1LMIX_VOL1 - [7:1] */
2189 #define WM2200_DSP1LMIX_VOL1_SHIFT                   1  /* DSP1LMIX_VOL1 - [7:1] */
2190 #define WM2200_DSP1LMIX_VOL1_WIDTH                   7  /* DSP1LMIX_VOL1 - [7:1] */
2193  * R1650 (0x672) - DSP1LMIX Input 2 Source
2195 #define WM2200_DSP1LMIX_SRC2_MASK               0x007F  /* DSP1LMIX_SRC2 - [6:0] */
2196 #define WM2200_DSP1LMIX_SRC2_SHIFT                   0  /* DSP1LMIX_SRC2 - [6:0] */
2197 #define WM2200_DSP1LMIX_SRC2_WIDTH                   7  /* DSP1LMIX_SRC2 - [6:0] */
2200  * R1651 (0x673) - DSP1LMIX Input 2 Volume
2202 #define WM2200_DSP1LMIX_VOL2_MASK               0x00FE  /* DSP1LMIX_VOL2 - [7:1] */
2203 #define WM2200_DSP1LMIX_VOL2_SHIFT                   1  /* DSP1LMIX_VOL2 - [7:1] */
2204 #define WM2200_DSP1LMIX_VOL2_WIDTH                   7  /* DSP1LMIX_VOL2 - [7:1] */
2207  * R1652 (0x674) - DSP1LMIX Input 3 Source
2209 #define WM2200_DSP1LMIX_SRC3_MASK               0x007F  /* DSP1LMIX_SRC3 - [6:0] */
2210 #define WM2200_DSP1LMIX_SRC3_SHIFT                   0  /* DSP1LMIX_SRC3 - [6:0] */
2211 #define WM2200_DSP1LMIX_SRC3_WIDTH                   7  /* DSP1LMIX_SRC3 - [6:0] */
2214  * R1653 (0x675) - DSP1LMIX Input 3 Volume
2216 #define WM2200_DSP1LMIX_VOL3_MASK               0x00FE  /* DSP1LMIX_VOL3 - [7:1] */
2217 #define WM2200_DSP1LMIX_VOL3_SHIFT                   1  /* DSP1LMIX_VOL3 - [7:1] */
2218 #define WM2200_DSP1LMIX_VOL3_WIDTH                   7  /* DSP1LMIX_VOL3 - [7:1] */
2221  * R1654 (0x676) - DSP1LMIX Input 4 Source
2223 #define WM2200_DSP1LMIX_SRC4_MASK               0x007F  /* DSP1LMIX_SRC4 - [6:0] */
2224 #define WM2200_DSP1LMIX_SRC4_SHIFT                   0  /* DSP1LMIX_SRC4 - [6:0] */
2225 #define WM2200_DSP1LMIX_SRC4_WIDTH                   7  /* DSP1LMIX_SRC4 - [6:0] */
2228  * R1655 (0x677) - DSP1LMIX Input 4 Volume
2230 #define WM2200_DSP1LMIX_VOL4_MASK               0x00FE  /* DSP1LMIX_VOL4 - [7:1] */
2231 #define WM2200_DSP1LMIX_VOL4_SHIFT                   1  /* DSP1LMIX_VOL4 - [7:1] */
2232 #define WM2200_DSP1LMIX_VOL4_WIDTH                   7  /* DSP1LMIX_VOL4 - [7:1] */
2235  * R1656 (0x678) - DSP1RMIX Input 1 Source
2237 #define WM2200_DSP1RMIX_SRC1_MASK               0x007F  /* DSP1RMIX_SRC1 - [6:0] */
2238 #define WM2200_DSP1RMIX_SRC1_SHIFT                   0  /* DSP1RMIX_SRC1 - [6:0] */
2239 #define WM2200_DSP1RMIX_SRC1_WIDTH                   7  /* DSP1RMIX_SRC1 - [6:0] */
2242  * R1657 (0x679) - DSP1RMIX Input 1 Volume
2244 #define WM2200_DSP1RMIX_VOL1_MASK               0x00FE  /* DSP1RMIX_VOL1 - [7:1] */
2245 #define WM2200_DSP1RMIX_VOL1_SHIFT                   1  /* DSP1RMIX_VOL1 - [7:1] */
2246 #define WM2200_DSP1RMIX_VOL1_WIDTH                   7  /* DSP1RMIX_VOL1 - [7:1] */
2249  * R1658 (0x67A) - DSP1RMIX Input 2 Source
2251 #define WM2200_DSP1RMIX_SRC2_MASK               0x007F  /* DSP1RMIX_SRC2 - [6:0] */
2252 #define WM2200_DSP1RMIX_SRC2_SHIFT                   0  /* DSP1RMIX_SRC2 - [6:0] */
2253 #define WM2200_DSP1RMIX_SRC2_WIDTH                   7  /* DSP1RMIX_SRC2 - [6:0] */
2256  * R1659 (0x67B) - DSP1RMIX Input 2 Volume
2258 #define WM2200_DSP1RMIX_VOL2_MASK               0x00FE  /* DSP1RMIX_VOL2 - [7:1] */
2259 #define WM2200_DSP1RMIX_VOL2_SHIFT                   1  /* DSP1RMIX_VOL2 - [7:1] */
2260 #define WM2200_DSP1RMIX_VOL2_WIDTH                   7  /* DSP1RMIX_VOL2 - [7:1] */
2263  * R1660 (0x67C) - DSP1RMIX Input 3 Source
2265 #define WM2200_DSP1RMIX_SRC3_MASK               0x007F  /* DSP1RMIX_SRC3 - [6:0] */
2266 #define WM2200_DSP1RMIX_SRC3_SHIFT                   0  /* DSP1RMIX_SRC3 - [6:0] */
2267 #define WM2200_DSP1RMIX_SRC3_WIDTH                   7  /* DSP1RMIX_SRC3 - [6:0] */
2270  * R1661 (0x67D) - DSP1RMIX Input 3 Volume
2272 #define WM2200_DSP1RMIX_VOL3_MASK               0x00FE  /* DSP1RMIX_VOL3 - [7:1] */
2273 #define WM2200_DSP1RMIX_VOL3_SHIFT                   1  /* DSP1RMIX_VOL3 - [7:1] */
2274 #define WM2200_DSP1RMIX_VOL3_WIDTH                   7  /* DSP1RMIX_VOL3 - [7:1] */
2277  * R1662 (0x67E) - DSP1RMIX Input 4 Source
2279 #define WM2200_DSP1RMIX_SRC4_MASK               0x007F  /* DSP1RMIX_SRC4 - [6:0] */
2280 #define WM2200_DSP1RMIX_SRC4_SHIFT                   0  /* DSP1RMIX_SRC4 - [6:0] */
2281 #define WM2200_DSP1RMIX_SRC4_WIDTH                   7  /* DSP1RMIX_SRC4 - [6:0] */
2284  * R1663 (0x67F) - DSP1RMIX Input 4 Volume
2286 #define WM2200_DSP1RMIX_VOL4_MASK               0x00FE  /* DSP1RMIX_VOL4 - [7:1] */
2287 #define WM2200_DSP1RMIX_VOL4_SHIFT                   1  /* DSP1RMIX_VOL4 - [7:1] */
2288 #define WM2200_DSP1RMIX_VOL4_WIDTH                   7  /* DSP1RMIX_VOL4 - [7:1] */
2291  * R1664 (0x680) - DSP1AUX1MIX Input 1 Source
2293 #define WM2200_DSP1AUX1MIX_SRC1_MASK            0x007F  /* DSP1AUX1MIX_SRC1 - [6:0] */
2294 #define WM2200_DSP1AUX1MIX_SRC1_SHIFT                0  /* DSP1AUX1MIX_SRC1 - [6:0] */
2295 #define WM2200_DSP1AUX1MIX_SRC1_WIDTH                7  /* DSP1AUX1MIX_SRC1 - [6:0] */
2298  * R1665 (0x681) - DSP1AUX2MIX Input 1 Source
2300 #define WM2200_DSP1AUX2MIX_SRC1_MASK            0x007F  /* DSP1AUX2MIX_SRC1 - [6:0] */
2301 #define WM2200_DSP1AUX2MIX_SRC1_SHIFT                0  /* DSP1AUX2MIX_SRC1 - [6:0] */
2302 #define WM2200_DSP1AUX2MIX_SRC1_WIDTH                7  /* DSP1AUX2MIX_SRC1 - [6:0] */
2305  * R1666 (0x682) - DSP1AUX3MIX Input 1 Source
2307 #define WM2200_DSP1AUX3MIX_SRC1_MASK            0x007F  /* DSP1AUX3MIX_SRC1 - [6:0] */
2308 #define WM2200_DSP1AUX3MIX_SRC1_SHIFT                0  /* DSP1AUX3MIX_SRC1 - [6:0] */
2309 #define WM2200_DSP1AUX3MIX_SRC1_WIDTH                7  /* DSP1AUX3MIX_SRC1 - [6:0] */
2312  * R1667 (0x683) - DSP1AUX4MIX Input 1 Source
2314 #define WM2200_DSP1AUX4MIX_SRC1_MASK            0x007F  /* DSP1AUX4MIX_SRC1 - [6:0] */
2315 #define WM2200_DSP1AUX4MIX_SRC1_SHIFT                0  /* DSP1AUX4MIX_SRC1 - [6:0] */
2316 #define WM2200_DSP1AUX4MIX_SRC1_WIDTH                7  /* DSP1AUX4MIX_SRC1 - [6:0] */
2319  * R1668 (0x684) - DSP1AUX5MIX Input 1 Source
2321 #define WM2200_DSP1AUX5MIX_SRC1_MASK            0x007F  /* DSP1AUX5MIX_SRC1 - [6:0] */
2322 #define WM2200_DSP1AUX5MIX_SRC1_SHIFT                0  /* DSP1AUX5MIX_SRC1 - [6:0] */
2323 #define WM2200_DSP1AUX5MIX_SRC1_WIDTH                7  /* DSP1AUX5MIX_SRC1 - [6:0] */
2326  * R1669 (0x685) - DSP1AUX6MIX Input 1 Source
2328 #define WM2200_DSP1AUX6MIX_SRC1_MASK            0x007F  /* DSP1AUX6MIX_SRC1 - [6:0] */
2329 #define WM2200_DSP1AUX6MIX_SRC1_SHIFT                0  /* DSP1AUX6MIX_SRC1 - [6:0] */
2330 #define WM2200_DSP1AUX6MIX_SRC1_WIDTH                7  /* DSP1AUX6MIX_SRC1 - [6:0] */
2333  * R1670 (0x686) - DSP2LMIX Input 1 Source
2335 #define WM2200_DSP2LMIX_SRC1_MASK               0x007F  /* DSP2LMIX_SRC1 - [6:0] */
2336 #define WM2200_DSP2LMIX_SRC1_SHIFT                   0  /* DSP2LMIX_SRC1 - [6:0] */
2337 #define WM2200_DSP2LMIX_SRC1_WIDTH                   7  /* DSP2LMIX_SRC1 - [6:0] */
2340  * R1671 (0x687) - DSP2LMIX Input 1 Volume
2342 #define WM2200_DSP2LMIX_VOL1_MASK               0x00FE  /* DSP2LMIX_VOL1 - [7:1] */
2343 #define WM2200_DSP2LMIX_VOL1_SHIFT                   1  /* DSP2LMIX_VOL1 - [7:1] */
2344 #define WM2200_DSP2LMIX_VOL1_WIDTH                   7  /* DSP2LMIX_VOL1 - [7:1] */
2347  * R1672 (0x688) - DSP2LMIX Input 2 Source
2349 #define WM2200_DSP2LMIX_SRC2_MASK               0x007F  /* DSP2LMIX_SRC2 - [6:0] */
2350 #define WM2200_DSP2LMIX_SRC2_SHIFT                   0  /* DSP2LMIX_SRC2 - [6:0] */
2351 #define WM2200_DSP2LMIX_SRC2_WIDTH                   7  /* DSP2LMIX_SRC2 - [6:0] */
2354  * R1673 (0x689) - DSP2LMIX Input 2 Volume
2356 #define WM2200_DSP2LMIX_VOL2_MASK               0x00FE  /* DSP2LMIX_VOL2 - [7:1] */
2357 #define WM2200_DSP2LMIX_VOL2_SHIFT                   1  /* DSP2LMIX_VOL2 - [7:1] */
2358 #define WM2200_DSP2LMIX_VOL2_WIDTH                   7  /* DSP2LMIX_VOL2 - [7:1] */
2361  * R1674 (0x68A) - DSP2LMIX Input 3 Source
2363 #define WM2200_DSP2LMIX_SRC3_MASK               0x007F  /* DSP2LMIX_SRC3 - [6:0] */
2364 #define WM2200_DSP2LMIX_SRC3_SHIFT                   0  /* DSP2LMIX_SRC3 - [6:0] */
2365 #define WM2200_DSP2LMIX_SRC3_WIDTH                   7  /* DSP2LMIX_SRC3 - [6:0] */
2368  * R1675 (0x68B) - DSP2LMIX Input 3 Volume
2370 #define WM2200_DSP2LMIX_VOL3_MASK               0x00FE  /* DSP2LMIX_VOL3 - [7:1] */
2371 #define WM2200_DSP2LMIX_VOL3_SHIFT                   1  /* DSP2LMIX_VOL3 - [7:1] */
2372 #define WM2200_DSP2LMIX_VOL3_WIDTH                   7  /* DSP2LMIX_VOL3 - [7:1] */
2375  * R1676 (0x68C) - DSP2LMIX Input 4 Source
2377 #define WM2200_DSP2LMIX_SRC4_MASK               0x007F  /* DSP2LMIX_SRC4 - [6:0] */
2378 #define WM2200_DSP2LMIX_SRC4_SHIFT                   0  /* DSP2LMIX_SRC4 - [6:0] */
2379 #define WM2200_DSP2LMIX_SRC4_WIDTH                   7  /* DSP2LMIX_SRC4 - [6:0] */
2382  * R1677 (0x68D) - DSP2LMIX Input 4 Volume
2384 #define WM2200_DSP2LMIX_VOL4_MASK               0x00FE  /* DSP2LMIX_VOL4 - [7:1] */
2385 #define WM2200_DSP2LMIX_VOL4_SHIFT                   1  /* DSP2LMIX_VOL4 - [7:1] */
2386 #define WM2200_DSP2LMIX_VOL4_WIDTH                   7  /* DSP2LMIX_VOL4 - [7:1] */
2389  * R1678 (0x68E) - DSP2RMIX Input 1 Source
2391 #define WM2200_DSP2RMIX_SRC1_MASK               0x007F  /* DSP2RMIX_SRC1 - [6:0] */
2392 #define WM2200_DSP2RMIX_SRC1_SHIFT                   0  /* DSP2RMIX_SRC1 - [6:0] */
2393 #define WM2200_DSP2RMIX_SRC1_WIDTH                   7  /* DSP2RMIX_SRC1 - [6:0] */
2396  * R1679 (0x68F) - DSP2RMIX Input 1 Volume
2398 #define WM2200_DSP2RMIX_VOL1_MASK               0x00FE  /* DSP2RMIX_VOL1 - [7:1] */
2399 #define WM2200_DSP2RMIX_VOL1_SHIFT                   1  /* DSP2RMIX_VOL1 - [7:1] */
2400 #define WM2200_DSP2RMIX_VOL1_WIDTH                   7  /* DSP2RMIX_VOL1 - [7:1] */
2403  * R1680 (0x690) - DSP2RMIX Input 2 Source
2405 #define WM2200_DSP2RMIX_SRC2_MASK               0x007F  /* DSP2RMIX_SRC2 - [6:0] */
2406 #define WM2200_DSP2RMIX_SRC2_SHIFT                   0  /* DSP2RMIX_SRC2 - [6:0] */
2407 #define WM2200_DSP2RMIX_SRC2_WIDTH                   7  /* DSP2RMIX_SRC2 - [6:0] */
2410  * R1681 (0x691) - DSP2RMIX Input 2 Volume
2412 #define WM2200_DSP2RMIX_VOL2_MASK               0x00FE  /* DSP2RMIX_VOL2 - [7:1] */
2413 #define WM2200_DSP2RMIX_VOL2_SHIFT                   1  /* DSP2RMIX_VOL2 - [7:1] */
2414 #define WM2200_DSP2RMIX_VOL2_WIDTH                   7  /* DSP2RMIX_VOL2 - [7:1] */
2417  * R1682 (0x692) - DSP2RMIX Input 3 Source
2419 #define WM2200_DSP2RMIX_SRC3_MASK               0x007F  /* DSP2RMIX_SRC3 - [6:0] */
2420 #define WM2200_DSP2RMIX_SRC3_SHIFT                   0  /* DSP2RMIX_SRC3 - [6:0] */
2421 #define WM2200_DSP2RMIX_SRC3_WIDTH                   7  /* DSP2RMIX_SRC3 - [6:0] */
2424  * R1683 (0x693) - DSP2RMIX Input 3 Volume
2426 #define WM2200_DSP2RMIX_VOL3_MASK               0x00FE  /* DSP2RMIX_VOL3 - [7:1] */
2427 #define WM2200_DSP2RMIX_VOL3_SHIFT                   1  /* DSP2RMIX_VOL3 - [7:1] */
2428 #define WM2200_DSP2RMIX_VOL3_WIDTH                   7  /* DSP2RMIX_VOL3 - [7:1] */
2431  * R1684 (0x694) - DSP2RMIX Input 4 Source
2433 #define WM2200_DSP2RMIX_SRC4_MASK               0x007F  /* DSP2RMIX_SRC4 - [6:0] */
2434 #define WM2200_DSP2RMIX_SRC4_SHIFT                   0  /* DSP2RMIX_SRC4 - [6:0] */
2435 #define WM2200_DSP2RMIX_SRC4_WIDTH                   7  /* DSP2RMIX_SRC4 - [6:0] */
2438  * R1685 (0x695) - DSP2RMIX Input 4 Volume
2440 #define WM2200_DSP2RMIX_VOL4_MASK               0x00FE  /* DSP2RMIX_VOL4 - [7:1] */
2441 #define WM2200_DSP2RMIX_VOL4_SHIFT                   1  /* DSP2RMIX_VOL4 - [7:1] */
2442 #define WM2200_DSP2RMIX_VOL4_WIDTH                   7  /* DSP2RMIX_VOL4 - [7:1] */
2445  * R1686 (0x696) - DSP2AUX1MIX Input 1 Source
2447 #define WM2200_DSP2AUX1MIX_SRC1_MASK            0x007F  /* DSP2AUX1MIX_SRC1 - [6:0] */
2448 #define WM2200_DSP2AUX1MIX_SRC1_SHIFT                0  /* DSP2AUX1MIX_SRC1 - [6:0] */
2449 #define WM2200_DSP2AUX1MIX_SRC1_WIDTH                7  /* DSP2AUX1MIX_SRC1 - [6:0] */
2452  * R1687 (0x697) - DSP2AUX2MIX Input 1 Source
2454 #define WM2200_DSP2AUX2MIX_SRC1_MASK            0x007F  /* DSP2AUX2MIX_SRC1 - [6:0] */
2455 #define WM2200_DSP2AUX2MIX_SRC1_SHIFT                0  /* DSP2AUX2MIX_SRC1 - [6:0] */
2456 #define WM2200_DSP2AUX2MIX_SRC1_WIDTH                7  /* DSP2AUX2MIX_SRC1 - [6:0] */
2459  * R1688 (0x698) - DSP2AUX3MIX Input 1 Source
2461 #define WM2200_DSP2AUX3MIX_SRC1_MASK            0x007F  /* DSP2AUX3MIX_SRC1 - [6:0] */
2462 #define WM2200_DSP2AUX3MIX_SRC1_SHIFT                0  /* DSP2AUX3MIX_SRC1 - [6:0] */
2463 #define WM2200_DSP2AUX3MIX_SRC1_WIDTH                7  /* DSP2AUX3MIX_SRC1 - [6:0] */
2466  * R1689 (0x699) - DSP2AUX4MIX Input 1 Source
2468 #define WM2200_DSP2AUX4MIX_SRC1_MASK            0x007F  /* DSP2AUX4MIX_SRC1 - [6:0] */
2469 #define WM2200_DSP2AUX4MIX_SRC1_SHIFT                0  /* DSP2AUX4MIX_SRC1 - [6:0] */
2470 #define WM2200_DSP2AUX4MIX_SRC1_WIDTH                7  /* DSP2AUX4MIX_SRC1 - [6:0] */
2473  * R1690 (0x69A) - DSP2AUX5MIX Input 1 Source
2475 #define WM2200_DSP2AUX5MIX_SRC1_MASK            0x007F  /* DSP2AUX5MIX_SRC1 - [6:0] */
2476 #define WM2200_DSP2AUX5MIX_SRC1_SHIFT                0  /* DSP2AUX5MIX_SRC1 - [6:0] */
2477 #define WM2200_DSP2AUX5MIX_SRC1_WIDTH                7  /* DSP2AUX5MIX_SRC1 - [6:0] */
2480  * R1691 (0x69B) - DSP2AUX6MIX Input 1 Source
2482 #define WM2200_DSP2AUX6MIX_SRC1_MASK            0x007F  /* DSP2AUX6MIX_SRC1 - [6:0] */
2483 #define WM2200_DSP2AUX6MIX_SRC1_SHIFT                0  /* DSP2AUX6MIX_SRC1 - [6:0] */
2484 #define WM2200_DSP2AUX6MIX_SRC1_WIDTH                7  /* DSP2AUX6MIX_SRC1 - [6:0] */
2487  * R1792 (0x700) - GPIO CTRL 1
2492 #define WM2200_GP1_DIR_WIDTH                         1  /* GP1_DIR */
2496 #define WM2200_GP1_PU_WIDTH                          1  /* GP1_PU */
2500 #define WM2200_GP1_PD_WIDTH                          1  /* GP1_PD */
2504 #define WM2200_GP1_POL_WIDTH                         1  /* GP1_POL */
2508 #define WM2200_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
2512 #define WM2200_GP1_DB_WIDTH                          1  /* GP1_DB */
2515 #define WM2200_GP1_LVL_SHIFT                         6  /* GP1_LVL */
2516 #define WM2200_GP1_LVL_WIDTH                         1  /* GP1_LVL */
2517 #define WM2200_GP1_FN_MASK                      0x003F  /* GP1_FN - [5:0] */
2518 #define WM2200_GP1_FN_SHIFT                          0  /* GP1_FN - [5:0] */
2519 #define WM2200_GP1_FN_WIDTH                          6  /* GP1_FN - [5:0] */
2522  * R1793 (0x701) - GPIO CTRL 2
2527 #define WM2200_GP2_DIR_WIDTH                         1  /* GP2_DIR */
2531 #define WM2200_GP2_PU_WIDTH                          1  /* GP2_PU */
2535 #define WM2200_GP2_PD_WIDTH                          1  /* GP2_PD */
2539 #define WM2200_GP2_POL_WIDTH                         1  /* GP2_POL */
2543 #define WM2200_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
2547 #define WM2200_GP2_DB_WIDTH                          1  /* GP2_DB */
2550 #define WM2200_GP2_LVL_SHIFT                         6  /* GP2_LVL */
2551 #define WM2200_GP2_LVL_WIDTH                         1  /* GP2_LVL */
2552 #define WM2200_GP2_FN_MASK                      0x003F  /* GP2_FN - [5:0] */
2553 #define WM2200_GP2_FN_SHIFT                          0  /* GP2_FN - [5:0] */
2554 #define WM2200_GP2_FN_WIDTH                          6  /* GP2_FN - [5:0] */
2557  * R1794 (0x702) - GPIO CTRL 3
2562 #define WM2200_GP3_DIR_WIDTH                         1  /* GP3_DIR */
2566 #define WM2200_GP3_PU_WIDTH                          1  /* GP3_PU */
2570 #define WM2200_GP3_PD_WIDTH                          1  /* GP3_PD */
2574 #define WM2200_GP3_POL_WIDTH                         1  /* GP3_POL */
2578 #define WM2200_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
2582 #define WM2200_GP3_DB_WIDTH                          1  /* GP3_DB */
2585 #define WM2200_GP3_LVL_SHIFT                         6  /* GP3_LVL */
2586 #define WM2200_GP3_LVL_WIDTH                         1  /* GP3_LVL */
2587 #define WM2200_GP3_FN_MASK                      0x003F  /* GP3_FN - [5:0] */
2588 #define WM2200_GP3_FN_SHIFT                          0  /* GP3_FN - [5:0] */
2589 #define WM2200_GP3_FN_WIDTH                          6  /* GP3_FN - [5:0] */
2592  * R1795 (0x703) - GPIO CTRL 4
2597 #define WM2200_GP4_DIR_WIDTH                         1  /* GP4_DIR */
2601 #define WM2200_GP4_PU_WIDTH                          1  /* GP4_PU */
2605 #define WM2200_GP4_PD_WIDTH                          1  /* GP4_PD */
2609 #define WM2200_GP4_POL_WIDTH                         1  /* GP4_POL */
2613 #define WM2200_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
2617 #define WM2200_GP4_DB_WIDTH                          1  /* GP4_DB */
2620 #define WM2200_GP4_LVL_SHIFT                         6  /* GP4_LVL */
2621 #define WM2200_GP4_LVL_WIDTH                         1  /* GP4_LVL */
2622 #define WM2200_GP4_FN_MASK                      0x003F  /* GP4_FN - [5:0] */
2623 #define WM2200_GP4_FN_SHIFT                          0  /* GP4_FN - [5:0] */
2624 #define WM2200_GP4_FN_WIDTH                          6  /* GP4_FN - [5:0] */
2627  * R1799 (0x707) - ADPS1 IRQ0
2631 #define WM2200_DSP_IRQ1_SHIFT                        1  /* DSP_IRQ1 */
2632 #define WM2200_DSP_IRQ1_WIDTH                        1  /* DSP_IRQ1 */
2636 #define WM2200_DSP_IRQ0_WIDTH                        1  /* DSP_IRQ0 */
2639  * R1800 (0x708) - ADPS1 IRQ1
2643 #define WM2200_DSP_IRQ3_SHIFT                        1  /* DSP_IRQ3 */
2644 #define WM2200_DSP_IRQ3_WIDTH                        1  /* DSP_IRQ3 */
2648 #define WM2200_DSP_IRQ2_WIDTH                        1  /* DSP_IRQ2 */
2651  * R1801 (0x709) - Misc Pad Ctrl 1
2656 #define WM2200_LDO1ENA_PD_WIDTH                      1  /* LDO1ENA_PD */
2660 #define WM2200_MCLK2_PD_WIDTH                        1  /* MCLK2_PD */
2664 #define WM2200_MCLK1_PD_WIDTH                        1  /* MCLK1_PD */
2668 #define WM2200_DACLRCLK1_PU_WIDTH                    1  /* DACLRCLK1_PU */
2672 #define WM2200_DACLRCLK1_PD_WIDTH                    1  /* DACLRCLK1_PD */
2676 #define WM2200_BCLK1_PU_WIDTH                        1  /* BCLK1_PU */
2680 #define WM2200_BCLK1_PD_WIDTH                        1  /* BCLK1_PD */
2683 #define WM2200_DACDAT1_PU_SHIFT                      6  /* DACDAT1_PU */
2684 #define WM2200_DACDAT1_PU_WIDTH                      1  /* DACDAT1_PU */
2688 #define WM2200_DACDAT1_PD_WIDTH                      1  /* DACDAT1_PD */
2692 #define WM2200_DMICDAT3_PD_WIDTH                     1  /* DMICDAT3_PD */
2696 #define WM2200_DMICDAT2_PD_WIDTH                     1  /* DMICDAT2_PD */
2700 #define WM2200_DMICDAT1_PD_WIDTH                     1  /* DMICDAT1_PD */
2703 #define WM2200_RSTB_PU_SHIFT                         1  /* RSTB_PU */
2704 #define WM2200_RSTB_PU_WIDTH                         1  /* RSTB_PU */
2708 #define WM2200_ADDR_PD_WIDTH                         1  /* ADDR_PD */
2711  * R2048 (0x800) - Interrupt Status 1
2716 #define WM2200_DSP_IRQ0_EINT_WIDTH                   1  /* DSP_IRQ0_EINT */
2719 #define WM2200_DSP_IRQ1_EINT_SHIFT                   6  /* DSP_IRQ1_EINT */
2720 #define WM2200_DSP_IRQ1_EINT_WIDTH                   1  /* DSP_IRQ1_EINT */
2724 #define WM2200_DSP_IRQ2_EINT_WIDTH                   1  /* DSP_IRQ2_EINT */
2728 #define WM2200_DSP_IRQ3_EINT_WIDTH                   1  /* DSP_IRQ3_EINT */
2732 #define WM2200_GP4_EINT_WIDTH                        1  /* GP4_EINT */
2736 #define WM2200_GP3_EINT_WIDTH                        1  /* GP3_EINT */
2739 #define WM2200_GP2_EINT_SHIFT                        1  /* GP2_EINT */
2740 #define WM2200_GP2_EINT_WIDTH                        1  /* GP2_EINT */
2744 #define WM2200_GP1_EINT_WIDTH                        1  /* GP1_EINT */
2747  * R2049 (0x801) - Interrupt Status 1 Mask
2752 #define WM2200_IM_DSP_IRQ0_EINT_WIDTH                1  /* IM_DSP_IRQ0_EINT */
2755 #define WM2200_IM_DSP_IRQ1_EINT_SHIFT                6  /* IM_DSP_IRQ1_EINT */
2756 #define WM2200_IM_DSP_IRQ1_EINT_WIDTH                1  /* IM_DSP_IRQ1_EINT */
2760 #define WM2200_IM_DSP_IRQ2_EINT_WIDTH                1  /* IM_DSP_IRQ2_EINT */
2764 #define WM2200_IM_DSP_IRQ3_EINT_WIDTH                1  /* IM_DSP_IRQ3_EINT */
2768 #define WM2200_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
2772 #define WM2200_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
2775 #define WM2200_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
2776 #define WM2200_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
2780 #define WM2200_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
2783  * R2050 (0x802) - Interrupt Status 2
2788 #define WM2200_WSEQ_BUSY_EINT_WIDTH                  1  /* WSEQ_BUSY_EINT */
2791 #define WM2200_FLL_LOCK_EINT_SHIFT                   1  /* FLL_LOCK_EINT */
2792 #define WM2200_FLL_LOCK_EINT_WIDTH                   1  /* FLL_LOCK_EINT */
2796 #define WM2200_CLKGEN_EINT_WIDTH                     1  /* CLKGEN_EINT */
2799  * R2051 (0x803) - Interrupt Raw Status 2
2804 #define WM2200_WSEQ_BUSY_STS_WIDTH                   1  /* WSEQ_BUSY_STS */
2807 #define WM2200_FLL_LOCK_STS_SHIFT                    1  /* FLL_LOCK_STS */
2808 #define WM2200_FLL_LOCK_STS_WIDTH                    1  /* FLL_LOCK_STS */
2812 #define WM2200_CLKGEN_STS_WIDTH                      1  /* CLKGEN_STS */
2815  * R2052 (0x804) - Interrupt Status 2 Mask
2820 #define WM2200_IM_WSEQ_BUSY_EINT_WIDTH               1  /* IM_WSEQ_BUSY_EINT */
2823 #define WM2200_IM_FLL_LOCK_EINT_SHIFT                1  /* IM_FLL_LOCK_EINT */
2824 #define WM2200_IM_FLL_LOCK_EINT_WIDTH                1  /* IM_FLL_LOCK_EINT */
2828 #define WM2200_IM_CLKGEN_EINT_WIDTH                  1  /* IM_CLKGEN_EINT */
2831  * R2056 (0x808) - Interrupt Control
2836 #define WM2200_IM_IRQ_WIDTH                          1  /* IM_IRQ */
2839  * R2304 (0x900) - EQL_1
2841 #define WM2200_EQL_B1_GAIN_MASK                 0xF800  /* EQL_B1_GAIN - [15:11] */
2842 #define WM2200_EQL_B1_GAIN_SHIFT                    11  /* EQL_B1_GAIN - [15:11] */
2843 #define WM2200_EQL_B1_GAIN_WIDTH                     5  /* EQL_B1_GAIN - [15:11] */
2844 #define WM2200_EQL_B2_GAIN_MASK                 0x07C0  /* EQL_B2_GAIN - [10:6] */
2845 #define WM2200_EQL_B2_GAIN_SHIFT                     6  /* EQL_B2_GAIN - [10:6] */
2846 #define WM2200_EQL_B2_GAIN_WIDTH                     5  /* EQL_B2_GAIN - [10:6] */
2847 #define WM2200_EQL_B3_GAIN_MASK                 0x003E  /* EQL_B3_GAIN - [5:1] */
2848 #define WM2200_EQL_B3_GAIN_SHIFT                     1  /* EQL_B3_GAIN - [5:1] */
2849 #define WM2200_EQL_B3_GAIN_WIDTH                     5  /* EQL_B3_GAIN - [5:1] */
2853 #define WM2200_EQL_ENA_WIDTH                         1  /* EQL_ENA */
2856  * R2305 (0x901) - EQL_2
2858 #define WM2200_EQL_B4_GAIN_MASK                 0xF800  /* EQL_B4_GAIN - [15:11] */
2859 #define WM2200_EQL_B4_GAIN_SHIFT                    11  /* EQL_B4_GAIN - [15:11] */
2860 #define WM2200_EQL_B4_GAIN_WIDTH                     5  /* EQL_B4_GAIN - [15:11] */
2861 #define WM2200_EQL_B5_GAIN_MASK                 0x07C0  /* EQL_B5_GAIN - [10:6] */
2862 #define WM2200_EQL_B5_GAIN_SHIFT                     6  /* EQL_B5_GAIN - [10:6] */
2863 #define WM2200_EQL_B5_GAIN_WIDTH                     5  /* EQL_B5_GAIN - [10:6] */
2866  * R2306 (0x902) - EQL_3
2868 #define WM2200_EQL_B1_A_MASK                    0xFFFF  /* EQL_B1_A - [15:0] */
2869 #define WM2200_EQL_B1_A_SHIFT                        0  /* EQL_B1_A - [15:0] */
2870 #define WM2200_EQL_B1_A_WIDTH                       16  /* EQL_B1_A - [15:0] */
2873  * R2307 (0x903) - EQL_4
2875 #define WM2200_EQL_B1_B_MASK                    0xFFFF  /* EQL_B1_B - [15:0] */
2876 #define WM2200_EQL_B1_B_SHIFT                        0  /* EQL_B1_B - [15:0] */
2877 #define WM2200_EQL_B1_B_WIDTH                       16  /* EQL_B1_B - [15:0] */
2880  * R2308 (0x904) - EQL_5
2882 #define WM2200_EQL_B1_PG_MASK                   0xFFFF  /* EQL_B1_PG - [15:0] */
2883 #define WM2200_EQL_B1_PG_SHIFT                       0  /* EQL_B1_PG - [15:0] */
2884 #define WM2200_EQL_B1_PG_WIDTH                      16  /* EQL_B1_PG - [15:0] */
2887  * R2309 (0x905) - EQL_6
2889 #define WM2200_EQL_B2_A_MASK                    0xFFFF  /* EQL_B2_A - [15:0] */
2890 #define WM2200_EQL_B2_A_SHIFT                        0  /* EQL_B2_A - [15:0] */
2891 #define WM2200_EQL_B2_A_WIDTH                       16  /* EQL_B2_A - [15:0] */
2894  * R2310 (0x906) - EQL_7
2896 #define WM2200_EQL_B2_B_MASK                    0xFFFF  /* EQL_B2_B - [15:0] */
2897 #define WM2200_EQL_B2_B_SHIFT                        0  /* EQL_B2_B - [15:0] */
2898 #define WM2200_EQL_B2_B_WIDTH                       16  /* EQL_B2_B - [15:0] */
2901  * R2311 (0x907) - EQL_8
2903 #define WM2200_EQL_B2_C_MASK                    0xFFFF  /* EQL_B2_C - [15:0] */
2904 #define WM2200_EQL_B2_C_SHIFT                        0  /* EQL_B2_C - [15:0] */
2905 #define WM2200_EQL_B2_C_WIDTH                       16  /* EQL_B2_C - [15:0] */
2908  * R2312 (0x908) - EQL_9
2910 #define WM2200_EQL_B2_PG_MASK                   0xFFFF  /* EQL_B2_PG - [15:0] */
2911 #define WM2200_EQL_B2_PG_SHIFT                       0  /* EQL_B2_PG - [15:0] */
2912 #define WM2200_EQL_B2_PG_WIDTH                      16  /* EQL_B2_PG - [15:0] */
2915  * R2313 (0x909) - EQL_10
2917 #define WM2200_EQL_B3_A_MASK                    0xFFFF  /* EQL_B3_A - [15:0] */
2918 #define WM2200_EQL_B3_A_SHIFT                        0  /* EQL_B3_A - [15:0] */
2919 #define WM2200_EQL_B3_A_WIDTH                       16  /* EQL_B3_A - [15:0] */
2922  * R2314 (0x90A) - EQL_11
2924 #define WM2200_EQL_B3_B_MASK                    0xFFFF  /* EQL_B3_B - [15:0] */
2925 #define WM2200_EQL_B3_B_SHIFT                        0  /* EQL_B3_B - [15:0] */
2926 #define WM2200_EQL_B3_B_WIDTH                       16  /* EQL_B3_B - [15:0] */
2929  * R2315 (0x90B) - EQL_12
2931 #define WM2200_EQL_B3_C_MASK                    0xFFFF  /* EQL_B3_C - [15:0] */
2932 #define WM2200_EQL_B3_C_SHIFT                        0  /* EQL_B3_C - [15:0] */
2933 #define WM2200_EQL_B3_C_WIDTH                       16  /* EQL_B3_C - [15:0] */
2936  * R2316 (0x90C) - EQL_13
2938 #define WM2200_EQL_B3_PG_MASK                   0xFFFF  /* EQL_B3_PG - [15:0] */
2939 #define WM2200_EQL_B3_PG_SHIFT                       0  /* EQL_B3_PG - [15:0] */
2940 #define WM2200_EQL_B3_PG_WIDTH                      16  /* EQL_B3_PG - [15:0] */
2943  * R2317 (0x90D) - EQL_14
2945 #define WM2200_EQL_B4_A_MASK                    0xFFFF  /* EQL_B4_A - [15:0] */
2946 #define WM2200_EQL_B4_A_SHIFT                        0  /* EQL_B4_A - [15:0] */
2947 #define WM2200_EQL_B4_A_WIDTH                       16  /* EQL_B4_A - [15:0] */
2950  * R2318 (0x90E) - EQL_15
2952 #define WM2200_EQL_B4_B_MASK                    0xFFFF  /* EQL_B4_B - [15:0] */
2953 #define WM2200_EQL_B4_B_SHIFT                        0  /* EQL_B4_B - [15:0] */
2954 #define WM2200_EQL_B4_B_WIDTH                       16  /* EQL_B4_B - [15:0] */
2957  * R2319 (0x90F) - EQL_16
2959 #define WM2200_EQL_B4_C_MASK                    0xFFFF  /* EQL_B4_C - [15:0] */
2960 #define WM2200_EQL_B4_C_SHIFT                        0  /* EQL_B4_C - [15:0] */
2961 #define WM2200_EQL_B4_C_WIDTH                       16  /* EQL_B4_C - [15:0] */
2964  * R2320 (0x910) - EQL_17
2966 #define WM2200_EQL_B4_PG_MASK                   0xFFFF  /* EQL_B4_PG - [15:0] */
2967 #define WM2200_EQL_B4_PG_SHIFT                       0  /* EQL_B4_PG - [15:0] */
2968 #define WM2200_EQL_B4_PG_WIDTH                      16  /* EQL_B4_PG - [15:0] */
2971  * R2321 (0x911) - EQL_18
2973 #define WM2200_EQL_B5_A_MASK                    0xFFFF  /* EQL_B5_A - [15:0] */
2974 #define WM2200_EQL_B5_A_SHIFT                        0  /* EQL_B5_A - [15:0] */
2975 #define WM2200_EQL_B5_A_WIDTH                       16  /* EQL_B5_A - [15:0] */
2978  * R2322 (0x912) - EQL_19
2980 #define WM2200_EQL_B5_B_MASK                    0xFFFF  /* EQL_B5_B - [15:0] */
2981 #define WM2200_EQL_B5_B_SHIFT                        0  /* EQL_B5_B - [15:0] */
2982 #define WM2200_EQL_B5_B_WIDTH                       16  /* EQL_B5_B - [15:0] */
2985  * R2323 (0x913) - EQL_20
2987 #define WM2200_EQL_B5_PG_MASK                   0xFFFF  /* EQL_B5_PG - [15:0] */
2988 #define WM2200_EQL_B5_PG_SHIFT                       0  /* EQL_B5_PG - [15:0] */
2989 #define WM2200_EQL_B5_PG_WIDTH                      16  /* EQL_B5_PG - [15:0] */
2992  * R2326 (0x916) - EQR_1
2994 #define WM2200_EQR_B1_GAIN_MASK                 0xF800  /* EQR_B1_GAIN - [15:11] */
2995 #define WM2200_EQR_B1_GAIN_SHIFT                    11  /* EQR_B1_GAIN - [15:11] */
2996 #define WM2200_EQR_B1_GAIN_WIDTH                     5  /* EQR_B1_GAIN - [15:11] */
2997 #define WM2200_EQR_B2_GAIN_MASK                 0x07C0  /* EQR_B2_GAIN - [10:6] */
2998 #define WM2200_EQR_B2_GAIN_SHIFT                     6  /* EQR_B2_GAIN - [10:6] */
2999 #define WM2200_EQR_B2_GAIN_WIDTH                     5  /* EQR_B2_GAIN - [10:6] */
3000 #define WM2200_EQR_B3_GAIN_MASK                 0x003E  /* EQR_B3_GAIN - [5:1] */
3001 #define WM2200_EQR_B3_GAIN_SHIFT                     1  /* EQR_B3_GAIN - [5:1] */
3002 #define WM2200_EQR_B3_GAIN_WIDTH                     5  /* EQR_B3_GAIN - [5:1] */
3006 #define WM2200_EQR_ENA_WIDTH                         1  /* EQR_ENA */
3009  * R2327 (0x917) - EQR_2
3011 #define WM2200_EQR_B4_GAIN_MASK                 0xF800  /* EQR_B4_GAIN - [15:11] */
3012 #define WM2200_EQR_B4_GAIN_SHIFT                    11  /* EQR_B4_GAIN - [15:11] */
3013 #define WM2200_EQR_B4_GAIN_WIDTH                     5  /* EQR_B4_GAIN - [15:11] */
3014 #define WM2200_EQR_B5_GAIN_MASK                 0x07C0  /* EQR_B5_GAIN - [10:6] */
3015 #define WM2200_EQR_B5_GAIN_SHIFT                     6  /* EQR_B5_GAIN - [10:6] */
3016 #define WM2200_EQR_B5_GAIN_WIDTH                     5  /* EQR_B5_GAIN - [10:6] */
3019  * R2328 (0x918) - EQR_3
3021 #define WM2200_EQR_B1_A_MASK                    0xFFFF  /* EQR_B1_A - [15:0] */
3022 #define WM2200_EQR_B1_A_SHIFT                        0  /* EQR_B1_A - [15:0] */
3023 #define WM2200_EQR_B1_A_WIDTH                       16  /* EQR_B1_A - [15:0] */
3026  * R2329 (0x919) - EQR_4
3028 #define WM2200_EQR_B1_B_MASK                    0xFFFF  /* EQR_B1_B - [15:0] */
3029 #define WM2200_EQR_B1_B_SHIFT                        0  /* EQR_B1_B - [15:0] */
3030 #define WM2200_EQR_B1_B_WIDTH                       16  /* EQR_B1_B - [15:0] */
3033  * R2330 (0x91A) - EQR_5
3035 #define WM2200_EQR_B1_PG_MASK                   0xFFFF  /* EQR_B1_PG - [15:0] */
3036 #define WM2200_EQR_B1_PG_SHIFT                       0  /* EQR_B1_PG - [15:0] */
3037 #define WM2200_EQR_B1_PG_WIDTH                      16  /* EQR_B1_PG - [15:0] */
3040  * R2331 (0x91B) - EQR_6
3042 #define WM2200_EQR_B2_A_MASK                    0xFFFF  /* EQR_B2_A - [15:0] */
3043 #define WM2200_EQR_B2_A_SHIFT                        0  /* EQR_B2_A - [15:0] */
3044 #define WM2200_EQR_B2_A_WIDTH                       16  /* EQR_B2_A - [15:0] */
3047  * R2332 (0x91C) - EQR_7
3049 #define WM2200_EQR_B2_B_MASK                    0xFFFF  /* EQR_B2_B - [15:0] */
3050 #define WM2200_EQR_B2_B_SHIFT                        0  /* EQR_B2_B - [15:0] */
3051 #define WM2200_EQR_B2_B_WIDTH                       16  /* EQR_B2_B - [15:0] */
3054  * R2333 (0x91D) - EQR_8
3056 #define WM2200_EQR_B2_C_MASK                    0xFFFF  /* EQR_B2_C - [15:0] */
3057 #define WM2200_EQR_B2_C_SHIFT                        0  /* EQR_B2_C - [15:0] */
3058 #define WM2200_EQR_B2_C_WIDTH                       16  /* EQR_B2_C - [15:0] */
3061  * R2334 (0x91E) - EQR_9
3063 #define WM2200_EQR_B2_PG_MASK                   0xFFFF  /* EQR_B2_PG - [15:0] */
3064 #define WM2200_EQR_B2_PG_SHIFT                       0  /* EQR_B2_PG - [15:0] */
3065 #define WM2200_EQR_B2_PG_WIDTH                      16  /* EQR_B2_PG - [15:0] */
3068  * R2335 (0x91F) - EQR_10
3070 #define WM2200_EQR_B3_A_MASK                    0xFFFF  /* EQR_B3_A - [15:0] */
3071 #define WM2200_EQR_B3_A_SHIFT                        0  /* EQR_B3_A - [15:0] */
3072 #define WM2200_EQR_B3_A_WIDTH                       16  /* EQR_B3_A - [15:0] */
3075  * R2336 (0x920) - EQR_11
3077 #define WM2200_EQR_B3_B_MASK                    0xFFFF  /* EQR_B3_B - [15:0] */
3078 #define WM2200_EQR_B3_B_SHIFT                        0  /* EQR_B3_B - [15:0] */
3079 #define WM2200_EQR_B3_B_WIDTH                       16  /* EQR_B3_B - [15:0] */
3082  * R2337 (0x921) - EQR_12
3084 #define WM2200_EQR_B3_C_MASK                    0xFFFF  /* EQR_B3_C - [15:0] */
3085 #define WM2200_EQR_B3_C_SHIFT                        0  /* EQR_B3_C - [15:0] */
3086 #define WM2200_EQR_B3_C_WIDTH                       16  /* EQR_B3_C - [15:0] */
3089  * R2338 (0x922) - EQR_13
3091 #define WM2200_EQR_B3_PG_MASK                   0xFFFF  /* EQR_B3_PG - [15:0] */
3092 #define WM2200_EQR_B3_PG_SHIFT                       0  /* EQR_B3_PG - [15:0] */
3093 #define WM2200_EQR_B3_PG_WIDTH                      16  /* EQR_B3_PG - [15:0] */
3096  * R2339 (0x923) - EQR_14
3098 #define WM2200_EQR_B4_A_MASK                    0xFFFF  /* EQR_B4_A - [15:0] */
3099 #define WM2200_EQR_B4_A_SHIFT                        0  /* EQR_B4_A - [15:0] */
3100 #define WM2200_EQR_B4_A_WIDTH                       16  /* EQR_B4_A - [15:0] */
3103  * R2340 (0x924) - EQR_15
3105 #define WM2200_EQR_B4_B_MASK                    0xFFFF  /* EQR_B4_B - [15:0] */
3106 #define WM2200_EQR_B4_B_SHIFT                        0  /* EQR_B4_B - [15:0] */
3107 #define WM2200_EQR_B4_B_WIDTH                       16  /* EQR_B4_B - [15:0] */
3110  * R2341 (0x925) - EQR_16
3112 #define WM2200_EQR_B4_C_MASK                    0xFFFF  /* EQR_B4_C - [15:0] */
3113 #define WM2200_EQR_B4_C_SHIFT                        0  /* EQR_B4_C - [15:0] */
3114 #define WM2200_EQR_B4_C_WIDTH                       16  /* EQR_B4_C - [15:0] */
3117  * R2342 (0x926) - EQR_17
3119 #define WM2200_EQR_B4_PG_MASK                   0xFFFF  /* EQR_B4_PG - [15:0] */
3120 #define WM2200_EQR_B4_PG_SHIFT                       0  /* EQR_B4_PG - [15:0] */
3121 #define WM2200_EQR_B4_PG_WIDTH                      16  /* EQR_B4_PG - [15:0] */
3124  * R2343 (0x927) - EQR_18
3126 #define WM2200_EQR_B5_A_MASK                    0xFFFF  /* EQR_B5_A - [15:0] */
3127 #define WM2200_EQR_B5_A_SHIFT                        0  /* EQR_B5_A - [15:0] */
3128 #define WM2200_EQR_B5_A_WIDTH                       16  /* EQR_B5_A - [15:0] */
3131  * R2344 (0x928) - EQR_19
3133 #define WM2200_EQR_B5_B_MASK                    0xFFFF  /* EQR_B5_B - [15:0] */
3134 #define WM2200_EQR_B5_B_SHIFT                        0  /* EQR_B5_B - [15:0] */
3135 #define WM2200_EQR_B5_B_WIDTH                       16  /* EQR_B5_B - [15:0] */
3138  * R2345 (0x929) - EQR_20
3140 #define WM2200_EQR_B5_PG_MASK                   0xFFFF  /* EQR_B5_PG - [15:0] */
3141 #define WM2200_EQR_B5_PG_SHIFT                       0  /* EQR_B5_PG - [15:0] */
3142 #define WM2200_EQR_B5_PG_WIDTH                      16  /* EQR_B5_PG - [15:0] */
3145  * R2366 (0x93E) - HPLPF1_1
3149 #define WM2200_LHPF1_MODE_SHIFT                      1  /* LHPF1_MODE */
3150 #define WM2200_LHPF1_MODE_WIDTH                      1  /* LHPF1_MODE */
3154 #define WM2200_LHPF1_ENA_WIDTH                       1  /* LHPF1_ENA */
3157  * R2367 (0x93F) - HPLPF1_2
3159 #define WM2200_LHPF1_COEFF_MASK                 0xFFFF  /* LHPF1_COEFF - [15:0] */
3160 #define WM2200_LHPF1_COEFF_SHIFT                     0  /* LHPF1_COEFF - [15:0] */
3161 #define WM2200_LHPF1_COEFF_WIDTH                    16  /* LHPF1_COEFF - [15:0] */
3164  * R2370 (0x942) - HPLPF2_1
3168 #define WM2200_LHPF2_MODE_SHIFT                      1  /* LHPF2_MODE */
3169 #define WM2200_LHPF2_MODE_WIDTH                      1  /* LHPF2_MODE */
3173 #define WM2200_LHPF2_ENA_WIDTH                       1  /* LHPF2_ENA */
3176  * R2371 (0x943) - HPLPF2_2
3178 #define WM2200_LHPF2_COEFF_MASK                 0xFFFF  /* LHPF2_COEFF - [15:0] */
3179 #define WM2200_LHPF2_COEFF_SHIFT                     0  /* LHPF2_COEFF - [15:0] */
3180 #define WM2200_LHPF2_COEFF_WIDTH                    16  /* LHPF2_COEFF - [15:0] */
3183  * R2560 (0xA00) - DSP1 Control 1
3188 #define WM2200_DSP1_RW_SEQUENCE_ENA_WIDTH            1  /* DSP1_RW_SEQUENCE_ENA */
3191  * R2562 (0xA02) - DSP1 Control 2
3193 #define WM2200_DSP1_PAGE_BASE_PM_0_MASK         0xFF00  /* DSP1_PAGE_BASE_PM - [15:8] */
3194 #define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT             8  /* DSP1_PAGE_BASE_PM - [15:8] */
3195 #define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH             8  /* DSP1_PAGE_BASE_PM - [15:8] */
3198  * R2563 (0xA03) - DSP1 Control 3
3200 #define WM2200_DSP1_PAGE_BASE_DM_0_MASK         0xFF00  /* DSP1_PAGE_BASE_DM - [15:8] */
3201 #define WM2200_DSP1_PAGE_BASE_DM_0_SHIFT             8  /* DSP1_PAGE_BASE_DM - [15:8] */
3202 #define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH             8  /* DSP1_PAGE_BASE_DM - [15:8] */
3205  * R2564 (0xA04) - DSP1 Control 4
3207 #define WM2200_DSP1_PAGE_BASE_ZM_0_MASK         0xFF00  /* DSP1_PAGE_BASE_ZM - [15:8] */
3208 #define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT             8  /* DSP1_PAGE_BASE_ZM - [15:8] */
3209 #define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH             8  /* DSP1_PAGE_BASE_ZM - [15:8] */
3212  * R2566 (0xA06) - DSP1 Control 5
3214 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - …
3215 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_0 -…
3216 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_0 -…
3219  * R2567 (0xA07) - DSP1 Control 6
3221 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - …
3222 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_1 -…
3223 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_1 -…
3226  * R2568 (0xA08) - DSP1 Control 7
3228 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - …
3229 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_2 -…
3230 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_2 -…
3233  * R2569 (0xA09) - DSP1 Control 8
3235 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - …
3236 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_3 -…
3237 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_3 -…
3240  * R2570 (0xA0A) - DSP1 Control 9
3242 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - …
3243 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_4 -…
3244 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_4 -…
3247  * R2571 (0xA0B) - DSP1 Control 10
3249 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - …
3250 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_5 -…
3251 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_5 -…
3254  * R2572 (0xA0C) - DSP1 Control 11
3256 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - …
3257 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_6 -…
3258 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_6 -…
3261  * R2573 (0xA0D) - DSP1 Control 12
3263 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF  /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - …
3264 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT      0  /* DSP1_START_ADDRESS_WDMA_BUFFER_7 -…
3265 #define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH     14  /* DSP1_START_ADDRESS_WDMA_BUFFER_7 -…
3268  * R2575 (0xA0F) - DSP1 Control 13
3270 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF  /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - …
3271 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT      0  /* DSP1_START_ADDRESS_RDMA_BUFFER_0 -…
3272 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH     14  /* DSP1_START_ADDRESS_RDMA_BUFFER_0 -…
3275  * R2576 (0xA10) - DSP1 Control 14
3277 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF  /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - …
3278 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT      0  /* DSP1_START_ADDRESS_RDMA_BUFFER_1 -…
3279 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH     14  /* DSP1_START_ADDRESS_RDMA_BUFFER_1 -…
3282  * R2577 (0xA11) - DSP1 Control 15
3284 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF  /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - …
3285 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT      0  /* DSP1_START_ADDRESS_RDMA_BUFFER_2 -…
3286 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH     14  /* DSP1_START_ADDRESS_RDMA_BUFFER_2 -…
3289  * R2578 (0xA12) - DSP1 Control 16
3291 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF  /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - …
3292 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT      0  /* DSP1_START_ADDRESS_RDMA_BUFFER_3 -…
3293 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH     14  /* DSP1_START_ADDRESS_RDMA_BUFFER_3 -…
3296  * R2579 (0xA13) - DSP1 Control 17
3298 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF  /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - …
3299 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT      0  /* DSP1_START_ADDRESS_RDMA_BUFFER_4 -…
3300 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH     14  /* DSP1_START_ADDRESS_RDMA_BUFFER_4 -…
3303  * R2580 (0xA14) - DSP1 Control 18
3305 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF  /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - …
3306 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT      0  /* DSP1_START_ADDRESS_RDMA_BUFFER_5 -…
3307 #define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH     14  /* DSP1_START_ADDRESS_RDMA_BUFFER_5 -…
3310  * R2582 (0xA16) - DSP1 Control 19
3312 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK     0x00FF  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3313 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT         0  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3314 #define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH         8  /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3317  * R2583 (0xA17) - DSP1 Control 20
3319 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK    0x00FF  /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3320 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT        0  /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3321 #define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH        8  /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3324  * R2584 (0xA18) - DSP1 Control 21
3326 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK    0x003F  /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3327 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT        0  /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3328 #define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH        6  /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3331  * R2586 (0xA1A) - DSP1 Control 22
3333 #define WM2200_DSP1_DM_SIZE_MASK                0xFFFF  /* DSP1_DM_SIZE - [15:0] */
3334 #define WM2200_DSP1_DM_SIZE_SHIFT                    0  /* DSP1_DM_SIZE - [15:0] */
3335 #define WM2200_DSP1_DM_SIZE_WIDTH                   16  /* DSP1_DM_SIZE - [15:0] */
3338  * R2587 (0xA1B) - DSP1 Control 23
3340 #define WM2200_DSP1_PM_SIZE_MASK                0xFFFF  /* DSP1_PM_SIZE - [15:0] */
3341 #define WM2200_DSP1_PM_SIZE_SHIFT                    0  /* DSP1_PM_SIZE - [15:0] */
3342 #define WM2200_DSP1_PM_SIZE_WIDTH                   16  /* DSP1_PM_SIZE - [15:0] */
3345  * R2588 (0xA1C) - DSP1 Control 24
3347 #define WM2200_DSP1_ZM_SIZE_MASK                0xFFFF  /* DSP1_ZM_SIZE - [15:0] */
3348 #define WM2200_DSP1_ZM_SIZE_SHIFT                    0  /* DSP1_ZM_SIZE - [15:0] */
3349 #define WM2200_DSP1_ZM_SIZE_WIDTH                   16  /* DSP1_ZM_SIZE - [15:0] */
3352  * R2590 (0xA1E) - DSP1 Control 25
3357 #define WM2200_DSP1_PING_FULL_WIDTH                  1  /* DSP1_PING_FULL */
3361 #define WM2200_DSP1_PONG_FULL_WIDTH                  1  /* DSP1_PONG_FULL */
3362 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK   0x00FF  /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3363 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT       0  /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3364 #define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH       8  /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3367  * R2592 (0xA20) - DSP1 Control 26
3369 #define WM2200_DSP1_SCRATCH_0_MASK              0xFFFF  /* DSP1_SCRATCH_0 - [15:0] */
3370 #define WM2200_DSP1_SCRATCH_0_SHIFT                  0  /* DSP1_SCRATCH_0 - [15:0] */
3371 #define WM2200_DSP1_SCRATCH_0_WIDTH                 16  /* DSP1_SCRATCH_0 - [15:0] */
3374  * R2593 (0xA21) - DSP1 Control 27
3376 #define WM2200_DSP1_SCRATCH_1_MASK              0xFFFF  /* DSP1_SCRATCH_1 - [15:0] */
3377 #define WM2200_DSP1_SCRATCH_1_SHIFT                  0  /* DSP1_SCRATCH_1 - [15:0] */
3378 #define WM2200_DSP1_SCRATCH_1_WIDTH                 16  /* DSP1_SCRATCH_1 - [15:0] */
3381  * R2594 (0xA22) - DSP1 Control 28
3383 #define WM2200_DSP1_SCRATCH_2_MASK              0xFFFF  /* DSP1_SCRATCH_2 - [15:0] */
3384 #define WM2200_DSP1_SCRATCH_2_SHIFT                  0  /* DSP1_SCRATCH_2 - [15:0] */
3385 #define WM2200_DSP1_SCRATCH_2_WIDTH                 16  /* DSP1_SCRATCH_2 - [15:0] */
3388  * R2595 (0xA23) - DSP1 Control 29
3390 #define WM2200_DSP1_SCRATCH_3_MASK              0xFFFF  /* DSP1_SCRATCH_3 - [15:0] */
3391 #define WM2200_DSP1_SCRATCH_3_SHIFT                  0  /* DSP1_SCRATCH_3 - [15:0] */
3392 #define WM2200_DSP1_SCRATCH_3_WIDTH                 16  /* DSP1_SCRATCH_3 - [15:0] */
3395  * R2596 (0xA24) - DSP1 Control 30
3400 #define WM2200_DSP1_DBG_CLK_ENA_WIDTH                1  /* DSP1_DBG_CLK_ENA */
3404 #define WM2200_DSP1_SYS_ENA_WIDTH                    1  /* DSP1_SYS_ENA */
3407 #define WM2200_DSP1_CORE_ENA_SHIFT                   1  /* DSP1_CORE_ENA */
3408 #define WM2200_DSP1_CORE_ENA_WIDTH                   1  /* DSP1_CORE_ENA */
3412 #define WM2200_DSP1_START_WIDTH                      1  /* DSP1_START */
3415  * R2598 (0xA26) - DSP1 Control 31
3417 #define WM2200_DSP1_CLK_RATE_MASK               0x0018  /* DSP1_CLK_RATE - [4:3] */
3418 #define WM2200_DSP1_CLK_RATE_SHIFT                   3  /* DSP1_CLK_RATE - [4:3] */
3419 #define WM2200_DSP1_CLK_RATE_WIDTH                   2  /* DSP1_CLK_RATE - [4:3] */
3423 #define WM2200_DSP1_CLK_AVAIL_WIDTH                  1  /* DSP1_CLK_AVAIL */
3424 #define WM2200_DSP1_CLK_REQ_MASK                0x0003  /* DSP1_CLK_REQ - [1:0] */
3425 #define WM2200_DSP1_CLK_REQ_SHIFT                    0  /* DSP1_CLK_REQ - [1:0] */
3426 #define WM2200_DSP1_CLK_REQ_WIDTH                    2  /* DSP1_CLK_REQ - [1:0] */
3429  * R2816 (0xB00) - DSP2 Control 1
3434 #define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH            1  /* DSP2_RW_SEQUENCE_ENA */
3437  * R2818 (0xB02) - DSP2 Control 2
3439 #define WM2200_DSP2_PAGE_BASE_PM_0_MASK         0xFF00  /* DSP2_PAGE_BASE_PM - [15:8] */
3440 #define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT             8  /* DSP2_PAGE_BASE_PM - [15:8] */
3441 #define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH             8  /* DSP2_PAGE_BASE_PM - [15:8] */
3444  * R2819 (0xB03) - DSP2 Control 3
3446 #define WM2200_DSP2_PAGE_BASE_DM_0_MASK         0xFF00  /* DSP2_PAGE_BASE_DM - [15:8] */
3447 #define WM2200_DSP2_PAGE_BASE_DM_0_SHIFT             8  /* DSP2_PAGE_BASE_DM - [15:8] */
3448 #define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH             8  /* DSP2_PAGE_BASE_DM - [15:8] */
3451  * R2820 (0xB04) - DSP2 Control 4
3453 #define WM2200_DSP2_PAGE_BASE_ZM_0_MASK         0xFF00  /* DSP2_PAGE_BASE_ZM - [15:8] */
3454 #define WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT             8  /* DSP2_PAGE_BASE_ZM - [15:8] */
3455 #define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH             8  /* DSP2_PAGE_BASE_ZM - [15:8] */
3458  * R2822 (0xB06) - DSP2 Control 5
3460 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - …
3461 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_0 -…
3462 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_0 -…
3465  * R2823 (0xB07) - DSP2 Control 6
3467 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - …
3468 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_1 -…
3469 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_1 -…
3472  * R2824 (0xB08) - DSP2 Control 7
3474 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - …
3475 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_2 -…
3476 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_2 -…
3479  * R2825 (0xB09) - DSP2 Control 8
3481 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - …
3482 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_3 -…
3483 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_3 -…
3486  * R2826 (0xB0A) - DSP2 Control 9
3488 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - …
3489 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_4 -…
3490 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_4 -…
3493  * R2827 (0xB0B) - DSP2 Control 10
3495 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - …
3496 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_5 -…
3497 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_5 -…
3500  * R2828 (0xB0C) - DSP2 Control 11
3502 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - …
3503 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_6 -…
3504 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_6 -…
3507  * R2829 (0xB0D) - DSP2 Control 12
3509 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF  /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - …
3510 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT      0  /* DSP2_START_ADDRESS_WDMA_BUFFER_7 -…
3511 #define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH     14  /* DSP2_START_ADDRESS_WDMA_BUFFER_7 -…
3514  * R2831 (0xB0F) - DSP2 Control 13
3516 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF  /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - …
3517 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT      0  /* DSP2_START_ADDRESS_RDMA_BUFFER_0 -…
3518 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH     14  /* DSP2_START_ADDRESS_RDMA_BUFFER_0 -…
3521  * R2832 (0xB10) - DSP2 Control 14
3523 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF  /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - …
3524 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT      0  /* DSP2_START_ADDRESS_RDMA_BUFFER_1 -…
3525 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH     14  /* DSP2_START_ADDRESS_RDMA_BUFFER_1 -…
3528  * R2833 (0xB11) - DSP2 Control 15
3530 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF  /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - …
3531 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT      0  /* DSP2_START_ADDRESS_RDMA_BUFFER_2 -…
3532 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH     14  /* DSP2_START_ADDRESS_RDMA_BUFFER_2 -…
3535  * R2834 (0xB12) - DSP2 Control 16
3537 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF  /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - …
3538 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT      0  /* DSP2_START_ADDRESS_RDMA_BUFFER_3 -…
3539 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH     14  /* DSP2_START_ADDRESS_RDMA_BUFFER_3 -…
3542  * R2835 (0xB13) - DSP2 Control 17
3544 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF  /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - …
3545 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT      0  /* DSP2_START_ADDRESS_RDMA_BUFFER_4 -…
3546 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH     14  /* DSP2_START_ADDRESS_RDMA_BUFFER_4 -…
3549  * R2836 (0xB14) - DSP2 Control 18
3551 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF  /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - …
3552 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT      0  /* DSP2_START_ADDRESS_RDMA_BUFFER_5 -…
3553 #define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH     14  /* DSP2_START_ADDRESS_RDMA_BUFFER_5 -…
3556  * R2838 (0xB16) - DSP2 Control 19
3558 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK     0x00FF  /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3559 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT         0  /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3560 #define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH         8  /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3563  * R2839 (0xB17) - DSP2 Control 20
3565 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK    0x00FF  /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3566 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT        0  /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3567 #define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH        8  /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3570  * R2840 (0xB18) - DSP2 Control 21
3572 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK    0x003F  /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3573 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT        0  /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3574 #define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH        6  /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3577  * R2842 (0xB1A) - DSP2 Control 22
3579 #define WM2200_DSP2_DM_SIZE_MASK                0xFFFF  /* DSP2_DM_SIZE - [15:0] */
3580 #define WM2200_DSP2_DM_SIZE_SHIFT                    0  /* DSP2_DM_SIZE - [15:0] */
3581 #define WM2200_DSP2_DM_SIZE_WIDTH                   16  /* DSP2_DM_SIZE - [15:0] */
3584  * R2843 (0xB1B) - DSP2 Control 23
3586 #define WM2200_DSP2_PM_SIZE_MASK                0xFFFF  /* DSP2_PM_SIZE - [15:0] */
3587 #define WM2200_DSP2_PM_SIZE_SHIFT                    0  /* DSP2_PM_SIZE - [15:0] */
3588 #define WM2200_DSP2_PM_SIZE_WIDTH                   16  /* DSP2_PM_SIZE - [15:0] */
3591  * R2844 (0xB1C) - DSP2 Control 24
3593 #define WM2200_DSP2_ZM_SIZE_MASK                0xFFFF  /* DSP2_ZM_SIZE - [15:0] */
3594 #define WM2200_DSP2_ZM_SIZE_SHIFT                    0  /* DSP2_ZM_SIZE - [15:0] */
3595 #define WM2200_DSP2_ZM_SIZE_WIDTH                   16  /* DSP2_ZM_SIZE - [15:0] */
3598  * R2846 (0xB1E) - DSP2 Control 25
3603 #define WM2200_DSP2_PING_FULL_WIDTH                  1  /* DSP2_PING_FULL */
3607 #define WM2200_DSP2_PONG_FULL_WIDTH                  1  /* DSP2_PONG_FULL */
3608 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK   0x00FF  /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3609 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT       0  /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3610 #define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH       8  /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3613  * R2848 (0xB20) - DSP2 Control 26
3615 #define WM2200_DSP2_SCRATCH_0_MASK              0xFFFF  /* DSP2_SCRATCH_0 - [15:0] */
3616 #define WM2200_DSP2_SCRATCH_0_SHIFT                  0  /* DSP2_SCRATCH_0 - [15:0] */
3617 #define WM2200_DSP2_SCRATCH_0_WIDTH                 16  /* DSP2_SCRATCH_0 - [15:0] */
3620  * R2849 (0xB21) - DSP2 Control 27
3622 #define WM2200_DSP2_SCRATCH_1_MASK              0xFFFF  /* DSP2_SCRATCH_1 - [15:0] */
3623 #define WM2200_DSP2_SCRATCH_1_SHIFT                  0  /* DSP2_SCRATCH_1 - [15:0] */
3624 #define WM2200_DSP2_SCRATCH_1_WIDTH                 16  /* DSP2_SCRATCH_1 - [15:0] */
3627  * R2850 (0xB22) - DSP2 Control 28
3629 #define WM2200_DSP2_SCRATCH_2_MASK              0xFFFF  /* DSP2_SCRATCH_2 - [15:0] */
3630 #define WM2200_DSP2_SCRATCH_2_SHIFT                  0  /* DSP2_SCRATCH_2 - [15:0] */
3631 #define WM2200_DSP2_SCRATCH_2_WIDTH                 16  /* DSP2_SCRATCH_2 - [15:0] */
3634  * R2851 (0xB23) - DSP2 Control 29
3636 #define WM2200_DSP2_SCRATCH_3_MASK              0xFFFF  /* DSP2_SCRATCH_3 - [15:0] */
3637 #define WM2200_DSP2_SCRATCH_3_SHIFT                  0  /* DSP2_SCRATCH_3 - [15:0] */
3638 #define WM2200_DSP2_SCRATCH_3_WIDTH                 16  /* DSP2_SCRATCH_3 - [15:0] */
3641  * R2852 (0xB24) - DSP2 Control 30
3646 #define WM2200_DSP2_DBG_CLK_ENA_WIDTH                1  /* DSP2_DBG_CLK_ENA */
3650 #define WM2200_DSP2_SYS_ENA_WIDTH                    1  /* DSP2_SYS_ENA */
3653 #define WM2200_DSP2_CORE_ENA_SHIFT                   1  /* DSP2_CORE_ENA */
3654 #define WM2200_DSP2_CORE_ENA_WIDTH                   1  /* DSP2_CORE_ENA */
3658 #define WM2200_DSP2_START_WIDTH                      1  /* DSP2_START */
3661  * R2854 (0xB26) - DSP2 Control 31
3663 #define WM2200_DSP2_CLK_RATE_MASK               0x0018  /* DSP2_CLK_RATE - [4:3] */
3664 #define WM2200_DSP2_CLK_RATE_SHIFT                   3  /* DSP2_CLK_RATE - [4:3] */
3665 #define WM2200_DSP2_CLK_RATE_WIDTH                   2  /* DSP2_CLK_RATE - [4:3] */
3669 #define WM2200_DSP2_CLK_AVAIL_WIDTH                  1  /* DSP2_CLK_AVAIL */
3670 #define WM2200_DSP2_CLK_REQ_MASK                0x0003  /* DSP2_CLK_REQ - [1:0] */
3671 #define WM2200_DSP2_CLK_REQ_SHIFT                    0  /* DSP2_CLK_REQ - [1:0] */
3672 #define WM2200_DSP2_CLK_REQ_WIDTH                    2  /* DSP2_CLK_REQ - [1:0] */