Lines Matching +full:dsp +full:- +full:aif2 +full:- +full:bclk
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
6 * Copyright 2009-12 Wolfson Microelectronics plc
34 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
35 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
36 { 4, 0x0001 }, /* R4 - VMID Control */
37 { 5, 0x0068 }, /* R5 - Bias Control 1 */
38 { 7, 0x0000 }, /* R7 - Analogue Mixer */
39 { 8, 0x0000 }, /* R8 - Anti Pop Control */
40 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
41 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
42 { 11, 0x0180 }, /* R11 - Power Management */
43 { 12, 0x0000 }, /* R12 - Clock Control 1 */
44 { 13, 0x0038 }, /* R13 - Clock Control 2 */
45 { 14, 0x4000 }, /* R14 - Clock Control 3 */
46 { 16, 0x0000 }, /* R16 - FLL Control 1 */
47 { 17, 0x0200 }, /* R17 - FLL Control 2 */
48 { 18, 0x0000 }, /* R18 - FLL Control 3 */
49 { 19, 0x0204 }, /* R19 - FLL Control 4 */
50 { 20, 0x0000 }, /* R20 - FLL Control 5 */
51 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
52 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
53 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
54 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
55 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
56 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
57 { 29, 0x0000 }, /* R29 - Interrupt Control */
58 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
59 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
60 { 32, 0x09AF }, /* R32 - DRC 1 */
61 { 33, 0x4201 }, /* R33 - DRC 2 */
62 { 34, 0x0000 }, /* R34 - DRC 3 */
63 { 35, 0x0000 }, /* R35 - DRC 4 */
64 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
65 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
66 { 40, 0x0002 }, /* R40 - MW Slave 1 */
67 { 42, 0x0000 }, /* R42 - EQ 1 */
68 { 43, 0x0000 }, /* R43 - EQ 2 */
69 { 44, 0x0FCA }, /* R44 - EQ 3 */
70 { 45, 0x0400 }, /* R45 - EQ 4 */
71 { 46, 0x00B8 }, /* R46 - EQ 5 */
72 { 47, 0x1EB5 }, /* R47 - EQ 6 */
73 { 48, 0xF145 }, /* R48 - EQ 7 */
74 { 49, 0x0B75 }, /* R49 - EQ 8 */
75 { 50, 0x01C5 }, /* R50 - EQ 9 */
76 { 51, 0x169E }, /* R51 - EQ 10 */
77 { 52, 0xF829 }, /* R52 - EQ 11 */
78 { 53, 0x07AD }, /* R53 - EQ 12 */
79 { 54, 0x1103 }, /* R54 - EQ 13 */
80 { 55, 0x1C58 }, /* R55 - EQ 14 */
81 { 56, 0xF373 }, /* R56 - EQ 15 */
82 { 57, 0x0A54 }, /* R57 - EQ 16 */
83 { 58, 0x0558 }, /* R58 - EQ 17 */
84 { 59, 0x0564 }, /* R59 - EQ 18 */
85 { 60, 0x0559 }, /* R60 - EQ 19 */
86 { 61, 0x4000 }, /* R61 - EQ 20 */
155 int bclk; member
243 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
244 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
245 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
253 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
255 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
257 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
258 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
259 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
347 ucontrol->value.enumerated.item[0] = 1; in speaker_mode_get()
349 ucontrol->value.enumerated.item[0] = 0; in speaker_mode_get()
357 * We also have some special anti-pop controls dependent on speaker
368 if (ucontrol->value.enumerated.item[0] == in speaker_mode_put()
374 return -EINVAL; in speaker_mode_put()
376 if (ucontrol->value.enumerated.item[0]) { in speaker_mode_put()
482 return -EINVAL; in fll_factors()
485 fll_div->fll_clk_ref_div = div / 2; in fll_factors()
492 /* Fvco should be 90-100MHz; don't check the upper bound */ in fll_factors()
501 return -EINVAL; in fll_factors()
504 fll_div->fll_outdiv = div; in fll_factors()
511 fll_div->fll_fratio = fll_fratios[i].fll_fratio; in fll_factors()
518 return -EINVAL; in fll_factors()
524 fll_div->n = Ndiv; in fll_factors()
528 /* Calculate fractional part - scale up so we can round. */ in fll_factors()
539 fll_div->k = K / 10; in fll_factors()
542 fll_div->n, fll_div->k, in fll_factors()
543 fll_div->fll_fratio, fll_div->fll_outdiv, in fll_factors()
544 fll_div->fll_clk_ref_div); in fll_factors()
559 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout) in wm9081_set_fll()
564 dev_dbg(component->dev, "FLL disabled\n"); in wm9081_set_fll()
565 wm9081->fll_fref = 0; in wm9081_set_fll()
566 wm9081->fll_fout = 0; in wm9081_set_fll()
584 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); in wm9081_set_fll()
585 return -EINVAL; in wm9081_set_fll()
632 dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); in wm9081_set_fll()
634 wm9081->fll_fref = Fref; in wm9081_set_fll()
635 wm9081->fll_fout = Fout; in wm9081_set_fll()
649 switch (wm9081->sysclk_source) { in configure_clock()
651 if (wm9081->mclk_rate > 12225000) { in configure_clock()
653 wm9081->sysclk_rate = wm9081->mclk_rate / 2; in configure_clock()
655 wm9081->sysclk_rate = wm9081->mclk_rate; in configure_clock()
662 * gives us a suitable DAC configuration, plus BCLK. in configure_clock()
668 if (wm9081->master && wm9081->bclk) { in configure_clock()
669 /* Make sure we can generate CLK_SYS and BCLK in configure_clock()
673 target = wm9081->fs * clk_sys_rates[i].ratio; in configure_clock()
675 if (target >= wm9081->bclk && in configure_clock()
681 return -EINVAL; in configure_clock()
683 } else if (wm9081->fs) { in configure_clock()
686 * wm9081->fs; in configure_clock()
692 return -EINVAL; in configure_clock()
699 wm9081->mclk_rate, new_sysclk); in configure_clock()
701 wm9081->sysclk_rate = new_sysclk; in configure_clock()
706 wm9081->sysclk_rate = wm9081->mclk_rate; in configure_clock()
711 return -EINVAL; in configure_clock()
728 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate); in configure_clock()
736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in clk_sys_event()
740 switch (wm9081->sysclk_source) { in clk_sys_event()
742 dev_dbg(component->dev, "Using %dHz MCLK\n", wm9081->mclk_rate); in clk_sys_event()
745 dev_dbg(component->dev, "Using %dHz MCLK with FLL\n", in clk_sys_event()
746 wm9081->mclk_rate); in clk_sys_event()
749 dev_err(component->dev, "System clock not configured\n"); in clk_sys_event()
750 return -EINVAL; in clk_sys_event()
841 regcache_cache_only(wm9081->regmap, false); in wm9081_set_bias_level()
842 regcache_sync(wm9081->regmap); in wm9081_set_bias_level()
896 regcache_cache_only(wm9081->regmap, true); in wm9081_set_bias_level()
906 struct snd_soc_component *component = dai->component; in wm9081_set_dai_fmt()
908 unsigned int aif2 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_2); in wm9081_set_dai_fmt() local
910 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV | in wm9081_set_dai_fmt()
915 wm9081->master = 0; in wm9081_set_dai_fmt()
918 aif2 |= WM9081_LRCLK_DIR; in wm9081_set_dai_fmt()
919 wm9081->master = 1; in wm9081_set_dai_fmt()
922 aif2 |= WM9081_BCLK_DIR; in wm9081_set_dai_fmt()
923 wm9081->master = 1; in wm9081_set_dai_fmt()
926 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR; in wm9081_set_dai_fmt()
927 wm9081->master = 1; in wm9081_set_dai_fmt()
930 return -EINVAL; in wm9081_set_dai_fmt()
935 aif2 |= WM9081_AIF_LRCLK_INV; in wm9081_set_dai_fmt()
938 aif2 |= 0x3; in wm9081_set_dai_fmt()
941 aif2 |= 0x2; in wm9081_set_dai_fmt()
946 aif2 |= 0x1; in wm9081_set_dai_fmt()
949 return -EINVAL; in wm9081_set_dai_fmt()
955 /* frame inversion not valid for DSP modes */ in wm9081_set_dai_fmt()
960 aif2 |= WM9081_AIF_BCLK_INV; in wm9081_set_dai_fmt()
963 return -EINVAL; in wm9081_set_dai_fmt()
974 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV; in wm9081_set_dai_fmt()
977 aif2 |= WM9081_AIF_BCLK_INV; in wm9081_set_dai_fmt()
980 aif2 |= WM9081_AIF_LRCLK_INV; in wm9081_set_dai_fmt()
983 return -EINVAL; in wm9081_set_dai_fmt()
987 return -EINVAL; in wm9081_set_dai_fmt()
990 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2); in wm9081_set_dai_fmt()
999 struct snd_soc_component *component = dai->component; in wm9081_hw_params()
1002 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4; in wm9081_hw_params() local
1009 aif2 = snd_soc_component_read32(component, WM9081_AUDIO_INTERFACE_2); in wm9081_hw_params()
1010 aif2 &= ~WM9081_AIF_WL_MASK; in wm9081_hw_params()
1018 wm9081->fs = params_rate(params); in wm9081_hw_params()
1020 if (wm9081->tdm_width) { in wm9081_hw_params()
1021 /* If TDM is set up then that fixes our BCLK. */ in wm9081_hw_params()
1025 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots; in wm9081_hw_params()
1027 /* Otherwise work out a BCLK from the sample size */ in wm9081_hw_params()
1028 wm9081->bclk = 2 * wm9081->fs; in wm9081_hw_params()
1032 wm9081->bclk *= 16; in wm9081_hw_params()
1035 wm9081->bclk *= 20; in wm9081_hw_params()
1036 aif2 |= 0x4; in wm9081_hw_params()
1039 wm9081->bclk *= 24; in wm9081_hw_params()
1040 aif2 |= 0x8; in wm9081_hw_params()
1043 wm9081->bclk *= 32; in wm9081_hw_params()
1044 aif2 |= 0xc; in wm9081_hw_params()
1047 return -EINVAL; in wm9081_hw_params()
1051 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm9081->bclk); in wm9081_hw_params()
1059 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio) in wm9081_hw_params()
1060 - wm9081->fs); in wm9081_hw_params()
1062 cur_val = abs((wm9081->sysclk_rate / in wm9081_hw_params()
1063 clk_sys_rates[i].ratio) - wm9081->fs); in wm9081_hw_params()
1069 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", in wm9081_hw_params()
1076 best_val = abs(wm9081->fs - sample_rates[0].rate); in wm9081_hw_params()
1079 cur_val = abs(wm9081->fs - sample_rates[i].rate); in wm9081_hw_params()
1085 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", in wm9081_hw_params()
1094 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div) in wm9081_hw_params()
1095 - wm9081->bclk; in wm9081_hw_params()
1103 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div; in wm9081_hw_params()
1104 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", in wm9081_hw_params()
1105 bclk_divs[best].div, wm9081->bclk); in wm9081_hw_params()
1108 /* LRCLK is a simple fraction of BCLK */ in wm9081_hw_params()
1109 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs); in wm9081_hw_params()
1110 aif4 |= wm9081->bclk / wm9081->fs; in wm9081_hw_params()
1113 if (wm9081->pdata.num_retune_configs) { in wm9081_hw_params()
1114 struct wm9081_pdata *pdata = &wm9081->pdata; in wm9081_hw_params()
1119 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs); in wm9081_hw_params()
1120 for (i = 0; i < pdata->num_retune_configs; i++) { in wm9081_hw_params()
1121 cur_val = abs(pdata->retune_configs[i].rate - in wm9081_hw_params()
1122 wm9081->fs); in wm9081_hw_params()
1128 s = &pdata->retune_configs[best]; in wm9081_hw_params()
1130 dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n", in wm9081_hw_params()
1131 s->name, s->rate); in wm9081_hw_params()
1139 for (i = 1; i < ARRAY_SIZE(s->config); i++) in wm9081_hw_params()
1140 snd_soc_component_write(component, WM9081_EQ_1 + i, s->config[i]); in wm9081_hw_params()
1142 eq1 |= (s->config[0] & ~WM9081_EQ_ENA); in wm9081_hw_params()
1147 snd_soc_component_write(component, WM9081_AUDIO_INTERFACE_2, aif2); in wm9081_hw_params()
1156 struct snd_soc_component *component = codec_dai->component; in wm9081_digital_mute()
1179 wm9081->sysclk_source = clk_id; in wm9081_set_sysclk()
1180 wm9081->mclk_rate = freq; in wm9081_set_sysclk()
1184 return -EINVAL; in wm9081_set_sysclk()
1193 struct snd_soc_component *component = dai->component; in wm9081_set_tdm_slot()
1200 return -EINVAL; in wm9081_set_tdm_slot()
1202 wm9081->tdm_width = slot_width; in wm9081_set_tdm_slot()
1207 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT; in wm9081_set_tdm_slot()
1222 return -EINVAL; in wm9081_set_tdm_slot()
1247 .name = "wm9081-hifi",
1268 if (!wm9081->pdata.num_retune_configs) { in wm9081_probe()
1269 dev_dbg(component->dev, in wm9081_probe()
1312 wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv), in wm9081_i2c_probe()
1315 return -ENOMEM; in wm9081_i2c_probe()
1319 wm9081->regmap = devm_regmap_init_i2c(i2c, &wm9081_regmap); in wm9081_i2c_probe()
1320 if (IS_ERR(wm9081->regmap)) { in wm9081_i2c_probe()
1321 ret = PTR_ERR(wm9081->regmap); in wm9081_i2c_probe()
1322 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); in wm9081_i2c_probe()
1326 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, ®); in wm9081_i2c_probe()
1328 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret); in wm9081_i2c_probe()
1332 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg); in wm9081_i2c_probe()
1333 return -EINVAL; in wm9081_i2c_probe()
1336 ret = wm9081_reset(wm9081->regmap); in wm9081_i2c_probe()
1338 dev_err(&i2c->dev, "Failed to issue reset\n"); in wm9081_i2c_probe()
1342 if (dev_get_platdata(&i2c->dev)) in wm9081_i2c_probe()
1343 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev), in wm9081_i2c_probe()
1344 sizeof(wm9081->pdata)); in wm9081_i2c_probe()
1347 if (wm9081->pdata.irq_high) in wm9081_i2c_probe()
1349 if (!wm9081->pdata.irq_cmos) in wm9081_i2c_probe()
1351 regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL, in wm9081_i2c_probe()
1354 regcache_cache_only(wm9081->regmap, true); in wm9081_i2c_probe()
1356 ret = devm_snd_soc_register_component(&i2c->dev, in wm9081_i2c_probe()