Lines Matching +full:rx +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
25 #include "imx-pcm.h"
84 * @rxclk: rx clock sources for capture
86 * @sysclk: system clock for rx clock rate measurement
116 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_dpll_lock()
117 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_dpll_lock()
123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", in spdif_irq_dpll_lock()
126 spdif_priv->dpll_locked = locked ? true : false; in spdif_irq_dpll_lock()
132 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_sym_error()
133 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_sym_error()
135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); in spdif_irq_sym_error()
138 if (!spdif_priv->dpll_locked) in spdif_irq_sym_error()
145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uqrx_full() local
146 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uqrx_full()
147 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uqrx_full()
152 pos = &ctrl->upos; in spdif_irq_uqrx_full()
157 pos = &ctrl->qpos; in spdif_irq_uqrx_full()
162 dev_err(&pdev->dev, "unsupported channel name\n"); in spdif_irq_uqrx_full()
166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); in spdif_irq_uqrx_full()
171 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); in spdif_irq_uqrx_full()
176 ctrl->subcode[*pos++] = val >> 16; in spdif_irq_uqrx_full()
177 ctrl->subcode[*pos++] = val >> 8; in spdif_irq_uqrx_full()
178 ctrl->subcode[*pos++] = val; in spdif_irq_uqrx_full()
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_sync() local
185 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_sync()
187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); in spdif_irq_uq_sync()
190 if (ctrl->qpos == 0) in spdif_irq_uq_sync()
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; in spdif_irq_uq_sync()
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_err() local
201 struct regmap *regmap = spdif_priv->regmap; in spdif_irq_uq_err()
202 struct platform_device *pdev = spdif_priv->pdev; in spdif_irq_uq_err()
205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); in spdif_irq_uq_err()
212 ctrl->ready_buf = 0; in spdif_irq_uq_err()
213 ctrl->upos = 0; in spdif_irq_uq_err()
214 ctrl->qpos = 0; in spdif_irq_uq_err()
220 struct regmap *regmap = spdif_priv->regmap; in spdif_intr_status_clear()
234 struct platform_device *pdev = spdif_priv->pdev; in spdif_isr()
243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); in spdif_isr()
246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); in spdif_isr()
249 dev_dbg(&pdev->dev, "isr: cstatus new\n"); in spdif_isr()
252 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); in spdif_isr()
258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); in spdif_isr()
264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); in spdif_isr()
270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); in spdif_isr()
279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); in spdif_isr()
282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); in spdif_isr()
289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); in spdif_isr()
291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ in spdif_isr()
293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); in spdif_isr()
300 struct regmap *regmap = spdif_priv->regmap; in spdif_softreset()
313 } while ((val & SCR_SOFT_RESET) && cycle--); in spdif_softreset()
322 return -EBUSY; in spdif_softreset()
325 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, in spdif_set_cstatus() argument
328 ctrl->ch_status[3] &= ~mask; in spdif_set_cstatus()
329 ctrl->ch_status[3] |= cstatus & mask; in spdif_set_cstatus()
334 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_write_channel_status() local
335 struct regmap *regmap = spdif_priv->regmap; in spdif_write_channel_status()
336 struct platform_device *pdev = spdif_priv->pdev; in spdif_write_channel_status()
339 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | in spdif_write_channel_status()
340 (bitrev8(ctrl->ch_status[1]) << 8) | in spdif_write_channel_status()
341 bitrev8(ctrl->ch_status[2]); in spdif_write_channel_status()
344 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); in spdif_write_channel_status()
346 ch_status = bitrev8(ctrl->ch_status[3]) << 16; in spdif_write_channel_status()
349 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); in spdif_write_channel_status()
352 /* Set SPDIF PhaseConfig register for rx clock */
356 struct regmap *regmap = spdif_priv->regmap; in spdif_set_rx_clksrc()
357 u8 clksrc = spdif_priv->rxclk_src; in spdif_set_rx_clksrc()
360 return -EINVAL; in spdif_set_rx_clksrc()
372 struct snd_soc_pcm_runtime *rtd = substream->private_data; in spdif_set_sample_rate()
373 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); in spdif_set_sample_rate()
374 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_set_sample_rate() local
375 struct regmap *regmap = spdif_priv->regmap; in spdif_set_sample_rate()
376 struct platform_device *pdev = spdif_priv->pdev; in spdif_set_sample_rate()
404 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); in spdif_set_sample_rate()
405 return -EINVAL; in spdif_set_sample_rate()
408 clk = spdif_priv->txclk_src[rate]; in spdif_set_sample_rate()
410 dev_err(&pdev->dev, "tx clock source is out of range\n"); in spdif_set_sample_rate()
411 return -EINVAL; in spdif_set_sample_rate()
414 txclk_df = spdif_priv->txclk_df[rate]; in spdif_set_sample_rate()
416 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); in spdif_set_sample_rate()
417 return -EINVAL; in spdif_set_sample_rate()
420 sysclk_df = spdif_priv->sysclk_df[rate]; in spdif_set_sample_rate()
427 ret = clk_set_rate(spdif_priv->txclk[rate], in spdif_set_sample_rate()
430 dev_err(&pdev->dev, "failed to set tx clock rate\n"); in spdif_set_sample_rate()
435 dev_dbg(&pdev->dev, "expected clock rate = %d\n", in spdif_set_sample_rate()
437 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", in spdif_set_sample_rate()
438 clk_get_rate(spdif_priv->txclk[rate])); in spdif_set_sample_rate()
441 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); in spdif_set_sample_rate()
450 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", in spdif_set_sample_rate()
451 spdif_priv->txrate[rate], sample_rate); in spdif_set_sample_rate()
459 struct snd_soc_pcm_runtime *rtd = substream->private_data; in fsl_spdif_startup()
460 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); in fsl_spdif_startup()
461 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_startup()
462 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_startup()
468 if (!cpu_dai->active) { in fsl_spdif_startup()
469 ret = clk_prepare_enable(spdif_priv->coreclk); in fsl_spdif_startup()
471 dev_err(&pdev->dev, "failed to enable core clock\n"); in fsl_spdif_startup()
475 if (!IS_ERR(spdif_priv->spbaclk)) { in fsl_spdif_startup()
476 ret = clk_prepare_enable(spdif_priv->spbaclk); in fsl_spdif_startup()
478 dev_err(&pdev->dev, "failed to enable spba clock\n"); in fsl_spdif_startup()
485 dev_err(&pdev->dev, "failed to soft reset\n"); in fsl_spdif_startup()
493 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_startup()
501 ret = clk_prepare_enable(spdif_priv->txclk[i]); in fsl_spdif_startup()
509 ret = clk_prepare_enable(spdif_priv->rxclk); in fsl_spdif_startup()
521 for (i--; i >= 0; i--) in fsl_spdif_startup()
522 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_startup()
524 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_startup()
525 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_startup()
527 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_startup()
535 struct snd_soc_pcm_runtime *rtd = substream->private_data; in fsl_spdif_shutdown()
536 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); in fsl_spdif_shutdown()
537 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_shutdown()
540 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_shutdown()
546 clk_disable_unprepare(spdif_priv->txclk[i]); in fsl_spdif_shutdown()
551 clk_disable_unprepare(spdif_priv->rxclk); in fsl_spdif_shutdown()
555 /* Power down SPDIF module only if tx&rx are both inactive */ in fsl_spdif_shutdown()
556 if (!cpu_dai->active) { in fsl_spdif_shutdown()
560 if (!IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_shutdown()
561 clk_disable_unprepare(spdif_priv->spbaclk); in fsl_spdif_shutdown()
562 clk_disable_unprepare(spdif_priv->coreclk); in fsl_spdif_shutdown()
570 struct snd_soc_pcm_runtime *rtd = substream->private_data; in fsl_spdif_hw_params()
571 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); in fsl_spdif_hw_params()
572 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_hw_params() local
573 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_hw_params()
577 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in fsl_spdif_hw_params()
580 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", in fsl_spdif_hw_params()
584 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, in fsl_spdif_hw_params()
588 /* Setup rx clock source */ in fsl_spdif_hw_params()
598 struct snd_soc_pcm_runtime *rtd = substream->private_data; in fsl_spdif_trigger()
599 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); in fsl_spdif_trigger()
600 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_trigger()
601 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; in fsl_spdif_trigger()
619 return -EINVAL; in fsl_spdif_trigger()
646 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; in fsl_spdif_info()
647 uinfo->count = 1; in fsl_spdif_info()
657 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_get() local
659 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; in fsl_spdif_pb_get()
660 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; in fsl_spdif_pb_get()
661 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; in fsl_spdif_pb_get()
662 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; in fsl_spdif_pb_get()
672 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_put() local
674 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; in fsl_spdif_pb_put()
675 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; in fsl_spdif_pb_put()
676 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; in fsl_spdif_pb_put()
677 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; in fsl_spdif_pb_put()
690 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_capture_get()
695 return -EAGAIN; in fsl_spdif_capture_get()
698 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
699 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
700 ucontrol->value.iec958.status[2] = cstatus & 0xFF; in fsl_spdif_capture_get()
703 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; in fsl_spdif_capture_get()
704 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; in fsl_spdif_capture_get()
705 ucontrol->value.iec958.status[5] = cstatus & 0xFF; in fsl_spdif_capture_get()
722 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_subcode_get() local
724 int ret = -EAGAIN; in fsl_spdif_subcode_get()
726 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
727 if (ctrl->ready_buf) { in fsl_spdif_subcode_get()
728 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; in fsl_spdif_subcode_get()
729 memcpy(&ucontrol->value.iec958.subcode[0], in fsl_spdif_subcode_get()
730 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); in fsl_spdif_subcode_get()
733 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
738 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */
742 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_spdif_qinfo()
743 uinfo->count = SPDIF_QSUB_SIZE; in fsl_spdif_qinfo()
754 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_qget() local
756 int ret = -EAGAIN; in fsl_spdif_qget()
758 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
759 if (ctrl->ready_buf) { in fsl_spdif_qget()
760 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; in fsl_spdif_qget()
761 memcpy(&ucontrol->value.bytes.data[0], in fsl_spdif_qget()
762 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); in fsl_spdif_qget()
765 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
774 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in fsl_spdif_vbit_info()
775 uinfo->count = 1; in fsl_spdif_vbit_info()
776 uinfo->value.integer.min = 0; in fsl_spdif_vbit_info()
777 uinfo->value.integer.max = 1; in fsl_spdif_vbit_info()
788 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_vbit_get()
792 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; in fsl_spdif_vbit_get()
802 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in fsl_spdif_rxrate_info()
803 uinfo->count = 1; in fsl_spdif_rxrate_info()
804 uinfo->value.integer.min = 16000; in fsl_spdif_rxrate_info()
805 uinfo->value.integer.max = 96000; in fsl_spdif_rxrate_info()
814 /* Get RX data clock rate given the SPDIF bus_clk */
818 struct regmap *regmap = spdif_priv->regmap; in spdif_get_rxclk_rate()
819 struct platform_device *pdev = spdif_priv->pdev; in spdif_get_rxclk_rate()
831 busclk_freq = clk_get_rate(spdif_priv->sysclk); in spdif_get_rxclk_rate()
838 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); in spdif_get_rxclk_rate()
839 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); in spdif_get_rxclk_rate()
840 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); in spdif_get_rxclk_rate()
857 if (spdif_priv->dpll_locked) in fsl_spdif_rxrate_get()
860 ucontrol->value.integer.value[0] = rate; in fsl_spdif_rxrate_get()
869 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; in fsl_spdif_usync_info()
870 uinfo->count = 1; in fsl_spdif_usync_info()
871 uinfo->value.integer.min = 0; in fsl_spdif_usync_info()
872 uinfo->value.integer.max = 1; in fsl_spdif_usync_info()
880 * 0 Non-CD data
887 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_get()
891 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; in fsl_spdif_usync_get()
899 * 0 Non-CD data
906 struct regmap *regmap = spdif_priv->regmap; in fsl_spdif_usync_put()
907 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; in fsl_spdif_usync_put()
946 .name = "IEC958 Q-subcode Capture Default",
955 .name = "IEC958 V-Bit Errors",
964 .name = "RX Sample Rate",
987 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, in fsl_spdif_dai_probe()
988 &spdif_private->dma_params_rx); in fsl_spdif_dai_probe()
998 .stream_name = "CPU-Playback",
1005 .stream_name = "CPU-Capture",
1015 .name = "fsl-spdif",
1110 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); in fsl_spdif_txclk_caldiv()
1133 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1134 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1135 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1139 sub = (u64)(arate - rate[index]) * 100000; in fsl_spdif_txclk_caldiv()
1144 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1145 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1146 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1149 sub = (u64)(rate[index] - arate) * 100000; in fsl_spdif_txclk_caldiv()
1154 spdif_priv->txclk_df[index] = txclk_df; in fsl_spdif_txclk_caldiv()
1155 spdif_priv->sysclk_df[index] = sysclk_df; in fsl_spdif_txclk_caldiv()
1156 spdif_priv->txrate[index] = arate; in fsl_spdif_txclk_caldiv()
1169 struct platform_device *pdev = spdif_priv->pdev; in fsl_spdif_probe_txclk()
1170 struct device *dev = &pdev->dev; in fsl_spdif_probe_txclk()
1178 clk = devm_clk_get(&pdev->dev, tmp); in fsl_spdif_probe_txclk()
1192 spdif_priv->txclk[index] = clk; in fsl_spdif_probe_txclk()
1193 spdif_priv->txclk_src[index] = i; in fsl_spdif_probe_txclk()
1200 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", in fsl_spdif_probe_txclk()
1201 spdif_priv->txclk_src[index], rate[index]); in fsl_spdif_probe_txclk()
1202 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", in fsl_spdif_probe_txclk()
1203 spdif_priv->txclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1204 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) in fsl_spdif_probe_txclk()
1205 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", in fsl_spdif_probe_txclk()
1206 spdif_priv->sysclk_df[index], rate[index]); in fsl_spdif_probe_txclk()
1207 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", in fsl_spdif_probe_txclk()
1208 rate[index], spdif_priv->txrate[index]); in fsl_spdif_probe_txclk()
1215 struct device_node *np = pdev->dev.of_node; in fsl_spdif_probe()
1217 struct spdif_mixer_control *ctrl; in fsl_spdif_probe() local
1223 return -ENODEV; in fsl_spdif_probe()
1225 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); in fsl_spdif_probe()
1227 return -ENOMEM; in fsl_spdif_probe()
1229 spdif_priv->pdev = pdev; in fsl_spdif_probe()
1232 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); in fsl_spdif_probe()
1233 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); in fsl_spdif_probe()
1237 regs = devm_ioremap_resource(&pdev->dev, res); in fsl_spdif_probe()
1241 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, in fsl_spdif_probe()
1243 if (IS_ERR(spdif_priv->regmap)) { in fsl_spdif_probe()
1244 dev_err(&pdev->dev, "regmap init failed\n"); in fsl_spdif_probe()
1245 return PTR_ERR(spdif_priv->regmap); in fsl_spdif_probe()
1250 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); in fsl_spdif_probe()
1254 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, in fsl_spdif_probe()
1255 dev_name(&pdev->dev), spdif_priv); in fsl_spdif_probe()
1257 dev_err(&pdev->dev, "could not claim irq %u\n", irq); in fsl_spdif_probe()
1261 /* Get system clock for rx clock rate calculation */ in fsl_spdif_probe()
1262 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); in fsl_spdif_probe()
1263 if (IS_ERR(spdif_priv->sysclk)) { in fsl_spdif_probe()
1264 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); in fsl_spdif_probe()
1265 return PTR_ERR(spdif_priv->sysclk); in fsl_spdif_probe()
1269 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_spdif_probe()
1270 if (IS_ERR(spdif_priv->coreclk)) { in fsl_spdif_probe()
1271 dev_err(&pdev->dev, "no core clock in devicetree\n"); in fsl_spdif_probe()
1272 return PTR_ERR(spdif_priv->coreclk); in fsl_spdif_probe()
1275 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); in fsl_spdif_probe()
1276 if (IS_ERR(spdif_priv->spbaclk)) in fsl_spdif_probe()
1277 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); in fsl_spdif_probe()
1279 /* Select clock source for rx/tx clock */ in fsl_spdif_probe()
1280 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); in fsl_spdif_probe()
1281 if (IS_ERR(spdif_priv->rxclk)) { in fsl_spdif_probe()
1282 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); in fsl_spdif_probe()
1283 return PTR_ERR(spdif_priv->rxclk); in fsl_spdif_probe()
1285 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; in fsl_spdif_probe()
1294 ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_probe()
1295 spin_lock_init(&ctrl->ctl_lock); in fsl_spdif_probe()
1298 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | in fsl_spdif_probe()
1300 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; in fsl_spdif_probe()
1301 ctrl->ch_status[2] = 0x00; in fsl_spdif_probe()
1302 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | in fsl_spdif_probe()
1305 spdif_priv->dpll_locked = false; in fsl_spdif_probe()
1307 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; in fsl_spdif_probe()
1308 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; in fsl_spdif_probe()
1309 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; in fsl_spdif_probe()
1310 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; in fsl_spdif_probe()
1313 dev_set_drvdata(&pdev->dev, spdif_priv); in fsl_spdif_probe()
1315 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, in fsl_spdif_probe()
1316 &spdif_priv->cpu_dai_drv, 1); in fsl_spdif_probe()
1318 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); in fsl_spdif_probe()
1324 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); in fsl_spdif_probe()
1334 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_suspend()
1335 &spdif_priv->regcache_srpc); in fsl_spdif_suspend()
1337 regcache_cache_only(spdif_priv->regmap, true); in fsl_spdif_suspend()
1338 regcache_mark_dirty(spdif_priv->regmap); in fsl_spdif_suspend()
1347 regcache_cache_only(spdif_priv->regmap, false); in fsl_spdif_resume()
1349 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, in fsl_spdif_resume()
1351 spdif_priv->regcache_srpc); in fsl_spdif_resume()
1353 return regcache_sync(spdif_priv->regmap); in fsl_spdif_resume()
1362 { .compatible = "fsl,imx35-spdif", },
1363 { .compatible = "fsl,vf610-spdif", },
1370 .name = "fsl-spdif-dai",
1382 MODULE_ALIAS("platform:fsl-spdif-dai");