Lines Matching full:gating

260 	/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */  in hsw_set_dsp_D3()
265 	/* enable power gating and switch off DRAM & IRAM blocks */  in hsw_set_dsp_D3()
287 	/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */  in hsw_set_dsp_D3()
316 	/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */  in hsw_set_dsp_D0()
352 	/* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */  in hsw_set_dsp_D0()
360 	/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */  in hsw_set_dsp_D0()
372 	/* set default power gating control, enable power gating control for all blocks. that is,  in hsw_set_dsp_D0()
554 	/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */  in hsw_block_enable()
566 	/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */  in hsw_block_enable()
590 	/* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */  in hsw_block_disable()
605 	/* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */  in hsw_block_disable()
684 	/* set default power gating control, enable power gating control for all blocks. that is,  in hsw_init()