Lines Matching +full:user +full:- +full:level

2  * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver
5  * Copyright (C) 2011 - NVIDIA, Inc.
8  * Copyright (c) 2008-2009, NVIDIA Corporation
22  * 02110-1301 USA
68 /* Transmit user Data */
89 /* Interrupt when RX user FIFO attention level is reached */
92 /* Interrupt when TX user FIFO attention level is reached */
95 /* Interrupt when RX data FIFO attention level is reached */
98 /* Interrupt when TX data FIFO attention level is reached */
166  * TX User data FIFO busy.
168  * there's data in the TX user FIFO.  This bit is deassert when either,
170  * (b) there's no data left in the TX user FIFO.
183 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
193 /* RX User Data Valid flag:  1=valid IU detected, 0 = no IU detected. */
197  * RX User FIFO Status:
198  * 1=attention level reached, 0=attention level not reached.
203  * TX User FIFO Status:
204  * 1=attention level reached, 0=attention level not reached.
210  * 1=attention level reached, 0=attention level not reached.
216  * 1=attention level reached, 0=attention level not reached.
224  * bi-phase period.
229 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
233  * Manual data strobe time within the bi-phase clock period (in terms of
234  * the number of over-sampling clocks).
240  * Manual SPDIFIN bi-phase clock period (in terms of the number of
241  * over-sampling clocks).
248 /* Clear Receiver User FIFO (RX USR.FIFO) */
256 /* RU FIFO attention level */
273 /* Clear Transmitter User FIFO (TX USR.FIFO) */
276 /* TU FIFO attention level */
301 /* RU FIFO attention level */
321 /* TU FIFO attention level */
342  * 16-bit        (BIT_MODE=00, PACK=0)
343  * 20-bit        (BIT_MODE=01, PACK=0)
344  * 24-bit        (BIT_MODE=10, PACK=0)
346  * 16-bit packed (BIT_MODE=00, PACK=1)
382  * 16-bit        (BIT_MODE=00, PACK=0)
383  * 20-bit        (BIT_MODE=01, PACK=0)
384  * 24-bit        (BIT_MODE=10, PACK=0)
386  * 16-bit packed (BIT_MODE=00, PACK=1)
388  * Bits 31:24 are common to all modes except 16-bit packed
431  * The 6-word receive channel data page buffer holds a block (192 frames) of
444  * The 6-word transmit channel data page buffer holds a block (192 frames) of
452  * This 4-word deep FIFO receives user FIFO field information. The order of
459  * This 4-word deep FIFO transmits user FIFO field information. The order of