Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
13 #include "clk-regmap.h"
14 #include "clk-pll.h"
15 #include "clk-mpll.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
86 .data = &(struct meson_clk_pll_data){
89 .shift = 30,
94 .shift = 0,
99 .shift = 9,
104 .shift = 0,
109 .shift = 31,
114 .shift = 29,
129 .data = &(struct clk_regmap_div_data){
131 .shift = 16,
163 .data = &(struct meson_clk_pll_data){
166 .shift = 30,
171 .shift = 0,
176 .shift = 9,
181 .shift = 0,
186 .shift = 31,
191 .shift = 28,
211 .data = &(struct meson_clk_pll_data){
214 .shift = 30,
219 .shift = 0,
224 .shift = 9,
228 * On gxl, there is a register shift due to
235 .shift = 0,
240 .shift = 31,
245 .shift = 28,
265 .data = &(struct clk_regmap_div_data){
267 .shift = 16,
283 .data = &(struct clk_regmap_div_data){
285 .shift = 22,
301 .data = &(struct clk_regmap_div_data){
303 .shift = 18,
319 .data = &(struct clk_regmap_div_data){
321 .shift = 21,
337 .data = &(struct clk_regmap_div_data){
339 .shift = 23,
355 .data = &(struct clk_regmap_div_data){
357 .shift = 19,
373 .data = &(struct meson_clk_pll_data){
376 .shift = 30,
381 .shift = 0,
386 .shift = 9,
391 .shift = 31,
396 .shift = 29,
411 .data = &(struct clk_regmap_div_data){
413 .shift = 10,
435 .data = &(struct meson_clk_pll_data){
438 .shift = 30,
443 .shift = 0,
448 .shift = 9,
453 .shift = 31,
458 .shift = 29,
484 .data = &(struct meson_clk_pll_data){
487 .shift = 30,
492 .shift = 0,
497 .shift = 9,
502 .shift = 0,
507 .shift = 31,
512 .shift = 29,
530 .data = &(struct clk_regmap_div_data){
532 .shift = 16,
548 .index = -1,
569 .data = &(struct clk_regmap_gate_data){
596 .data = &(struct clk_regmap_gate_data){
615 * b) CCF has a clock hand-off mechanism to make the sure the
634 .data = &(struct clk_regmap_gate_data){
660 .data = &(struct clk_regmap_gate_data){
686 .data = &(struct clk_regmap_gate_data){
701 .data = &(struct clk_regmap_div_data){
703 .shift = 12,
715 .data = &(struct meson_clk_mpll_data){
718 .shift = 0,
723 .shift = 15,
728 .shift = 16,
744 .data = &(struct clk_regmap_gate_data){
758 .data = &(struct meson_clk_mpll_data){
761 .shift = 0,
766 .shift = 15,
771 .shift = 16,
787 .data = &(struct clk_regmap_gate_data){
801 .data = &(struct meson_clk_mpll_data){
804 .shift = 0,
809 .shift = 15,
814 .shift = 16,
830 .data = &(struct clk_regmap_gate_data){
855 .data = &(struct clk_regmap_mux_data){
858 .shift = 12,
875 .data = &(struct clk_regmap_div_data){
877 .shift = 0,
892 .data = &(struct clk_regmap_gate_data){
908 .data = &(struct clk_regmap_mux_data){
911 .shift = 9,
926 .data = &(struct clk_regmap_div_data){
928 .shift = 0,
943 .data = &(struct clk_regmap_gate_data){
960 * muxed by a glitch-free switch. The CCF can manage this glitch-free
961 * mux because it does top-to-bottom updates the each clock tree and
977 .data = &(struct clk_regmap_mux_data){
980 .shift = 9,
998 .data = &(struct clk_regmap_div_data){
1000 .shift = 0,
1015 .data = &(struct clk_regmap_gate_data){
1031 .data = &(struct clk_regmap_mux_data){
1034 .shift = 25,
1052 .data = &(struct clk_regmap_div_data){
1054 .shift = 16,
1069 .data = &(struct clk_regmap_gate_data){
1090 .data = &(struct clk_regmap_mux_data){
1093 .shift = 31,
1105 .data = &(struct clk_regmap_mux_data){
1108 .shift = 9,
1125 .data = &(struct clk_regmap_div_data) {
1127 .shift = 0,
1143 .data = &(struct clk_regmap_gate_data){
1159 .data = &(struct clk_regmap_mux_data){
1162 .shift = 25,
1179 .data = &(struct clk_regmap_div_data){
1181 .shift = 16,
1197 .data = &(struct clk_regmap_gate_data){
1213 .data = &(struct clk_regmap_mux_data){
1216 .shift = 27,
1227 *The parent is specific to origin of the audio data. Let the
1241 { .name = "cts_slow_oscin", .index = -1 },
1247 .data = &(struct clk_regmap_mux_data){
1250 .shift = 16,
1262 .data = &(struct clk_regmap_div_data){
1264 .shift = 0,
1279 .data = &(struct clk_regmap_gate_data){
1310 .data = &(struct clk_regmap_mux_data){
1313 .shift = 9,
1325 .data = &(struct clk_regmap_div_data){
1327 .shift = 0,
1343 .data = &(struct clk_regmap_gate_data){
1360 .data = &(struct clk_regmap_mux_data){
1363 .shift = 25,
1375 .data = &(struct clk_regmap_div_data){
1377 .shift = 16,
1393 .data = &(struct clk_regmap_gate_data){
1410 .data = &(struct clk_regmap_mux_data){
1413 .shift = 9,
1425 .data = &(struct clk_regmap_div_data){
1427 .shift = 0,
1443 .data = &(struct clk_regmap_gate_data){
1468 .data = &(struct clk_regmap_mux_data){
1471 .shift = 9,
1487 .data = &(struct clk_regmap_div_data){
1489 .shift = 0,
1502 .data = &(struct clk_regmap_gate_data){
1516 .data = &(struct clk_regmap_mux_data){
1519 .shift = 25,
1535 .data = &(struct clk_regmap_div_data){
1537 .shift = 16,
1550 .data = &(struct clk_regmap_gate_data){
1564 .data = &(struct clk_regmap_mux_data){
1567 .shift = 31,
1595 .data = &(struct clk_regmap_mux_data){
1598 .shift = 9,
1614 .data = &(struct clk_regmap_div_data){
1616 .shift = 0,
1631 .data = &(struct clk_regmap_gate_data){
1647 .data = &(struct clk_regmap_mux_data){
1650 .shift = 25,
1666 .data = &(struct clk_regmap_div_data){
1668 .shift = 16,
1683 .data = &(struct clk_regmap_gate_data){
1699 .data = &(struct clk_regmap_mux_data){
1702 .shift = 31,
1721 .data = &(struct clk_regmap_gate_data){
1737 .data = &(struct meson_vid_pll_div_data){
1740 .shift = 0,
1745 .shift = 16,
1761 .index = -1,
1777 { .name = "hdmi_pll", .index = -1 },
1781 .data = &(struct clk_regmap_mux_data){
1784 .shift = 18,
1800 .data = &(struct clk_regmap_gate_data){
1826 .data = &(struct clk_regmap_mux_data){
1829 .shift = 16,
1846 .data = &(struct clk_regmap_mux_data){
1849 .shift = 16,
1866 .data = &(struct clk_regmap_gate_data){
1880 .data = &(struct clk_regmap_gate_data){
1894 .data = &(struct clk_regmap_div_data){
1896 .shift = 0,
1911 .data = &(struct clk_regmap_div_data){
1913 .shift = 0,
1928 .data = &(struct clk_regmap_gate_data){
1942 .data = &(struct clk_regmap_gate_data){
1956 .data = &(struct clk_regmap_gate_data){
1970 .data = &(struct clk_regmap_gate_data){
1984 .data = &(struct clk_regmap_gate_data){
1998 .data = &(struct clk_regmap_gate_data){
2012 .data = &(struct clk_regmap_gate_data){
2026 .data = &(struct clk_regmap_gate_data){
2040 .data = &(struct clk_regmap_gate_data){
2054 .data = &(struct clk_regmap_gate_data){
2068 .data = &(struct clk_regmap_gate_data){
2082 .data = &(struct clk_regmap_gate_data){
2214 .data = &(struct clk_regmap_mux_data){
2217 .shift = 28,
2230 .data = &(struct clk_regmap_mux_data){
2233 .shift = 20,
2246 .data = &(struct clk_regmap_mux_data){
2249 .shift = 28,
2277 .data = &(struct clk_regmap_mux_data){
2280 .shift = 16,
2299 .data = &(struct clk_regmap_gate_data){
2315 .data = &(struct clk_regmap_gate_data){
2331 .data = &(struct clk_regmap_gate_data){
2347 .data = &(struct clk_regmap_gate_data){
2372 .data = &(struct clk_regmap_mux_data){
2375 .shift = 9,
2388 .data = &(struct clk_regmap_div_data){
2390 .shift = 0,
2403 .data = &(struct clk_regmap_gate_data){
2426 .data = &(struct clk_regmap_mux_data){
2429 .shift = 9,
2442 .data = &(struct clk_regmap_div_data){
2444 .shift = 0,
2460 .data = &(struct clk_regmap_gate_data){
2476 .data = &(struct clk_regmap_mux_data){
2479 .shift = 25,
2492 .data = &(struct clk_regmap_div_data){
2494 .shift = 16,
2510 .data = &(struct clk_regmap_gate_data){
2542 .data = &(struct clk_regmap_mux_data){
2545 .shift = 12,
2563 .data = &(struct clk_regmap_div_data){
2565 .shift = 0,
2580 .data = &(struct clk_regmap_gate_data){
3518 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3519 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3526 .name = "gxbb-clkc",