Lines Matching +full:multi +full:- +full:system

1 # SPDX-License-Identifier: GPL-2.0-only
164 	  Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
185 	  Support for Multi Timer Unit. MTU provides access
187 	  32-bit free running decrementing counters.
241 	bool "Integrator-AP timer driver" if COMPILE_TEST
244 	  Enables support for the Integrator-AP timer.
277 	  available on many OMAP-like platforms.
286 	  It has a 64-bit counter with update rate up to 1000MHz.
287 	  This counter is accessed via couple of 32-bit memory-mapped registers.
306 	bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
310 	  These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
315 	bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
319 	  This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
337 	  power-of-2 divisor of the clock rate. The behaviour can also be
340 	  The main use of the event stream is wfe-based timeouts of userspace
351 	bool "Workaround for Freescale/NXP Erratum A-008585"
357 	  A-008585 ("ARM generic timer may contain an erroneous
359 	  fsl,erratum-a008585 property is found in the timer node.
368 	  161010101. The workaround will be active if the hisilicon,erratum-161010101
372 	bool "Workaround for Cortex-A73 erratum 858921"
377 	  This option enables a workaround applicable to Cortex-A73
390 	  allwinner,erratum-unknown1 property is found in the timer node.
413 	bool "Support for the ARMv7M system time" if COMPILE_TEST
417 	  This option enables support for the ARMv7M system timer unit.
442 	bool "Exynos multi core timer driver" if COMPILE_TEST
445 	  Support for Multi Core Timer controller on Exynos SoCs.
506 	bool "J-Core PIT timer driver" if COMPILE_TEST
512 	  the integrated PIT in the J-Core synthesizable, open source SoC.
520 	  the Compare Match Timer (CMT) hardware available in 16/32/48-bit
528 	  This enables build of a clockevent driver for the Multi-Function
530 	  This hardware comes with 16-bit timer registers.
545 	  the 32-bit Timer Unit (TMU) hardware available on a wide range
554 	  the 48-bit System Timer (STI) hardware available on a SoCs
572 	  counter available in the "System Registers" block of
590 	bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
594 	  This enables OST0 support available on PXA and SA-11x0
632 	bool "i.MX system counter timer" if COMPILE_TEST
635 	  Enable this option to use i.MX system counter timer as a
657 	bool "Timer for the RISC-V platform" if COMPILE_TEST
662 	  This enables the per-hart timer built into all RISC-V systems, which
664 	  required for all RISC-V systems.
667 	bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
672 	  This option enables the CLINT timer for RISC-V systems.  The CLINT
673 	  driver is usually used for NoMMU RISC-V systems.
676 	bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
680 	  Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
681 	  system.
682 	  csky,mptimer is not only used in SMP system, it also could be used in
683 	  single core system. It's not a mmio reg and it uses mtcr/mfcr instruction.
686 	bool "Gx6605s SOC system timer driver" if COMPILE_TEST
729 	  Support for the Operating System Timer of the Ingenic JZ SoCs.
738 	  based system. It supports the oneshot, the periodic