Lines Matching +full:supports +full:- +full:cqe
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
119 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
180 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
182 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
188 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
201 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
204 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
205 host->ioaddr + SDHCI_TRANSFER_MODE); in tegra_sdhci_writew()
209 writew(val, host->ioaddr + reg); in tegra_sdhci_writew()
216 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_writel()
225 writel(val, host->ioaddr + reg); in tegra_sdhci_writel()
227 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && in tegra_sdhci_writel()
230 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
235 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
275 writew(val, host->ioaddr + reg); in tegra210_sdhci_writew()
287 * Write-enable shall be assumed if GPIO is missing in a board's in tegra_sdhci_get_ro()
288 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on in tegra_sdhci_get_ro()
291 return mmc_gpio_get_ro(host->mmc); in tegra_sdhci_get_ro()
308 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_is_pad_and_regulator_valid()
311 if (IS_ERR(host->mmc->supply.vqmmc)) in tegra_sdhci_is_pad_and_regulator_valid()
314 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
317 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
321 return tegra_host->pad_control_available; in tegra_sdhci_is_pad_and_regulator_valid()
331 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_set_tap()
341 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) in tegra_sdhci_set_tap()
349 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && in tegra_sdhci_set_tap()
365 if (ios->enhanced_strobe) in tegra_sdhci_hs400_enhanced_strobe()
378 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_reset()
386 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_reset()
401 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) in tegra_sdhci_reset()
404 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
406 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in tegra_sdhci_reset()
408 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) in tegra_sdhci_reset()
410 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
414 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; in tegra_sdhci_reset()
419 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { in tegra_sdhci_reset()
425 tegra_host->pad_calib_required = true; in tegra_sdhci_reset()
428 tegra_host->ddr_signaling = false; in tegra_sdhci_reset()
469 &tegra_host->autocal_offsets; in tegra_sdhci_set_padctrl()
478 if (tegra_host->pinctrl_state_1v8_drv) { in tegra_sdhci_set_padctrl()
480 tegra_host->pinctrl_state_1v8_drv; in tegra_sdhci_set_padctrl()
482 drvup = offsets->pull_up_1v8_timeout; in tegra_sdhci_set_padctrl()
483 drvdn = offsets->pull_down_1v8_timeout; in tegra_sdhci_set_padctrl()
486 if (tegra_host->pinctrl_state_3v3_drv) { in tegra_sdhci_set_padctrl()
488 tegra_host->pinctrl_state_3v3_drv; in tegra_sdhci_set_padctrl()
490 drvup = offsets->pull_up_3v3_timeout; in tegra_sdhci_set_padctrl()
491 drvdn = offsets->pull_down_3v3_timeout; in tegra_sdhci_set_padctrl()
496 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
499 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
512 if (!tegra_host->pad_control_available) in tegra_sdhci_set_padctrl()
516 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
517 tegra_host->pinctrl_state_1v8); in tegra_sdhci_set_padctrl()
519 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
522 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
523 tegra_host->pinctrl_state_3v3); in tegra_sdhci_set_padctrl()
525 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
538 tegra_host->autocal_offsets; in tegra_sdhci_pad_autocalib()
539 struct mmc_ios *ios = &host->mmc->ios; in tegra_sdhci_pad_autocalib()
545 switch (ios->timing) { in tegra_sdhci_pad_autocalib()
553 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in tegra_sdhci_pad_autocalib()
559 /* Set initial offset before auto-calibration */ in tegra_sdhci_pad_autocalib()
572 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, in tegra_sdhci_pad_autocalib()
581 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); in tegra_sdhci_pad_autocalib()
588 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); in tegra_sdhci_pad_autocalib()
590 dev_err(mmc_dev(host->mmc), in tegra_sdhci_pad_autocalib()
600 &tegra_host->autocal_offsets; in tegra_sdhci_parse_pad_autocal_dt()
603 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
604 "nvidia,pad-autocal-pull-up-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
605 &autocal->pull_up_3v3); in tegra_sdhci_parse_pad_autocal_dt()
607 autocal->pull_up_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
609 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
610 "nvidia,pad-autocal-pull-down-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
611 &autocal->pull_down_3v3); in tegra_sdhci_parse_pad_autocal_dt()
613 autocal->pull_down_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
615 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
616 "nvidia,pad-autocal-pull-up-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
617 &autocal->pull_up_1v8); in tegra_sdhci_parse_pad_autocal_dt()
619 autocal->pull_up_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
621 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
622 "nvidia,pad-autocal-pull-down-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
623 &autocal->pull_down_1v8); in tegra_sdhci_parse_pad_autocal_dt()
625 autocal->pull_down_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
627 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
628 "nvidia,pad-autocal-pull-up-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
629 &autocal->pull_up_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
631 autocal->pull_up_sdr104 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
633 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
634 "nvidia,pad-autocal-pull-down-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
635 &autocal->pull_down_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
637 autocal->pull_down_sdr104 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
639 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
640 "nvidia,pad-autocal-pull-up-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
641 &autocal->pull_up_hs400); in tegra_sdhci_parse_pad_autocal_dt()
643 autocal->pull_up_hs400 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
645 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
646 "nvidia,pad-autocal-pull-down-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
647 &autocal->pull_down_hs400); in tegra_sdhci_parse_pad_autocal_dt()
649 autocal->pull_down_hs400 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
652 * Different fail-safe drive strength values based on the signaling in tegra_sdhci_parse_pad_autocal_dt()
657 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_parse_pad_autocal_dt()
660 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
661 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
662 &autocal->pull_up_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
664 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
665 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
666 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
667 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
668 autocal->pull_up_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
671 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
672 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
673 &autocal->pull_down_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
675 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
676 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
677 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
678 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
679 autocal->pull_down_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
682 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
683 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
684 &autocal->pull_up_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
686 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
687 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
688 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
689 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
690 autocal->pull_up_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
693 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
694 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
695 &autocal->pull_down_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
697 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
698 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
699 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
700 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
701 autocal->pull_down_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
710 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); in tegra_sdhci_request()
715 tegra_host->last_calib = ktime_get(); in tegra_sdhci_request()
727 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", in tegra_sdhci_parse_tap_and_trim()
728 &tegra_host->default_tap); in tegra_sdhci_parse_tap_and_trim()
730 tegra_host->default_tap = 0; in tegra_sdhci_parse_tap_and_trim()
732 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", in tegra_sdhci_parse_tap_and_trim()
733 &tegra_host->default_trim); in tegra_sdhci_parse_tap_and_trim()
735 tegra_host->default_trim = 0; in tegra_sdhci_parse_tap_and_trim()
737 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", in tegra_sdhci_parse_tap_and_trim()
738 &tegra_host->dqs_trim); in tegra_sdhci_parse_tap_and_trim()
740 tegra_host->dqs_trim = 0x11; in tegra_sdhci_parse_tap_and_trim()
748 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) in tegra_sdhci_parse_dt()
749 tegra_host->enable_hwcq = true; in tegra_sdhci_parse_dt()
751 tegra_host->enable_hwcq = false; in tegra_sdhci_parse_dt()
770 * sdhci_calc_clk(). The divider is calculated from host->max_clk and in tegra_sdhci_set_clock()
773 * By setting the host->max_clk to clock * 2 the divider calculation in tegra_sdhci_set_clock()
778 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; in tegra_sdhci_set_clock()
779 clk_set_rate(pltfm_host->clk, host_clk); in tegra_sdhci_set_clock()
780 tegra_host->curr_clk_rate = host_clk; in tegra_sdhci_set_clock()
781 if (tegra_host->ddr_signaling) in tegra_sdhci_set_clock()
782 host->max_clk = host_clk; in tegra_sdhci_set_clock()
784 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
788 if (tegra_host->pad_calib_required) { in tegra_sdhci_set_clock()
790 tegra_host->pad_calib_required = false; in tegra_sdhci_set_clock()
798 return clk_round_rate(pltfm_host->clk, UINT_MAX); in tegra_sdhci_get_max_clock()
821 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, in tegra_sdhci_hs400_dll_cal()
825 dev_err(mmc_dev(host->mmc), in tegra_sdhci_hs400_dll_cal()
846 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; in tegra_sdhci_tap_correction()
849 * Read auto-tuned results and extract good valid passing window by in tegra_sdhci_tap_correction()
850 * filtering out un-wanted bubble/partial/merged windows. in tegra_sdhci_tap_correction()
879 end_pass_tap = tap - 1; in tegra_sdhci_tap_correction()
883 window = end_pass_tap - start_pass_tap; in tegra_sdhci_tap_correction()
891 tegra_host->tuned_tap_delay = tap; in tegra_sdhci_tap_correction()
904 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; in tegra_sdhci_tap_correction()
905 if (edge1 - 1 > fixed_tap) in tegra_sdhci_tap_correction()
906 tegra_host->tuned_tap_delay = edge1 - fixed_tap; in tegra_sdhci_tap_correction()
908 tegra_host->tuned_tap_delay = edge1 + fixed_tap; in tegra_sdhci_tap_correction()
916 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_post_tuning()
925 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> in tegra_sdhci_post_tuning()
927 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { in tegra_sdhci_post_tuning()
928 min_tap_dly = soc_data->min_tap_delay; in tegra_sdhci_post_tuning()
929 max_tap_dly = soc_data->max_tap_delay; in tegra_sdhci_post_tuning()
930 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; in tegra_sdhci_post_tuning()
951 window_width = end_tap - start_tap; in tegra_sdhci_post_tuning()
952 num_iter = host->tuning_loop_count; in tegra_sdhci_post_tuning()
958 if (start_tap == 0 || (end_tap == (num_iter - 1)) || in tegra_sdhci_post_tuning()
959 (end_tap == num_iter - 2) || window_width >= thdupper) { in tegra_sdhci_post_tuning()
961 mmc_hostname(host->mmc)); in tegra_sdhci_post_tuning()
967 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_post_tuning()
976 if (!err && !host->tuning_err) in tegra_sdhci_execute_hw_tuning()
993 tegra_host->ddr_signaling = false; in tegra_sdhci_set_uhs_signaling()
1009 tegra_host->ddr_signaling = true; in tegra_sdhci_set_uhs_signaling()
1027 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; in tegra_sdhci_set_uhs_signaling()
1033 if (tegra_host->tuned_tap_delay && !set_default_tap) in tegra_sdhci_set_uhs_signaling()
1034 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_set_uhs_signaling()
1036 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_set_uhs_signaling()
1039 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); in tegra_sdhci_set_uhs_signaling()
1057 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in tegra_sdhci_execute_tuning()
1066 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in tegra_sdhci_execute_tuning()
1067 max--; in tegra_sdhci_execute_tuning()
1074 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); in tegra_sdhci_execute_tuning()
1076 return mmc_send_tuning(host->mmc, opcode, NULL); in tegra_sdhci_execute_tuning()
1087 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { in sdhci_tegra_start_signal_voltage_switch()
1088 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1092 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in sdhci_tegra_start_signal_voltage_switch()
1096 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1099 if (tegra_host->pad_calib_required) in sdhci_tegra_start_signal_voltage_switch()
1108 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); in tegra_sdhci_init_pinctrl_info()
1109 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { in tegra_sdhci_init_pinctrl_info()
1111 PTR_ERR(tegra_host->pinctrl_sdmmc)); in tegra_sdhci_init_pinctrl_info()
1112 return -1; in tegra_sdhci_init_pinctrl_info()
1115 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1116 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); in tegra_sdhci_init_pinctrl_info()
1117 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { in tegra_sdhci_init_pinctrl_info()
1118 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1119 tegra_host->pinctrl_state_1v8_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1122 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1123 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); in tegra_sdhci_init_pinctrl_info()
1124 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { in tegra_sdhci_init_pinctrl_info()
1125 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1126 tegra_host->pinctrl_state_3v3_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1129 tegra_host->pinctrl_state_3v3 = in tegra_sdhci_init_pinctrl_info()
1130 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); in tegra_sdhci_init_pinctrl_info()
1131 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { in tegra_sdhci_init_pinctrl_info()
1133 PTR_ERR(tegra_host->pinctrl_state_3v3)); in tegra_sdhci_init_pinctrl_info()
1134 return -1; in tegra_sdhci_init_pinctrl_info()
1137 tegra_host->pinctrl_state_1v8 = in tegra_sdhci_init_pinctrl_info()
1138 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); in tegra_sdhci_init_pinctrl_info()
1139 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { in tegra_sdhci_init_pinctrl_info()
1141 PTR_ERR(tegra_host->pinctrl_state_1v8)); in tegra_sdhci_init_pinctrl_info()
1142 return -1; in tegra_sdhci_init_pinctrl_info()
1145 tegra_host->pad_control_available = true; in tegra_sdhci_init_pinctrl_info()
1154 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_voltage_switch()
1156 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in tegra_sdhci_voltage_switch()
1157 tegra_host->pad_calib_required = true; in tegra_sdhci_voltage_switch()
1162 struct mmc_host *mmc = cq_host->mmc; in tegra_cqhci_writel()
1169 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to in tegra_cqhci_writel()
1171 * to be re-configured. in tegra_cqhci_writel()
1173 * CQE is unhalted. So handling CQE resume sequence here to configure in tegra_cqhci_writel()
1174 * SDHCI block registers prior to exiting CQE halt state. in tegra_cqhci_writel()
1180 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1189 * CQE usually resumes very quick, but incase if Tegra CQE in tegra_cqhci_writel()
1193 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1195 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1204 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in sdhci_tegra_update_dcmd_desc()
1206 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && in sdhci_tegra_update_dcmd_desc()
1207 mrq->cmd->flags & MMC_RSP_R1B) in sdhci_tegra_update_dcmd_desc()
1213 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_enable()
1219 * register when CQE is enabled and unhalted. in sdhci_tegra_cqe_enable()
1220 * CQHCI driver enables CQE prior to activation, so disable CQE before in sdhci_tegra_cqe_enable()
1223 if (!cq_host->activated) { in sdhci_tegra_cqe_enable()
1259 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_tegra_cqhci_irq()
1283 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) in tegra_sdhci_set_timeout()
1294 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_pre_enable()
1304 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_post_disable()
1328 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; in tegra_sdhci_set_dma_mask()
1329 struct device *dev = mmc_dev(host->mmc); in tegra_sdhci_set_dma_mask()
1331 if (soc->dma_mask) in tegra_sdhci_set_dma_mask()
1332 return dma_set_mask_and_coherent(dev, soc->dma_mask); in tegra_sdhci_set_dma_mask()
1377 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1534 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1535 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1536 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1537 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1538 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1539 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1540 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1553 if (!tegra_host->enable_hwcq) in sdhci_tegra_add_host()
1562 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_tegra_add_host()
1564 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_tegra_add_host()
1567 ret = -ENOMEM; in sdhci_tegra_add_host()
1571 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; in sdhci_tegra_add_host()
1572 cq_host->ops = &sdhci_tegra_cqhci_ops; in sdhci_tegra_add_host()
1574 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_tegra_add_host()
1576 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_tegra_add_host()
1578 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_tegra_add_host()
1603 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); in sdhci_tegra_probe()
1605 return -EINVAL; in sdhci_tegra_probe()
1606 soc_data = match->data; in sdhci_tegra_probe()
1608 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); in sdhci_tegra_probe()
1614 tegra_host->ddr_signaling = false; in sdhci_tegra_probe()
1615 tegra_host->pad_calib_required = false; in sdhci_tegra_probe()
1616 tegra_host->pad_control_available = false; in sdhci_tegra_probe()
1617 tegra_host->soc_data = soc_data; in sdhci_tegra_probe()
1619 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { in sdhci_tegra_probe()
1620 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); in sdhci_tegra_probe()
1622 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_tegra_probe()
1627 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in sdhci_tegra_probe()
1628 host->mmc_host_ops.request = tegra_sdhci_request; in sdhci_tegra_probe()
1630 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_tegra_probe()
1633 if (!host->ops->platform_execute_tuning) in sdhci_tegra_probe()
1634 host->mmc_host_ops.execute_tuning = in sdhci_tegra_probe()
1637 rc = mmc_of_parse(host->mmc); in sdhci_tegra_probe()
1641 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in sdhci_tegra_probe()
1642 host->mmc->caps |= MMC_CAP_1_8V_DDR; in sdhci_tegra_probe()
1645 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_tegra_probe()
1649 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", in sdhci_tegra_probe()
1651 if (IS_ERR(tegra_host->power_gpio)) { in sdhci_tegra_probe()
1652 rc = PTR_ERR(tegra_host->power_gpio); in sdhci_tegra_probe()
1671 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { in sdhci_tegra_probe()
1672 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1675 if (rc == -EPROBE_DEFER) in sdhci_tegra_probe()
1678 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1685 dev_err(&pdev->dev, in sdhci_tegra_probe()
1690 tegra_host->tmclk = clk; in sdhci_tegra_probe()
1693 clk = devm_clk_get(mmc_dev(host->mmc), NULL); in sdhci_tegra_probe()
1695 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_tegra_probe()
1700 pltfm_host->clk = clk; in sdhci_tegra_probe()
1702 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, in sdhci_tegra_probe()
1704 if (IS_ERR(tegra_host->rst)) { in sdhci_tegra_probe()
1705 rc = PTR_ERR(tegra_host->rst); in sdhci_tegra_probe()
1706 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); in sdhci_tegra_probe()
1710 rc = reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1716 rc = reset_control_deassert(tegra_host->rst); in sdhci_tegra_probe()
1729 reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1731 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_probe()
1733 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_probe()
1748 reset_control_assert(tegra_host->rst); in sdhci_tegra_remove()
1750 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_remove()
1751 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_remove()
1765 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_suspend()
1766 ret = cqhci_suspend(host->mmc); in sdhci_tegra_suspend()
1773 cqhci_resume(host->mmc); in sdhci_tegra_suspend()
1777 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_suspend()
1787 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_tegra_resume()
1795 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_resume()
1796 ret = cqhci_resume(host->mmc); in sdhci_tegra_resume()
1806 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_resume()
1816 .name = "sdhci-tegra",