Lines Matching +full:4 +full:a
4 * Permission is hereby granted, free of charge, to any person obtaining a
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
38 * fourcc code, a Format Modifier may optionally be provided, in order to
44 * Format modifiers are used in conjunction with a fourcc code, forming a
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
69 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ argument
99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian…
100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian…
101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian…
102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian…
104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian…
105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian…
106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian…
107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian…
114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian…
115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian…
116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian…
117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian…
123 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
124 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian…
128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian…
129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian…
130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian…
132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian…
133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian…
134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian…
135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian…
142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little …
143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little …
144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little …
145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little …
152 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 litt…
153 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 litt…
155 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 litt…
156 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 litt…
164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian …
166 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
174 … fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian…
181 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 litt…
182 …ine DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:…
183 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 lit…
186 …1616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian…
187 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 lit…
191 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
204 * 1-plane YUV 4:2:0
207 * These formats can only be used with a non-Linear modifier.
213 * 2 plane RGB + A
215 * index 1 = A plane, [7:0] A
217 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
218 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
219 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
220 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
221 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
222 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
223 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
224 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
237 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
238 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
262 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
263 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
280 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
288 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
299 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) plane…
300 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) plane…
301 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) plane…
302 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) plane…
307 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) plane…
308 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) plane…
314 * Format modifiers describe, typically, a re-ordering or modification
315 * of the data in a plane of an FB. This can be used to express tiled/
316 * swizzled formats, or compression, or a combination of the two.
318 * The upper 8 bits of the format modifier are a vendor-id as assigned
346 * When adding a new token please document the layout with a code comment,
354 * compatibility, in cases where a vendor-specific definition already exists and
355 * a generic name for it is desired, the common name is a purely symbolic alias
362 * In future cases where a generic layout is identified before merging with a
363 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
366 * apply to a single vendor.
379 * This modifier can be used as a sentinel to terminate the format modifiers
380 * list, or to initialize a variable with an invalid modifier. It might also be
391 * and so might actually result in a tiled framebuffer.
400 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
402 * a platform-dependent stride. On top of that the memory can apply
407 * cross-driver sharing. It exists since on a given platform it does uniquely
408 * identify the layout in a simple way for i915-specific userspace, which
417 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
419 * chunks column-major, with a platform-dependent height. On top of that the
425 * cross-driver sharing. It exists since on a given platform it does uniquely
426 * identify the layout in a simple way for i915-specific userspace, which
435 * This is a tiled layout using 4Kb tiles in row-major layout.
441 * either a square block or a 2:1 unit.
454 * Each CCS tile matches a 1024x512 pixel area of the main surface.
459 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
464 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
471 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
472 * main surface. In other words, 4 bits in CCS map to a main surface cache
473 * line pair. The main surface pitch is required to be a multiple of four
482 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
483 * main surface. In other words, 4 bits in CCS map to a main surface cache
484 * line pair. The main surface pitch is required to be a multiple of four
494 * Macroblocks are laid in a Z-shape, and each pixel data is following the
509 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
510 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
518 * Refers to a compressed variant of the base format that is compressed.
521 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
524 * Entire pixel data buffer is aligned with 4k(bytes).
531 * Vivante 4x4 tiling layout
533 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
541 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
542 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
551 * Vivante 4x4 tiling layout for dual-pipe
553 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
562 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
563 * starts at a different base address. Offsets from the base addresses are
566 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
571 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
583 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
585 * a block depth or height of "4").
598 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
606 * hardware support a block width of two gobs, but it is impractical
614 * 19:12 k Page Kind. This value directly maps to a field in the page
627 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
632 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
636 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
653 * 4 = CDE vertical
687 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
689 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
698 * 4 == SIXTEEN_GOBS
716 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
743 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
746 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
749 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
750 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
753 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
754 * tiles) or right-to-left (odd rows of 4k tiles).
777 * and UV. Some SAND-using hardware stores UV in a separate tiled
787 fourcc_mod_broadcom_code(4, v)
807 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
816 * necessary to reduce the padding. If a hardware block can't do XOR,
817 * the assumption is that a no-XOR tiling modifier will be created.
824 * AFBC is a proprietary lossless image compression protocol and format.
837 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
839 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
855 * size (in pixels) must be aligned to a multiple of the superblock size.
868 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
876 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
882 * half of the payload is positioned at a predefined offset from the start
890 * This flag indicates that the payload of each superblock must be stored at a
911 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
912 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
913 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
924 * can be reduced if a whole superblock is a single color.
931 * Indicates that the buffer is allocated in a layout safe for front-buffer
949 * affects the storage mode of the individual superblocks. Note that even a
969 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
982 * Amlogic uses a proprietary lossless image compression protocol and format
1016 * - a body content organized in 64x32 superblocks with 4096 bytes per
1018 * - a 32 bytes per 128x64 header block
1039 * The user-space clients should expect a failure while trying to mmap