Lines Matching +full:stm32 +full:- +full:dsi
1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
3 --- a/arch/arm/Kconfig
5 @@ -330,7 +330,7 @@ config ARCH_MULTIPLATFORM
9 - select AUTO_ZRELADDR
14 @@ -751,6 +751,8 @@ source "arch/arm/mach-highbank/Kconfig"
16 source "arch/arm/mach-hisi/Kconfig"
18 +source "arch/arm/mach-hibvt/Kconfig"
20 source "arch/arm/mach-imx/Kconfig"
22 source "arch/arm/mach-integrator/Kconfig"
23 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
25 --- a/arch/arm/Makefile
27 @@ -173,6 +173,7 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge
28 machine-$(CONFIG_ARCH_GEMINI) += gemini
29 machine-$(CONFIG_ARCH_HIGHBANK) += highbank
30 machine-$(CONFIG_ARCH_HISI) += hisi
31 +machine-$(CONFIG_ARCH_HISI_BVT) += hibvt
32 machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
33 machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
34 machine-$(CONFIG_ARCH_IOP32X) += iop32x
35 @@ -238,6 +239,8 @@ plat-$(CONFIG_PLAT_ORION) += orion
36 plat-$(CONFIG_PLAT_PXA) += pxa
37 plat-$(CONFIG_PLAT_S3C24XX) += samsung
38 plat-$(CONFIG_PLAT_VERSATILE) += versatile
39 +plat-$(CONFIG_ARCH_HI3519AV100) += hi3519av100
40 +plat-$(CONFIG_ARCH_HI3556AV100) += hi3556av100
44 @@ -272,6 +275,10 @@ endif
49 +KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
55 diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
57 --- a/arch/arm/boot/Makefile
59 @@ -16,6 +16,8 @@ OBJCOPYFLAGS :=-O binary -R .comment -S
63 +include $(srctree)/arch/arm/mach-hibvt/Makefile.boot
68 @@ -24,10 +26,12 @@ endif
69 ZRELADDR := $(zreladdr-y)
70 PARAMS_PHYS := $(params_phys-y)
71 INITRD_PHYS := $(initrd_phys-y)
72 +DTB_OBJS ?= $(dtb-y)
77 -targets := Image zImage xipImage bootpImage uImage
78 +targets := Image zImage xipImage bootpImage uImage zImage-dtb
82 @@ -66,6 +70,10 @@ $(obj)/compressed/vmlinux: $(obj)/Image FORCE
86 +$(obj)/zImage-dtb: $(obj)/zImage $(DTB_OBJS_FULL) FORCE
93 @@ -86,7 +94,7 @@ if [ $(words $(UIMAGE_LOADADDR)) -ne 1 ]; then \
97 -$(obj)/uImage: $(obj)/zImage FORCE
98 +$(obj)/uImage: $(obj)/zImage-dtb FORCE
102 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
104 --- a/arch/arm/boot/dts/Makefile
106 @@ -222,6 +222,71 @@ dtb-$(CONFIG_ARCH_HISI) += \
107 hi3519-demb.dtb
108 dtb-$(CONFIG_ARCH_HIX5HD2) += \
109 hisi-x5hd2-dkb.dtb
110 +dtb-$(CONFIG_ARCH_HI3521DV200) += \
111 + hi3521dv200-demb.dtb
112 +dtb-$(CONFIG_ARCH_HI3520DV500) += \
113 + hi3520dv500-demb.dtb
114 +dtb-$(CONFIG_ARCH_HI3516A) += \
115 + hi3516a-demb.dtb
116 +dtb-$(CONFIG_ARCH_HI3516CV500) += \
117 + hi3516cv500-demb.dtb
118 +dtb-$(CONFIG_ARCH_HI3516EV200) += \
119 + hi3516ev200-demb.dtb
120 +dtb-$(CONFIG_ARCH_HI3516EV300) += \
121 + hi3516ev300-demb.dtb
122 +dtb-$(CONFIG_ARCH_HI3518EV300) += \
123 + hi3518ev300-demb.dtb
124 +dtb-$(CONFIG_ARCH_HI3516DV200) += \
125 + hi3516dv200-demb.dtb
127 +dtb-$(CONFIG_ARCH_HI3516DV300) += \
128 + hi3516dv300-demb.dtb
129 +dtb-$(CONFIG_ARCH_HI3556V200) += \
130 + hi3556v200-demb.dtb
131 +dtb-$(CONFIG_ARCH_HI3559V200) += \
132 + hi3559v200-demb.dtb
133 +dtb-$(CONFIG_ARCH_HI3562V100) += \
134 + hi3562v100-demb.dtb
135 +dtb-$(CONFIG_ARCH_HI3566V100) += \
136 + hi3566v100-demb.dtb
137 +dtb-$(CONFIG_ARCH_HI3518EV20X) += \
138 + hi3518ev20x-demb.dtb
139 +dtb-$(CONFIG_ARCH_HI3521A) += \
140 + hi3521a-demb.dtb
141 +dtb-$(CONFIG_ARCH_HI3531A) += \
142 + hi3531a-demb.dtb
143 +dtb-$(CONFIG_ARCH_HI3536DV100) += \
144 + hi3536dv100-demb.dtb
149 +dtb-$(CONFIG_ARCH_HI3556AV100) += \
150 + hi3556av100-flash.dtb
151 +dtb-$(CONFIG_ARCH_HI3519AV100) += \
152 + hi3519av100-flash.dtb
153 +dtb-$(CONFIG_ARCH_HI3568V100) += \
154 + hi3568v100-flash.dtb
156 +dtb-$(CONFIG_ARCH_HI3556AV100) += \
157 + hi3556av100-emmc.dtb
158 +dtb-$(CONFIG_ARCH_HI3519AV100) += \
159 + hi3519av100-emmc.dtb
160 +dtb-$(CONFIG_ARCH_HI3568V100) += \
161 + hi3568v100-emmc.dtb
167 +dtb-$(CONFIG_ARCH_HI3519AV100) += \
168 + hi3519av100-smp-flash.dtb
170 +dtb-$(CONFIG_ARCH_HI3519AV100) += \
171 + hi3519av100-smp-emmc.dtb
175 dtb-$(CONFIG_ARCH_INTEGRATOR) += \
178 @@ -1207,3 +1272,4 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
179 aspeed-bmc-opp-zaius.dtb \
180 aspeed-bmc-portwell-neptune.dtb \
181 aspeed-bmc-quanta-q71l.dtb
183 diff --git a/arch/arm/boot/dts/hi3516a-demb.dts b/arch/arm/boot/dts/hi3516a-demb.dts
186 --- /dev/null
187 +++ b/arch/arm/boot/dts/hi3516a-demb.dts
188 @@ -0,0 +1,240 @@
190 + * Copyright (c) 2013-2014 Linaro Ltd.
191 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
208 +/dts-v1/;
217 + #address-cells = <1>;
218 + #size-cells = <0>;
222 + compatible = "arm,cortex-a7";
225 + operating-points = <
238 + clock-names = "a7_mux","400m", "500m","apll";
240 + vcc-supply = <&a7_regulator>;
246 + avs-num = <2>;
247 + avs-name-array = "cpu-avs","media-avs";
249 + avs-name = "cpu-avs";
250 + opp-num = <5>;
251 + opp-freq = <600000 732000 850000 500000 400000>;
252 + opp-volt-min = <940000 1000000 1070000 940000 940000>;
253 + opp-hpm = <270 325 365 255 240>;
254 + opp-div = <11 14 16 10 8>;
255 + opp-volt-max = <1310000>;
259 + avs-name = "media-avs";
260 + opp-num = <5>;
261 + opp-freq = <0 1 2 3 4>;
262 + opp-volt-min = <930000 930000 930000 930000 930000>;
263 + opp-hpm = <245 245 245 260 285>;
264 + opp-div = <3 3 4 5 5>;
265 + opp-volt-max = <1310000>;
307 + num-cs = <1>;
313 + pl022,com-mode = <0>;
314 + spi-max-frequency = <25000000>;
320 + num-cs = <3>;
326 + pl022,com-mode = <0>;
327 + spi-max-frequency = <25000000>;
334 + pl022,com-mode = <0>;
335 + spi-max-frequency = <25000000>;
342 + pl022,com-mode = <0>;
343 + spi-max-frequency = <25000000>;
348 + ethphy: ethernet-phy@1 {
354 + phy-handle = <ðphy>;
355 + phy-mode = "rgmii";
429 diff --git a/arch/arm/boot/dts/hi3516a.dtsi b/arch/arm/boot/dts/hi3516a.dtsi
432 --- /dev/null
434 @@ -0,0 +1,690 @@
436 + * Copyright (c) 2013-2014 Linaro Ltd.
437 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
455 +#include <dt-bindings/clock/hi3516a-clock.h>
484 + compatible = "hisilicon,hi3516a-clock";
485 + #address-cells = <1>;
486 + #size-cells = <1>;
487 + #clock-cells = <1>;
488 + #reset-cells = <2>;
492 + gic: interrupt-controller@20300000 {
493 + compatible = "arm,cortex-a7-gic";
494 + #interrupt-cells = <3>;
495 + #address-cells = <0>;
496 + interrupt-controller;
501 + sysctrl: system-controller@20050000 {
504 + #clock-cells = <1>;
508 + compatible = "syscon-reboot";
515 + #address-cells = <1>;
516 + #size-cells = <1>;
517 + compatible = "simple-bus";
518 + interrupt-parent = <&gic>;
523 + compatible = "arm,cortex-a7-pmu";
528 + #address-cells = <1>;
529 + #size-cells = <1>;
530 + compatible = "arm,amba-bus";
538 + clock-names = "apb_pclk";
547 + clock-names = "apb_pclk";
556 + clock-names = "apb_pclk";
565 + clock-names = "apb_pclk";
572 + compatible = "hisilicon,hisi-usb-phy";
575 + #phy-cells = <0>;
579 + compatible = "generic-ehci";
585 + clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
589 + compatible = "generic-ohci";
595 + clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
604 + clock-names = "clk";
614 + clock-names = "timer0", "timer1", "apb_pclk";
626 + clock-names = "timer2", "timer3", "apb_pclk";
630 + hidmac: hidma-controller@10060000 {
631 + compatible = "hisilicon,hisi-dmac";
635 + clock-names = "dmac_clk";
637 + reset-names = "dma-reset";
638 + #dma-cells = <2>;
643 + compatible = "hisilicon,hisi-i2c-hisilicon";
647 + clock-frequency = <100000>;
648 + io-size = <0x1000>;
654 + compatible = "hisilicon,hisi-i2c-hisilicon";
658 + clock-frequency = <100000>;
659 + io-size = <0x1000>;
665 + compatible = "hisilicon,hisi-i2c-hisilicon";
669 + clock-frequency = <100000>;
670 + io-size = <0x1000>;
677 + arm,primecell-periphid = <0x00800022>;
681 + clock-names = "apb_pclk";
683 + #address-cells = <1>;
684 + #size-cells = <0>;
689 + arm,primecell-periphid = <0x00800022>;
693 + clock-names = "apb_pclk";
695 + #address-cells = <1>;
696 + #size-cells = <0>;
702 + compatible = "hisilicon,hisi-spi-nor";
705 + reg-names = "control", "memory";
707 + assigned-clocks = <&clock HI3516A_SNOR_CLK>;
708 + assigned-clock-rates = <24000000>;
709 + #address-cells = <1>;
710 + #size-cells = <0>;
713 + compatible = "jedec,spi-nor";
719 + compatible = "hisilicon,hisi-spi-nand";
721 + reg-names = "control", "memory";
723 + assigned-clocks = <&clock HI3516A_SNAND_CLK>;
724 + assigned-clock-rates = <24000000>;
725 + #address-cells = <1>;
726 + #size-cells = <0>;
729 + compatible = "jedec,spi-nand";
735 + compatible = "hisilicon,hisi-parallel-nand";
737 + reg-names = "control", "memory";
739 + assigned-clocks = <&clock HI3516A_NAND_CLK>;
740 + assigned-clock-rates = <198000000>;
741 + #address-cells = <1>;
742 + #size-cells = <0>;
745 + compatible = "jedec,parallel-nand";
755 + clock-names = "apb_pclk";
756 + #gpio-cells = <2>;
765 + clock-names = "apb_pclk";
766 + #gpio-cells = <2>;
775 + clock-names = "apb_pclk";
776 + #gpio-cells = <2>;
785 + clock-names = "apb_pclk";
786 + #gpio-cells = <2>;
795 + clock-names = "apb_pclk";
796 + #gpio-cells = <2>;
805 + clock-names = "apb_pclk";
806 + #gpio-cells = <2>;
815 + clock-names = "apb_pclk";
816 + #gpio-cells = <2>;
825 + clock-names = "apb_pclk";
826 + #gpio-cells = <2>;
835 + clock-names = "apb_pclk";
836 + #gpio-cells = <2>;
845 + clock-names = "apb_pclk";
846 + #gpio-cells = <2>;
855 + clock-names = "apb_pclk";
856 + #gpio-cells = <2>;
865 + clock-names = "apb_pclk";
866 + #gpio-cells = <2>;
875 + clock-names = "apb_pclk";
876 + #gpio-cells = <2>;
885 + clock-names = "apb_pclk";
886 + #gpio-cells = <2>;
895 + clock-names = "apb_pclk";
896 + #gpio-cells = <2>;
905 + clock-names = "apb_pclk";
906 + #gpio-cells = <2>;
913 + regulator-num = <2>;
914 + regulator-name-array = "regulator-a7","regulator-media";
917 + regulator-name = "regulator-a7";
918 + regulator-min-microvolt = <800000>;
919 + regulator-max-microvolt = <1310000>;
920 + regulator-always-on;
925 + regulator-name = "regulator-media";
926 + regulator-min-microvolt = <800000>;
927 + regulator-max-microvolt = <1310000>;
928 + regulator-always-on;
933 + compatible = "hisilicon,hisi-gemac-mdio";
937 + assigned-clocks = <&clock HI3516A_ETH_PHY_MUX>;
938 + assigned-clock-rates = <25000000>;
939 + #address-cells = <1>;
940 + #size-cells = <0>;
950 + clock-names = "higmac_clk",
955 + reset-names = "port_reset",
958 + mac-address = [00 00 00 00 00 00];
962 + compatible = "hisilicon,hi3516a-himci";
966 + clock-names = "mmc_clk";
968 + reset-names = "mmc_reset";
969 + max-frequency = <100000000>;
970 + bus-width = <4>;
971 + cap-sd-highspeed;
972 + sd-uhs-sdr12;
973 + sd-uhs-sdr25;
974 + sd-uhs-sdr50;
975 + sd-uhs-sdr104;
981 + compatible = "hisilicon,hi3516a-himci";
985 + clock-names = "mmc_clk";
987 + reset-names = "mmc_reset";
988 + max-frequency = <100000000>;
989 + bus-width = <4>;
990 + cap-sd-highspeed;
991 + sd-uhs-sdr12;
992 + sd-uhs-sdr25;
993 + sd-uhs-sdr50;
994 + sd-uhs-sdr104;
1001 + #address-cells = <1>;
1002 + #size-cells = <1>;
1003 + compatible = "simple-bus";
1004 + interrupt-parent = <&gic>;
1011 + reg-names = "crg", "sys", "ddr", "misc";
1018 + reg-names = "aiao";
1043 + reg-names = "reg_vicap_base_va", "reg_isp_base_va";
1095 + compatible = "hisilicon,hi3516cv300-pwm";
1102 + reg-names = "wtdg";
1108 + interrupt-names = "rtc", "rtc_temp";
1125 diff --git a/arch/arm/boot/dts/hi3516cv500-demb.dts b/arch/arm/boot/dts/hi3516cv500-demb.dts
1128 --- /dev/null
1129 +++ b/arch/arm/boot/dts/hi3516cv500-demb.dts
1130 @@ -0,0 +1,234 @@
1132 + * Copyright (c) 2013-2014 Linaro Ltd.
1133 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
1150 +/dts-v1/;
1170 + clock-frequency = <100000>;
1175 + clock-frequency = <100000>;
1180 + clock-frequency = <100000>;
1185 + clock-frequency = <100000>;
1190 + clock-frequency = <100000>;
1195 + clock-frequency = <100000>;
1200 + clock-frequency = <100000>;
1205 + clock-frequency = <100000>;
1210 + num-cs = <1>;
1216 + pl022,com-mode = <0>;
1217 + spi-max-frequency = <25000000>;
1222 + num-cs = <2>;
1228 + pl022,com-mode = <0>;
1229 + spi-max-frequency = <25000000>;
1235 + pl022,com-mode = <0>;
1236 + spi-max-frequency = <25000000>;
1241 + num-cs = <1>;
1247 + pl022,com-mode = <0>;
1248 + spi-max-frequency = <25000000>;
1254 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
1255 + phy0: ethernet-phy@1 {
1261 + mac-address = [00 00 00 00 00 00];
1262 + phy-mode = "rmii";
1263 + phy-handle = <&phy0>;
1269 + compatible = "jedec,spi-nor";
1271 + spi-max-frequency = <160000000>;
1277 + compatible = "jedec,spi-nand";
1279 + spi-max-frequency = <160000000>;
1365 diff --git a/arch/arm/boot/dts/hi3516cv500.dtsi b/arch/arm/boot/dts/hi3516cv500.dtsi
1368 --- /dev/null
1370 @@ -0,0 +1,890 @@
1372 + * Copyright (c) 2013-2014 Linaro Ltd.
1373 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
1391 +#include <dt-bindings/clock/hi3516cv500-clock.h>
1425 + #address-cells = <1>;
1426 + #size-cells = <0>;
1427 + enable-method = "hisilicon,hi3516cv500";
1431 + compatible = "arm,cortex-a7";
1432 + clock-frequency = <HI3516CV500_FIXED_1000M>;
1438 + compatible = "arm,cortex-a7";
1439 + clock-frequency = <HI3516CV500_FIXED_1000M>;
1446 + compatible = "hisilicon,hi3516cv500-clock";
1447 + #address-cells = <1>;
1448 + #size-cells = <1>;
1449 + #clock-cells = <1>;
1450 + #reset-cells = <2>;
1454 + gic: interrupt-controller@10300000 {
1455 + compatible = "arm,cortex-a7-gic";
1456 + #interrupt-cells = <3>;
1457 + #address-cells = <0>;
1458 + interrupt-controller;
1464 + compatible = "arm,armv7-timer";
1465 + interrupt-parent = <&gic>;
1468 + clock-frequency = <50000000>;
1472 + #address-cells = <1>;
1473 + #size-cells = <1>;
1474 + compatible = "simple-bus";
1475 + interrupt-parent = <&gic>;
1479 + compatible = "fixed-clock";
1480 + #clock-cells = <0>;
1481 + clock-frequency = <3000000>;
1485 + compatible = "fixed-clock";
1486 + #clock-cells = <0>;
1487 + clock-frequency = <50000000>;
1491 + compatible = "arm,cortex-a7-pmu";
1495 + hiedmacv310_0: hiedma-controller@10060000 {
1500 + clock-names = "apb_pclk", "axi_aclk";
1501 + #clock-cells = <2>;
1503 + reset-names = "dma-reset";
1504 + dma-requests = <32>;
1505 + dma-channels = <8>;
1507 + #dma-cells = <2>;
1512 + hiedmacv310_0: hiedma-controller@10060000 {
1517 + clock-names = "apb_pclk", "axi_aclk";
1518 + #clock-cells = <2>;
1520 + reset-names = "dma-reset";
1521 + dma-requests = <32>;
1522 + dma-channels = <8>;
1524 + #dma-cells = <2>;
1529 + sysctrl: system-controller@12020000 {
1532 + reboot-offset = <0x4>;
1533 + #clock-cells = <1>;
1537 + #address-cells = <1>;
1538 + #size-cells = <1>;
1539 + compatible = "arm,amba-bus";
1553 + clock-names = "timer0", "timer1", "timer2";
1562 + clock-names = "timer20", "timer21", "apb_pclk";
1567 + compatible = "arm,sp805-wdt", "arm,primecell";
1568 + arm,primecell-periphid = <0x00141805>;
1571 + clock-names = "wdog_clk", "apb_pclk";
1576 + compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
1580 + #pwm-cells = <2>;
1589 + clock-names = "apb_pclk";
1598 + clock-names = "apb_pclk";
1601 + dma-names = "tx","rx";
1611 + clock-names = "apb_pclk";
1614 + dma-names = "tx","rx";
1624 + clock-names = "apb_pclk";
1627 + dma-names = "tx","rx";
1636 + compatible = "hisilicon,hibvt-i2c";
1641 + dma-names = "tx","rx";
1647 + compatible = "hisilicon,hibvt-i2c";
1652 + dma-names = "tx","rx";
1658 + compatible = "hisilicon,hibvt-i2c";
1663 + dma-names = "tx","rx";
1669 + compatible = "hisilicon,hibvt-i2c";
1674 + dma-names = "tx","rx";
1680 + compatible = "hisilicon,hibvt-i2c";
1685 + dma-names = "tx","rx";
1690 + compatible = "hisilicon,hibvt-i2c";
1695 + dma-names = "tx","rx";
1701 + compatible = "hisilicon,hibvt-i2c";
1706 + dma-names = "tx","rx";
1712 + compatible = "hisilicon,hibvt-i2c";
1717 + dma-names = "tx","rx";
1725 + arm,primecell-periphid = <0x00800022>;
1729 + clock-names = "apb_pclk";
1730 + #address-cells = <1>;
1731 + #size-cells = <0>;
1734 + dma-names = "tx","rx";
1741 + arm,primecell-periphid = <0x00800022>;
1745 + clock-names = "apb_pclk";
1746 + #address-cells = <1>;
1747 + #size-cells = <0>;
1748 + num-cs = <2>;
1753 + dma-names = "tx","rx";
1760 + arm,primecell-periphid = <0x00800022>;
1764 + clock-names = "apb_pclk";
1765 + #address-cells = <1>;
1766 + #size-cells = <0>;
1769 + dma-names = "tx","rx";
1776 + compatible = "hisilicon,ipcm-interrupt";
1777 + interrupt-parent = <&gic>;
1784 + compatible = "hisilicon,hisi-femac-mdio";
1787 + clock-names = "mdio";
1788 + assigned-clocks = <&clock HI3516CV500_ETH0_CLK>;
1789 + assigned-clock-rates = <54000000>;
1791 + reset-names = "external-phy";
1792 + #address-cells = <1>;
1793 + #size-cells = <0>;
1797 + compatible = "hisilicon,hi3516cv500-femac",
1798 + "hisilicon,hisi-femac-v2";
1803 + reset-names = "mac";
1806 + fmc: flash-memory-controller@10000000 {
1807 + compatible = "hisilicon,hisi-fmc";
1809 + reg-names = "control", "memory";
1811 + max-dma-size = <0x2000>;
1812 + #address-cells = <1>;
1813 + #size-cells = <0>;
1815 + hisfc:spi-nor@0 {
1816 + compatible = "hisilicon,fmc-spi-nor";
1817 + assigned-clocks = <&clock HI3516CV500_FMC_CLK>;
1818 + assigned-clock-rates = <24000000>;
1819 + #address-cells = <1>;
1820 + #size-cells = <0>;
1823 + hisnfc:spi-nand@0 {
1824 + compatible = "hisilicon,fmc-spi-nand";
1825 + assigned-clocks = <&clock HI3516CV500_FMC_CLK>;
1826 + assigned-clock-rates = <24000000>;
1827 + #address-cells = <1>;
1828 + #size-cells = <0>;
1833 + compatible = "hisilicon,hi3516cv500-himci";
1837 + clock-names = "mmc_clk";
1839 + reset-names = "mmc_reset";
1840 + max-frequency = <100000000>;
1841 + bus-width = <4>;
1842 + cap-mmc-highspeed;
1843 + cap-mmc-hw-reset;
1844 + mmc-hs200-1_8v;
1850 + compatible = "hisilicon,hi3516cv500-himci";
1854 + clock-names = "mmc_clk";
1856 + reset-names = "mmc_reset";
1857 + max-frequency = <100000000>;
1858 + bus-width = <4>;
1859 + cap-sd-highspeed;
1860 + sd-uhs-sdr12;
1861 + sd-uhs-sdr25;
1862 + sd-uhs-sdr50;
1863 + sd-uhs-sdr104;
1864 + full-pwr-cycle;
1870 + compatible = "hisilicon,hi3516cv500-himci";
1874 + clock-names = "mmc_clk";
1876 + reset-names = "mmc_reset";
1877 + max-frequency = <100000000>;
1878 + bus-width = <4>;
1879 + cap-sd-highspeed;
1880 + sd-uhs-sdr12;
1881 + sd-uhs-sdr25;
1882 + sd-uhs-sdr50;
1883 + sd-uhs-sdr104;
1884 + full-pwr-cycle;
1889 + hidmac: hidma-controller@10060000 {
1890 + compatible = "hisilicon,hisi-dmac";
1894 + clock-names = "dmac_clk";
1896 + reset-names = "dma-reset";
1897 + #dma-cells = <2>;
1902 + compatible = "hisilicon,hisi-usb-phy";
1904 + #phy-cells = <0>;
1909 + compatible = "generic-xhci";
1912 + usb2-lpm-disable;
1920 + interrupt-names = "peripheral";
1921 + maximum-speed = "high-speed";
1930 + clock-names = "apb_pclk";
1931 + #gpio-cells = <2>;
1940 + clock-names = "apb_pclk";
1941 + #gpio-cells = <2>;
1950 + clock-names = "apb_pclk";
1951 + #gpio-cells = <2>;
1960 + clock-names = "apb_pclk";
1961 + #gpio-cells = <2>;
1970 + clock-names = "apb_pclk";
1971 + #gpio-cells = <2>;
1980 + clock-names = "apb_pclk";
1981 + #gpio-cells = <2>;
1990 + clock-names = "apb_pclk";
1991 + #gpio-cells = <2>;
2000 + clock-names = "apb_pclk";
2001 + #gpio-cells = <2>;
2010 + clock-names = "apb_pclk";
2011 + #gpio-cells = <2>;
2020 + clock-names = "apb_pclk";
2021 + #gpio-cells = <2>;
2030 + clock-names = "apb_pclk";
2031 + #gpio-cells = <2>;
2040 + clock-names = "apb_pclk";
2041 + #gpio-cells = <2>;
2046 + compatible = "hisilicon,hisi-cipher";
2048 + reg-names = "cipher";
2050 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
2056 + #address-cells = <1>;
2057 + #size-cells = <1>;
2058 + compatible = "simple-bus";
2059 + interrupt-parent = <&gic>;
2071 + compatible = "hisilicon,hisi-sys";
2074 + reg-names = "crg", "sys", "ddr", "misc";
2078 + compatible = "hisilicon,hisi-mipi";
2080 + reg-names = "mipi_rx";
2082 + interrupt-names = "mipi_rx";
2086 + compatible = "hisilicon,hisi-mipi_tx";
2088 + reg-names = "mipi_tx";
2090 + interrupt-names = "mipi_tx";
2094 + compatible = "hisilicon,hisi-vi";
2096 + reg-names = "VI_CAP0", "VI_PROC0";
2098 + interrupt-names = "VI_CAP0", "VI_PROC0";
2102 + compatible = "hisilicon,hisi-isp";
2104 + reg-names = "ISP";
2106 + interrupt-names = "ISP";
2110 + compatible = "hisilicon,hisi-vpss";
2112 + reg-names = "vpss0";
2114 + interrupt-names = "vpss0";
2118 + compatible = "hisilicon,hisi-vgs";
2120 + reg-names = "vgs0";
2122 + interrupt-names = "vgs0";
2126 + compatible = "hisilicon,hisi-vo";
2128 + reg-names = "vo";
2130 + interrupt-names = "vo";
2134 + compatible = "hisilicon,hisi-hifb";
2136 + reg-names = "hifb", "sys";
2138 + interrupt-names = "hifb", "hifb_soft";
2142 + compatible = "hisilicon,hisi-tde";
2144 + reg-names = "tde";
2146 + interrupt-names = "tde_osr_isr";
2150 + compatible = "hisilicon,hisi-gyro-dis";
2154 + compatible = "hisilicon,hisi-gdc";
2156 + reg-names = "gdc", "nnie0";
2158 + interrupt-names = "gdc", "nnie0";
2162 + compatible = "hisilicon,hisi-gzip";
2164 + reg-names = "gzip";
2166 + interrupt-names = "gzip";
2170 + compatible = "hisilicon,hisi-jpegd";
2172 + reg-names = "jpegd";
2174 + interrupt-names = "jpegd";
2178 + compatible = "hisilicon,hisi-vedu";
2180 + reg-names = "vedu0", "jpge";
2182 + interrupt-names = "vedu0","jpge";
2186 + compatible = "hisilicon,hisi-venc";
2190 + compatible = "hisilicon,hisi-scd";
2192 + reg-names = "scd";
2194 + interrupt-names = "scd";
2198 + compatible = "hisilicon,hisi-hdmi";
2200 + reg-names = "hdmi0";
2204 + compatible = "hisilicon,hisi-aiao";
2206 + reg-names = "aiao","acodec","crg";
2208 + interrupt-names = "AIO";
2212 + compatible = "hisilicon,hisi-nnie";
2214 + reg-names = "nnie0","gdc";
2216 + interrupt-names = "nnie0","gdc";
2220 + compatible = "hisilicon,hisi-ive";
2222 + reg-names = "ive";
2224 + interrupt-names = "ive";
2228 + compatible = "hisilicon,hisi-lsadc";
2232 + reset-names = "lsadc-crg";
2242 + compatible = "hisilicon,hi35xx-rtc";
2255 + reg-names = "vgs", "vpss0", "scd", "aiao", …
2257 + interrupt-names = "scd","new", "VI_CAP0", "VI_PROC0","vpss0","vgs0", "vo", "vedu0", "jpge",…
2261 diff --git a/arch/arm/boot/dts/hi3516dv200-demb.dts b/arch/arm/boot/dts/hi3516dv200-demb.dts
2264 --- /dev/null
2265 +++ b/arch/arm/boot/dts/hi3516dv200-demb.dts
2266 @@ -0,0 +1,175 @@
2268 + * Copyright (c) 2013-2014 Linaro Ltd.
2269 + * Copyright (c) 2015-2019 HiSilicon Technologies Co., Ltd.
2286 +/dts-v1/;
2313 + clock-frequency = <100000>;
2318 + clock-frequency = <100000>;
2323 + clock-frequency = <100000>;
2328 + num-cs = <1>;
2334 + pl022,com-mode = <0>;
2335 + spi-max-frequency = <25000000>;
2341 + num-cs = <2>;
2347 + pl022,com-mode = <0>;
2348 + spi-max-frequency = <25000000>;
2354 + pl022,com-mode = <0>;
2355 + spi-max-frequency = <25000000>;
2364 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
2365 + phy0: ethernet-phy@1 {
2371 + mac-address = [00 00 00 00 00 00];
2372 + phy-mode = "mii";
2373 + phy-handle = <&phy0>;
2379 + compatible = "jedec,spi-nor";
2381 + spi-max-frequency = <160000000>;
2387 + compatible = "jedec,spi-nand";
2389 + spi-max-frequency = <160000000>;
2442 diff --git a/arch/arm/boot/dts/hi3516dv200.dtsi b/arch/arm/boot/dts/hi3516dv200.dtsi
2445 --- /dev/null
2447 @@ -0,0 +1,700 @@
2449 + * Copyright (c) 2013-2014 Linaro Ltd.
2450 + * Copyright (c) 2015-2019 HiSilicon Technologies Co., Ltd.
2468 +#include <dt-bindings/clock/hi3516dv200-clock.h>
2496 + #address-cells = <1>;
2497 + #size-cells = <0>;
2498 + enable-method = "hisilicon,hi3516dv200";
2502 + compatible = "arm,cortex-a7";
2503 + clock-frequency = <HI3516DV200_FIXED_1000M>;
2510 + compatible = "hisilicon,hi3516dv200-clock", "syscon";
2511 + #address-cells = <1>;
2512 + #size-cells = <1>;
2513 + #clock-cells = <1>;
2514 + #reset-cells = <2>;
2518 + gic: interrupt-controller@10300000 {
2519 + compatible = "arm,cortex-a7-gic";
2520 + #interrupt-cells = <3>;
2521 + #address-cells = <0>;
2522 + interrupt-controller;
2528 + compatible = "arm,armv7-timer";
2529 + interrupt-parent = <&gic>;
2532 + clock-frequency = <50000000>;
2536 + #address-cells = <1>;
2537 + #size-cells = <1>;
2538 + compatible = "simple-bus";
2539 + interrupt-parent = <&gic>;
2543 + compatible = "fixed-clock";
2544 + #clock-cells = <0>;
2545 + clock-frequency = <3000000>;
2549 + compatible = "fixed-clock";
2550 + #clock-cells = <0>;
2551 + clock-frequency = <50000000>;
2555 + compatible = "arm,cortex-a7-pmu";
2559 + hiedmacv310_0: hiedma-controller@100B0000 {
2564 + clock-names = "apb_pclk", "axi_aclk";
2565 + clock-cells = <2>;
2567 + reset-names = "dma-reset";
2568 + dma-requests = <32>;
2569 + dma-channels = <4>;
2571 + #dma-cells = <2>;
2577 + hiedmacv310_0: hiedma-controller@100B0000 {
2582 + clock-names = "apb_pclk", "axi_aclk";
2583 + clock-cells = <2>;
2585 + reset-names = "dma-reset";
2586 + dma-requests = <32>;
2587 + dma-channels = <4>;
2589 + #dma-cells = <2>;
2595 + sysctrl: system-controller@12020000 {
2598 + reboot-offset = <0x4>;
2599 + #clock-cells = <1>;
2603 + #address-cells = <1>;
2604 + #size-cells = <1>;
2605 + compatible = "arm,amba-bus";
2614 + clock-names = "timer00", "timer01", "apb_pclk";
2624 + clock-names = "timer10", "timer11", "apb_pclk";
2633 + clock-names = "apb_pclk";
2642 + clock-names = "apb_pclk";
2645 + dma-names = "tx","rx";
2655 + clock-names = "apb_pclk";
2658 + dma-names = "tx","rx";
2666 + compatible = "hisilicon,hi3516dv200-i2c",
2667 + "hisilicon,hibvt-i2c";
2674 + compatible = "hisilicon,hi3516dv200-i2c",
2675 + "hisilicon,hibvt-i2c";
2682 + compatible = "hisilicon,hi3516dv200-i2c",
2683 + "hisilicon,hibvt-i2c";
2691 + arm,primecell-periphid = <0x00800022>;
2695 + clock-names = "apb_pclk";
2696 + #address-cells = <1>;
2697 + #size-cells = <0>;
2700 + dma-names = "tx","rx";
2707 + arm,primecell-periphid = <0x00800022>;
2711 + clock-names = "apb_pclk";
2712 + #address-cells = <1>;
2713 + #size-cells = <0>;
2714 + num-cs = <2>;
2719 + dma-names = "tx","rx";
2725 + compatible = "hisilicon,hisi-femac-mdio";
2728 + clock-names = "mdio";
2730 + reset-names = "internal-phy";
2731 + #address-cells = <1>;
2732 + #size-cells = <0>;
2736 + compatible = "hisilicon,hi3516dv200-femac",
2737 + "hisilicon,hisi-femac-v2";
2742 + reset-names = "mac";
2745 + fmc: flash-memory-controller@10000000 {
2746 + compatible = "hisilicon,hisi-fmc";
2748 + reg-names = "control", "memory";
2750 + max-dma-size = <0x2000>;
2751 + #address-cells = <1>;
2752 + #size-cells = <0>;
2754 + hisfc:spi-nor@0 {
2755 + compatible = "hisilicon,fmc-spi-nor";
2756 + assigned-clocks = <&clock HI3516DV200_FMC_CLK>;
2757 + assigned-clock-rates = <24000000>;
2758 + #address-cells = <1>;
2759 + #size-cells = <0>;
2762 + hisnfc:spi-nand@0 {
2763 + compatible = "hisilicon,fmc-spi-nand";
2764 + assigned-clocks = <&clock HI3516DV200_FMC_CLK>;
2765 + assigned-clock-rates = <24000000>;
2766 + #address-cells = <1>;
2767 + #size-cells = <0>;
2771 + iocfg_ctrl: iocfg-controller@100c0000 {
2772 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
2781 + clock-names = "mmc_clk";
2783 + reset-names = "crg_reset", "dll_reset";
2784 + max-frequency = <90000000>;
2787 + bus-width = <8>;
2788 + cap-mmc-highspeed;
2789 + cap-mmc-hw-reset;
2790 + cap-sd-highspeed;
2791 + mmc-hs200-1_8v;
2792 + mmc-hs400-1_8v;
2793 + mmc-hs400-enhanced-strobe;
2794 + full-pwr-cycle;
2795 + disable-wp;
2805 + clock-names = "mmc_clk";
2807 + reset-names = "crg_reset", "dll_reset";
2808 + max-frequency = <50000000>;
2811 + bus-width = <4>;
2812 + cap-sd-highspeed;
2813 + full-pwr-cycle;
2814 + disable-wp;
2819 + usb2_phy0: phy2-0 {
2820 + compatible = "hisilicon,hixvp-usb2-phy";
2827 + clock-names = "clk_u2phy_apb_ref",
2832 + reset-names = "phy_por_reset",
2868 + #phy-cells = <0>;
2871 + usbdrd3_0: usb3-0{
2875 + #address-cells = <1>;
2876 + #size-cells = <1>;
2883 + clock-names = "usb2_bus_clk",
2887 + reset-names = "vcc_reset";
2894 + interrupt-names = "peripheral";
2896 + phy-names = "usb2-phy";
2897 + maximum-speed = "high-speed";
2902 + snps,usb2-lpm-disable;
2911 + clock-names = "apb_pclk";
2912 + #gpio-cells = <2>;
2921 + clock-names = "apb_pclk";
2922 + #gpio-cells = <2>;
2931 + clock-names = "apb_pclk";
2932 + #gpio-cells = <2>;
2941 + clock-names = "apb_pclk";
2942 + #gpio-cells = <2>;
2951 + clock-names = "apb_pclk";
2952 + #gpio-cells = <2>;
2961 + clock-names = "apb_pclk";
2962 + #gpio-cells = <2>;
2971 + clock-names = "apb_pclk";
2972 + #gpio-cells = <2>;
2981 + clock-names = "apb_pclk";
2982 + #gpio-cells = <2>;
2991 + clock-names = "apb_pclk";
2992 + #gpio-cells = <2>;
3001 + clock-names = "apb_pclk";
3002 + #gpio-cells = <2>;
3007 + compatible = "hisilicon,hisi-cipher";
3009 + reg-names = "cipher";
3011 + interrupt-names = "cipher", "hash";
3015 + compatible = "hisilicon,hi35xx-rtc";
3021 + compatible = "hisilicon,hisi-lsadc";
3024 + interrupt-names = "hi_adc";
3026 + reset-names = "lsadc-crg";
3033 + reg-names = "hi_wdg";
3035 + interrupt-names = "hi_wdg";
3041 + #address-cells = <1>;
3042 + #size-cells = <1>;
3043 + compatible = "simple-bus";
3044 + interrupt-parent = <&gic>;
3052 + compatible = "hisilicon,hisi-sys";
3056 + compatible = "hisilicon,hisi-mipi";
3058 + reg-names = "mipi_rx";
3060 + interrupt-names = "mipi_rx";
3064 + compatible = "hisilicon,hisi-vi";
3066 + reg-names = "VI_CAP0", "VI_PROC0";
3068 + interrupt-names = "VI_CAP0", "VI_PROC0";
3072 + compatible = "hisilicon,hisi-isp";
3074 + reg-names = "ISP";
3076 + interrupt-names = "ISP";
3080 + compatible = "hisilicon,hisi-vpss";
3082 + reg-names = "vpss0";
3084 + interrupt-names = "vpss0";
3088 + compatible = "hisilicon,hisi-vo";
3090 + reg-names = "vo";
3092 + interrupt-names = "vo";
3096 + compatible = "hisilicon,hisi-hifb";
3098 + reg-names = "hifb";
3100 + interrupt-names = "hifb";
3104 + compatible = "hisilicon,hisi-vgs";
3106 + reg-names = "vgs0";
3108 + interrupt-names = "vgs0";
3112 + compatible = "hisilicon,hisi-gzip";
3114 + reg-names = "gzip";
3116 + interrupt-names = "gzip";
3120 + compatible = "hisilicon,hisi-vedu";
3122 + reg-names = "vedu0", "jpge";
3124 + interrupt-names = "vedu0","jpge";
3128 + compatible = "hisilicon,hisi-venc";
3132 + compatible = "hisilicon,hisi-aiao";
3134 + reg-names = "aiao","acodec";
3136 + interrupt-names = "AIO";
3140 + compatible = "hisilicon,hisi-ive";
3142 + reg-names = "ive";
3144 + interrupt-names = "ive";
3148 diff --git a/arch/arm/boot/dts/hi3516dv300-demb.dts b/arch/arm/boot/dts/hi3516dv300-demb.dts
3151 --- /dev/null
3152 +++ b/arch/arm/boot/dts/hi3516dv300-demb.dts
3153 @@ -0,0 +1,270 @@
3155 + * Copyright (c) 2013-2014 Linaro Ltd.
3156 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
3173 +/dts-v1/;
3193 + dev = "/dev/block/platform/soc/f9830000.himciv200.MMC/by-name/system";
3201 + //dev = "/dev/block/by-name/vendor";
3202 + //dev = "/dev/block/platform/soc/100f0000.eMMC/by-name/vendor";
3203 + //dev = "/dev/block/platform/soc/10100000.eMMC/by-name/vendor";
3204 + dev = "/dev/block/platform/soc/10100000.himci.eMMC/by-name/vendor";
3206 + //dev = "/dev/block/platform/soc/f9830000.himciv200.MMC/by-name/vendor";
3226 + clock-frequency = <100000>;
3231 + clock-frequency = <100000>;
3236 + clock-frequency = <100000>;
3241 + clock-frequency = <100000>;
3246 + clock-frequency = <100000>;
3251 + clock-frequency = <100000>;
3256 + clock-frequency = <100000>;
3261 + clock-frequency = <100000>;
3266 + num-cs = <1>;
3272 + pl022,com-mode = <0>;
3273 + spi-max-frequency = <25000000>;
3278 + num-cs = <2>;
3284 + pl022,com-mode = <0>;
3285 + spi-max-frequency = <25000000>;
3291 + pl022,com-mode = <0>;
3292 + spi-max-frequency = <25000000>;
3297 + num-cs = <1>;
3303 + pl022,com-mode = <0>;
3304 + spi-max-frequency = <25000000>;
3310 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
3311 + phy0: ethernet-phy@1 {
3317 + mac-address = [00 00 00 00 00 00];
3318 + phy-mode = "rmii";
3319 + phy-handle = <&phy0>;
3325 + compatible = "jedec,spi-nor";
3327 + spi-max-frequency = <160000000>;
3333 + compatible = "jedec,spi-nand";
3335 + spi-max-frequency = <160000000>;
3424 diff --git a/arch/arm/boot/dts/hi3516dv300.dtsi b/arch/arm/boot/dts/hi3516dv300.dtsi
3427 --- /dev/null
3429 @@ -0,0 +1,906 @@
3431 + * Copyright (c) 2013-2014 Linaro Ltd.
3432 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
3450 +#include "clock/hi3516dv300-clock.h"
3484 + #address-cells = <1>;
3485 + #size-cells = <0>;
3486 + enable-method = "hisilicon,hi3516dv300";
3490 + compatible = "arm,cortex-a7";
3491 + clock-frequency = <HI3516DV300_FIXED_1000M>;
3497 + compatible = "arm,cortex-a7";
3498 + clock-frequency = <HI3516DV300_FIXED_1000M>;
3505 + compatible = "hisilicon,hi3516dv300-clock";
3506 + #address-cells = <1>;
3507 + #size-cells = <1>;
3508 + #clock-cells = <1>;
3509 + #reset-cells = <2>;
3513 + gic: interrupt-controller@10300000 {
3514 + compatible = "arm,cortex-a7-gic";
3515 + #interrupt-cells = <3>;
3516 + #address-cells = <0>;
3517 + interrupt-controller;
3523 + compatible = "arm,armv7-timer";
3524 + interrupt-parent = <&gic>;
3527 + clock-frequency = <50000000>;
3531 + #address-cells = <1>;
3532 + #size-cells = <1>;
3533 + compatible = "simple-bus";
3534 + interrupt-parent = <&gic>;
3538 + compatible = "fixed-clock";
3539 + #clock-cells = <0>;
3540 + clock-frequency = <3000000>;
3544 + compatible = "fixed-clock";
3545 + #clock-cells = <0>;
3546 + clock-frequency = <50000000>;
3550 + compatible = "arm,cortex-a7-pmu";
3554 + hiedmacv310_0: hiedma-controller@10060000 {
3559 + clock-names = "apb_pclk", "axi_aclk";
3560 + #clock-cells = <2>;
3562 + reset-names = "dma-reset";
3563 + dma-requests = <32>;
3564 + dma-channels = <8>;
3566 + #dma-cells = <2>;
3571 + hiedmacv310_0: hiedma-controller@10060000 {
3576 + clock-names = "apb_pclk", "axi_aclk";
3577 + #clock-cells = <2>;
3579 + reset-names = "dma-reset";
3580 + dma-requests = <32>;
3581 + dma-channels = <8>;
3583 + #dma-cells = <2>;
3588 + sysctrl: system-controller@12020000 {
3591 + reboot-offset = <0x4>;
3592 + #clock-cells = <1>;
3596 + #address-cells = <1>;
3597 + #size-cells = <1>;
3598 + compatible = "arm,amba-bus";
3612 + clock-names = "timer0", "timer1", "timer2";
3621 + clock-names = "timer20", "timer21", "apb_pclk";
3626 + compatible = "arm,sp805-wdt", "arm,primecell";
3627 + arm,primecell-periphid = <0x00141805>;
3630 + clock-names = "wdog_clk", "apb_pclk";
3639 + clock-names = "apb_pclk";
3648 + clock-names = "apb_pclk";
3651 + dma-names = "tx","rx";
3661 + clock-names = "apb_pclk";
3664 + dma-names = "tx","rx";
3674 + clock-names = "apb_pclk";
3677 + dma-names = "tx","rx";
3687 + clock-names = "apb_pclk";
3690 + dma-names = "tx","rx";
3699 + compatible = "hisilicon,hibvt-i2c";
3704 + dma-names = "tx","rx";
3710 + compatible = "hisilicon,hibvt-i2c";
3715 + dma-names = "tx","rx";
3721 + compatible = "hisilicon,hibvt-i2c";
3726 + dma-names = "tx","rx";
3732 + compatible = "hisilicon,hibvt-i2c";
3737 + dma-names = "tx","rx";
3743 + compatible = "hisilicon,hibvt-i2c";
3748 + dma-names = "tx","rx";
3753 + compatible = "hisilicon,hibvt-i2c";
3758 + dma-names = "tx","rx";
3764 + compatible = "hisilicon,hibvt-i2c";
3769 + dma-names = "tx","rx";
3775 + compatible = "hisilicon,hibvt-i2c";
3780 + dma-names = "tx","rx";
3788 + arm,primecell-periphid = <0x00800022>;
3792 + clock-names = "apb_pclk";
3793 + #address-cells = <1>;
3794 + #size-cells = <0>;
3797 + dma-names = "tx","rx";
3804 + arm,primecell-periphid = <0x00800022>;
3808 + clock-names = "apb_pclk";
3809 + #address-cells = <1>;
3810 + #size-cells = <0>;
3811 + num-cs = <2>;
3816 + dma-names = "tx","rx";
3823 + arm,primecell-periphid = <0x00800022>;
3827 + clock-names = "apb_pclk";
3828 + #address-cells = <1>;
3829 + #size-cells = <0>;
3832 + dma-names = "tx","rx";
3839 + compatible = "hisilicon,ipcm-interrupt";
3840 + interrupt-parent = <&gic>;
3847 + compatible = "hisilicon,hisi-femac-mdio";
3850 + clock-names = "mdio";
3851 + assigned-clocks = <&clock HI3516DV300_ETH0_CLK>;
3852 + assigned-clock-rates = <54000000>;
3854 + reset-names = "external-phy";
3855 + #address-cells = <1>;
3856 + #size-cells = <0>;
3860 + compatible = "hisilicon,hi3516dv300-femac",
3861 + "hisilicon,hisi-femac-v2";
3866 + reset-names = "mac";
3869 + fmc: flash-memory-controller@10000000 {
3870 + compatible = "hisilicon,hisi-fmc";
3872 + reg-names = "control", "memory";
3874 + max-dma-size = <0x2000>;
3875 + #address-cells = <1>;
3876 + #size-cells = <0>;
3878 + hisfc:spi-nor@0 {
3879 + compatible = "hisilicon,fmc-spi-nor";
3880 + assigned-clocks = <&clock HI3516DV300_FMC_CLK>;
3881 + assigned-clock-rates = <24000000>;
3882 + #address-cells = <1>;
3883 + #size-cells = <0>;
3886 + hisnfc:spi-nand@0 {
3887 + compatible = "hisilicon,fmc-spi-nand";
3888 + assigned-clocks = <&clock HI3516DV300_FMC_CLK>;
3889 + assigned-clock-rates = <24000000>;
3890 + #address-cells = <1>;
3891 + #size-cells = <0>;
3896 + compatible = "hisilicon,hi3516dv300-himci";
3900 + clock-names = "mmc_clk";
3902 + reset-names = "mmc_reset";
3903 + max-frequency = <100000000>;
3904 + bus-width = <4>;
3905 + cap-mmc-highspeed;
3906 + cap-mmc-hw-reset;
3912 + compatible = "hisilicon,hi3516dv300-himci";
3916 + clock-names = "mmc_clk";
3918 + reset-names = "mmc_reset";
3919 + max-frequency = <100000000>;
3920 + bus-width = <4>;
3921 + cap-sd-highspeed;
3922 + sd-uhs-sdr12;
3923 + sd-uhs-sdr25;
3924 + sd-uhs-sdr50;
3925 + sd-uhs-sdr104;
3926 + full-pwr-cycle;
3932 + compatible = "hisilicon,hi3516dv300-himci";
3936 + clock-names = "mmc_clk";
3938 + reset-names = "mmc_reset";
3939 + max-frequency = <100000000>;
3940 + bus-width = <4>;
3941 + cap-sd-highspeed;
3942 + cap-sdio-irq;
3943 + full-pwr-cycle;
3948 + hidmac: hidma-controller@10060000 {
3949 + compatible = "hisilicon,hisi-dmac";
3953 + clock-names = "dmac_clk";
3955 + reset-names = "dma-reset";
3956 + #dma-cells = <2>;
3961 + compatible = "hisilicon,hisi-usb-phy";
3963 + #phy-cells = <0>;
3968 + compatible = "generic-xhci";
3971 + usb2-lpm-disable;
3979 + interrupt-names = "peripheral";
3980 + maximum-speed = "high-speed";
3989 + clock-names = "apb_pclk";
3990 + #gpio-cells = <2>;
3999 + clock-names = "apb_pclk";
4000 + #gpio-cells = <2>;
4009 + clock-names = "apb_pclk";
4010 + #gpio-cells = <2>;
4019 + clock-names = "apb_pclk";
4020 + #gpio-cells = <2>;
4029 + clock-names = "apb_pclk";
4030 + #gpio-cells = <2>;
4039 + clock-names = "apb_pclk";
4040 + #gpio-cells = <2>;
4049 + clock-names = "apb_pclk";
4050 + #gpio-cells = <2>;
4059 + clock-names = "apb_pclk";
4060 + #gpio-cells = <2>;
4069 + clock-names = "apb_pclk";
4070 + #gpio-cells = <2>;
4079 + clock-names = "apb_pclk";
4080 + #gpio-cells = <2>;
4089 + clock-names = "apb_pclk";
4090 + #gpio-cells = <2>;
4099 + clock-names = "apb_pclk";
4100 + #gpio-cells = <2>;
4105 + compatible = "hisilicon,hisi-cipher";
4107 + reg-names = "cipher";
4109 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
4115 + compatible = "hisilicon,hi-drm";
4119 + #address-cells = <1>;
4120 + #size-cells = <1>;
4121 + compatible = "simple-bus";
4122 + interrupt-parent = <&gic>;
4134 + compatible = "hisilicon,hisi-sys";
4137 + reg-names = "crg", "sys", "ddr", "misc";
4141 + compatible = "hisilicon,hisi-mipi";
4143 + reg-names = "mipi_rx";
4145 + interrupt-names = "mipi_rx";
4149 + compatible = "hisilicon,hisi-mipi_tx";
4151 + reg-names = "mipi_tx";
4153 + interrupt-names = "mipi_tx";
4157 + compatible = "hisilicon,hisi-vi";
4159 + reg-names = "VI_CAP0", "VI_PROC0";
4161 + interrupt-names = "VI_CAP0", "VI_PROC0";
4165 + compatible = "hisilicon,hisi-isp";
4167 + reg-names = "ISP";
4169 + interrupt-names = "ISP";
4173 + compatible = "hisilicon,hisi-vpss";
4175 + reg-names = "vpss0";
4177 + interrupt-names = "vpss0";
4181 + compatible = "hisilicon,hisi-vgs";
4183 + reg-names = "vgs0";
4185 + interrupt-names = "vgs0";
4189 + compatible = "hisilicon,hisi-vo";
4191 + reg-names = "vo";
4193 + interrupt-names = "vo";
4197 + compatible = "hisilicon,hisi-hifb";
4199 + reg-names = "hifb", "sys";
4201 + interrupt-names = "hifb", "hifb_soft";
4205 + compatible = "hisilicon,hisi-tde";
4207 + reg-names = "tde";
4209 + interrupt-names = "tde_osr_isr";
4213 + compatible = "hisilicon,hisi-gyro-dis";
4217 + compatible = "hisilicon,hisi-gdc";
4219 + reg-names = "gdc", "nnie0";
4221 + interrupt-names = "gdc", "nnie0";
4225 + compatible = "hisilicon,hisi-gzip";
4227 + reg-names = "gzip";
4229 + interrupt-names = "gzip";
4233 + compatible = "hisilicon,hisi-jpegd";
4235 + reg-names = "jpegd";
4237 + interrupt-names = "jpegd";
4241 + compatible = "hisilicon,hisi-vedu";
4243 + reg-names = "vedu0", "jpge";
4245 + interrupt-names = "vedu0","jpge";
4249 + compatible = "hisilicon,hisi-venc";
4253 + compatible = "hisilicon,hisi-scd";
4255 + reg-names = "scd";
4257 + interrupt-names = "scd";
4261 + compatible = "hisilicon,hisi-hdmi";
4263 + reg-names = "hdmi0";
4267 + compatible = "hisilicon,hisi-aiao";
4269 + reg-names = "aiao","acodec","crg";
4271 + interrupt-names = "AIO";
4275 + compatible = "hisilicon,hisi-nnie";
4277 + reg-names = "nnie0","gdc";
4279 + interrupt-names = "nnie0","gdc";
4283 + compatible = "hisilicon,hisi-ive";
4285 + reg-names = "ive";
4287 + interrupt-names = "ive";
4291 + compatible = "hisilicon,hisi-lsadc";
4295 + reset-names = "lsadc-crg";
4305 + compatible = "hisilicon,hi35xx-rtc";
4330 + reg-names = "vgs", "vpss0", "scd", "aiao", …
4332 + interrupt-names = "scd","new", "VI_CAP0", "VI_PROC0","vpss0","vgs0", "vo", "vedu0", "jpge",…
4336 diff --git a/arch/arm/boot/dts/hi3516ev200-demb.dts b/arch/arm/boot/dts/hi3516ev200-demb.dts
4339 --- /dev/null
4340 +++ b/arch/arm/boot/dts/hi3516ev200-demb.dts
4341 @@ -0,0 +1,166 @@
4343 + * Copyright (c) 2013-2014 Linaro Ltd.
4344 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
4361 +/dts-v1/;
4388 + clock-frequency = <100000>;
4393 + clock-frequency = <100000>;
4398 + clock-frequency = <100000>;
4403 + num-cs = <1>;
4409 + pl022,com-mode = <0>;
4410 + spi-max-frequency = <25000000>;
4416 + num-cs = <2>;
4422 + pl022,com-mode = <0>;
4423 + spi-max-frequency = <25000000>;
4429 + pl022,com-mode = <0>;
4430 + spi-max-frequency = <25000000>;
4439 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
4440 + phy0: ethernet-phy@1 {
4446 + mac-address = [00 00 00 00 00 00];
4447 + phy-mode = "mii";
4448 + phy-handle = <&phy0>;
4454 + compatible = "jedec,spi-nor";
4456 + spi-max-frequency = <160000000>;
4462 + compatible = "jedec,spi-nand";
4464 + spi-max-frequency = <160000000>;
4508 diff --git a/arch/arm/boot/dts/hi3516ev200.dtsi b/arch/arm/boot/dts/hi3516ev200.dtsi
4511 --- /dev/null
4513 @@ -0,0 +1,678 @@
4515 + * Copyright (c) 2013-2014 Linaro Ltd.
4516 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
4534 +#include <dt-bindings/clock/hi3516ev200-clock.h>
4560 + #address-cells = <1>;
4561 + #size-cells = <0>;
4562 + enable-method = "hisilicon,hi3516ev200";
4566 + compatible = "arm,cortex-a7";
4567 + clock-frequency = <HI3516EV200_FIXED_1000M>;
4574 + compatible = "hisilicon,hi3516ev200-clock", "syscon";
4575 + #address-cells = <1>;
4576 + #size-cells = <1>;
4577 + #clock-cells = <1>;
4578 + #reset-cells = <2>;
4582 + gic: interrupt-controller@10300000 {
4583 + compatible = "arm,cortex-a7-gic";
4584 + #interrupt-cells = <3>;
4585 + #address-cells = <0>;
4586 + interrupt-controller;
4592 + compatible = "arm,armv7-timer";
4593 + interrupt-parent = <&gic>;
4596 + clock-frequency = <50000000>;
4600 + #address-cells = <1>;
4601 + #size-cells = <1>;
4602 + compatible = "simple-bus";
4603 + interrupt-parent = <&gic>;
4607 + compatible = "fixed-clock";
4608 + #clock-cells = <0>;
4609 + clock-frequency = <3000000>;
4613 + compatible = "fixed-clock";
4614 + #clock-cells = <0>;
4615 + clock-frequency = <50000000>;
4619 + compatible = "arm,cortex-a7-pmu";
4623 + hiedmacv310_0: hiedma-controller@100B0000 {
4628 + clock-names = "apb_pclk", "axi_aclk";
4629 + clock-cells = <2>;
4631 + reset-names = "dma-reset";
4632 + dma-requests = <32>;
4633 + dma-channels = <4>;
4635 + #dma-cells = <2>;
4640 + hiedmacv310_0: hiedma-controller@100B0000 {
4645 + clock-names = "apb_pclk", "axi_aclk";
4646 + clock-cells = <2>;
4648 + reset-names = "dma-reset";
4649 + dma-requests = <32>;
4650 + dma-channels = <4>;
4652 + #dma-cells = <2>;
4656 + sysctrl: system-controller@12020000 {
4659 + reboot-offset = <0x4>;
4660 + #clock-cells = <1>;
4664 + #address-cells = <1>;
4665 + #size-cells = <1>;
4666 + compatible = "arm,amba-bus";
4675 + clock-names = "timer00", "timer01", "apb_pclk";
4685 + clock-names = "timer10", "timer11", "apb_pclk";
4694 + clock-names = "apb_pclk";
4703 + clock-names = "apb_pclk";
4706 + dma-names = "tx","rx";
4716 + clock-names = "apb_pclk";
4719 + dma-names = "tx","rx";
4727 + compatible = "hisilicon,hi3516ev200-i2c",
4728 + "hisilicon,hibvt-i2c";
4735 + compatible = "hisilicon,hi3516ev200-i2c",
4736 + "hisilicon,hibvt-i2c";
4743 + compatible = "hisilicon,hi3516ev200-i2c",
4744 + "hisilicon,hibvt-i2c";
4752 + arm,primecell-periphid = <0x00800022>;
4756 + clock-names = "apb_pclk";
4757 + #address-cells = <1>;
4758 + #size-cells = <0>;
4761 + dma-names = "tx","rx";
4768 + arm,primecell-periphid = <0x00800022>;
4772 + clock-names = "apb_pclk";
4773 + #address-cells = <1>;
4774 + #size-cells = <0>;
4775 + num-cs = <2>;
4780 + dma-names = "tx","rx";
4786 + compatible = "hisilicon,hisi-femac-mdio";
4789 + clock-names = "mdio";
4791 + reset-names = "internal-phy";
4792 + #address-cells = <1>;
4793 + #size-cells = <0>;
4797 + compatible = "hisilicon,hi3516ev200-femac",
4798 + "hisilicon,hisi-femac-v2";
4803 + reset-names = "mac";
4806 + fmc: flash-memory-controller@10000000 {
4807 + compatible = "hisilicon,hisi-fmc";
4809 + reg-names = "control", "memory";
4811 + max-dma-size = <0x2000>;
4812 + #address-cells = <1>;
4813 + #size-cells = <0>;
4815 + hisfc:spi-nor@0 {
4816 + compatible = "hisilicon,fmc-spi-nor";
4817 + assigned-clocks = <&clock HI3516EV200_FMC_CLK>;
4818 + assigned-clock-rates = <24000000>;
4819 + #address-cells = <1>;
4820 + #size-cells = <0>;
4823 + hisnfc:spi-nand@0 {
4824 + compatible = "hisilicon,fmc-spi-nand";
4825 + assigned-clocks = <&clock HI3516EV200_FMC_CLK>;
4826 + assigned-clock-rates = <24000000>;
4827 + #address-cells = <1>;
4828 + #size-cells = <0>;
4832 + iocfg_ctrl: iocfg-controller@100c0000 {
4833 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
4837 + iocfg_ctrl2: iocfg-controller2@112c0000 {
4838 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
4847 + clock-names = "mmc_clk";
4849 + reset-names = "crg_reset", "dll_reset";
4850 + max-frequency = <150000000>;
4853 + bus-width = <4>;
4854 + cap-mmc-highspeed;
4855 + cap-mmc-hw-reset;
4856 + cap-sd-highspeed;
4857 + mmc-hs200-1_8v;
4858 + full-pwr-cycle;
4859 + disable-wp;
4869 + clock-names = "mmc_clk";
4871 + reset-names = "crg_reset", "dll_reset";
4872 + max-frequency = <50000000>;
4875 + bus-width = <4>;
4876 + cap-sd-highspeed;
4877 + full-pwr-cycle;
4878 + disable-wp;
4883 + usb2_phy0: phy2-0 {
4884 + compatible = "hisilicon,hixvp-usb2-phy";
4891 + clock-names = "clk_u2phy_apb_ref",
4896 + reset-names = "phy_por_reset",
4932 + #phy-cells = <0>;
4935 + usbdrd3_0: usb3-0{
4939 + #address-cells = <1>;
4940 + #size-cells = <1>;
4947 + clock-names = "usb2_bus_clk",
4951 + reset-names = "vcc_reset";
4958 + interrupt-names = "peripheral";
4960 + phy-names = "usb2-phy";
4961 + maximum-speed = "high-speed";
4966 + snps,usb2-lpm-disable;
4975 + clock-names = "apb_pclk";
4976 + #gpio-cells = <2>;
4985 + clock-names = "apb_pclk";
4986 + #gpio-cells = <2>;
4995 + clock-names = "apb_pclk";
4996 + #gpio-cells = <2>;
5005 + clock-names = "apb_pclk";
5006 + #gpio-cells = <2>;
5015 + clock-names = "apb_pclk";
5016 + #gpio-cells = <2>;
5025 + clock-names = "apb_pclk";
5026 + #gpio-cells = <2>;
5035 + clock-names = "apb_pclk";
5036 + #gpio-cells = <2>;
5045 + clock-names = "apb_pclk";
5046 + #gpio-cells = <2>;
5051 + compatible = "hisilicon,hisi-cipher";
5053 + reg-names = "cipher";
5055 + interrupt-names = "cipher", "hash";
5059 + compatible = "hisilicon,hi35xx-rtc";
5065 + compatible = "hisilicon,hisi-lsadc";
5068 + interrupt-names = "hi_adc";
5070 + reset-names = "lsadc-crg";
5077 + reg-names = "hi_wdg";
5079 + interrupt-names = "hi_wdg";
5085 + #address-cells = <1>;
5086 + #size-cells = <1>;
5087 + compatible = "simple-bus";
5088 + interrupt-parent = <&gic>;
5096 + compatible = "hisilicon,hisi-sys";
5100 + compatible = "hisilicon,hisi-mipi";
5102 + reg-names = "mipi_rx";
5104 + interrupt-names = "mipi_rx";
5108 + compatible = "hisilicon,hisi-vi";
5110 + reg-names = "VI_CAP0", "VI_PROC0";
5112 + interrupt-names = "VI_CAP0", "VI_PROC0";
5116 + compatible = "hisilicon,hisi-isp";
5118 + reg-names = "ISP";
5120 + interrupt-names = "ISP";
5124 + compatible = "hisilicon,hisi-vpss";
5126 + reg-names = "vpss0";
5128 + interrupt-names = "vpss0";
5132 + compatible = "hisilicon,hisi-vo";
5134 + reg-names = "vo";
5136 + interrupt-names = "vo";
5140 + compatible = "hisilicon,hisi-hifb";
5142 + reg-names = "hifb";
5144 + interrupt-names = "hifb";
5148 + compatible = "hisilicon,hisi-vgs";
5150 + reg-names = "vgs0";
5152 + interrupt-names = "vgs0";
5156 + compatible = "hisilicon,hisi-gzip";
5158 + reg-names = "gzip";
5160 + interrupt-names = "gzip";
5164 + compatible = "hisilicon,hisi-vedu";
5166 + reg-names = "vedu0", "jpge";
5168 + interrupt-names = "vedu0","jpge";
5172 + compatible = "hisilicon,hisi-venc";
5176 + compatible = "hisilicon,hisi-aiao";
5178 + reg-names = "aiao","acodec";
5180 + interrupt-names = "AIO";
5184 + compatible = "hisilicon,hisi-ive";
5186 + reg-names = "ive";
5188 + interrupt-names = "ive";
5192 diff --git a/arch/arm/boot/dts/hi3516ev300-demb.dts b/arch/arm/boot/dts/hi3516ev300-demb.dts
5195 --- /dev/null
5196 +++ b/arch/arm/boot/dts/hi3516ev300-demb.dts
5197 @@ -0,0 +1,174 @@
5199 + * Copyright (c) 2013-2014 Linaro Ltd.
5200 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
5217 +/dts-v1/;
5244 + clock-frequency = <100000>;
5249 + clock-frequency = <100000>;
5254 + clock-frequency = <100000>;
5259 + num-cs = <1>;
5265 + pl022,com-mode = <0>;
5266 + spi-max-frequency = <25000000>;
5272 + num-cs = <2>;
5278 + pl022,com-mode = <0>;
5279 + spi-max-frequency = <25000000>;
5285 + pl022,com-mode = <0>;
5286 + spi-max-frequency = <25000000>;
5295 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
5296 + phy0: ethernet-phy@1 {
5302 + mac-address = [00 00 00 00 00 00];
5303 + phy-mode = "mii";
5304 + phy-handle = <&phy0>;
5310 + compatible = "jedec,spi-nor";
5312 + spi-max-frequency = <160000000>;
5318 + compatible = "jedec,spi-nand";
5320 + spi-max-frequency = <160000000>;
5372 diff --git a/arch/arm/boot/dts/hi3516ev300.dtsi b/arch/arm/boot/dts/hi3516ev300.dtsi
5375 --- /dev/null
5377 @@ -0,0 +1,699 @@
5379 + * Copyright (c) 2013-2014 Linaro Ltd.
5380 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
5398 +#include <dt-bindings/clock/hi3516ev300-clock.h>
5426 + #address-cells = <1>;
5427 + #size-cells = <0>;
5428 + enable-method = "hisilicon,hi3516ev300";
5432 + compatible = "arm,cortex-a7";
5433 + clock-frequency = <HI3516EV300_FIXED_1000M>;
5440 + compatible = "hisilicon,hi3516ev300-clock", "syscon";
5441 + #address-cells = <1>;
5442 + #size-cells = <1>;
5443 + #clock-cells = <1>;
5444 + #reset-cells = <2>;
5448 + gic: interrupt-controller@10300000 {
5449 + compatible = "arm,cortex-a7-gic";
5450 + #interrupt-cells = <3>;
5451 + #address-cells = <0>;
5452 + interrupt-controller;
5458 + compatible = "arm,armv7-timer";
5459 + interrupt-parent = <&gic>;
5462 + clock-frequency = <50000000>;
5466 + #address-cells = <1>;
5467 + #size-cells = <1>;
5468 + compatible = "simple-bus";
5469 + interrupt-parent = <&gic>;
5473 + compatible = "fixed-clock";
5474 + #clock-cells = <0>;
5475 + clock-frequency = <3000000>;
5479 + compatible = "fixed-clock";
5480 + #clock-cells = <0>;
5481 + clock-frequency = <50000000>;
5485 + compatible = "arm,cortex-a7-pmu";
5489 + hiedmacv310_0: hiedma-controller@100B0000 {
5494 + clock-names = "apb_pclk", "axi_aclk";
5495 + clock-cells = <2>;
5497 + reset-names = "dma-reset";
5498 + dma-requests = <32>;
5499 + dma-channels = <4>;
5501 + #dma-cells = <2>;
5507 + hiedmacv310_0: hiedma-controller@100B0000 {
5512 + clock-names = "apb_pclk", "axi_aclk";
5513 + clock-cells = <2>;
5515 + reset-names = "dma-reset";
5516 + dma-requests = <32>;
5517 + dma-channels = <4>;
5519 + #dma-cells = <2>;
5524 + sysctrl: system-controller@12020000 {
5527 + reboot-offset = <0x4>;
5528 + #clock-cells = <1>;
5532 + #address-cells = <1>;
5533 + #size-cells = <1>;
5534 + compatible = "arm,amba-bus";
5543 + clock-names = "timer00", "timer01", "apb_pclk";
5553 + clock-names = "timer10", "timer11", "apb_pclk";
5562 + clock-names = "apb_pclk";
5571 + clock-names = "apb_pclk";
5574 + dma-names = "tx","rx";
5584 + clock-names = "apb_pclk";
5587 + dma-names = "tx","rx";
5595 + compatible = "hisilicon,hi3516ev300-i2c",
5596 + "hisilicon,hibvt-i2c";
5603 + compatible = "hisilicon,hi3516ev300-i2c",
5604 + "hisilicon,hibvt-i2c";
5611 + compatible = "hisilicon,hi3516ev300-i2c",
5612 + "hisilicon,hibvt-i2c";
5620 + arm,primecell-periphid = <0x00800022>;
5624 + clock-names = "apb_pclk";
5625 + #address-cells = <1>;
5626 + #size-cells = <0>;
5629 + dma-names = "tx","rx";
5636 + arm,primecell-periphid = <0x00800022>;
5640 + clock-names = "apb_pclk";
5641 + #address-cells = <1>;
5642 + #size-cells = <0>;
5643 + num-cs = <2>;
5648 + dma-names = "tx","rx";
5654 + compatible = "hisilicon,hisi-femac-mdio";
5657 + clock-names = "mdio";
5659 + reset-names = "internal-phy";
5660 + #address-cells = <1>;
5661 + #size-cells = <0>;
5665 + compatible = "hisilicon,hi3516ev300-femac",
5666 + "hisilicon,hisi-femac-v2";
5671 + reset-names = "mac";
5674 + fmc: flash-memory-controller@10000000 {
5675 + compatible = "hisilicon,hisi-fmc";
5677 + reg-names = "control", "memory";
5679 + max-dma-size = <0x2000>;
5680 + #address-cells = <1>;
5681 + #size-cells = <0>;
5683 + hisfc:spi-nor@0 {
5684 + compatible = "hisilicon,fmc-spi-nor";
5685 + assigned-clocks = <&clock HI3516EV300_FMC_CLK>;
5686 + assigned-clock-rates = <24000000>;
5687 + #address-cells = <1>;
5688 + #size-cells = <0>;
5691 + hisnfc:spi-nand@0 {
5692 + compatible = "hisilicon,fmc-spi-nand";
5693 + assigned-clocks = <&clock HI3516EV300_FMC_CLK>;
5694 + assigned-clock-rates = <24000000>;
5695 + #address-cells = <1>;
5696 + #size-cells = <0>;
5700 + iocfg_ctrl: iocfg-controller@100c0000 {
5701 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
5710 + clock-names = "mmc_clk";
5712 + reset-names = "crg_reset", "dll_reset";
5713 + max-frequency = <90000000>;
5716 + bus-width = <8>;
5717 + cap-mmc-highspeed;
5718 + cap-mmc-hw-reset;
5719 + cap-sd-highspeed;
5720 + mmc-hs200-1_8v;
5721 + mmc-hs400-1_8v;
5722 + mmc-hs400-enhanced-strobe;
5723 + full-pwr-cycle;
5724 + disable-wp;
5734 + clock-names = "mmc_clk";
5736 + reset-names = "crg_reset", "dll_reset";
5737 + max-frequency = <50000000>;
5740 + bus-width = <4>;
5741 + cap-sd-highspeed;
5742 + full-pwr-cycle;
5743 + disable-wp;
5748 + usb2_phy0: phy2-0 {
5749 + compatible = "hisilicon,hixvp-usb2-phy";
5756 + clock-names = "clk_u2phy_apb_ref",
5761 + reset-names = "phy_por_reset",
5797 + #phy-cells = <0>;
5800 + usbdrd3_0: usb3-0{
5804 + #address-cells = <1>;
5805 + #size-cells = <1>;
5812 + clock-names = "usb2_bus_clk",
5816 + reset-names = "vcc_reset";
5823 + interrupt-names = "peripheral";
5825 + phy-names = "usb2-phy";
5826 + maximum-speed = "high-speed";
5831 + snps,usb2-lpm-disable;
5840 + clock-names = "apb_pclk";
5841 + #gpio-cells = <2>;
5850 + clock-names = "apb_pclk";
5851 + #gpio-cells = <2>;
5860 + clock-names = "apb_pclk";
5861 + #gpio-cells = <2>;
5870 + clock-names = "apb_pclk";
5871 + #gpio-cells = <2>;
5880 + clock-names = "apb_pclk";
5881 + #gpio-cells = <2>;
5890 + clock-names = "apb_pclk";
5891 + #gpio-cells = <2>;
5900 + clock-names = "apb_pclk";
5901 + #gpio-cells = <2>;
5910 + clock-names = "apb_pclk";
5911 + #gpio-cells = <2>;
5920 + clock-names = "apb_pclk";
5921 + #gpio-cells = <2>;
5930 + clock-names = "apb_pclk";
5931 + #gpio-cells = <2>;
5936 + compatible = "hisilicon,hisi-cipher";
5938 + reg-names = "cipher";
5940 + interrupt-names = "cipher", "hash";
5944 + compatible = "hisilicon,hi35xx-rtc";
5950 + compatible = "hisilicon,hisi-lsadc";
5953 + interrupt-names = "hi_adc";
5955 + reset-names = "lsadc-crg";
5962 + reg-names = "hi_wdg";
5964 + interrupt-names = "hi_wdg";
5970 + #address-cells = <1>;
5971 + #size-cells = <1>;
5972 + compatible = "simple-bus";
5973 + interrupt-parent = <&gic>;
5981 + compatible = "hisilicon,hisi-sys";
5985 + compatible = "hisilicon,hisi-mipi";
5987 + reg-names = "mipi_rx";
5989 + interrupt-names = "mipi_rx";
5993 + compatible = "hisilicon,hisi-vi";
5995 + reg-names = "VI_CAP0", "VI_PROC0";
5997 + interrupt-names = "VI_CAP0", "VI_PROC0";
6001 + compatible = "hisilicon,hisi-isp";
6003 + reg-names = "ISP";
6005 + interrupt-names = "ISP";
6009 + compatible = "hisilicon,hisi-vpss";
6011 + reg-names = "vpss0";
6013 + interrupt-names = "vpss0";
6017 + compatible = "hisilicon,hisi-vo";
6019 + reg-names = "vo";
6021 + interrupt-names = "vo";
6025 + compatible = "hisilicon,hisi-hifb";
6027 + reg-names = "hifb";
6029 + interrupt-names = "hifb";
6033 + compatible = "hisilicon,hisi-vgs";
6035 + reg-names = "vgs0";
6037 + interrupt-names = "vgs0";
6041 + compatible = "hisilicon,hisi-gzip";
6043 + reg-names = "gzip";
6045 + interrupt-names = "gzip";
6049 + compatible = "hisilicon,hisi-vedu";
6051 + reg-names = "vedu0", "jpge";
6053 + interrupt-names = "vedu0","jpge";
6057 + compatible = "hisilicon,hisi-venc";
6061 + compatible = "hisilicon,hisi-aiao";
6063 + reg-names = "aiao","acodec";
6065 + interrupt-names = "AIO";
6069 + compatible = "hisilicon,hisi-ive";
6071 + reg-names = "ive";
6073 + interrupt-names = "ive";
6077 diff --git a/arch/arm/boot/dts/hi3518ev20x-demb.dts b/arch/arm/boot/dts/hi3518ev20x-demb.dts
6080 --- /dev/null
6081 +++ b/arch/arm/boot/dts/hi3518ev20x-demb.dts
6082 @@ -0,0 +1,197 @@
6084 + * Copyright (c) 2013-2014 Linaro Ltd.
6085 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
6102 +/dts-v1/;
6153 + compatible = "jedec,spi-nor";
6155 + spi-max-frequency = <160000000>;
6156 + m25p,fast-read;
6162 + compatible = "jedec,spi-nand";
6164 + spi-max-frequency = <160000000>;
6165 + m25p,fast-read;
6170 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
6171 + phy0: ethernet-phy@1 {
6177 + mac-address = [00 00 00 00 00 00];
6178 + phy-mode = "rmii";
6179 + phy-handle = <&phy0>;
6213 + num-cs = <1>;
6219 + pl022,com-mode = <0>;
6220 + spi-max-frequency = <24750000>;
6226 + num-cs = <2>;
6232 + pl022,com-mode = <0>;
6233 + spi-max-frequency = <24750000>;
6240 + pl022,com-mode = <0>;
6241 + spi-max-frequency = <24750000>;
6280 diff --git a/arch/arm/boot/dts/hi3518ev20x.dtsi b/arch/arm/boot/dts/hi3518ev20x.dtsi
6283 --- /dev/null
6285 @@ -0,0 +1,577 @@
6287 + * Copyright (c) 2013-2014 Linaro Ltd.
6288 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
6305 +#include <dt-bindings/clock/hi3518ev20x-clock.h>
6307 + #address-cells = <1>;
6308 + #size-cells = <1>;
6311 + #address-cells = <1>;
6312 + #size-cells = <0>;
6316 + compatible = "arm,arm926ej-s";
6321 + vic: interrupt-controller@100d0000 {
6322 + compatible = "arm,pl190-vic";
6323 + interrupt-controller;
6324 + #interrupt-cells = <1>;
6329 + #address-cells = <1>;
6330 + #size-cells = <1>;
6331 + compatible = "simple-bus";
6332 + interrupt-parent = <&vic>;
6336 + compatible = "hisilicon,hi3518ev20x-clock";
6338 + #clock-cells = <1>;
6339 + #reset-cells = <2>;
6342 + sysctrl: system-controller@20050000 {
6346 + #clock-cells = <1>;
6350 + compatible = "syscon-reboot";
6364 + clock-names = "timer0", "timer1", "apb_pclk";
6376 + clock-names = "timer2", "timer3", "apb_pclk";
6385 + clock-names = "apb_pclk";
6394 + clock-names = "apb_pclk";
6403 + clock-names = "apb_pclk";
6408 + compatible = "hisilicon,hisi-usb-phy";
6411 + #phy-cells = <0>;
6415 + compatible = "generic-ehci";
6421 + clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
6425 + compatible = "generic-ohci";
6431 + clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
6440 + clock-names = "clk";
6444 + compatible = "hisilicon,hisi-i2c-hisilicon";
6448 + clock-frequency = <100000>;
6449 + io-size = <0x1000>;
6455 + compatible = "hisilicon,hisi-i2c-hisilicon";
6459 + clock-frequency = <100000>;
6460 + io-size = <0x1000>;
6466 + compatible = "hisilicon,hisi-i2c-hisilicon";
6470 + clock-frequency = <100000>;
6471 + io-size = <0x1000>;
6478 + arm,primecell-periphid = <0x00800022>;
6482 + clock-names = "apb_pclk";
6484 + #address-cells = <1>;
6485 + #size-cells = <0>;
6490 + arm,primecell-periphid = <0x00800022>;
6494 + clock-names = "apb_pclk";
6496 + #address-cells = <1>;
6497 + #size-cells = <0>;
6502 + fmc: flash-memory-controller@10010000 {
6503 + compatible = "hisilicon,hisi-fmc";
6505 + reg-names = "control", "memory";
6507 + max-dma-size = <0x2000>;
6508 + #address-cells = <1>;
6509 + #size-cells = <0>;
6511 + hisfc:spi-nor@0 {
6512 + compatible = "hisilicon,fmc-spi-nor";
6513 + assigned-clocks = <&clock HI3518EV20X_FMC_CLK>;
6514 + assigned-clock-rates = <24000000>;
6515 + #address-cells = <1>;
6516 + #size-cells = <0>;
6519 + hisnfc:spi-nand@0 {
6520 + compatible = "hisilicon,fmc-spi-nand";
6521 + assigned-clocks = <&clock HI3518EV20X_FMC_CLK>;
6522 + assigned-clock-rates = <24000000>;
6523 + #address-cells = <1>;
6524 + #size-cells = <0>;
6529 + compatible = "hisilicon,hisi-femac-mdio";
6532 + clock-names = "mdio";
6533 + assigned-clocks = <&clock HI3518EV20X_ETH_CLK>;
6534 + assigned-clock-rates = <54000000>;
6536 + reset-names = "external-phy";
6537 + #address-cells = <1>;
6538 + #size-cells = <0>;
6542 + compatible = "hisilicon,hi3518ev20x-femac",
6543 + "hisilicon,hisi-femac-v2";
6548 + reset-names = "mac";
6552 + compatible = "hisilicon,hi3518ev20x-himci";
6556 + clock-names = "mmc_clk";
6557 + max-frequency = <99000000>;
6559 + reset-names = "mmc_reset";
6560 + bus-width = <8>;
6561 + cap-mmc-highspeed;
6562 + cap-mmc-hw-reset;
6563 + mmc-hs200-1_8v;
6564 + full-pwr-cycle;
6570 + compatible = "hisilicon,hi3518ev20x-himci";
6574 + clock-names = "mmc_clk";
6575 + max-frequency = <99000000>;
6577 + reset-names = "mmc_reset";
6578 + bus-width = <4>;
6579 + cap-sd-highspeed;
6580 + sd-uhs-sdr12;
6581 + sd-uhs-sdr25;
6582 + sd-uhs-sdr50;
6583 + sd-uhs-sdr104;
6589 + compatible = "hisilicon,hi3518ev20x-himci";
6593 + clock-names = "mmc_clk";
6594 + max-frequency = <49500000>;
6596 + reset-names = "mmc_reset";
6597 + bus-width = <4>;
6598 + cap-sd-highspeed;
6604 + compatible = "pinctrl-single";
6606 + #address-cells = <1>;
6607 + #size-cells = <1>;
6608 + #gpio-range-cells = <3>;
6611 + pinctrl-single,register-width = <32>;
6612 + pinctrl-single,function-mask = <7>;
6614 + pinctrl-single,gpio-range = <&range 0 5 0
6618 + range: gpio-range {
6619 + #pinctrl-single,gpio-range-cells = <3>;
6624 + compatible = "pinconf-single";
6626 + #address-cells = <1>;
6627 + #size-cells = <1>;
6630 + pinctrl-single,register-width = <32>;
6638 + clock-names = "apb_pclk";
6639 + #gpio-cells = <2>;
6640 + gpio-ranges = <&pmux 0 28 3>, <&pmux 3 12 1>,
6650 + clock-names = "apb_pclk";
6651 + #gpio-cells = <2>;
6652 + gpio-ranges = <&pmux 0 31 8>;
6661 + clock-names = "apb_pclk";
6662 + #gpio-cells = <2>;
6663 + gpio-ranges = <&pmux 0 4 8>;
6672 + clock-names = "apb_pclk";
6673 + #gpio-cells = <2>;
6674 + gpio-ranges = <&pmux 0 13 8>;
6683 + clock-names = "apb_pclk";
6684 + #gpio-cells = <2>;
6685 + gpio-ranges = <&pmux 0 21 7>, <&pmux 7 39 1>;
6694 + clock-names = "apb_pclk";
6695 + #gpio-cells = <2>;
6696 + gpio-ranges = <&pmux 0 40 8>;
6705 + clock-names = "apb_pclk";
6706 + #gpio-cells = <2>;
6707 + gpio-ranges = <&pmux 0 48 8>;
6716 + clock-names = "apb_pclk";
6717 + #gpio-cells = <2>;
6718 + gpio-ranges = <&pmux 0 56 8>;
6727 + clock-names = "apb_pclk";
6728 + #gpio-cells = <2>;
6729 + gpio-ranges = <&pmux 0 64 2>;
6733 + hidmac: hidma-controller@10060000 {
6734 + compatible = "hisilicon,hisi-dmac";
6738 + clock-names = "dmac_clk";
6740 + reset-names = "dma-reset";
6741 + #dma-cells = <2>;
6747 + #address-cells = <1>;
6748 + #size-cells = <1>;
6749 + compatible = "simple-bus";
6750 + interrupt-parent = <&vic>;
6761 + reg-names = "crg", "sys", "ddr", "misc";
6768 + reg-names = "aiao";
6787 + reg-names = "reg_vicap_base_va", "reg_isp_base_va";
6833 + compatible = "hisilicon,hi3516cv300-pwm";
6840 + reg-names = "wtdg";
6846 + interrupt-names = "rtc", "rtc_temp";
6863 diff --git a/arch/arm/boot/dts/hi3518ev300-demb.dts b/arch/arm/boot/dts/hi3518ev300-demb.dts
6866 --- /dev/null
6867 +++ b/arch/arm/boot/dts/hi3518ev300-demb.dts
6868 @@ -0,0 +1,166 @@
6870 + * Copyright (c) 2013-2014 Linaro Ltd.
6871 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
6888 +/dts-v1/;
6915 + clock-frequency = <100000>;
6920 + clock-frequency = <100000>;
6925 + clock-frequency = <100000>;
6930 + num-cs = <1>;
6936 + pl022,com-mode = <0>;
6937 + spi-max-frequency = <25000000>;
6943 + num-cs = <2>;
6949 + pl022,com-mode = <0>;
6950 + spi-max-frequency = <25000000>;
6956 + pl022,com-mode = <0>;
6957 + spi-max-frequency = <25000000>;
6966 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
6967 + phy0: ethernet-phy@1 {
6973 + mac-address = [00 00 00 00 00 00];
6974 + phy-mode = "mii";
6975 + phy-handle = <&phy0>;
6981 + compatible = "jedec,spi-nor";
6983 + spi-max-frequency = <160000000>;
6989 + compatible = "jedec,spi-nand";
6991 + spi-max-frequency = <160000000>;
7035 diff --git a/arch/arm/boot/dts/hi3518ev300.dtsi b/arch/arm/boot/dts/hi3518ev300.dtsi
7038 --- /dev/null
7040 @@ -0,0 +1,678 @@
7042 + * Copyright (c) 2013-2014 Linaro Ltd.
7043 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
7061 +#include <dt-bindings/clock/hi3518ev300-clock.h>
7087 + #address-cells = <1>;
7088 + #size-cells = <0>;
7089 + enable-method = "hisilicon,hi3518ev300";
7093 + compatible = "arm,cortex-a7";
7094 + clock-frequency = <HI3518EV300_FIXED_1000M>;
7101 + compatible = "hisilicon,hi3518ev300-clock", "syscon";
7102 + #address-cells = <1>;
7103 + #size-cells = <1>;
7104 + #clock-cells = <1>;
7105 + #reset-cells = <2>;
7109 + gic: interrupt-controller@10300000 {
7110 + compatible = "arm,cortex-a7-gic";
7111 + #interrupt-cells = <3>;
7112 + #address-cells = <0>;
7113 + interrupt-controller;
7119 + compatible = "arm,armv7-timer";
7120 + interrupt-parent = <&gic>;
7123 + clock-frequency = <50000000>;
7127 + #address-cells = <1>;
7128 + #size-cells = <1>;
7129 + compatible = "simple-bus";
7130 + interrupt-parent = <&gic>;
7134 + compatible = "fixed-clock";
7135 + #clock-cells = <0>;
7136 + clock-frequency = <3000000>;
7140 + compatible = "fixed-clock";
7141 + #clock-cells = <0>;
7142 + clock-frequency = <50000000>;
7146 + compatible = "arm,cortex-a7-pmu";
7150 + hiedmacv310_0: hiedma-controller@100B0000 {
7155 + clock-names = "apb_pclk", "axi_aclk";
7156 + clock-cells = <2>;
7158 + reset-names = "dma-reset";
7159 + dma-requests = <32>;
7160 + dma-channels = <4>;
7162 + #dma-cells = <2>;
7167 + hiedmacv310_0: hiedma-controller@100B0000 {
7172 + clock-names = "apb_pclk", "axi_aclk";
7173 + clock-cells = <2>;
7175 + reset-names = "dma-reset";
7176 + dma-requests = <32>;
7177 + dma-channels = <4>;
7179 + #dma-cells = <2>;
7183 + sysctrl: system-controller@12020000 {
7186 + reboot-offset = <0x4>;
7187 + #clock-cells = <1>;
7191 + #address-cells = <1>;
7192 + #size-cells = <1>;
7193 + compatible = "arm,amba-bus";
7202 + clock-names = "timer00", "timer01", "apb_pclk";
7212 + clock-names = "timer10", "timer11", "apb_pclk";
7221 + clock-names = "apb_pclk";
7230 + clock-names = "apb_pclk";
7233 + dma-names = "tx","rx";
7243 + clock-names = "apb_pclk";
7246 + dma-names = "tx","rx";
7254 + compatible = "hisilicon,hi3518ev300-i2c",
7255 + "hisilicon,hibvt-i2c";
7262 + compatible = "hisilicon,hi3518ev300-i2c",
7263 + "hisilicon,hibvt-i2c";
7270 + compatible = "hisilicon,hi3518ev300-i2c",
7271 + "hisilicon,hibvt-i2c";
7279 + arm,primecell-periphid = <0x00800022>;
7283 + clock-names = "apb_pclk";
7284 + #address-cells = <1>;
7285 + #size-cells = <0>;
7288 + dma-names = "tx","rx";
7295 + arm,primecell-periphid = <0x00800022>;
7299 + clock-names = "apb_pclk";
7300 + #address-cells = <1>;
7301 + #size-cells = <0>;
7302 + num-cs = <2>;
7307 + dma-names = "tx","rx";
7313 + compatible = "hisilicon,hisi-femac-mdio";
7316 + clock-names = "mdio";
7318 + reset-names = "internal-phy";
7319 + #address-cells = <1>;
7320 + #size-cells = <0>;
7324 + compatible = "hisilicon,hi3518ev300-femac",
7325 + "hisilicon,hisi-femac-v2";
7330 + reset-names = "mac";
7333 + fmc: flash-memory-controller@10000000 {
7334 + compatible = "hisilicon,hisi-fmc";
7336 + reg-names = "control", "memory";
7338 + max-dma-size = <0x2000>;
7339 + #address-cells = <1>;
7340 + #size-cells = <0>;
7342 + hisfc:spi-nor@0 {
7343 + compatible = "hisilicon,fmc-spi-nor";
7344 + assigned-clocks = <&clock HI3518EV300_FMC_CLK>;
7345 + assigned-clock-rates = <24000000>;
7346 + #address-cells = <1>;
7347 + #size-cells = <0>;
7350 + hisnfc:spi-nand@0 {
7351 + compatible = "hisilicon,fmc-spi-nand";
7352 + assigned-clocks = <&clock HI3518EV300_FMC_CLK>;
7353 + assigned-clock-rates = <24000000>;
7354 + #address-cells = <1>;
7355 + #size-cells = <0>;
7359 + iocfg_ctrl: iocfg-controller@100c0000 {
7360 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
7364 + iocfg_ctrl2: iocfg-controller2@112c0000 {
7365 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
7374 + clock-names = "mmc_clk";
7376 + reset-names = "crg_reset", "dll_reset";
7377 + max-frequency = <150000000>;
7380 + bus-width = <4>;
7381 + cap-mmc-highspeed;
7382 + cap-mmc-hw-reset;
7383 + cap-sd-highspeed;
7384 + mmc-hs200-1_8v;
7385 + full-pwr-cycle;
7386 + disable-wp;
7396 + clock-names = "mmc_clk";
7398 + reset-names = "crg_reset", "dll_reset";
7399 + max-frequency = <50000000>;
7402 + bus-width = <4>;
7403 + cap-sd-highspeed;
7404 + full-pwr-cycle;
7405 + disable-wp;
7410 + usb2_phy0: phy2-0 {
7411 + compatible = "hisilicon,hixvp-usb2-phy";
7418 + clock-names = "clk_u2phy_apb_ref",
7423 + reset-names = "phy_por_reset",
7459 + #phy-cells = <0>;
7462 + usbdrd3_0: usb3-0{
7466 + #address-cells = <1>;
7467 + #size-cells = <1>;
7474 + clock-names = "usb2_bus_clk",
7478 + reset-names = "vcc_reset";
7485 + interrupt-names = "peripheral";
7487 + phy-names = "usb2-phy";
7488 + maximum-speed = "high-speed";
7493 + snps,usb2-lpm-disable;
7502 + clock-names = "apb_pclk";
7503 + #gpio-cells = <2>;
7512 + clock-names = "apb_pclk";
7513 + #gpio-cells = <2>;
7522 + clock-names = "apb_pclk";
7523 + #gpio-cells = <2>;
7532 + clock-names = "apb_pclk";
7533 + #gpio-cells = <2>;
7542 + clock-names = "apb_pclk";
7543 + #gpio-cells = <2>;
7552 + clock-names = "apb_pclk";
7553 + #gpio-cells = <2>;
7562 + clock-names = "apb_pclk";
7563 + #gpio-cells = <2>;
7572 + clock-names = "apb_pclk";
7573 + #gpio-cells = <2>;
7578 + compatible = "hisilicon,hisi-cipher";
7580 + reg-names = "cipher";
7582 + interrupt-names = "cipher", "hash";
7586 + compatible = "hisilicon,hi35xx-rtc";
7592 + compatible = "hisilicon,hisi-lsadc";
7595 + interrupt-names = "hi_adc";
7597 + reset-names = "lsadc-crg";
7604 + reg-names = "hi_wdg";
7606 + interrupt-names = "hi_wdg";
7612 + #address-cells = <1>;
7613 + #size-cells = <1>;
7614 + compatible = "simple-bus";
7615 + interrupt-parent = <&gic>;
7623 + compatible = "hisilicon,hisi-sys";
7627 + compatible = "hisilicon,hisi-mipi";
7629 + reg-names = "mipi_rx";
7631 + interrupt-names = "mipi_rx";
7635 + compatible = "hisilicon,hisi-vi";
7637 + reg-names = "VI_CAP0", "VI_PROC0";
7639 + interrupt-names = "VI_CAP0", "VI_PROC0";
7643 + compatible = "hisilicon,hisi-isp";
7645 + reg-names = "ISP";
7647 + interrupt-names = "ISP";
7651 + compatible = "hisilicon,hisi-vpss";
7653 + reg-names = "vpss0";
7655 + interrupt-names = "vpss0";
7659 + compatible = "hisilicon,hisi-vo";
7661 + reg-names = "vo";
7663 + interrupt-names = "vo";
7667 + compatible = "hisilicon,hisi-hifb";
7669 + reg-names = "hifb";
7671 + interrupt-names = "hifb";
7675 + compatible = "hisilicon,hisi-vgs";
7677 + reg-names = "vgs0";
7679 + interrupt-names = "vgs0";
7683 + compatible = "hisilicon,hisi-gzip";
7685 + reg-names = "gzip";
7687 + interrupt-names = "gzip";
7691 + compatible = "hisilicon,hisi-vedu";
7693 + reg-names = "vedu0", "jpge";
7695 + interrupt-names = "vedu0","jpge";
7699 + compatible = "hisilicon,hisi-venc";
7703 + compatible = "hisilicon,hisi-aiao";
7705 + reg-names = "aiao","acodec";
7707 + interrupt-names = "AIO";
7711 + compatible = "hisilicon,hisi-ive";
7713 + reg-names = "ive";
7715 + interrupt-names = "ive";
7719 diff --git a/arch/arm/boot/dts/hi3519av100-emmc.dts b/arch/arm/boot/dts/hi3519av100-emmc.dts
7722 --- /dev/null
7723 +++ b/arch/arm/boot/dts/hi3519av100-emmc.dts
7724 @@ -0,0 +1,25 @@
7750 diff --git a/arch/arm/boot/dts/hi3519av100-flash.dts b/arch/arm/boot/dts/hi3519av100-flash.dts
7753 --- /dev/null
7754 +++ b/arch/arm/boot/dts/hi3519av100-flash.dts
7755 @@ -0,0 +1,25 @@
7781 diff --git a/arch/arm/boot/dts/hi3519av100-smp-emmc.dts b/arch/arm/boot/dts/hi3519av100-smp-emmc.dts
7784 --- /dev/null
7785 +++ b/arch/arm/boot/dts/hi3519av100-smp-emmc.dts
7786 @@ -0,0 +1,25 @@
7803 +#include "hi3519av100-smp.dts"
7812 diff --git a/arch/arm/boot/dts/hi3519av100-smp-flash.dts b/arch/arm/boot/dts/hi3519av100-smp-flash.…
7815 --- /dev/null
7816 +++ b/arch/arm/boot/dts/hi3519av100-smp-flash.dts
7817 @@ -0,0 +1,25 @@
7834 +#include "hi3519av100-smp.dts"
7843 diff --git a/arch/arm/boot/dts/hi3519av100-smp.dts b/arch/arm/boot/dts/hi3519av100-smp.dts
7846 --- /dev/null
7847 +++ b/arch/arm/boot/dts/hi3519av100-smp.dts
7848 @@ -0,0 +1,289 @@
7850 + * Copyright (c) 2013-2014 Linaro Ltd.
7868 +/dts-v1/;
7876 + linux,initrd-start = <0x23000040>;
7877 + linux,initrd-end = <0x24000000>;
7881 + #address-cells = <1>;
7882 + #size-cells = <0>;
7883 + enable-method = "hisilicon,hi3519av100-smp";
7886 + compatible = "arm,cortex-a53";
7889 + cci-control-port = <&cci_control0>;
7893 + compatible = "arm,cortex-a53";
7896 + cci-control-port = <&cci_control1>;
7962 + pl022,com-mode = <0>;
7963 + spi-max-frequency = <50000000>;
7974 + pl022,com-mode = <0>;
7975 + spi-max-frequency = <50000000>;
7986 + pl022,com-mode = <0>;
7987 + spi-max-frequency = <50000000>;
7998 + pl022,com-mode = <0>;
7999 + spi-max-frequency = <50000000>;
8010 + pl022,com-mode = <0>;
8011 + spi-max-frequency = <50000000>;
8016 + ethphy: ethernet-phy@1 {
8022 + phy-handle = <ðphy>;
8023 + phy-mode = "rgmii";
8028 + compatible = "jedec,spi-nor";
8030 + spi-max-frequency = <160000000>;
8031 + m25p,fast-read;
8037 + compatible = "jedec,spi-nand";
8039 + spi-max-frequency = <160000000>;
8047 + nand-max-frequency = <200000000>;
8138 diff --git a/arch/arm/boot/dts/hi3519av100.dts b/arch/arm/boot/dts/hi3519av100.dts
8141 --- /dev/null
8143 @@ -0,0 +1,280 @@
8145 + * Copyright (c) 2013-2014 Linaro Ltd.
8163 +/dts-v1/;
8171 + linux,initrd-start = <0x23000040>;
8172 + linux,initrd-end = <0x24000000>;
8176 + #address-cells = <1>;
8177 + #size-cells = <0>;
8180 + compatible = "arm,cortex-a53";
8183 + cci-control-port = <&cci_control0>;
8248 + pl022,com-mode = <0>;
8249 + spi-max-frequency = <50000000>;
8260 + pl022,com-mode = <0>;
8261 + spi-max-frequency = <50000000>;
8272 + pl022,com-mode = <0>;
8273 + spi-max-frequency = <50000000>;
8284 + pl022,com-mode = <0>;
8285 + spi-max-frequency = <50000000>;
8296 + pl022,com-mode = <0>;
8297 + spi-max-frequency = <50000000>;
8302 + ethphy: ethernet-phy@1 {
8308 + phy-handle = <ðphy>;
8309 + phy-mode = "rgmii";
8314 + compatible = "jedec,spi-nor";
8316 + spi-max-frequency = <160000000>;
8317 + m25p,fast-read;
8323 + compatible = "jedec,spi-nand";
8325 + spi-max-frequency = <160000000>;
8333 + nand-max-frequency = <200000000>;
8424 diff --git a/arch/arm/boot/dts/hi3519av100.dtsi b/arch/arm/boot/dts/hi3519av100.dtsi
8427 --- /dev/null
8429 @@ -0,0 +1,1070 @@
8431 + * Copyright (c) 2013-2014 Linaro Ltd.
8432 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
8450 +#include <dt-bindings/clock/hi3519av100-clock.h>
8490 + gic: interrupt-controller@1F100000 {
8491 + compatible = "arm,gic-400";
8492 + #interrupt-cells = <3>;
8493 + #address-cells = <0>;
8494 + interrupt-controller;
8500 + compatible = "hisilicon,hi3519av100-clock", "syscon";
8501 + #address-cells = <1>;
8502 + #size-cells = <1>;
8503 + #clock-cells = <1>;
8504 + #reset-cells = <2>;
8510 + compatible = "fixed-clock";
8511 + #clock-cells = <0>;
8512 + clock-frequency = <3000000>;
8516 + compatible = "arm,armv8-timer";
8517 + interrupt-parent = <&gic>;
8520 + clock-frequency = <24000000>;
8524 + compatible = "hisilicon,ipcm-interrupt";
8525 + interrupt-parent = <&gic>;
8532 + #address-cells = <1>;
8533 + #size-cells = <1>;
8534 + compatible = "simple-bus";
8535 + interrupt-parent = <&gic>;
8539 + #address-cells = <1>;
8540 + #size-cells = <1>;
8541 + compatible = "arm,amba-bus";
8549 + clock-names = "apb_pclk";
8558 + clock-names = "apb_pclk";
8560 + dma-names = "tx","rx";
8569 + clock-names = "apb_pclk";
8571 + dma-names = "tx","rx";
8580 + clock-names = "apb_pclk";
8582 + dma-names = "tx","rx";
8591 + clock-names = "apb_pclk";
8593 + dma-names = "tx","rx";
8598 + compatible = "hisilicon,hibvt-i2c";
8601 + clock-frequency = <100000>;
8604 + dma-names = "tx","rx";
8608 + compatible = "hisilicon,hibvt-i2c";
8611 + clock-frequency = <100000>;
8614 + dma-names = "tx","rx";
8618 + compatible = "hisilicon,hibvt-i2c";
8621 + clock-frequency = <100000>;
8624 + dma-names = "tx","rx";
8628 + compatible = "hisilicon,hibvt-i2c";
8631 + clock-frequency = <100000>;
8634 + dma-names = "tx","rx";
8638 + compatible = "hisilicon,hibvt-i2c";
8641 + clock-frequency = <100000>;
8644 + dma-names = "tx","rx";
8648 + compatible = "hisilicon,hibvt-i2c";
8651 + clock-frequency = <100000>;
8654 + dma-names = "tx","rx";
8658 + compatible = "hisilicon,hibvt-i2c";
8661 + clock-frequency = <100000>;
8664 + dma-names = "tx","rx";
8668 + compatible = "hisilicon,hibvt-i2c";
8671 + clock-frequency = <100000>;
8674 + dma-names = "tx","rx";
8678 + compatible = "hisilicon,hibvt-i2c";
8681 + clock-frequency = <100000>;
8684 + dma-names = "tx","rx";
8688 + compatible = "hisilicon,hibvt-i2c";
8691 + clock-frequency = <100000>;
8694 + dma-names = "tx","rx";
8699 + arm,primecell-periphid = <0x00800022>;
8703 + clock-names = "apb_pclk";
8704 + #address-cells = <1>;
8705 + #size-cells = <0>;
8707 + num-cs = <1>;
8709 + dma-names = "tx","rx";
8714 + arm,primecell-periphid = <0x00800022>;
8718 + clock-names = "apb_pclk";
8719 + #address-cells = <1>;
8720 + #size-cells = <0>;
8722 + num-cs = <1>;
8724 + dma-names = "tx","rx";
8729 + arm,primecell-periphid = <0x00800022>;
8733 + clock-names = "apb_pclk";
8734 + #address-cells = <1>;
8735 + #size-cells = <0>;
8737 + num-cs = <1>;
8739 + dma-names = "tx","rx";
8744 + arm,primecell-periphid = <0x00800022>;
8748 + clock-names = "apb_pclk";
8749 + #address-cells = <1>;
8750 + #size-cells = <0>;
8752 + num-cs = <1>;
8754 + dma-names = "tx","rx";
8759 + arm,primecell-periphid = <0x00800022>;
8763 + clock-names = "apb_pclk";
8764 + #address-cells = <1>;
8765 + #size-cells = <0>;
8767 + num-cs = <1>;
8769 + dma-names = "tx","rx";
8776 + #gpio-cells = <2>;
8778 + clock-names = "apb_pclk";
8786 + #gpio-cells = <2>;
8788 + clock-names = "apb_pclk";
8796 + #gpio-cells = <2>;
8798 + clock-names = "apb_pclk";
8806 + #gpio-cells = <2>;
8808 + clock-names = "apb_pclk";
8816 + #gpio-cells = <2>;
8818 + clock-names = "apb_pclk";
8826 + #gpio-cells = <2>;
8828 + clock-names = "apb_pclk";
8836 + #gpio-cells = <2>;
8838 + clock-names = "apb_pclk";
8846 + #gpio-cells = <2>;
8848 + clock-names = "apb_pclk";
8856 + #gpio-cells = <2>;
8858 + clock-names = "apb_pclk";
8866 + #gpio-cells = <2>;
8868 + clock-names = "apb_pclk";
8876 + #gpio-cells = <2>;
8878 + clock-names = "apb_pclk";
8886 + #gpio-cells = <2>;
8888 + clock-names = "apb_pclk";
8896 + #gpio-cells = <2>;
8898 + clock-names = "apb_pclk";
8906 + #gpio-cells = <2>;
8908 + clock-names = "apb_pclk";
8916 + #gpio-cells = <2>;
8918 + clock-names = "apb_pclk";
8939 + clock-names = "timer0", "timer1", "timer2";
8944 + hivdmac: hivdma-controller@04c10000 {
8945 + compatible = "hisilicon,hisi-vdmac";
8949 + clock-names = "apb_pclk";
8951 + reset-names = "dma-reset";
8952 + #dma-cells = <2>;
8956 + hiedmacv310_0: hiedma-controller@04040000 {
8963 + clock-names = "apb_pclk", "axi_aclk";
8964 + #clock-cells = <2>;
8966 + reset-names = "dma-reset";
8967 + dma-requests = <32>;
8968 + dma-channels = <8>;
8970 + #dma-cells = <2>;
8974 + hiedmacv310_1: hiedma-controller@04050000 {
8981 + clock-names = "apb_pclk", "axi_aclk";
8982 + #clock-cells = <2>;
8984 + reset-names = "dma-reset";
8985 + dma-requests = <32>;
8986 + dma-channels = <8>;
8988 + #dma-cells = <2>;
8992 + sysctrl: system-controller@00000000 {
8995 + #clock-cells = <1>;
8999 + compatible = "syscon-reboot";
9006 + misc_ctrl: misc-controller@04528000 {
9007 + compatible = "hisilicon,hisi-miscctrl", "syscon";
9012 + compatible = "hisilicon,hisi-ioconfig", "syscon";
9017 + compatible = "hisilicon,hisi-ioconfig", "syscon";
9022 + compatible = "hisilicon,hisi-ioconfig", "syscon";
9027 + compatible = "hisilicon,hisi-ioconfig", "syscon";
9032 + compatible = "hisilicon,hisi-usb-phy";
9034 + #phy-cells = <0>;
9039 + compatible = "generic-xhci";
9042 + usb2-lpm-disable;
9048 + compatible = "generic-xhci";
9051 + usb2-lpm-disable;
9060 + interrupt-names = "peripheral";
9061 + maximum-speed = "super-speed";
9073 + interrupt-names = "peripheral";
9074 + maximum-speed = "high-speed";
9079 + compatible = "arm,cci-400";
9080 + #address-cells = <1>;
9081 + #size-cells = <1>;
9085 + cci_control0: slave-if@4000 {
9086 + compatible = "arm,cci-400-ctrl-if";
9087 + interface-type = "ace";
9091 + cci_control1: slave-if@5000 {
9092 + compatible = "arm,cci-400-ctrl-if";
9093 + interface-type = "ace";
9100 + compatible = "hisilicon,hisi-gemac-mdio";
9104 + reset-names = "phy_reset";
9105 + #address-cells = <1>;
9106 + #size-cells = <0>;
9116 + clock-names = "higmac_clk",
9121 + reset-names = "port_reset",
9124 + mac-address = [00 00 00 00 00 00];
9127 + fmc: flash-memory-controller@10000000 {
9128 + compatible = "hisilicon,hisi-fmc";
9130 + reg-names = "control", "memory";
9132 + max-dma-size = <0x2000>;
9133 + #address-cells = <1>;
9134 + #size-cells = <0>;
9137 + compatible = "hisilicon,fmc-spi-nor";
9138 + assigned-clocks = <&clock HI3519AV100_FMC_CLK>;
9139 + assigned-clock-rates = <24000000>;
9140 + #address-cells = <1>;
9141 + #size-cells = <0>;
9145 + compatible = "hisilicon,fmc-spi-nand";
9146 + assigned-clocks = <&clock HI3519AV100_FMC_CLK>;
9147 + assigned-clock-rates = <24000000>;
9148 + #address-cells = <1>;
9149 + #size-cells = <0>;
9152 + hinfc:parallel-nand-controller {
9153 + compatible = "hisilicon,fmc-nand";
9154 + assigned-clocks = <&clock HI3519AV100_FMC_CLK>;
9155 + assigned-clock-rates = <200000000>;
9156 + #address-cells = <1>;
9157 + #size-cells = <0>;
9166 + clock-names = "mmc_clk";
9168 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
9169 + max-frequency = <198000000>;
9171 + non-removable;
9172 + bus-width = <8>;
9173 + cap-mmc-highspeed;
9174 + mmc-hs400-1_8v;
9175 + mmc-hs400-enhanced-strobe;
9176 + cap-mmc-hw-reset;
9186 + clock-names = "mmc_clk";
9188 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
9189 + max-frequency = <198000000>;
9193 + bus-width = <4>;
9194 + cap-sd-highspeed;
9195 + sd-uhs-sdr104;
9196 + full-pwr-cycle;
9197 + disable-wp;
9203 + compatible = "hisi-sdhci";
9207 + clock-names = "mmc_clk";
9209 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
9210 + max-frequency = <198000000>;
9214 + bus-width = <4>;
9215 + cap-sd-highspeed;
9216 + sd-uhs-sdr104;
9217 + full-pwr-cycle;
9218 + disable-wp;
9225 + compatible = "hisilicon,hisi-pcie";
9226 + #size-cells = <2>;
9227 + #address-cells = <3>;
9228 + #interrupt-cells = <1>;
9229 + bus-range = <0x0 0xff>;
9232 + interrupt-names = "msi";
9233 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
9234 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 102 0x4
9252 + compatible = "hisilicon,hisi-cipher";
9254 + reg-names = "cipher", "rsa";
9256 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash", "rsa", "nonsec_rsa";
9266 + compatible = "hisilicon,hi35xx-rtc";
9280 + #address-cells = <1>;
9281 + #size-cells = <1>;
9282 + compatible = "simple-bus";
9283 + interrupt-parent = <&gic>;
9291 + compatible = "hisilicon,hisi-sys";
9294 + reg-names = "crg", "sys", "ddr", "misc";
9298 + compatible = "hisilicon,hisi-mipi";
9300 + reg-names = "mipi_rx", "slvs";
9302 + interrupt-names = "mipi_rx", "slvs";
9306 + compatible = "hisilicon,hisi-mipi_tx";
9308 + reg-names = "mipi_tx";
9310 + interrupt-names = "mipi_tx";
9314 + compatible = "hisilicon,hisi-vi";
9316 + reg-names = "VI_CAP0", "VI_PROC0";
9318 + interrupt-names = "VI_CAP0", "VI_PROC0";
9322 + compatible = "hisilicon,hisi-isp";
9324 + reg-names = "ISP";
9326 + interrupt-names = "ISP";
9330 + compatible = "hisilicon,hisi-vpss";
9332 + reg-names = "vpss0";
9334 + interrupt-names = "vpss0";
9338 + compatible = "hisilicon,hisi-vgs";
9340 + reg-names = "vgs0";
9342 + interrupt-names = "vgs0";
9346 + compatible = "hisilicon,hisi-vo";
9348 + reg-names = "vo";
9350 + interrupt-names = "vo";
9354 + compatible = "hisilicon,hisi-hifb";
9356 + reg-names = "hifb";
9358 + interrupt-names = "hifb";
9362 + compatible = "hisilicon,hisi-tde";
9364 + reg-names = "tde";
9366 + interrupt-names = "tde_osr_isr";
9370 + compatible = "hisilicon,hisi-avs";
9372 + reg-names = "avs";
9374 + interrupt-names = "avs";
9378 + compatible = "hisilicon,hisi-dis";
9380 + reg-names = "dis";
9382 + interrupt-names = "dis";
9386 + compatible = "hisilicon,hisi-gyro-dis";
9390 + compatible = "hisilicon,hisi-gdc";
9392 + reg-names = "gdc";
9394 + interrupt-names = "gdc";
9398 + compatible = "hisilicon,hisi-gzip";
9400 + reg-names = "gzip";
9402 + interrupt-names = "gzip";
9406 + compatible = "hisilicon,hisi-jpegd";
9408 + reg-names = "jpegd";
9410 + interrupt-names = "jpegd";
9414 + compatible = "hisilicon,hisi-vedu";
9416 + reg-names = "vedu0", "jpge";
9418 + interrupt-names = "vedu0","jpge";
9422 + compatible = "hisilicon,hisi-venc";
9426 + compatible = "hisilicon,hisi-vdh";
9428 + reg-names = "vdh_scd";
9430 + interrupt-names = "scd","vdh";
9434 + compatible = "hisilicon,hisi-hdmi";
9436 + reg-names = "hdmi0";
9440 + compatible = "hisilicon,hisi-aiao";
9442 + reg-names = "aiao","acodec","crg";
9444 + interrupt-names = "AIO","VOIE";
9448 + compatible = "hisilicon,hisi-nnie";
9450 + reg-names = "nnie0";
9452 + interrupt-names = "nnie0";
9456 + compatible = "hisilicon,hisi-dpu_rect";
9458 + reg-names = "dpu_rect";
9460 + interrupt-names = "rect";
9464 + compatible = "hisilicon,hisi-dpu_match";
9466 + reg-names = "dpu_match";
9468 + interrupt-names = "match";
9472 + compatible = "hisilicon,hisi-dsp";
9474 + reg-names = "dsp0";
9478 + compatible = "hisilicon,hisi-ive";
9480 + reg-names = "ive";
9482 + interrupt-names = "ive";
9486 + compatible = "hisilicon,hi3519av100-lsadc";
9490 + reset-names = "lsadc-crg";
9500 diff --git a/arch/arm/boot/dts/hi3520dv500-demb.dts b/arch/arm/boot/dts/hi3520dv500-demb.dts
9503 --- /dev/null
9504 +++ b/arch/arm/boot/dts/hi3520dv500-demb.dts
9505 @@ -0,0 +1,211 @@
9507 + * Copyright (c) 2013-2014 Linaro Ltd.
9508 + * Copyright (c) 2015-2020 HiSilicon Technologies Co., Ltd.
9525 +/dts-v1/;
9595 + num-cs = <1>;
9601 + pl022,com-mode = <0>;
9602 + spi-max-frequency = <24750000>;
9608 + num-cs = <1>;
9614 + pl022,com-mode = <0>;
9615 + spi-max-frequency = <24750000>;
9624 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
9625 + phy0: ethernet-phy@0 {
9631 + mac-address = [00 00 00 00 00 00];
9632 + phy-mode = "mii";
9633 + phy-handle = <&phy0>;
9639 + compatible = "jedec,spi-nor";
9641 + spi-max-frequency = <160000000>;
9647 + compatible = "jedec,spi-nand";
9649 + spi-max-frequency = <160000000>;
9717 diff --git a/arch/arm/boot/dts/hi3521a-demb.dts b/arch/arm/boot/dts/hi3521a-demb.dts
9720 --- /dev/null
9721 +++ b/arch/arm/boot/dts/hi3521a-demb.dts
9722 @@ -0,0 +1,103 @@
9724 + * Copyright (c) 2013-2014 Linaro Ltd.
9725 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
9742 +/dts-v1/;
9775 + compatible = "jedec,spi-nor";
9777 + spi-max-frequency = <160000000>;
9778 + m25p,fast-read;
9784 + compatible = "jedec,spi-nand";
9786 + spi-max-frequency = <160000000>;
9787 + m25p,fast-read;
9792 + ethphy: ethernet-phy@1 {
9798 + phy-handle = <ðphy>;
9799 + phy-mode = "rgmii";
9808 + num-cs = <2>;
9814 + pl022,com-mode = <0>;
9815 + spi-max-frequency = <31250000>;
9822 + pl022,com-mode = <0>;
9823 + spi-max-frequency = <31250000>;
9826 diff --git a/arch/arm/boot/dts/hi3521a.dtsi b/arch/arm/boot/dts/hi3521a.dtsi
9829 --- /dev/null
9831 @@ -0,0 +1,406 @@
9833 + * Copyright (c) 2013-2014 Linaro Ltd.
9834 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
9851 +#include <dt-bindings/clock/hi3521a-clock.h>
9853 + #address-cells = <1>;
9854 + #size-cells = <1>;
9857 + #address-cells = <1>;
9858 + #size-cells = <0>;
9862 + compatible = "arm,cortex-a7";
9867 + gic: interrupt-controller@10300000 {
9868 + compatible = "arm,cortex-a7-gic";
9869 + #interrupt-cells = <3>;
9870 + #address-cells = <0>;
9871 + interrupt-controller;
9877 + #address-cells = <1>;
9878 + #size-cells = <1>;
9879 + compatible = "simple-bus";
9880 + interrupt-parent = <&gic>;
9884 + compatible = "hisilicon,hi3521a-clock";
9886 + #clock-cells = <1>;
9887 + #reset-cells = <2>;
9890 + sysctrl: system-controller@12050000 {
9893 + #clock-cells = <1>;
9897 + compatible = "syscon-reboot";
9911 + clock-names = "timer0", "timer1", "apb_pclk";
9923 + clock-names = "timer2", "timer3", "apb_pclk";
9935 + clock-names = "timer4", "timer5", "apb_pclk";
9948 + clock-names = "timer6", "timer7", "apb_pclk";
9952 + hidmac: hidma-controller@10060000 {
9953 + compatible = "hisilicon,hisi-dmac";
9957 + clock-names = "dmac_clk";
9959 + reset-names = "dma-reset";
9960 + #dma-cells = <2>;
9969 + clock-names = "apb_pclk";
9978 + clock-names = "apb_pclk";
9987 + clock-names = "apb_pclk";
9992 + compatible = "hisilicon,hisi-i2c-hisilicon";
9996 + clock-frequency = <100000>;
9997 + io-size = <0x1000>;
10004 + arm,primecell-periphid = <0x00800022>;
10008 + clock-names = "apb_pclk";
10010 + #address-cells = <1>;
10011 + #size-cells = <0>;
10017 + compatible = "hisilicon,hisi-usb-phy";
10019 + #phy-cells = <0>;
10023 + compatible = "generic-ehci";
10029 + compatible = "generic-ohci";
10034 + fmc: flash-memory-controller@10000000 {
10035 + compatible = "hisilicon,hisi-fmc";
10037 + reg-names = "control", "memory";
10039 + max-dma-size = <0x2000>;
10040 + #address-cells = <1>;
10041 + #size-cells = <0>;
10043 + hisfc:spi-nor@0 {
10044 + compatible = "hisilicon,fmc-spi-nor";
10045 + assigned-clocks = <&clock HI3521A_FMC_CLK>;
10046 + assigned-clock-rates = <24000000>;
10047 + #address-cells = <1>;
10048 + #size-cells = <0>;
10051 + hisnfc:spi-nand@0 {
10052 + compatible = "hisilicon,fmc-spi-nand";
10053 + assigned-clocks = <&clock HI3521A_FMC_CLK>;
10054 + assigned-clock-rates = <24000000>;
10055 + #address-cells = <1>;
10056 + #size-cells = <0>;
10061 + compatible = "hisilicon,hisi-gemac-mdio";
10065 + assigned-clocks = <&clock HI3521A_ETH_PHY_MUX>;
10066 + assigned-clock-rates = <25000000>;
10068 + reset-names = "phy_reset";
10069 + #address-cells = <1>;
10070 + #size-cells = <0>;
10081 + clock-names = "higmac_clk",
10086 + reset-names = "port_reset",
10089 + mac-address = [00 00 00 00 00 00];
10093 + compatible = "hisilicon,hisi-sata-phy";
10096 + #phy-cells = <0>;
10100 + compatible = "hisilicon,hisi-ahci";
10104 + phy-names = "sata-phy";
10105 + #address-cells = <1>;
10106 + #size-cells = <0>;
10111 + #address-cells = <1>;
10112 + #size-cells = <1>;
10113 + compatible = "simple-bus";
10114 + interrupt-parent = <&gic>;
10121 + reg-names = "crg", "sys", "ddr", "misc";
10157 + interrupt-names = "vpss0";
10159 + reg-names = "vpss0";
10186 + reg-names = "vedu0", "vedu1";
10198 + interrupt-names = "jpgd";
10200 + reg-names = "jpgd";
10212 + interrupt-names = "scd";
10214 + reg-names = "scd";
10221 + reg-names = "aiao";
10228 + reg-names = "aenc";
10234 + reg-names = "hdmi";
10238 diff --git a/arch/arm/boot/dts/hi3521dv200-demb.dts b/arch/arm/boot/dts/hi3521dv200-demb.dts
10241 --- /dev/null
10242 +++ b/arch/arm/boot/dts/hi3521dv200-demb.dts
10243 @@ -0,0 +1,211 @@
10245 + * Copyright (c) 2013-2014 Linaro Ltd.
10246 + * Copyright (c) 2015-2020 HiSilicon Technologies Co., Ltd.
10263 +/dts-v1/;
10333 + num-cs = <1>;
10339 + pl022,com-mode = <0>;
10340 + spi-max-frequency = <24750000>;
10346 + num-cs = <1>;
10352 + pl022,com-mode = <0>;
10353 + spi-max-frequency = <24750000>;
10362 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
10363 + phy0: ethernet-phy@0 {
10369 + mac-address = [00 00 00 00 00 00];
10370 + phy-mode = "mii";
10371 + phy-handle = <&phy0>;
10377 + compatible = "jedec,spi-nor";
10379 + spi-max-frequency = <160000000>;
10385 + compatible = "jedec,spi-nand";
10387 + spi-max-frequency = <160000000>;
10455 diff --git a/arch/arm/boot/dts/hi3521dv200.dtsi b/arch/arm/boot/dts/hi3521dv200.dtsi
10458 --- /dev/null
10460 @@ -0,0 +1,719 @@
10461 +/* Copyright (c) 2019-2020 HiSilicon Technologies Co., Ltd.
10478 +#include <dt-bindings/clock/hi3521dv200-clock.h>
10479 +#include <dt-bindings/interrupt-controller/irq.h>
10480 +#include <dt-bindings/interrupt-controller/arm-gic.h>
10482 + #address-cells = <1>;
10483 + #size-cells = <1>;
10485 + interrupt-parent = <&gic>;
10488 + #address-cells = <1>;
10489 + #size-cells = <0>;
10490 + enable-method = "hisilicon,hi3521dv200";
10494 + compatible = "arm,cortex-a7";
10495 + clock-frequency = <HI3521DV200_FIXED_1200M>;
10501 + compatible = "arm,cortex-a7";
10502 + clock-frequency = <HI3521DV200_FIXED_1200M>;
10508 + compatible = "arm,cortex-a7";
10509 + clock-frequency = <HI3521DV200_FIXED_1200M>;
10515 + compatible = "arm,cortex-a7";
10516 + clock-frequency = <HI3521DV200_FIXED_1200M>;
10523 + compatible = "arm,cortex-a7-pmu";
10531 + compatible = "hisilicon,hi3521dv200-clock", "syscon";
10532 + #address-cells = <1>;
10533 + #size-cells = <1>;
10534 + #clock-cells = <1>;
10535 + #reset-cells = <2>;
10539 + gic: interrupt-controller@12400000 {
10540 + compatible = "arm,cortex-a7-gic";
10541 + #interrupt-cells = <3>;
10542 + #address-cells = <0>;
10543 + interrupt-controller;
10549 + compatible = "arm,armv7-timer";
10552 + clock-frequency = <24000000>;
10553 + always-on;
10557 + #address-cells = <1>;
10558 + #size-cells = <1>;
10559 + compatible = "simple-bus";
10563 + compatible = "fixed-clock";
10564 + #clock-cells = <0>;
10565 + clock-frequency = <3000000>;
10568 + hiedmacv310_0: hiedma-controller@10280000 {
10573 + clock-names = "apb_pclk", "axi_aclk";
10574 + clock-cells = <2>;
10576 + reset-names = "dma-reset";
10577 + dma-requests = <32>;
10578 + dma-channels = <8>;
10580 + #dma-cells = <2>;
10584 + sysctrl: system-controller@11020000 {
10587 + reboot-offset = <0x4>;
10588 + #clock-cells = <1>;
10592 + #address-cells = <1>;
10593 + #size-cells = <1>;
10594 + compatible = "arm,amba-bus";
10602 + clock-names = "apb_pclk";
10611 + clock-names = "apb_pclk";
10613 + dma-names = "tx","rx";
10622 + clock-names = "apb_pclk";
10624 + dma-names = "tx","rx";
10633 + clock-names = "apb_pclk";
10635 + dma-names = "tx","rx";
10644 + clock-names = "apb_pclk";
10646 + dma-names = "tx","rx";
10652 + compatible = "hisilicon,hibvt-i2c";
10655 + clock-frequency = <100000>;
10660 + compatible = "hisilicon,hibvt-i2c";
10663 + clock-frequency = <100000>;
10669 + arm,primecell-periphid = <0x00800022>;
10673 + clock-names = "apb_pclk";
10674 + #address-cells = <1>;
10675 + #size-cells = <0>;
10677 + dma-names = "tx","rx";
10683 + arm,primecell-periphid = <0x00800022>;
10687 + clock-names = "apb_pclk";
10688 + #address-cells = <1>;
10689 + #size-cells = <0>;
10691 + dma-names = "tx","rx";
10699 + #gpio-cells = <2>;
10701 + clock-names = "apb_pclk";
10709 + #gpio-cells = <2>;
10711 + clock-names = "apb_pclk";
10719 + #gpio-cells = <2>;
10721 + clock-names = "apb_pclk";
10729 + #gpio-cells = <2>;
10731 + clock-names = "apb_pclk";
10739 + #gpio-cells = <2>;
10741 + clock-names = "apb_pclk";
10749 + #gpio-cells = <2>;
10751 + clock-names = "apb_pclk";
10759 + #gpio-cells = <2>;
10761 + clock-names = "apb_pclk";
10769 + #gpio-cells = <2>;
10771 + clock-names = "apb_pclk";
10779 + #gpio-cells = <2>;
10781 + clock-names = "apb_pclk";
10789 + #gpio-cells = <2>;
10791 + clock-names = "apb_pclk";
10799 + #gpio-cells = <2>;
10801 + clock-names = "apb_pclk";
10809 + #gpio-cells = <2>;
10811 + clock-names = "apb_pclk";
10819 + #gpio-cells = <2>;
10821 + clock-names = "apb_pclk";
10829 + #gpio-cells = <2>;
10831 + clock-names = "apb_pclk";
10836 + compatible = "hisilicon,hi35xx-rtc";
10844 + fmc: flash-memory-controller@10000000 { //todo
10845 + compatible = "hisilicon,hisi-fmc";
10847 + reg-names = "control", "memory";
10849 + max-dma-size = <0x2000>;
10850 + #address-cells = <1>;
10851 + #size-cells = <0>;
10854 + compatible = "hisilicon,fmc-spi-nor";
10855 + assigned-clocks = <&clock HI3521DV200_FMC_CLK>;
10856 + assigned-clock-rates = <24000000>;
10857 + #address-cells = <1>;
10858 + #size-cells = <0>;
10862 + compatible = "hisilicon,fmc-spi-nand";
10863 + assigned-clocks = <&clock HI3521DV200_FMC_CLK>;
10864 + assigned-clock-rates = <24000000>;
10865 + #address-cells = <1>;
10866 + #size-cells = <0>;
10872 + compatible = "hisilicon,hisi-femac-mdio";
10875 + clock-names = "mdio";
10877 + reset-names = "internal-phy";
10878 + #address-cells = <1>;
10879 + #size-cells = <0>;
10883 + compatible = "hisilicon,hisi-femac-v2";
10888 + reset-names = "mac";
10891 + iocfg_ctrl: iocfg-controller@10ff0000 {
10892 + compatible = "hisilicon,hisi-iocfgctrl", "syscon";
10902 + clock-names = "mmc_clk";
10904 + reset-names = "crg_reset", "dll_reset";
10905 + max-frequency = <148500000>;
10908 + non-removable;
10909 + bus-width = <8>;
10910 + cap-mmc-highspeed;
10911 + mmc-hs200-1_8v;
10912 + mmc-hs400-1_8v;
10913 + mmc-hs400-enhanced-strobe;
10914 + cap-mmc-hw-reset;
10915 + no-sdio;
10916 + no-sd;
10926 + clock-names = "mmc_clk";
10928 + reset-names = "crg_reset", "dll_reset";
10929 + max-frequency = <50000000>;
10932 + bus-width = <4>;
10933 + cap-sd-highspeed;
10934 + disable-wp;
10935 + no-sdio;
10945 + clock-names = "mmc_clk";
10947 + reset-names = "crg_reset", "dll_reset";
10948 + max-frequency = <150000000>;
10951 + bus-width = <4>;
10952 + cap-sd-highspeed;
10953 + sd-uhs-sdr104;
10954 + non-removable;
10961 + compatible = "hisilicon,hisi-usb-phy";
10966 + compatible = "generic-xhci";
10969 + usb2-lpm-disable;
10973 + compatible = "generic-xhci";
10976 + usb2-lpm-disable;
10980 + compatible = "hisilicon,hisi-sata-phy";
10983 + #phy-cells = <0>;
10987 + compatible = "hisilicon,hisi-ahci";
10991 + phy-names = "sata-phy";
10992 + #address-cells = <1>;
10993 + #size-cells = <0>;
10997 + compatible = "hisilicon,hisi-cipher";
10999 + reg-names = "cipher";
11004 + interrupt-names = "cipher","hash","nonsec_cipher","nonsec_hash";
11008 + compatible = "hisilicon,hisi-otp";
11010 + reg-names = "otp";
11016 + reg-names = "hi_wdg";
11018 + interrupt-names = "hi_wdg";
11024 + #address-cells = <1>;
11025 + #size-cells = <1>;
11026 + compatible = "simple-bus";
11034 + compatible = "hisilicon,hisi-sys";
11039 + reg-names = "crg", "sys", "ddr", "misc";
11043 + compatible = "hisilicon,hisi-vi";
11046 + reg-names = "vi_cap", "vi_timer";
11049 + interrupt-names = "vi_cap", "vi_timer";
11053 + compatible = "hisilicon,hisi-mipi";
11055 + reg-names = "mipi";
11057 + interrupt-names = "mipi";
11061 + compatible = "hisilicon,hisi-vpss";
11063 + reg-names = "vpss";
11065 + interrupt-names = "vpss";
11069 + compatible = "hisilicon,hisi-vgs";
11071 + reg-names = "vgs";
11073 + interrupt-names = "vgs";
11077 + compatible = "hisilicon,hisi-vo";
11079 + reg-names = "vo";
11081 + interrupt-names = "vo";
11085 + compatible = "hisilicon,hisi-hifb";
11086 + reg-names = "hifb";
11088 + interrupt-names = "hifb";
11092 + compatible = "hisilicon,hisi-hdmi";
11094 + reg-names = "hdmi0","phy";
11096 + interrupt-names = "tx_aon","tx_pwd","tx_sec";
11100 + compatible = "hisilicon,hisi-vedu";
11102 + reg-names = "vedu0", "jpge";
11104 + interrupt-names = "vedu0","jpge";
11108 + compatible = "hisilicon,hisi-vdh";
11110 + reg-names = "vdh_scd";
11112 + interrupt-names = "vdh_pxp", "scd";
11116 + compatible = "hisilicon,hisi-jpegd";
11118 + reg-names = "jpegd";
11120 + interrupt-names = "jpegd";
11124 + compatible = "hisilicon,hisi-vda";
11126 + reg-names = "vda";
11128 + interrupt-names = "vda";
11132 + compatible = "hisilicon,hisi-nnie";
11134 + reg-names = "nnie0";
11136 + interrupt-names = "nnie0";
11140 + compatible = "hisilicon,hisi-ive";
11142 + reg-names = "ive";
11144 + interrupt-names = "ive";
11148 + compatible = "hisilicon,hisi-mau";
11150 + reg-names = "mau0";
11152 + interrupt-names = "mau0";
11156 + compatible = "hisilicon,hisi-aiao";
11158 + reg-names = "aiao";
11160 + interrupt-names = "AIO";
11164 + compatible = "hisilicon,hisi-tde";
11166 + reg-names = "tde";
11168 + interrupt-names = "tde_osr_isr";
11172 + compatible = "hisilicon,hi-ir";
11174 + reg-names = "hi-ir";
11176 + interrupt-names = "hi-ir";
11180 diff --git a/arch/arm/boot/dts/hi3531a-demb.dts b/arch/arm/boot/dts/hi3531a-demb.dts
11183 --- /dev/null
11184 +++ b/arch/arm/boot/dts/hi3531a-demb.dts
11185 @@ -0,0 +1,146 @@
11187 + * Copyright (c) 2013-2014 Linaro Ltd.
11188 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
11205 +/dts-v1/;
11213 + linux,initrd-start = <0x42000000>;
11217 + #address-cells = <1>;
11218 + #size-cells = <0>;
11219 + enable-method = "hisilicon,hi3531a-smp";
11222 + compatible = "arm,cortex-a9";
11225 + next-level-cache = <&L2>;
11229 + compatible = "arm,cortex-a9";
11232 + next-level-cache = <&L2>;
11252 + compatible = "jedec,spi-nor";
11254 + spi-max-frequency = <160000000>;
11255 + m25p,fast-read;
11261 + compatible = "jedec,spi-nand";
11263 + spi-max-frequency = <160000000>;
11268 + assigned-clocks = <&clock HI3531A_NFC_CLK>;
11269 + assigned-clock-rates = <200000000>;
11274 + nand-max-frequency = <200000000>;
11279 + ethphy: ethernet-phy@1 {
11285 + phy-handle = <ðphy>;
11286 + phy-mode = "rgmii";
11299 + num-cs = <4>;
11305 + pl022,com-mode = <0>;
11306 + spi-max-frequency = <31250000>;
11313 + pl022,com-mode = <0>;
11314 + spi-max-frequency = <31250000>;
11321 + pl022,com-mode = <0>;
11322 + spi-max-frequency = <31250000>;
11328 + pl022,com-mode = <0>;
11329 + spi-max-frequency = <31250000>;
11332 diff --git a/arch/arm/boot/dts/hi3531a.dtsi b/arch/arm/boot/dts/hi3531a.dtsi
11335 --- /dev/null
11337 @@ -0,0 +1,508 @@
11339 + * Copyright (c) 2013-2014 Linaro Ltd.
11340 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
11357 +#include <dt-bindings/clock/hi3531a-clock.h>
11359 + #address-cells = <1>;
11360 + #size-cells = <1>;
11373 + gic: interrupt-controller@10300000 {
11374 + compatible = "arm,cortex-a9-gic";
11375 + #interrupt-cells = <3>;
11376 + #address-cells = <0>;
11377 + interrupt-controller;
11383 + #address-cells = <1>;
11384 + #size-cells = <1>;
11385 + compatible = "simple-bus";
11386 + interrupt-parent = <&gic>;
11390 + compatible = "hisilicon,hi3531a-clock";
11392 + #clock-cells = <1>;
11393 + #reset-cells = <2>;
11396 + sysctrl: system-controller@12050000 {
11399 + #clock-cells = <1>;
11403 + compatible = "syscon-reboot";
11410 + compatible = "arm,cortex-a9-pmu";
11415 + L2: l2-cache@10700000 {
11416 + compatible = "arm,pl310-cache";
11419 + cache-unified;
11420 + cache-level = <2>;
11423 + hidmac: hidma-controller@10060000 {
11424 + compatible = "hisilicon,hisi-dmac";
11428 + clock-names = "dmac_clk";
11430 + reset-names = "dma-reset";
11431 + #dma-cells = <2>;
11440 + clock-names = "apb_pclk";
11449 + clock-names = "apb_pclk";
11458 + clock-names = "apb_pclk";
11467 + clock-names = "apb_pclk";
11472 + compatible = "hisilicon,hisi-usb-phy";
11474 + #phy-cells = <0>;
11478 + compatible = "hisilicon,hisi-usb3-phy";
11480 + #phy-cells = <0>;
11484 + compatible = "generic-xhci";
11487 + usb2-lpm-disable;
11491 + compatible = "generic-ehci";
11497 + compatible = "generic-ohci";
11503 + compatible = "hisilicon,hisi-i2c-hisilicon";
11507 + clock-frequency = <100000>;
11508 + io-size = <0x1000>;
11514 + compatible = "hisilicon,hisi-i2c-hisilicon";
11518 + clock-frequency = <100000>;
11519 + io-size = <0x1000>;
11526 + arm,primecell-periphid = <0x00800022>;
11530 + clock-names = "apb_pclk";
11532 + #address-cells = <1>;
11533 + #size-cells = <0>;
11549 + clock-names = "timer0", "timer1", "timer2";
11560 + clock-names = "timer4", "timer5", "peri_pclk";
11572 + clock-names = "timer6", "timer7", "peri_pclk";
11576 + fmc: flash-memory-controller@10000000 {
11577 + compatible = "hisilicon,hisi-fmc";
11579 + reg-names = "control", "memory";
11581 + max-dma-size = <0x2000>;
11582 + #address-cells = <1>;
11583 + #size-cells = <0>;
11586 + compatible = "hisilicon,fmc-spi-nor";
11587 + assigned-clocks = <&clock HI3531A_FMC_CLK>;
11588 + assigned-clock-rates = <24000000>;
11589 + #address-cells = <1>;
11590 + #size-cells = <0>;
11594 + compatible = "hisilicon,fmc-spi-nand";
11595 + assigned-clocks = <&clock HI3531A_FMC_CLK>;
11596 + assigned-clock-rates = <24000000>;
11597 + #address-cells = <1>;
11598 + #size-cells = <0>;
11602 + hinfc610: parallel-nand-controller@10010000 {
11603 + compatible = "hisilicon,hisi-parallel-nand";
11605 + reg-names = "control", "memory";
11607 + #address-cells = <1>;
11608 + #size-cells = <0>;
11612 + compatible = "hisilicon,hisi-gemac-mdio";
11616 + assigned-clocks = <&clock HI3531A_ETH_PHY_MUX>;
11617 + assigned-clock-rates = <25000000>;
11619 + reset-names = "phy_reset";
11620 + #address-cells = <1>;
11621 + #size-cells = <0>;
11632 + clock-names = "higmac_clk",
11637 + reset-names = "port_reset",
11640 + mac-address = [00 00 00 00 00 00];
11644 + compatible = "hisilicon,hisi-sata-phy";
11647 + #phy-cells = <0>;
11651 + compatible = "hisilicon,hisi-ahci";
11655 + phy-names = "sata-phy";
11656 + #address-cells = <1>;
11657 + #size-cells = <0>;
11662 + compatible = "hisilicon,hisi-pcie";
11663 + bus-range = <0x0 0xff>;
11664 + #size-cells = <2>;
11665 + #address-cells = <3>;
11667 + #interrupt-cells = <1>;
11668 + interrupt-map-mask = <0x0 0x0 0x0 0x4>;
11669 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
11679 + compatible = "hisilicon,hisi-pcie";
11680 + bus-range = <0x0 0xff>;
11681 + #size-cells = <2>;
11682 + #address-cells = <3>;
11684 + #interrupt-cells = <1>;
11685 + interrupt-map-mask = <0x0 0x0 0x0 0x4>;
11686 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
11711 + #address-cells = <1>;
11712 + #size-cells = <1>;
11713 + compatible = "simple-bus";
11714 + interrupt-parent = <&gic>;
11721 + reg-names = "crg", "sys", "ddr", "misc";
11759 + interrupt-names = "vpss0", "vpss1", "vpss2";
11763 + reg-names = "vpss0", "vpss1", "vpss2";
11794 + reg-names = "vedu0", "vedu1", "vedu2", "vedu3";
11806 + interrupt-names = "jpgd";
11808 + reg-names = "jpgd";
11820 + interrupt-names = "scd";
11822 + reg-names = "scd";
11829 + reg-names = "aiao";
11836 + reg-names = "aenc";
11842 + reg-names = "hdmi";
11846 diff --git a/arch/arm/boot/dts/hi3536dv100-demb.dts b/arch/arm/boot/dts/hi3536dv100-demb.dts
11849 --- /dev/null
11850 +++ b/arch/arm/boot/dts/hi3536dv100-demb.dts
11851 @@ -0,0 +1,192 @@
11853 + * Copyright (c) 2013-2014 Linaro Ltd.
11854 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
11871 +/dts-v1/;
11890 + clock-frequency = <100000>;
11898 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
11899 + phy0: ethernet-phy@1 {
11905 + mac-address = [00 00 00 00 00 00];
11906 + phy-mode = "mii";
11907 + phy-handle = <&phy0>;
11912 + compatible = "jedec,spi-nor";
11914 + spi-max-frequency = <160000000>;
11920 + compatible = "jedec,spi-nand";
11922 + spi-max-frequency = <160000000>;
11957 + pinctrl-single,pins = <
11966 + pinctrl-single,pins = <
11977 + padctrl-ability,demo = <
11984 + padctrl-ability,sck = <
11991 + sysctrl-ddr,pins = <
11992 + 0x12120078 0x55322100 /* JPGD - JPGE - TFE - VGS - VDH - A7 - VDP - AIAO */
11993 + 0x1212007c 0x65665526 /* FMC - DMA1 - DMA9 - DDRT - SATA - ETH1 - ETH0 - VOIE */
11994 + 0x12120080 0x66666666 /* - - - - - - CIPHER - USB */
11995 + 0x12120084 0x55522100 /* JPGD - JPGE - TFE - VGS - VDH - A7 - VDP - AIAO */
11996 + 0x12120088 0x65665526 /* FMC - DMA1 - DMA9 - DDRT - SATA - ETH1 - ETH0 - VOIE */
11997 + 0x1212008c 0x66626666 /* - - - - - - CIPHER - USB */
12030 + 0x121140f4 0x00000033 /*row-hit enable */
12031 + 0x121140ec 0x00000044 /*row-hit */
12032 + 0x121140f0 0x00003333 /*row-hit */
12039 + pinctrl-names = "demo", "sck", "default";
12040 + pinctrl-0 = <&i2s1_pmux>;
12041 + pinctrl-1 = <&i2s2_pmux>;
12042 + pinctrl-2 = <>;
12044 diff --git a/arch/arm/boot/dts/hi3536dv100.dtsi b/arch/arm/boot/dts/hi3536dv100.dtsi
12047 --- /dev/null
12049 @@ -0,0 +1,445 @@
12051 + * Copyright (c) 2013-2014 Linaro Ltd.
12052 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
12070 +#include <dt-bindings/clock/hi3536dv100-clock.h>
12084 + #address-cells = <1>;
12085 + #size-cells = <0>;
12089 + compatible = "arm,cortex-a7";
12095 + compatible = "hisilicon,hi3536dv100-clock";
12096 + #address-cells = <1>;
12097 + #size-cells = <1>;
12098 + #clock-cells = <1>;
12099 + #reset-cells = <2>;
12103 + gic: interrupt-controller@10300000 {
12104 + compatible = "arm,cortex-a7-gic";
12105 + #interrupt-cells = <3>;
12106 + #address-cells = <0>;
12107 + interrupt-controller;
12113 + #address-cells = <1>;
12114 + #size-cells = <1>;
12115 + compatible = "simple-bus";
12116 + interrupt-parent = <&gic>;
12120 + compatible = "arm,cortex-a7-pmu";
12124 + sysctrl: system-controller@12050000 {
12127 + #clock-cells = <1>;
12131 + compatible = "syscon-reboot";
12138 + #address-cells = <1>;
12139 + #size-cells = <1>;
12140 + compatible = "arm,amba-bus";
12151 + clock-names = "timer0", "timer1", "apb_pclk";
12163 + clock-names = "timer2", "timer3", "apb_pclk";
12175 + clock-names = "timer4", "timer5", "apb_pclk";
12187 + clock-names = "timer6", "timer7", "apb_pclk";
12196 + clock-names = "apb_pclk";
12205 + clock-names = "apb_pclk";
12214 + clock-names = "apb_pclk";
12221 + compatible = "hisilicon,hi3536dv100-i2c",
12222 + "hisilicon,hibvt-i2c";
12229 + compatible = "hisilicon,hisi-sata-phy";
12232 + #phy-cells = <0>;
12236 + compatible = "hisilicon,hisi-ahci";
12240 + phy-names = "sata-phy";
12241 + #address-cells = <1>;
12242 + #size-cells = <0>;
12246 + compatible = "hisilicon,hisi-femac-mdio";
12251 + clock-names = "mdio", "phy";
12253 + reset-names = "external-phy", "internal-phy";
12254 + #address-cells = <1>;
12255 + #size-cells = <0>;
12259 + compatible = "hisilicon,hi3536dv100-femac",
12260 + "hisilicon,hisi-femac-v2";
12265 + reset-names = "mac";
12269 + compatible = "hisilicon,hisi-usb-phy";
12274 + compatible = "generic-ehci";
12280 + compatible = "generic-ohci";
12285 + fmc: flash-memory-controller@10000000 {
12286 + compatible = "hisilicon,hisi-fmc";
12288 + reg-names = "control", "memory";
12290 + max-dma-size = <0x2000>;
12291 + #address-cells = <1>;
12292 + #size-cells = <0>;
12294 + hisfc:spi-nor@0 {
12295 + compatible = "hisilicon,fmc-spi-nor";
12296 + assigned-clocks = <&clock HI3536DV100_FMC_CLK>;
12297 + assigned-clock-rates = <24000000>;
12298 + #address-cells = <1>;
12299 + #size-cells = <0>;
12302 + hisnfc:spi-nand@0 {
12303 + compatible = "hisilicon,fmc-spi-nand";
12304 + assigned-clocks = <&clock HI3536DV100_FMC_CLK>;
12305 + assigned-clock-rates = <24000000>;
12306 + #address-cells = <1>;
12307 + #size-cells = <0>;
12311 + hidmac: hidma-controller@11020000 {
12312 + compatible = "hisilicon,hisi-dmac";
12316 + clock-names = "dmac_clk";
12318 + reset-names = "dma-reset";
12319 + #dma-cells = <2>;
12328 + clock-names = "apb_pclk";
12329 + #gpio-cells = <2>;
12338 + clock-names = "apb_pclk";
12339 + #gpio-cells = <2>;
12348 + clock-names = "apb_pclk";
12349 + #gpio-cells = <2>;
12358 + clock-names = "apb_pclk";
12359 + #gpio-cells = <2>;
12368 + clock-names = "apb_pclk";
12369 + #gpio-cells = <2>;
12378 + clock-names = "apb_pclk";
12379 + #gpio-cells = <2>;
12384 + compatible = "pinctrl-single";
12386 + #address-cells = <1>;
12387 + #size-cells = <1>;
12388 + #gpio-range-cells = <3>;
12391 + pinctrl-single,register-width = <32>;
12392 + pinctrl-single,function-mask = <7>;
12394 + pinctrl-single,gpio-range = <&range 0 54 0
12397 + range: gpio-range {
12398 + #pinctrl-single,gpio-range-cells = <3>;
12404 + #address-cells = <1>;
12405 + #size-cells = <1>;
12406 + compatible = "simple-bus";
12407 + interrupt-parent = <&gic>;
12418 + reg-names = "crg", "sys", "ddr", "misc";
12422 + compatible = "hisilicon,hi35xx-rtc";
12443 + reg-names = "aiao", "acodec";
12449 + interrupt-names = "vdm", "scd";
12451 + reg-names = "vdm", "scd";
12463 + interrupt-names = "jpgd";
12465 + reg-names = "jpgd";
12487 + compatible = "hisilicon,pinctrl-ddr";
12495 diff --git a/arch/arm/boot/dts/hi3556av100-emmc.dts b/arch/arm/boot/dts/hi3556av100-emmc.dts
12498 --- /dev/null
12499 +++ b/arch/arm/boot/dts/hi3556av100-emmc.dts
12500 @@ -0,0 +1,25 @@
12526 diff --git a/arch/arm/boot/dts/hi3556av100-flash.dts b/arch/arm/boot/dts/hi3556av100-flash.dts
12529 --- /dev/null
12530 +++ b/arch/arm/boot/dts/hi3556av100-flash.dts
12531 @@ -0,0 +1,25 @@
12557 diff --git a/arch/arm/boot/dts/hi3556av100.dts b/arch/arm/boot/dts/hi3556av100.dts
12560 --- /dev/null
12562 @@ -0,0 +1,275 @@
12564 + * Copyright (c) 2013-2014 Linaro Ltd.
12582 +/dts-v1/;
12594 + #address-cells = <1>;
12595 + #size-cells = <0>;
12598 + compatible = "arm,cortex-a53";
12601 + cci-control-port = <&cci_control0>;
12666 + pl022,com-mode = <0>;
12667 + spi-max-frequency = <50000000>;
12678 + pl022,com-mode = <0>;
12679 + spi-max-frequency = <50000000>;
12690 + pl022,com-mode = <0>;
12691 + spi-max-frequency = <50000000>;
12702 + pl022,com-mode = <0>;
12703 + spi-max-frequency = <50000000>;
12714 + pl022,com-mode = <0>;
12715 + spi-max-frequency = <50000000>;
12720 + ethphy: ethernet-phy@1 {
12726 + phy-handle = <ðphy>;
12727 + phy-mode = "rgmii";
12732 + compatible = "jedec,spi-nor";
12734 + spi-max-frequency = <160000000>;
12735 + m25p,fast-read;
12741 + compatible = "jedec,spi-nand";
12743 + spi-max-frequency = <160000000>;
12751 + nand-max-frequency = <200000000>;
12838 diff --git a/arch/arm/boot/dts/hi3556av100.dtsi b/arch/arm/boot/dts/hi3556av100.dtsi
12841 --- /dev/null
12843 @@ -0,0 +1,974 @@
12845 + * Copyright (c) 2013-2014 Linaro Ltd.
12846 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
12864 +#include <dt-bindings/clock/hi3556av100-clock.h>
12904 + gic: interrupt-controller@1F100000 {
12905 + compatible = "arm,gic-400";
12906 + #interrupt-cells = <3>;
12907 + #address-cells = <0>;
12908 + interrupt-controller;
12914 + compatible = "hisilicon,hi3556av100-clock", "syscon";
12915 + #address-cells = <1>;
12916 + #size-cells = <1>;
12917 + #clock-cells = <1>;
12918 + #reset-cells = <2>;
12924 + compatible = "fixed-clock";
12925 + #clock-cells = <0>;
12926 + clock-frequency = <3000000>;
12930 + compatible = "arm,armv8-timer";
12931 + interrupt-parent = <&gic>;
12934 + clock-frequency = <24000000>;
12938 + compatible = "hisilicon,ipcm-interrupt";
12939 + interrupt-parent = <&gic>;
12946 + #address-cells = <1>;
12947 + #size-cells = <1>;
12948 + compatible = "simple-bus";
12949 + interrupt-parent = <&gic>;
12953 + #address-cells = <1>;
12954 + #size-cells = <1>;
12955 + compatible = "arm,amba-bus";
12963 + clock-names = "apb_pclk";
12972 + clock-names = "apb_pclk";
12981 + clock-names = "apb_pclk";
12990 + clock-names = "apb_pclk";
12999 + clock-names = "apb_pclk";
13004 + compatible = "hisilicon,hibvt-i2c";
13007 + clock-frequency = <100000>;
13012 + compatible = "hisilicon,hibvt-i2c";
13015 + clock-frequency = <100000>;
13020 + compatible = "hisilicon,hibvt-i2c";
13023 + clock-frequency = <100000>;
13028 + compatible = "hisilicon,hibvt-i2c";
13031 + clock-frequency = <100000>;
13036 + compatible = "hisilicon,hibvt-i2c";
13039 + clock-frequency = <100000>;
13044 + compatible = "hisilicon,hibvt-i2c";
13047 + clock-frequency = <100000>;
13052 + compatible = "hisilicon,hibvt-i2c";
13055 + clock-frequency = <100000>;
13060 + compatible = "hisilicon,hibvt-i2c";
13063 + clock-frequency = <100000>;
13068 + compatible = "hisilicon,hibvt-i2c";
13071 + clock-frequency = <100000>;
13076 + compatible = "hisilicon,hibvt-i2c";
13079 + clock-frequency = <100000>;
13085 + arm,primecell-periphid = <0x00800022>;
13089 + clock-names = "apb_pclk";
13090 + #address-cells = <1>;
13091 + #size-cells = <0>;
13093 + num-cs = <1>;
13098 + arm,primecell-periphid = <0x00800022>;
13102 + clock-names = "apb_pclk";
13103 + #address-cells = <1>;
13104 + #size-cells = <0>;
13106 + num-cs = <1>;
13111 + arm,primecell-periphid = <0x00800022>;
13115 + clock-names = "apb_pclk";
13116 + #address-cells = <1>;
13117 + #size-cells = <0>;
13119 + num-cs = <1>;
13124 + arm,primecell-periphid = <0x00800022>;
13128 + clock-names = "apb_pclk";
13129 + #address-cells = <1>;
13130 + #size-cells = <0>;
13132 + num-cs = <1>;
13137 + arm,primecell-periphid = <0x00800022>;
13141 + clock-names = "apb_pclk";
13142 + #address-cells = <1>;
13143 + #size-cells = <0>;
13145 + num-cs = <1>;
13152 + #gpio-cells = <2>;
13154 + clock-names = "apb_pclk";
13162 + #gpio-cells = <2>;
13164 + clock-names = "apb_pclk";
13172 + #gpio-cells = <2>;
13174 + clock-names = "apb_pclk";
13182 + #gpio-cells = <2>;
13184 + clock-names = "apb_pclk";
13192 + #gpio-cells = <2>;
13194 + clock-names = "apb_pclk";
13202 + #gpio-cells = <2>;
13204 + clock-names = "apb_pclk";
13212 + #gpio-cells = <2>;
13214 + clock-names = "apb_pclk";
13222 + #gpio-cells = <2>;
13224 + clock-names = "apb_pclk";
13232 + #gpio-cells = <2>;
13234 + clock-names = "apb_pclk";
13242 + #gpio-cells = <2>;
13244 + clock-names = "apb_pclk";
13252 + #gpio-cells = <2>;
13254 + clock-names = "apb_pclk";
13262 + #gpio-cells = <2>;
13264 + clock-names = "apb_pclk";
13272 + #gpio-cells = <2>;
13274 + clock-names = "apb_pclk";
13282 + #gpio-cells = <2>;
13284 + clock-names = "apb_pclk";
13292 + #gpio-cells = <2>;
13294 + clock-names = "apb_pclk";
13315 + clock-names = "timer0", "timer1", "timer2";
13321 + hivdmac: hivdma-controller@04c10000 {
13322 + compatible = "hisilicon,hisi-vdmac";
13326 + clock-names = "apb_pclk";
13328 + reset-names = "dma-reset";
13329 + #dma-cells = <2>;
13334 + hidmac: hidma-controller@04040000 {
13335 + compatible = "hisilicon,hisi-dmac";
13339 + clock-names = "apb_pclk";
13341 + reset-names = "dma-reset";
13342 + #dma-cells = <2>;
13346 + sysctrl: system-controller@00000000 {
13349 + #clock-cells = <1>;
13353 + compatible = "syscon-reboot";
13360 + misc_ctrl: misc-controller@04528000 {
13361 + compatible = "hisilicon,hisi-miscctrl", "syscon";
13366 + compatible = "hisilicon,hisi-ioconfig", "syscon";
13371 + compatible = "hisilicon,hisi-ioconfig", "syscon";
13376 + compatible = "hisilicon,hisi-ioconfig", "syscon";
13381 + compatible = "hisilicon,hisi-ioconfig", "syscon";
13386 + compatible = "hisilicon,hisi-usb-phy";
13388 + #phy-cells = <0>;
13392 + compatible = "generic-xhci";
13395 + usb2-lpm-disable;
13400 + compatible = "generic-xhci";
13403 + usb2-lpm-disable;
13411 + interrupt-names = "peripheral";
13412 + maximum-speed = "super-speed";
13423 + interrupt-names = "peripheral";
13424 + maximum-speed = "high-speed";
13429 + compatible = "arm,cci-400";
13430 + #address-cells = <1>;
13431 + #size-cells = <1>;
13435 + cci_control0: slave-if@4000 {
13436 + compatible = "arm,cci-400-ctrl-if";
13437 + interface-type = "ace";
13441 + cci_control1: slave-if@5000 {
13442 + compatible = "arm,cci-400-ctrl-if";
13443 + interface-type = "ace";
13450 + compatible = "hisilicon,hisi-gemac-mdio";
13454 + reset-names = "phy_reset";
13455 + #address-cells = <1>;
13456 + #size-cells = <0>;
13466 + clock-names = "higmac_clk",
13471 + reset-names = "port_reset",
13474 + mac-address = [00 00 00 00 00 00];
13477 + fmc: flash-memory-controller@10000000 {
13478 + compatible = "hisilicon,hisi-fmc";
13480 + reg-names = "control", "memory";
13482 + max-dma-size = <0x2000>;
13483 + #address-cells = <1>;
13484 + #size-cells = <0>;
13487 + compatible = "hisilicon,fmc-spi-nor";
13488 + assigned-clocks = <&clock HI3556AV100_FMC_CLK>;
13489 + assigned-clock-rates = <24000000>;
13490 + #address-cells = <1>;
13491 + #size-cells = <0>;
13495 + compatible = "hisilicon,fmc-spi-nand";
13496 + assigned-clocks = <&clock HI3556AV100_FMC_CLK>;
13497 + assigned-clock-rates = <24000000>;
13498 + #address-cells = <1>;
13499 + #size-cells = <0>;
13502 + hinfc:parallel-nand-controller {
13503 + compatible = "hisilicon,fmc-nand";
13504 + assigned-clocks = <&clock HI3556AV100_FMC_CLK>;
13505 + assigned-clock-rates = <200000000>;
13506 + #address-cells = <1>;
13507 + #size-cells = <0>;
13516 + clock-names = "mmc_clk";
13518 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
13519 + max-frequency = <198000000>;
13521 + non-removable;
13522 + bus-width = <8>;
13523 + cap-mmc-highspeed;
13524 + mmc-hs400-1_8v;
13525 + mmc-hs400-enhanced-strobe;
13526 + cap-mmc-hw-reset;
13536 + clock-names = "mmc_clk";
13538 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
13539 + max-frequency = <198000000>;
13543 + bus-width = <4>;
13544 + cap-sd-highspeed;
13545 + sd-uhs-sdr104;
13546 + full-pwr-cycle;
13547 + disable-wp;
13557 + clock-names = "mmc_clk";
13559 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
13560 + max-frequency = <198000000>;
13564 + bus-width = <4>;
13565 + cap-sd-highspeed;
13566 + sd-uhs-sdr104;
13567 + full-pwr-cycle;
13568 + disable-wp;
13574 + compatible = "hisilicon,hisi-cipher";
13576 + reg-names = "cipher", "rsa";
13578 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash", "rsa", "nonsec_rsa";
13588 + compatible = "hisilicon,hi35xx-rtc";
13602 + #address-cells = <1>;
13603 + #size-cells = <1>;
13604 + compatible = "simple-bus";
13605 + interrupt-parent = <&gic>;
13613 + compatible = "hisilicon,hisi-sys";
13616 + reg-names = "crg", "sys", "ddr", "misc";
13620 + compatible = "hisilicon,hisi-mipi";
13622 + reg-names = "mipi_rx", "slvs";
13624 + interrupt-names = "mipi_rx", "slvs";
13628 + compatible = "hisilicon,hisi-mipi_tx";
13630 + reg-names = "mipi_tx";
13632 + interrupt-names = "mipi_tx";
13636 + compatible = "hisilicon,hisi-vi";
13638 + reg-names = "VI_CAP0", "VI_PROC0";
13640 + interrupt-names = "VI_CAP0", "VI_PROC0";
13644 + compatible = "hisilicon,hisi-isp";
13646 + reg-names = "ISP";
13648 + interrupt-names = "ISP";
13652 + compatible = "hisilicon,hisi-vpss";
13654 + reg-names = "vpss0";
13656 + interrupt-names = "vpss0";
13660 + compatible = "hisilicon,hisi-vgs";
13662 + reg-names = "vgs0";
13664 + interrupt-names = "vgs0";
13668 + compatible = "hisilicon,hisi-vo";
13670 + reg-names = "vo";
13672 + interrupt-names = "vo";
13676 + compatible = "hisilicon,hisi-hifb";
13678 + reg-names = "hifb";
13680 + interrupt-names = "hifb";
13684 + compatible = "hisilicon,hisi-tde";
13686 + reg-names = "tde";
13688 + interrupt-names = "tde_osr_isr";
13692 + compatible = "hisilicon,hisi-avs";
13694 + reg-names = "avs";
13696 + interrupt-names = "avs";
13700 + compatible = "hisilicon,hisi-dis";
13702 + reg-names = "dis";
13704 + interrupt-names = "dis";
13708 + compatible = "hisilicon,hisi-gdc";
13710 + reg-names = "gdc";
13712 + interrupt-names = "gdc";
13716 + compatible = "hisilicon,hisi-gzip";
13718 + reg-names = "gzip";
13720 + interrupt-names = "gzip";
13724 + compatible = "hisilicon,hisi-jpegd";
13726 + reg-names = "jpegd";
13728 + interrupt-names = "jpegd";
13732 + compatible = "hisilicon,hisi-vedu";
13734 + reg-names = "vedu0", "jpge";
13736 + interrupt-names = "vedu0","jpge";
13740 + compatible = "hisilicon,hisi-venc";
13744 + compatible = "hisilicon,hisi-vdh";
13746 + reg-names = "vdh_scd";
13748 + interrupt-names = "scd","vdh";
13752 + compatible = "hisilicon,hisi-hdmi";
13754 + reg-names = "hdmi0";
13758 + compatible = "hisilicon,hisi-aiao";
13760 + reg-names = "aiao","acodec","crg";
13762 + interrupt-names = "AIO","VOIE";
13766 + compatible = "hisilicon,hisi-nnie";
13768 + reg-names = "nnie0";
13770 + interrupt-names = "nnie0";
13774 + compatible = "hisilicon,hisi-dpu_rect";
13776 + reg-names = "dpu_rect";
13778 + interrupt-names = "rect";
13782 + compatible = "hisilicon,hisi-dpu_match";
13784 + reg-names = "dpu_match";
13786 + interrupt-names = "match";
13790 + compatible = "hisilicon,hisi-dsp";
13792 + reg-names = "dsp0";
13796 + compatible = "hisilicon,hisi-ive";
13798 + reg-names = "ive";
13800 + interrupt-names = "ive";
13804 + compatible = "hisilicon,hi3519av100-lsadc";
13808 + reset-names = "lsadc-crg";
13818 diff --git a/arch/arm/boot/dts/hi3556v200-demb.dts b/arch/arm/boot/dts/hi3556v200-demb.dts
13821 --- /dev/null
13822 +++ b/arch/arm/boot/dts/hi3556v200-demb.dts
13823 @@ -0,0 +1,250 @@
13825 + * Copyright (c) 2013-2014 Linaro Ltd.
13826 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
13843 +/dts-v1/;
13874 + clock-frequency = <100000>;
13879 + clock-frequency = <100000>;
13884 + clock-frequency = <400000>;
13890 + clock-frequency = <100000>;
13895 + clock-frequency = <100000>;
13900 + clock-frequency = <100000>;
13905 + clock-frequency = <100000>;
13910 + clock-frequency = <100000>;
13915 + num-cs = <1>;
13921 + pl022,com-mode = <0>;
13922 + spi-max-frequency = <25000000>;
13927 + num-cs = <2>;
13933 + pl022,com-mode = <0>;
13934 + spi-max-frequency = <25000000>;
13940 + pl022,com-mode = <0>;
13941 + spi-max-frequency = <25000000>;
13946 + num-cs = <1>;
13952 + pl022,com-mode = <0>;
13953 + spi-max-frequency = <25000000>;
13959 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
13960 + phy0: ethernet-phy@1 {
13966 + mac-address = [00 00 00 00 00 00];
13967 + phy-mode = "rmii";
13968 + phy-handle = <&phy0>;
13974 + compatible = "jedec,spi-nor";
13976 + spi-max-frequency = <160000000>;
13982 + compatible = "jedec,spi-nand";
13984 + spi-max-frequency = <160000000>;
14074 diff --git a/arch/arm/boot/dts/hi3556v200.dtsi b/arch/arm/boot/dts/hi3556v200.dtsi
14077 --- /dev/null
14079 @@ -0,0 +1,896 @@
14081 + * Copyright (c) 2013-2014 Linaro Ltd.
14082 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
14100 +#include <dt-bindings/clock/hi3556v200-clock.h>
14135 + #address-cells = <1>;
14136 + #size-cells = <0>;
14137 + enable-method = "hisilicon,hi3556v200";
14141 + compatible = "arm,cortex-a7";
14142 + clock-frequency = <HI3556V200_FIXED_1000M>;
14148 + compatible = "arm,cortex-a7";
14149 + clock-frequency = <HI3556V200_FIXED_1000M>;
14156 + compatible = "hisilicon,hi3556v200-clock";
14157 + #address-cells = <1>;
14158 + #size-cells = <1>;
14159 + #clock-cells = <1>;
14160 + #reset-cells = <2>;
14164 + gic: interrupt-controller@10300000 {
14165 + compatible = "arm,cortex-a7-gic";
14166 + #interrupt-cells = <3>;
14167 + #address-cells = <0>;
14168 + interrupt-controller;
14174 + compatible = "arm,armv7-timer";
14175 + interrupt-parent = <&gic>;
14178 + clock-frequency = <50000000>;
14182 + #address-cells = <1>;
14183 + #size-cells = <1>;
14184 + compatible = "simple-bus";
14185 + interrupt-parent = <&gic>;
14189 + compatible = "fixed-clock";
14190 + #clock-cells = <0>;
14191 + clock-frequency = <3000000>;
14195 + compatible = "fixed-clock";
14196 + #clock-cells = <0>;
14197 + clock-frequency = <50000000>;
14201 + compatible = "arm,cortex-a7-pmu";
14205 + hiedmacv310_0: hiedma-controller@10060000 {
14210 + clock-names = "apb_pclk", "axi_aclk";
14211 + #clock-cells = <2>;
14213 + reset-names = "dma-reset";
14214 + dma-requests = <32>;
14215 + dma-channels = <8>;
14217 + #dma-cells = <2>;
14222 + hiedmacv310_0: hiedma-controller@10060000 {
14227 + clock-names = "apb_pclk", "axi_aclk";
14228 + #clock-cells = <2>;
14230 + reset-names = "dma-reset";
14231 + dma-requests = <32>;
14232 + dma-channels = <8>;
14234 + #dma-cells = <2>;
14239 + sysctrl: system-controller@12020000 {
14242 + reboot-offset = <0x4>;
14243 + #clock-cells = <1>;
14247 + #address-cells = <1>;
14248 + #size-cells = <1>;
14249 + compatible = "arm,amba-bus";
14263 + clock-names = "timer0", "timer1", "timer2";
14272 + clock-names = "timer20", "timer21", "apb_pclk";
14277 + compatible = "arm,sp805-wdt", "arm,primecell";
14278 + arm,primecell-periphid = <0x00141805>;
14281 + clock-names = "wdog_clk", "apb_pclk";
14286 + compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
14290 + #pwm-cells = <2>;
14299 + clock-names = "apb_pclk";
14308 + clock-names = "apb_pclk";
14311 + dma-names = "tx","rx";
14321 + clock-names = "apb_pclk";
14324 + dma-names = "tx","rx";
14334 + clock-names = "apb_pclk";
14337 + dma-names = "tx","rx";
14347 + clock-names = "apb_pclk";
14350 + dma-names = "tx","rx";
14359 + compatible = "hisilicon,hibvt-i2c";
14364 + dma-names = "tx","rx";
14370 + compatible = "hisilicon,hibvt-i2c";
14375 + dma-names = "tx","rx";
14382 + compatible = "hisilicon,hibvt-i2c";
14387 + dma-names = "tx","rx";
14393 + compatible = "hisilicon,hibvt-i2c";
14398 + dma-names = "tx","rx";
14403 + compatible = "hisilicon,hibvt-i2c";
14408 + dma-names = "tx","rx";
14414 + compatible = "hisilicon,hibvt-i2c";
14419 + dma-names = "tx","rx";
14425 + compatible = "hisilicon,hibvt-i2c";
14430 + dma-names = "tx","rx";
14436 + compatible = "hisilicon,hibvt-i2c";
14441 + dma-names = "tx","rx";
14449 + arm,primecell-periphid = <0x00800022>;
14453 + clock-names = "apb_pclk";
14454 + #address-cells = <1>;
14455 + #size-cells = <0>;
14458 + dma-names = "tx","rx";
14465 + arm,primecell-periphid = <0x00800022>;
14469 + clock-names = "apb_pclk";
14470 + #address-cells = <1>;
14471 + #size-cells = <0>;
14472 + num-cs = <2>;
14477 + dma-names = "tx","rx";
14484 + arm,primecell-periphid = <0x00800022>;
14488 + clock-names = "apb_pclk";
14489 + #address-cells = <1>;
14490 + #size-cells = <0>;
14493 + dma-names = "tx","rx";
14500 + compatible = "hisilicon,ipcm-interrupt";
14501 + interrupt-parent = <&gic>;
14508 + compatible = "hisilicon,hisi-femac-mdio";
14511 + clock-names = "mdio";
14512 + assigned-clocks = <&clock HI3556V200_ETH0_CLK>;
14513 + assigned-clock-rates = <54000000>;
14515 + reset-names = "external-phy";
14516 + #address-cells = <1>;
14517 + #size-cells = <0>;
14521 + compatible = "hisilicon,hi3556v200-femac",
14522 + "hisilicon,hisi-femac-v2";
14527 + reset-names = "mac";
14530 + fmc: flash-memory-controller@10000000 {
14531 + compatible = "hisilicon,hisi-fmc";
14533 + reg-names = "control", "memory";
14535 + max-dma-size = <0x2000>;
14536 + #address-cells = <1>;
14537 + #size-cells = <0>;
14539 + hisfc:spi-nor@0 {
14540 + compatible = "hisilicon,fmc-spi-nor";
14541 + assigned-clocks = <&clock HI3556V200_FMC_CLK>;
14542 + assigned-clock-rates = <24000000>;
14543 + #address-cells = <1>;
14544 + #size-cells = <0>;
14547 + hisnfc:spi-nand@0 {
14548 + compatible = "hisilicon,fmc-spi-nand";
14549 + assigned-clocks = <&clock HI3556V200_FMC_CLK>;
14550 + assigned-clock-rates = <24000000>;
14551 + #address-cells = <1>;
14552 + #size-cells = <0>;
14557 + compatible = "hisilicon,hi3556v200-himci";
14561 + clock-names = "mmc_clk";
14563 + reset-names = "mmc_reset";
14564 + max-frequency = <150000000>;
14565 + bus-width = <4>;
14566 + cap-mmc-highspeed;
14567 + cap-mmc-hw-reset;
14568 + mmc-hs200-1_8v;
14569 + full-pwr-cycle;
14575 + compatible = "hisilicon,hi3556v200-himci";
14579 + clock-names = "mmc_clk";
14581 + reset-names = "mmc_reset";
14582 + max-frequency = <150000000>;
14583 + bus-width = <4>;
14584 + cap-sd-highspeed;
14585 + sd-uhs-sdr12;
14586 + sd-uhs-sdr25;
14587 + sd-uhs-sdr50;
14588 + sd-uhs-sdr104;
14594 + compatible = "hisilicon,hi3556v200-himci";
14598 + clock-names = "mmc_clk";
14600 + reset-names = "mmc_reset";
14601 + max-frequency = <100000000>;
14602 + bus-width = <4>;
14603 + cap-sd-highspeed;
14604 + sd-uhs-sdr12;
14605 + sd-uhs-sdr25;
14606 + sd-uhs-sdr50;
14607 + sd-uhs-sdr104;
14612 + hidmac: hidma-controller@10060000 {
14613 + compatible = "hisilicon,hisi-dmac";
14617 + clock-names = "dmac_clk";
14619 + reset-names = "dma-reset";
14620 + #dma-cells = <2>;
14625 + compatible = "hisilicon,hisi-usb-phy";
14627 + #phy-cells = <0>;
14632 + compatible = "generic-xhci";
14635 + usb2-lpm-disable;
14643 + interrupt-names = "peripheral";
14644 + maximum-speed = "high-speed";
14653 + clock-names = "apb_pclk";
14654 + #gpio-cells = <2>;
14663 + clock-names = "apb_pclk";
14664 + #gpio-cells = <2>;
14673 + clock-names = "apb_pclk";
14674 + #gpio-cells = <2>;
14683 + clock-names = "apb_pclk";
14684 + #gpio-cells = <2>;
14693 + clock-names = "apb_pclk";
14694 + #gpio-cells = <2>;
14703 + clock-names = "apb_pclk";
14704 + #gpio-cells = <2>;
14713 + clock-names = "apb_pclk";
14714 + #gpio-cells = <2>;
14723 + clock-names = "apb_pclk";
14724 + #gpio-cells = <2>;
14733 + clock-names = "apb_pclk";
14734 + #gpio-cells = <2>;
14743 + clock-names = "apb_pclk";
14744 + #gpio-cells = <2>;
14753 + clock-names = "apb_pclk";
14754 + #gpio-cells = <2>;
14763 + clock-names = "apb_pclk";
14764 + #gpio-cells = <2>;
14769 + compatible = "hisilicon,hisi-cipher";
14771 + reg-names = "cipher";
14773 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
14779 + #address-cells = <1>;
14780 + #size-cells = <1>;
14781 + compatible = "simple-bus";
14782 + interrupt-parent = <&gic>;
14794 + compatible = "hisilicon,hisi-sys";
14797 + reg-names = "crg", "sys", "ddr", "misc";
14801 + compatible = "hisilicon,hisi-mipi";
14803 + reg-names = "mipi_rx";
14805 + interrupt-names = "mipi_rx";
14809 + compatible = "hisilicon,hisi-mipi_tx";
14811 + reg-names = "mipi_tx";
14813 + interrupt-names = "mipi_tx";
14817 + compatible = "hisilicon,hisi-vi";
14819 + reg-names = "VI_CAP0", "VI_PROC0";
14821 + interrupt-names = "VI_CAP0", "VI_PROC0";
14825 + compatible = "hisilicon,hisi-isp";
14827 + reg-names = "ISP";
14829 + interrupt-names = "ISP";
14833 + compatible = "hisilicon,hisi-vpss";
14835 + reg-names = "vpss0";
14837 + interrupt-names = "vpss0";
14841 + compatible = "hisilicon,hisi-vgs";
14843 + reg-names = "vgs0";
14845 + interrupt-names = "vgs0";
14849 + compatible = "hisilicon,hisi-vo";
14851 + reg-names = "vo";
14853 + interrupt-names = "vo";
14857 + compatible = "hisilicon,hisi-hifb";
14859 + reg-names = "hifb", "sys";
14861 + interrupt-names = "hifb", "hifb_soft";
14865 + compatible = "hisilicon,hisi-tde";
14867 + reg-names = "tde";
14869 + interrupt-names = "tde_osr_isr";
14873 + compatible = "hisilicon,hisi-gyro-dis";
14877 + compatible = "hisilicon,hisi-gdc";
14879 + reg-names = "gdc", "nnie0";
14881 + interrupt-names = "gdc", "nnie0";
14885 + compatible = "hisilicon,hisi-gzip";
14887 + reg-names = "gzip";
14889 + interrupt-names = "gzip";
14893 + compatible = "hisilicon,hisi-jpegd";
14895 + reg-names = "jpegd";
14897 + interrupt-names = "jpegd";
14901 + compatible = "hisilicon,hisi-vedu";
14903 + reg-names = "vedu0", "jpge";
14905 + interrupt-names = "vedu0","jpge";
14909 + compatible = "hisilicon,hisi-venc";
14913 + compatible = "hisilicon,hisi-scd";
14915 + reg-names = "scd";
14917 + interrupt-names = "scd";
14921 + compatible = "hisilicon,hisi-hdmi";
14923 + reg-names = "hdmi0";
14927 + compatible = "hisilicon,hisi-aiao";
14929 + reg-names = "aiao","acodec","crg";
14931 + interrupt-names = "AIO";
14935 + compatible = "hisilicon,hisi-nnie";
14937 + reg-names = "nnie0","gdc";
14939 + interrupt-names = "nnie0","gdc";
14943 + compatible = "hisilicon,hisi-ive";
14945 + reg-names = "ive";
14947 + interrupt-names = "ive";
14951 + compatible = "hisilicon,hisi-lsadc";
14955 + reset-names = "lsadc-crg";
14965 + compatible = "hisilicon,hi35xx-rtc";
14976 diff --git a/arch/arm/boot/dts/hi3559v200-demb.dts b/arch/arm/boot/dts/hi3559v200-demb.dts
14979 --- /dev/null
14980 +++ b/arch/arm/boot/dts/hi3559v200-demb.dts
14981 @@ -0,0 +1,250 @@
14983 + * Copyright (c) 2013-2014 Linaro Ltd.
14984 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
15001 +/dts-v1/;
15032 + clock-frequency = <100000>;
15037 + clock-frequency = <100000>;
15042 + clock-frequency = <400000>;
15048 + clock-frequency = <100000>;
15053 + clock-frequency = <100000>;
15058 + clock-frequency = <100000>;
15063 + clock-frequency = <100000>;
15068 + clock-frequency = <100000>;
15073 + num-cs = <1>;
15079 + pl022,com-mode = <0>;
15080 + spi-max-frequency = <25000000>;
15085 + num-cs = <2>;
15091 + pl022,com-mode = <0>;
15092 + spi-max-frequency = <25000000>;
15098 + pl022,com-mode = <0>;
15099 + spi-max-frequency = <25000000>;
15104 + num-cs = <1>;
15110 + pl022,com-mode = <0>;
15111 + spi-max-frequency = <25000000>;
15117 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
15118 + phy0: ethernet-phy@1 {
15124 + mac-address = [00 00 00 00 00 00];
15125 + phy-mode = "rmii";
15126 + phy-handle = <&phy0>;
15132 + compatible = "jedec,spi-nor";
15134 + spi-max-frequency = <160000000>;
15140 + compatible = "jedec,spi-nand";
15142 + spi-max-frequency = <160000000>;
15232 diff --git a/arch/arm/boot/dts/hi3559v200.dtsi b/arch/arm/boot/dts/hi3559v200.dtsi
15235 --- /dev/null
15237 @@ -0,0 +1,895 @@
15239 + * Copyright (c) 2013-2014 Linaro Ltd.
15240 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
15258 +#include <dt-bindings/clock/hi3559v200-clock.h>
15293 + #address-cells = <1>;
15294 + #size-cells = <0>;
15295 + enable-method = "hisilicon,hi3559v200";
15299 + compatible = "arm,cortex-a7";
15300 + clock-frequency = <HI3559V200_FIXED_1000M>;
15306 + compatible = "arm,cortex-a7";
15307 + clock-frequency = <HI3559V200_FIXED_1000M>;
15314 + compatible = "hisilicon,hi3559v200-clock";
15315 + #address-cells = <1>;
15316 + #size-cells = <1>;
15317 + #clock-cells = <1>;
15318 + #reset-cells = <2>;
15322 + gic: interrupt-controller@10300000 {
15323 + compatible = "arm,cortex-a7-gic";
15324 + #interrupt-cells = <3>;
15325 + #address-cells = <0>;
15326 + interrupt-controller;
15332 + compatible = "arm,armv7-timer";
15333 + interrupt-parent = <&gic>;
15336 + clock-frequency = <50000000>;
15340 + #address-cells = <1>;
15341 + #size-cells = <1>;
15342 + compatible = "simple-bus";
15343 + interrupt-parent = <&gic>;
15347 + compatible = "fixed-clock";
15348 + #clock-cells = <0>;
15349 + clock-frequency = <3000000>;
15353 + compatible = "fixed-clock";
15354 + #clock-cells = <0>;
15355 + clock-frequency = <50000000>;
15359 + compatible = "arm,cortex-a7-pmu";
15363 + hiedmacv310_0: hiedma-controller@10060000 {
15368 + clock-names = "apb_pclk", "axi_aclk";
15369 + #clock-cells = <2>;
15371 + reset-names = "dma-reset";
15372 + dma-requests = <32>;
15373 + dma-channels = <8>;
15375 + #dma-cells = <2>;
15380 + hiedmacv310_0: hiedma-controller@10060000 {
15385 + clock-names = "apb_pclk", "axi_aclk";
15386 + #clock-cells = <2>;
15388 + reset-names = "dma-reset";
15389 + dma-requests = <32>;
15390 + dma-channels = <8>;
15392 + #dma-cells = <2>;
15397 + sysctrl: system-controller@12020000 {
15400 + reboot-offset = <0x4>;
15401 + #clock-cells = <1>;
15405 + #address-cells = <1>;
15406 + #size-cells = <1>;
15407 + compatible = "arm,amba-bus";
15421 + clock-names = "timer0", "timer1", "timer2";
15430 + clock-names = "timer20", "timer21", "apb_pclk";
15435 + compatible = "arm,sp805-wdt", "arm,primecell";
15436 + arm,primecell-periphid = <0x00141805>;
15439 + clock-names = "wdog_clk", "apb_pclk";
15444 + compatible = "hisilicon,hi3516xx-pwm","hisilicon,hibvt-pwm";
15448 + #pwm-cells = <2>;
15457 + clock-names = "apb_pclk";
15466 + clock-names = "apb_pclk";
15469 + dma-names = "tx","rx";
15479 + clock-names = "apb_pclk";
15482 + dma-names = "tx","rx";
15492 + clock-names = "apb_pclk";
15495 + dma-names = "tx","rx";
15505 + clock-names = "apb_pclk";
15508 + dma-names = "tx","rx";
15517 + compatible = "hisilicon,hibvt-i2c";
15522 + dma-names = "tx","rx";
15528 + compatible = "hisilicon,hibvt-i2c";
15533 + dma-names = "tx","rx";
15540 + compatible = "hisilicon,hibvt-i2c";
15545 + dma-names = "tx","rx";
15551 + compatible = "hisilicon,hibvt-i2c";
15556 + dma-names = "tx","rx";
15561 + compatible = "hisilicon,hibvt-i2c";
15566 + dma-names = "tx","rx";
15571 + compatible = "hisilicon,hibvt-i2c";
15576 + dma-names = "tx","rx";
15582 + compatible = "hisilicon,hibvt-i2c";
15587 + dma-names = "tx","rx";
15593 + compatible = "hisilicon,hibvt-i2c";
15598 + dma-names = "tx","rx";
15606 + arm,primecell-periphid = <0x00800022>;
15610 + clock-names = "apb_pclk";
15611 + #address-cells = <1>;
15612 + #size-cells = <0>;
15615 + dma-names = "tx","rx";
15622 + arm,primecell-periphid = <0x00800022>;
15626 + clock-names = "apb_pclk";
15627 + #address-cells = <1>;
15628 + #size-cells = <0>;
15629 + num-cs = <2>;
15634 + dma-names = "tx","rx";
15641 + arm,primecell-periphid = <0x00800022>;
15645 + clock-names = "apb_pclk";
15646 + #address-cells = <1>;
15647 + #size-cells = <0>;
15650 + dma-names = "tx","rx";
15657 + compatible = "hisilicon,ipcm-interrupt";
15658 + interrupt-parent = <&gic>;
15665 + compatible = "hisilicon,hisi-femac-mdio";
15668 + clock-names = "mdio";
15669 + assigned-clocks = <&clock HI3559V200_ETH0_CLK>;
15670 + assigned-clock-rates = <54000000>;
15672 + reset-names = "external-phy";
15673 + #address-cells = <1>;
15674 + #size-cells = <0>;
15678 + compatible = "hisilicon,hi3559v200-femac",
15679 + "hisilicon,hisi-femac-v2";
15684 + reset-names = "mac";
15687 + fmc: flash-memory-controller@10000000 {
15688 + compatible = "hisilicon,hisi-fmc";
15690 + reg-names = "control", "memory";
15692 + max-dma-size = <0x2000>;
15693 + #address-cells = <1>;
15694 + #size-cells = <0>;
15696 + hisfc:spi-nor@0 {
15697 + compatible = "hisilicon,fmc-spi-nor";
15698 + assigned-clocks = <&clock HI3559V200_FMC_CLK>;
15699 + assigned-clock-rates = <24000000>;
15700 + #address-cells = <1>;
15701 + #size-cells = <0>;
15704 + hisnfc:spi-nand@0 {
15705 + compatible = "hisilicon,fmc-spi-nand";
15706 + assigned-clocks = <&clock HI3559V200_FMC_CLK>;
15707 + assigned-clock-rates = <24000000>;
15708 + #address-cells = <1>;
15709 + #size-cells = <0>;
15714 + compatible = "hisilicon,hi3559v200-himci";
15718 + clock-names = "mmc_clk";
15720 + reset-names = "mmc_reset";
15721 + max-frequency = <150000000>;
15722 + bus-width = <4>;
15723 + cap-mmc-highspeed;
15724 + cap-mmc-hw-reset;
15725 + mmc-hs200-1_8v;
15726 + full-pwr-cycle;
15732 + compatible = "hisilicon,hi3559v200-himci";
15736 + clock-names = "mmc_clk";
15738 + reset-names = "mmc_reset";
15739 + max-frequency = <150000000>;
15740 + bus-width = <4>;
15741 + cap-sd-highspeed;
15742 + sd-uhs-sdr12;
15743 + sd-uhs-sdr25;
15744 + sd-uhs-sdr50;
15745 + sd-uhs-sdr104;
15751 + compatible = "hisilicon,hi3559v200-himci";
15755 + clock-names = "mmc_clk";
15757 + reset-names = "mmc_reset";
15758 + max-frequency = <100000000>;
15759 + bus-width = <4>;
15760 + cap-sd-highspeed;
15761 + sd-uhs-sdr12;
15762 + sd-uhs-sdr25;
15763 + sd-uhs-sdr50;
15764 + sd-uhs-sdr104;
15769 + hidmac: hidma-controller@10060000 {
15770 + compatible = "hisilicon,hisi-dmac";
15774 + clock-names = "dmac_clk";
15776 + reset-names = "dma-reset";
15777 + #dma-cells = <2>;
15782 + compatible = "hisilicon,hisi-usb-phy";
15784 + #phy-cells = <0>;
15789 + compatible = "generic-xhci";
15792 + usb2-lpm-disable;
15800 + interrupt-names = "peripheral";
15801 + maximum-speed = "high-speed";
15810 + clock-names = "apb_pclk";
15811 + #gpio-cells = <2>;
15820 + clock-names = "apb_pclk";
15821 + #gpio-cells = <2>;
15830 + clock-names = "apb_pclk";
15831 + #gpio-cells = <2>;
15840 + clock-names = "apb_pclk";
15841 + #gpio-cells = <2>;
15850 + clock-names = "apb_pclk";
15851 + #gpio-cells = <2>;
15860 + clock-names = "apb_pclk";
15861 + #gpio-cells = <2>;
15870 + clock-names = "apb_pclk";
15871 + #gpio-cells = <2>;
15880 + clock-names = "apb_pclk";
15881 + #gpio-cells = <2>;
15890 + clock-names = "apb_pclk";
15891 + #gpio-cells = <2>;
15900 + clock-names = "apb_pclk";
15901 + #gpio-cells = <2>;
15910 + clock-names = "apb_pclk";
15911 + #gpio-cells = <2>;
15920 + clock-names = "apb_pclk";
15921 + #gpio-cells = <2>;
15926 + compatible = "hisilicon,hisi-cipher";
15928 + reg-names = "cipher";
15930 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
15936 + #address-cells = <1>;
15937 + #size-cells = <1>;
15938 + compatible = "simple-bus";
15939 + interrupt-parent = <&gic>;
15951 + compatible = "hisilicon,hisi-sys";
15954 + reg-names = "crg", "sys", "ddr", "misc";
15958 + compatible = "hisilicon,hisi-mipi";
15960 + reg-names = "mipi_rx";
15962 + interrupt-names = "mipi_rx";
15966 + compatible = "hisilicon,hisi-mipi_tx";
15968 + reg-names = "mipi_tx";
15970 + interrupt-names = "mipi_tx";
15974 + compatible = "hisilicon,hisi-vi";
15976 + reg-names = "VI_CAP0", "VI_PROC0";
15978 + interrupt-names = "VI_CAP0", "VI_PROC0";
15982 + compatible = "hisilicon,hisi-isp";
15984 + reg-names = "ISP";
15986 + interrupt-names = "ISP";
15990 + compatible = "hisilicon,hisi-vpss";
15992 + reg-names = "vpss0";
15994 + interrupt-names = "vpss0";
15998 + compatible = "hisilicon,hisi-vgs";
16000 + reg-names = "vgs0";
16002 + interrupt-names = "vgs0";
16006 + compatible = "hisilicon,hisi-vo";
16008 + reg-names = "vo";
16010 + interrupt-names = "vo";
16014 + compatible = "hisilicon,hisi-hifb";
16016 + reg-names = "hifb", "sys";
16018 + interrupt-names = "hifb", "hifb_soft";
16022 + compatible = "hisilicon,hisi-tde";
16024 + reg-names = "tde";
16026 + interrupt-names = "tde_osr_isr";
16030 + compatible = "hisilicon,hisi-gyro-dis";
16034 + compatible = "hisilicon,hisi-gdc";
16036 + reg-names = "gdc", "nnie0";
16038 + interrupt-names = "gdc", "nnie0";
16042 + compatible = "hisilicon,hisi-gzip";
16044 + reg-names = "gzip";
16046 + interrupt-names = "gzip";
16050 + compatible = "hisilicon,hisi-jpegd";
16052 + reg-names = "jpegd";
16054 + interrupt-names = "jpegd";
16058 + compatible = "hisilicon,hisi-vedu";
16060 + reg-names = "vedu0", "jpge";
16062 + interrupt-names = "vedu0","jpge";
16066 + compatible = "hisilicon,hisi-venc";
16070 + compatible = "hisilicon,hisi-scd";
16072 + reg-names = "scd";
16074 + interrupt-names = "scd";
16078 + compatible = "hisilicon,hisi-hdmi";
16080 + reg-names = "hdmi0";
16084 + compatible = "hisilicon,hisi-aiao";
16086 + reg-names = "aiao","acodec","crg";
16088 + interrupt-names = "AIO";
16092 + compatible = "hisilicon,hisi-nnie";
16094 + reg-names = "nnie0","gdc";
16096 + interrupt-names = "nnie0","gdc";
16100 + compatible = "hisilicon,hisi-ive";
16102 + reg-names = "ive";
16104 + interrupt-names = "ive";
16108 + compatible = "hisilicon,hisi-lsadc";
16112 + reset-names = "lsadc-crg";
16122 + compatible = "hisilicon,hi35xx-rtc";
16133 diff --git a/arch/arm/boot/dts/hi3562v100-demb.dts b/arch/arm/boot/dts/hi3562v100-demb.dts
16136 --- /dev/null
16137 +++ b/arch/arm/boot/dts/hi3562v100-demb.dts
16138 @@ -0,0 +1,233 @@
16140 + * Copyright (c) 2013-2014 Linaro Ltd.
16141 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
16158 +/dts-v1/;
16184 + clock-frequency = <100000>;
16189 + clock-frequency = <100000>;
16195 + clock-frequency = <100000>;
16200 + clock-frequency = <100000>;
16205 + clock-frequency = <100000>;
16210 + clock-frequency = <100000>;
16215 + clock-frequency = <100000>;
16220 + clock-frequency = <100000>;
16225 + num-cs = <1>;
16231 + pl022,com-mode = <0>;
16232 + spi-max-frequency = <25000000>;
16237 + num-cs = <2>;
16243 + pl022,com-mode = <0>;
16244 + spi-max-frequency = <25000000>;
16250 + pl022,com-mode = <0>;
16251 + spi-max-frequency = <25000000>;
16256 + num-cs = <1>;
16262 + pl022,com-mode = <0>;
16263 + spi-max-frequency = <25000000>;
16269 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
16270 + phy0: ethernet-phy@1 {
16276 + mac-address = [00 00 00 00 00 00];
16277 + phy-mode = "rmii";
16278 + phy-handle = <&phy0>;
16284 + compatible = "jedec,spi-nor";
16286 + spi-max-frequency = <160000000>;
16292 + compatible = "jedec,spi-nand";
16294 + spi-max-frequency = <160000000>;
16372 diff --git a/arch/arm/boot/dts/hi3562v100.dtsi b/arch/arm/boot/dts/hi3562v100.dtsi
16375 --- /dev/null
16377 @@ -0,0 +1,868 @@
16379 + * Copyright (c) 2013-2014 Linaro Ltd.
16380 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
16398 +#include <dt-bindings/clock/hi3559v200-clock.h>
16431 + #address-cells = <1>;
16432 + #size-cells = <0>;
16433 + enable-method = "hisilicon,hi3559v200";
16437 + compatible = "arm,cortex-a7";
16438 + clock-frequency = <HI3559V200_FIXED_1000M>;
16444 + compatible = "arm,cortex-a7";
16445 + clock-frequency = <HI3559V200_FIXED_1000M>;
16452 + compatible = "hisilicon,hi3559v200-clock";
16453 + #address-cells = <1>;
16454 + #size-cells = <1>;
16455 + #clock-cells = <1>;
16456 + #reset-cells = <2>;
16460 + gic: interrupt-controller@10300000 {
16461 + compatible = "arm,cortex-a7-gic";
16462 + #interrupt-cells = <3>;
16463 + #address-cells = <0>;
16464 + interrupt-controller;
16470 + compatible = "arm,armv7-timer";
16471 + interrupt-parent = <&gic>;
16474 + clock-frequency = <50000000>;
16478 + #address-cells = <1>;
16479 + #size-cells = <1>;
16480 + compatible = "simple-bus";
16481 + interrupt-parent = <&gic>;
16485 + compatible = "fixed-clock";
16486 + #clock-cells = <0>;
16487 + clock-frequency = <3000000>;
16491 + compatible = "fixed-clock";
16492 + #clock-cells = <0>;
16493 + clock-frequency = <50000000>;
16497 + compatible = "arm,cortex-a7-pmu";
16501 + hiedmacv310_0: hiedma-controller@10060000 {
16506 + clock-names = "apb_pclk", "axi_aclk";
16507 + #clock-cells = <2>;
16509 + reset-names = "dma-reset";
16510 + dma-requests = <32>;
16511 + dma-channels = <8>;
16513 + #dma-cells = <2>;
16518 + hiedmacv310_0: hiedma-controller@10060000 {
16523 + clock-names = "apb_pclk", "axi_aclk";
16524 + #clock-cells = <2>;
16526 + reset-names = "dma-reset";
16527 + dma-requests = <32>;
16528 + dma-channels = <8>;
16530 + #dma-cells = <2>;
16535 + sysctrl: system-controller@12020000 {
16538 + reboot-offset = <0x4>;
16539 + #clock-cells = <1>;
16543 + #address-cells = <1>;
16544 + #size-cells = <1>;
16545 + compatible = "arm,amba-bus";
16559 + clock-names = "timer0", "timer1", "timer2";
16568 + clock-names = "timer20", "timer21", "apb_pclk";
16577 + clock-names = "apb_pclk";
16586 + clock-names = "apb_pclk";
16589 + dma-names = "tx","rx";
16599 + clock-names = "apb_pclk";
16602 + dma-names = "tx","rx";
16612 + clock-names = "apb_pclk";
16615 + dma-names = "tx","rx";
16625 + clock-names = "apb_pclk";
16628 + dma-names = "tx","rx";
16637 + compatible = "hisilicon,hibvt-i2c";
16642 + dma-names = "tx","rx";
16648 + compatible = "hisilicon,hibvt-i2c";
16653 + dma-names = "tx","rx";
16659 + compatible = "hisilicon,hibvt-i2c";
16664 + dma-names = "tx","rx";
16671 + compatible = "hisilicon,hibvt-i2c";
16676 + dma-names = "tx","rx";
16681 + compatible = "hisilicon,hibvt-i2c";
16686 + dma-names = "tx","rx";
16691 + compatible = "hisilicon,hibvt-i2c";
16696 + dma-names = "tx","rx";
16702 + compatible = "hisilicon,hibvt-i2c";
16707 + dma-names = "tx","rx";
16713 + compatible = "hisilicon,hibvt-i2c";
16718 + dma-names = "tx","rx";
16726 + arm,primecell-periphid = <0x00800022>;
16730 + clock-names = "apb_pclk";
16731 + #address-cells = <1>;
16732 + #size-cells = <0>;
16735 + dma-names = "tx","rx";
16742 + arm,primecell-periphid = <0x00800022>;
16746 + clock-names = "apb_pclk";
16747 + #address-cells = <1>;
16748 + #size-cells = <0>;
16749 + num-cs = <2>;
16754 + dma-names = "tx","rx";
16761 + arm,primecell-periphid = <0x00800022>;
16765 + clock-names = "apb_pclk";
16766 + #address-cells = <1>;
16767 + #size-cells = <0>;
16770 + dma-names = "tx","rx";
16777 + compatible = "hisilicon,ipcm-interrupt";
16778 + interrupt-parent = <&gic>;
16785 + compatible = "hisilicon,hisi-femac-mdio";
16788 + clock-names = "mdio";
16789 + assigned-clocks = <&clock HI3559V200_ETH0_CLK>;
16790 + assigned-clock-rates = <54000000>;
16792 + reset-names = "external-phy";
16793 + #address-cells = <1>;
16794 + #size-cells = <0>;
16798 + compatible = "hisilicon,hi3559v200-femac",
16799 + "hisilicon,hisi-femac-v2";
16804 + reset-names = "mac";
16807 + fmc: flash-memory-controller@10000000 {
16808 + compatible = "hisilicon,hisi-fmc";
16810 + reg-names = "control", "memory";
16812 + max-dma-size = <0x2000>;
16813 + #address-cells = <1>;
16814 + #size-cells = <0>;
16816 + hisfc:spi-nor@0 {
16817 + compatible = "hisilicon,fmc-spi-nor";
16818 + assigned-clocks = <&clock HI3559V200_FMC_CLK>;
16819 + assigned-clock-rates = <24000000>;
16820 + #address-cells = <1>;
16821 + #size-cells = <0>;
16824 + hisnfc:spi-nand@0 {
16825 + compatible = "hisilicon,fmc-spi-nand";
16826 + assigned-clocks = <&clock HI3559V200_FMC_CLK>;
16827 + assigned-clock-rates = <24000000>;
16828 + #address-cells = <1>;
16829 + #size-cells = <0>;
16834 + compatible = "hisilicon,hi3559v200-himci";
16838 + clock-names = "mmc_clk";
16840 + reset-names = "mmc_reset";
16841 + max-frequency = <150000000>;
16842 + bus-width = <4>;
16843 + cap-mmc-highspeed;
16844 + cap-mmc-hw-reset;
16845 + mmc-hs200-1_8v;
16846 + full-pwr-cycle;
16852 + compatible = "hisilicon,hi3559v200-himci";
16856 + clock-names = "mmc_clk";
16858 + reset-names = "mmc_reset";
16859 + max-frequency = <150000000>;
16860 + bus-width = <4>;
16861 + cap-sd-highspeed;
16862 + sd-uhs-sdr12;
16863 + sd-uhs-sdr25;
16864 + sd-uhs-sdr50;
16865 + sd-uhs-sdr104;
16871 + compatible = "hisilicon,hi3559v200-himci";
16875 + clock-names = "mmc_clk";
16877 + reset-names = "mmc_reset";
16878 + max-frequency = <100000000>;
16879 + bus-width = <4>;
16880 + cap-sd-highspeed;
16881 + sd-uhs-sdr12;
16882 + sd-uhs-sdr25;
16883 + sd-uhs-sdr50;
16884 + sd-uhs-sdr104;
16889 + hidmac: hidma-controller@10060000 {
16890 + compatible = "hisilicon,hisi-dmac";
16894 + clock-names = "dmac_clk";
16896 + reset-names = "dma-reset";
16897 + #dma-cells = <2>;
16902 + compatible = "hisilicon,hisi-usb-phy";
16904 + #phy-cells = <0>;
16909 + compatible = "generic-xhci";
16912 + usb2-lpm-disable;
16920 + interrupt-names = "peripheral";
16921 + maximum-speed = "high-speed";
16930 + clock-names = "apb_pclk";
16931 + #gpio-cells = <2>;
16940 + clock-names = "apb_pclk";
16941 + #gpio-cells = <2>;
16950 + clock-names = "apb_pclk";
16951 + #gpio-cells = <2>;
16960 + clock-names = "apb_pclk";
16961 + #gpio-cells = <2>;
16970 + clock-names = "apb_pclk";
16971 + #gpio-cells = <2>;
16980 + clock-names = "apb_pclk";
16981 + #gpio-cells = <2>;
16990 + clock-names = "apb_pclk";
16991 + #gpio-cells = <2>;
17000 + clock-names = "apb_pclk";
17001 + #gpio-cells = <2>;
17010 + clock-names = "apb_pclk";
17011 + #gpio-cells = <2>;
17020 + clock-names = "apb_pclk";
17021 + #gpio-cells = <2>;
17030 + clock-names = "apb_pclk";
17031 + #gpio-cells = <2>;
17040 + clock-names = "apb_pclk";
17041 + #gpio-cells = <2>;
17046 + compatible = "hisilicon,hisi-cipher";
17048 + reg-names = "cipher";
17050 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
17056 + #address-cells = <1>;
17057 + #size-cells = <1>;
17058 + compatible = "simple-bus";
17059 + interrupt-parent = <&gic>;
17067 + compatible = "hisilicon,hisi-sys";
17070 + reg-names = "crg", "sys", "ddr", "misc";
17074 + compatible = "hisilicon,hisi-mipi";
17076 + reg-names = "mipi_rx";
17078 + interrupt-names = "mipi_rx";
17082 + compatible = "hisilicon,hisi-mipi_tx";
17084 + reg-names = "mipi_tx";
17086 + interrupt-names = "mipi_tx";
17090 + compatible = "hisilicon,hisi-vi";
17092 + reg-names = "VI_CAP0", "VI_PROC0";
17094 + interrupt-names = "VI_CAP0", "VI_PROC0";
17098 + compatible = "hisilicon,hisi-isp";
17100 + reg-names = "ISP";
17102 + interrupt-names = "ISP";
17106 + compatible = "hisilicon,hisi-vpss";
17108 + reg-names = "vpss0";
17110 + interrupt-names = "vpss0";
17114 + compatible = "hisilicon,hisi-vgs";
17116 + reg-names = "vgs0";
17118 + interrupt-names = "vgs0";
17122 + compatible = "hisilicon,hisi-vo";
17124 + reg-names = "vo";
17126 + interrupt-names = "vo";
17130 + compatible = "hisilicon,hisi-hifb";
17132 + reg-names = "hifb", "sys";
17134 + interrupt-names = "hifb", "hifb_soft";
17138 + compatible = "hisilicon,hisi-tde";
17140 + reg-names = "tde";
17142 + interrupt-names = "tde_osr_isr";
17146 + compatible = "hisilicon,hisi-gdc";
17148 + reg-names = "gdc", "nnie0";
17150 + interrupt-names = "gdc", "nnie0";
17154 + compatible = "hisilicon,hisi-gzip";
17156 + reg-names = "gzip";
17158 + interrupt-names = "gzip";
17162 + compatible = "hisilicon,hisi-jpegd";
17164 + reg-names = "jpegd";
17166 + interrupt-names = "jpegd";
17170 + compatible = "hisilicon,hisi-vedu";
17172 + reg-names = "vedu0", "jpge";
17174 + interrupt-names = "vedu0","jpge";
17178 + compatible = "hisilicon,hisi-scd";
17180 + reg-names = "scd";
17182 + interrupt-names = "scd";
17186 + compatible = "hisilicon,hisi-hdmi";
17188 + reg-names = "hdmi0";
17192 + compatible = "hisilicon,hisi-aiao";
17194 + reg-names = "aiao","acodec","crg";
17196 + interrupt-names = "AIO";
17200 + compatible = "hisilicon,hisi-nnie";
17202 + reg-names = "nnie0","gdc";
17204 + interrupt-names = "nnie0","gdc";
17208 + compatible = "hisilicon,hisi-ive";
17210 + reg-names = "ive";
17212 + interrupt-names = "ive";
17216 + compatible = "hisilicon,hisi-lsadc";
17220 + reset-names = "lsadc-crg";
17230 + compatible = "hisilicon,hi35xx-rtc";
17242 + reg-names = "pmc";
17246 diff --git a/arch/arm/boot/dts/hi3566v100-demb.dts b/arch/arm/boot/dts/hi3566v100-demb.dts
17249 --- /dev/null
17250 +++ b/arch/arm/boot/dts/hi3566v100-demb.dts
17251 @@ -0,0 +1,233 @@
17253 + * Copyright (c) 2013-2014 Linaro Ltd.
17254 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
17271 +/dts-v1/;
17297 + clock-frequency = <100000>;
17302 + clock-frequency = <100000>;
17308 + clock-frequency = <100000>;
17313 + clock-frequency = <100000>;
17318 + clock-frequency = <100000>;
17323 + clock-frequency = <100000>;
17328 + clock-frequency = <100000>;
17333 + clock-frequency = <100000>;
17338 + num-cs = <1>;
17344 + pl022,com-mode = <0>;
17345 + spi-max-frequency = <25000000>;
17350 + num-cs = <2>;
17356 + pl022,com-mode = <0>;
17357 + spi-max-frequency = <25000000>;
17363 + pl022,com-mode = <0>;
17364 + spi-max-frequency = <25000000>;
17369 + num-cs = <1>;
17375 + pl022,com-mode = <0>;
17376 + spi-max-frequency = <25000000>;
17382 + hisilicon,phy-reset-delays-us = <10000 20000 150000>;
17383 + phy0: ethernet-phy@1 {
17389 + mac-address = [00 00 00 00 00 00];
17390 + phy-mode = "rmii";
17391 + phy-handle = <&phy0>;
17397 + compatible = "jedec,spi-nor";
17399 + spi-max-frequency = <160000000>;
17405 + compatible = "jedec,spi-nand";
17407 + spi-max-frequency = <160000000>;
17485 diff --git a/arch/arm/boot/dts/hi3566v100.dtsi b/arch/arm/boot/dts/hi3566v100.dtsi
17488 --- /dev/null
17490 @@ -0,0 +1,868 @@
17492 + * Copyright (c) 2013-2014 Linaro Ltd.
17493 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
17511 +#include <dt-bindings/clock/hi3559v200-clock.h>
17544 + #address-cells = <1>;
17545 + #size-cells = <0>;
17546 + enable-method = "hisilicon,hi3559v200";
17550 + compatible = "arm,cortex-a7";
17551 + clock-frequency = <HI3559V200_FIXED_1000M>;
17557 + compatible = "arm,cortex-a7";
17558 + clock-frequency = <HI3559V200_FIXED_1000M>;
17565 + compatible = "hisilicon,hi3559v200-clock";
17566 + #address-cells = <1>;
17567 + #size-cells = <1>;
17568 + #clock-cells = <1>;
17569 + #reset-cells = <2>;
17573 + gic: interrupt-controller@10300000 {
17574 + compatible = "arm,cortex-a7-gic";
17575 + #interrupt-cells = <3>;
17576 + #address-cells = <0>;
17577 + interrupt-controller;
17583 + compatible = "arm,armv7-timer";
17584 + interrupt-parent = <&gic>;
17587 + clock-frequency = <50000000>;
17591 + #address-cells = <1>;
17592 + #size-cells = <1>;
17593 + compatible = "simple-bus";
17594 + interrupt-parent = <&gic>;
17598 + compatible = "fixed-clock";
17599 + #clock-cells = <0>;
17600 + clock-frequency = <3000000>;
17604 + compatible = "fixed-clock";
17605 + #clock-cells = <0>;
17606 + clock-frequency = <50000000>;
17610 + compatible = "arm,cortex-a7-pmu";
17614 + hiedmacv310_0: hiedma-controller@10060000 {
17619 + clock-names = "apb_pclk", "axi_aclk";
17620 + #clock-cells = <2>;
17622 + reset-names = "dma-reset";
17623 + dma-requests = <32>;
17624 + dma-channels = <8>;
17626 + #dma-cells = <2>;
17631 + hiedmacv310_0: hiedma-controller@10060000 {
17636 + clock-names = "apb_pclk", "axi_aclk";
17637 + #clock-cells = <2>;
17639 + reset-names = "dma-reset";
17640 + dma-requests = <32>;
17641 + dma-channels = <8>;
17643 + #dma-cells = <2>;
17648 + sysctrl: system-controller@12020000 {
17651 + reboot-offset = <0x4>;
17652 + #clock-cells = <1>;
17656 + #address-cells = <1>;
17657 + #size-cells = <1>;
17658 + compatible = "arm,amba-bus";
17672 + clock-names = "timer0", "timer1", "timer2";
17681 + clock-names = "timer20", "timer21", "apb_pclk";
17690 + clock-names = "apb_pclk";
17699 + clock-names = "apb_pclk";
17702 + dma-names = "tx","rx";
17712 + clock-names = "apb_pclk";
17715 + dma-names = "tx","rx";
17725 + clock-names = "apb_pclk";
17728 + dma-names = "tx","rx";
17738 + clock-names = "apb_pclk";
17741 + dma-names = "tx","rx";
17750 + compatible = "hisilicon,hibvt-i2c";
17755 + dma-names = "tx","rx";
17761 + compatible = "hisilicon,hibvt-i2c";
17766 + dma-names = "tx","rx";
17772 + compatible = "hisilicon,hibvt-i2c";
17777 + dma-names = "tx","rx";
17784 + compatible = "hisilicon,hibvt-i2c";
17789 + dma-names = "tx","rx";
17794 + compatible = "hisilicon,hibvt-i2c";
17799 + dma-names = "tx","rx";
17804 + compatible = "hisilicon,hibvt-i2c";
17809 + dma-names = "tx","rx";
17815 + compatible = "hisilicon,hibvt-i2c";
17820 + dma-names = "tx","rx";
17826 + compatible = "hisilicon,hibvt-i2c";
17831 + dma-names = "tx","rx";
17839 + arm,primecell-periphid = <0x00800022>;
17843 + clock-names = "apb_pclk";
17844 + #address-cells = <1>;
17845 + #size-cells = <0>;
17848 + dma-names = "tx","rx";
17855 + arm,primecell-periphid = <0x00800022>;
17859 + clock-names = "apb_pclk";
17860 + #address-cells = <1>;
17861 + #size-cells = <0>;
17862 + num-cs = <2>;
17867 + dma-names = "tx","rx";
17874 + arm,primecell-periphid = <0x00800022>;
17878 + clock-names = "apb_pclk";
17879 + #address-cells = <1>;
17880 + #size-cells = <0>;
17883 + dma-names = "tx","rx";
17890 + compatible = "hisilicon,ipcm-interrupt";
17891 + interrupt-parent = <&gic>;
17898 + compatible = "hisilicon,hisi-femac-mdio";
17901 + clock-names = "mdio";
17902 + assigned-clocks = <&clock HI3559V200_ETH0_CLK>;
17903 + assigned-clock-rates = <54000000>;
17905 + reset-names = "external-phy";
17906 + #address-cells = <1>;
17907 + #size-cells = <0>;
17911 + compatible = "hisilicon,hi3559v200-femac",
17912 + "hisilicon,hisi-femac-v2";
17917 + reset-names = "mac";
17920 + fmc: flash-memory-controller@10000000 {
17921 + compatible = "hisilicon,hisi-fmc";
17923 + reg-names = "control", "memory";
17925 + max-dma-size = <0x2000>;
17926 + #address-cells = <1>;
17927 + #size-cells = <0>;
17929 + hisfc:spi-nor@0 {
17930 + compatible = "hisilicon,fmc-spi-nor";
17931 + assigned-clocks = <&clock HI3559V200_FMC_CLK>;
17932 + assigned-clock-rates = <24000000>;
17933 + #address-cells = <1>;
17934 + #size-cells = <0>;
17937 + hisnfc:spi-nand@0 {
17938 + compatible = "hisilicon,fmc-spi-nand";
17939 + assigned-clocks = <&clock HI3559V200_FMC_CLK>;
17940 + assigned-clock-rates = <24000000>;
17941 + #address-cells = <1>;
17942 + #size-cells = <0>;
17947 + compatible = "hisilicon,hi3559v200-himci";
17951 + clock-names = "mmc_clk";
17953 + reset-names = "mmc_reset";
17954 + max-frequency = <150000000>;
17955 + bus-width = <4>;
17956 + cap-mmc-highspeed;
17957 + cap-mmc-hw-reset;
17958 + mmc-hs200-1_8v;
17959 + full-pwr-cycle;
17965 + compatible = "hisilicon,hi3559v200-himci";
17969 + clock-names = "mmc_clk";
17971 + reset-names = "mmc_reset";
17972 + max-frequency = <150000000>;
17973 + bus-width = <4>;
17974 + cap-sd-highspeed;
17975 + sd-uhs-sdr12;
17976 + sd-uhs-sdr25;
17977 + sd-uhs-sdr50;
17978 + sd-uhs-sdr104;
17984 + compatible = "hisilicon,hi3559v200-himci";
17988 + clock-names = "mmc_clk";
17990 + reset-names = "mmc_reset";
17991 + max-frequency = <100000000>;
17992 + bus-width = <4>;
17993 + cap-sd-highspeed;
17994 + sd-uhs-sdr12;
17995 + sd-uhs-sdr25;
17996 + sd-uhs-sdr50;
17997 + sd-uhs-sdr104;
18002 + hidmac: hidma-controller@10060000 {
18003 + compatible = "hisilicon,hisi-dmac";
18007 + clock-names = "dmac_clk";
18009 + reset-names = "dma-reset";
18010 + #dma-cells = <2>;
18015 + compatible = "hisilicon,hisi-usb-phy";
18017 + #phy-cells = <0>;
18022 + compatible = "generic-xhci";
18025 + usb2-lpm-disable;
18033 + interrupt-names = "peripheral";
18034 + maximum-speed = "high-speed";
18043 + clock-names = "apb_pclk";
18044 + #gpio-cells = <2>;
18053 + clock-names = "apb_pclk";
18054 + #gpio-cells = <2>;
18063 + clock-names = "apb_pclk";
18064 + #gpio-cells = <2>;
18073 + clock-names = "apb_pclk";
18074 + #gpio-cells = <2>;
18083 + clock-names = "apb_pclk";
18084 + #gpio-cells = <2>;
18093 + clock-names = "apb_pclk";
18094 + #gpio-cells = <2>;
18103 + clock-names = "apb_pclk";
18104 + #gpio-cells = <2>;
18113 + clock-names = "apb_pclk";
18114 + #gpio-cells = <2>;
18123 + clock-names = "apb_pclk";
18124 + #gpio-cells = <2>;
18133 + clock-names = "apb_pclk";
18134 + #gpio-cells = <2>;
18143 + clock-names = "apb_pclk";
18144 + #gpio-cells = <2>;
18153 + clock-names = "apb_pclk";
18154 + #gpio-cells = <2>;
18159 + compatible = "hisilicon,hisi-cipher";
18161 + reg-names = "cipher";
18163 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash";
18169 + #address-cells = <1>;
18170 + #size-cells = <1>;
18171 + compatible = "simple-bus";
18172 + interrupt-parent = <&gic>;
18180 + compatible = "hisilicon,hisi-sys";
18183 + reg-names = "crg", "sys", "ddr", "misc";
18187 + compatible = "hisilicon,hisi-mipi";
18189 + reg-names = "mipi_rx";
18191 + interrupt-names = "mipi_rx";
18195 + compatible = "hisilicon,hisi-mipi_tx";
18197 + reg-names = "mipi_tx";
18199 + interrupt-names = "mipi_tx";
18203 + compatible = "hisilicon,hisi-vi";
18205 + reg-names = "VI_CAP0", "VI_PROC0";
18207 + interrupt-names = "VI_CAP0", "VI_PROC0";
18211 + compatible = "hisilicon,hisi-isp";
18213 + reg-names = "ISP";
18215 + interrupt-names = "ISP";
18219 + compatible = "hisilicon,hisi-vpss";
18221 + reg-names = "vpss0";
18223 + interrupt-names = "vpss0";
18227 + compatible = "hisilicon,hisi-vgs";
18229 + reg-names = "vgs0";
18231 + interrupt-names = "vgs0";
18235 + compatible = "hisilicon,hisi-vo";
18237 + reg-names = "vo";
18239 + interrupt-names = "vo";
18243 + compatible = "hisilicon,hisi-hifb";
18245 + reg-names = "hifb", "sys";
18247 + interrupt-names = "hifb", "hifb_soft";
18251 + compatible = "hisilicon,hisi-tde";
18253 + reg-names = "tde";
18255 + interrupt-names = "tde_osr_isr";
18259 + compatible = "hisilicon,hisi-gdc";
18261 + reg-names = "gdc", "nnie0";
18263 + interrupt-names = "gdc", "nnie0";
18267 + compatible = "hisilicon,hisi-gzip";
18269 + reg-names = "gzip";
18271 + interrupt-names = "gzip";
18275 + compatible = "hisilicon,hisi-jpegd";
18277 + reg-names = "jpegd";
18279 + interrupt-names = "jpegd";
18283 + compatible = "hisilicon,hisi-vedu";
18285 + reg-names = "vedu0", "jpge";
18287 + interrupt-names = "vedu0","jpge";
18291 + compatible = "hisilicon,hisi-scd";
18293 + reg-names = "scd";
18295 + interrupt-names = "scd";
18299 + compatible = "hisilicon,hisi-hdmi";
18301 + reg-names = "hdmi0";
18305 + compatible = "hisilicon,hisi-aiao";
18307 + reg-names = "aiao","acodec","crg";
18309 + interrupt-names = "AIO";
18313 + compatible = "hisilicon,hisi-nnie";
18315 + reg-names = "nnie0","gdc";
18317 + interrupt-names = "nnie0","gdc";
18321 + compatible = "hisilicon,hisi-ive";
18323 + reg-names = "ive";
18325 + interrupt-names = "ive";
18329 + compatible = "hisilicon,hisi-lsadc";
18333 + reset-names = "lsadc-crg";
18343 + compatible = "hisilicon,hi35xx-rtc";
18355 + reg-names = "pmc";
18359 diff --git a/arch/arm/boot/dts/hi3568v100-emmc.dts b/arch/arm/boot/dts/hi3568v100-emmc.dts
18362 --- /dev/null
18363 +++ b/arch/arm/boot/dts/hi3568v100-emmc.dts
18364 @@ -0,0 +1,25 @@
18390 diff --git a/arch/arm/boot/dts/hi3568v100-flash.dts b/arch/arm/boot/dts/hi3568v100-flash.dts
18393 --- /dev/null
18394 +++ b/arch/arm/boot/dts/hi3568v100-flash.dts
18395 @@ -0,0 +1,25 @@
18421 diff --git a/arch/arm/boot/dts/hi3568v100.dts b/arch/arm/boot/dts/hi3568v100.dts
18424 --- /dev/null
18426 @@ -0,0 +1,284 @@
18428 + * Copyright (c) 2013-2014 Linaro Ltd.
18446 +/dts-v1/;
18454 + linux,initrd-start = <0x23000040>;
18455 + linux,initrd-end = <0x24000000>;
18459 + #address-cells = <1>;
18460 + #size-cells = <0>;
18463 + compatible = "arm,cortex-a53";
18466 + cci-control-port = <&cci_control0>;
18531 + pl022,com-mode = <0>;
18532 + spi-max-frequency = <50000000>;
18543 + pl022,com-mode = <0>;
18544 + spi-max-frequency = <50000000>;
18555 + pl022,com-mode = <0>;
18556 + spi-max-frequency = <50000000>;
18567 + pl022,com-mode = <0>;
18568 + spi-max-frequency = <50000000>;
18579 + pl022,com-mode = <0>;
18580 + spi-max-frequency = <50000000>;
18585 + ethphy: ethernet-phy@1 {
18591 + phy-handle = <ðphy>;
18592 + phy-mode = "rgmii";
18597 + compatible = "jedec,spi-nor";
18599 + spi-max-frequency = <160000000>;
18600 + m25p,fast-read;
18606 + compatible = "jedec,spi-nand";
18608 + spi-max-frequency = <160000000>;
18616 + nand-max-frequency = <200000000>;
18711 diff --git a/arch/arm/boot/dts/hi3568v100.dtsi b/arch/arm/boot/dts/hi3568v100.dtsi
18714 --- /dev/null
18716 @@ -0,0 +1,1081 @@
18718 + * Copyright (c) 2013-2014 Linaro Ltd.
18719 + * Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
18737 +#include <dt-bindings/clock/hi3519av100-clock.h>
18777 + gic: interrupt-controller@1F100000 {
18778 + compatible = "arm,gic-400";
18779 + #interrupt-cells = <3>;
18780 + #address-cells = <0>;
18781 + interrupt-controller;
18787 + compatible = "hisilicon,hi3519av100-clock", "syscon";
18788 + #address-cells = <1>;
18789 + #size-cells = <1>;
18790 + #clock-cells = <1>;
18791 + #reset-cells = <2>;
18797 + compatible = "fixed-clock";
18798 + #clock-cells = <0>;
18799 + clock-frequency = <3000000>;
18803 + compatible = "arm,armv8-timer";
18804 + interrupt-parent = <&gic>;
18807 + clock-frequency = <24000000>;
18811 + compatible = "hisilicon,ipcm-interrupt";
18812 + interrupt-parent = <&gic>;
18819 + #address-cells = <1>;
18820 + #size-cells = <1>;
18821 + compatible = "simple-bus";
18822 + interrupt-parent = <&gic>;
18826 + #address-cells = <1>;
18827 + #size-cells = <1>;
18828 + compatible = "arm,amba-bus";
18836 + clock-names = "apb_pclk";
18845 + clock-names = "apb_pclk";
18847 + dma-names = "tx","rx";
18856 + clock-names = "apb_pclk";
18858 + dma-names = "tx","rx";
18867 + clock-names = "apb_pclk";
18869 + dma-names = "tx","rx";
18878 + clock-names = "apb_pclk";
18880 + dma-names = "tx","rx";
18885 + compatible = "hisilicon,hibvt-i2c";
18888 + clock-frequency = <100000>;
18891 + dma-names = "tx","rx";
18895 + compatible = "hisilicon,hibvt-i2c";
18898 + clock-frequency = <100000>;
18901 + dma-names = "tx","rx";
18905 + compatible = "hisilicon,hibvt-i2c";
18908 + clock-frequency = <100000>;
18911 + dma-names = "tx","rx";
18915 + compatible = "hisilicon,hibvt-i2c";
18918 + clock-frequency = <100000>;
18921 + dma-names = "tx","rx";
18925 + compatible = "hisilicon,hibvt-i2c";
18928 + clock-frequency = <100000>;
18931 + dma-names = "tx","rx";
18935 + compatible = "hisilicon,hibvt-i2c";
18938 + clock-frequency = <100000>;
18941 + dma-names = "tx","rx";
18945 + compatible = "hisilicon,hibvt-i2c";
18948 + clock-frequency = <100000>;
18951 + dma-names = "tx","rx";
18955 + compatible = "hisilicon,hibvt-i2c";
18958 + clock-frequency = <100000>;
18961 + dma-names = "tx","rx";
18965 + compatible = "hisilicon,hibvt-i2c";
18968 + clock-frequency = <100000>;
18971 + dma-names = "tx","rx";
18975 + compatible = "hisilicon,hibvt-i2c";
18978 + clock-frequency = <100000>;
18981 + dma-names = "tx","rx";
18986 + arm,primecell-periphid = <0x00800022>;
18990 + clock-names = "apb_pclk";
18991 + #address-cells = <1>;
18992 + #size-cells = <0>;
18994 + num-cs = <1>;
18996 + dma-names = "tx","rx";
19001 + arm,primecell-periphid = <0x00800022>;
19005 + clock-names = "apb_pclk";
19006 + #address-cells = <1>;
19007 + #size-cells = <0>;
19009 + num-cs = <1>;
19011 + dma-names = "tx","rx";
19016 + arm,primecell-periphid = <0x00800022>;
19020 + clock-names = "apb_pclk";
19021 + #address-cells = <1>;
19022 + #size-cells = <0>;
19024 + num-cs = <1>;
19026 + dma-names = "tx","rx";
19031 + arm,primecell-periphid = <0x00800022>;
19035 + clock-names = "apb_pclk";
19036 + #address-cells = <1>;
19037 + #size-cells = <0>;
19039 + num-cs = <1>;
19041 + dma-names = "tx","rx";
19046 + arm,primecell-periphid = <0x00800022>;
19050 + clock-names = "apb_pclk";
19051 + #address-cells = <1>;
19052 + #size-cells = <0>;
19054 + num-cs = <1>;
19056 + dma-names = "tx","rx";
19063 + #gpio-cells = <2>;
19065 + clock-names = "apb_pclk";
19073 + #gpio-cells = <2>;
19075 + clock-names = "apb_pclk";
19083 + #gpio-cells = <2>;
19085 + clock-names = "apb_pclk";
19093 + #gpio-cells = <2>;
19095 + clock-names = "apb_pclk";
19103 + #gpio-cells = <2>;
19105 + clock-names = "apb_pclk";
19113 + #gpio-cells = <2>;
19115 + clock-names = "apb_pclk";
19123 + #gpio-cells = <2>;
19125 + clock-names = "apb_pclk";
19133 + #gpio-cells = <2>;
19135 + clock-names = "apb_pclk";
19143 + #gpio-cells = <2>;
19145 + clock-names = "apb_pclk";
19153 + #gpio-cells = <2>;
19155 + clock-names = "apb_pclk";
19163 + #gpio-cells = <2>;
19165 + clock-names = "apb_pclk";
19173 + #gpio-cells = <2>;
19175 + clock-names = "apb_pclk";
19183 + #gpio-cells = <2>;
19185 + clock-names = "apb_pclk";
19193 + #gpio-cells = <2>;
19195 + clock-names = "apb_pclk";
19203 + #gpio-cells = <2>;
19205 + clock-names = "apb_pclk";
19226 + clock-names = "timer0", "timer1", "timer2";
19231 + hivdmac: hivdma-controller@04c10000 {
19232 + compatible = "hisilicon,hisi-vdmac";
19236 + clock-names = "apb_pclk";
19238 + reset-names = "dma-reset";
19239 + #dma-cells = <2>;
19244 + hidmac: hidma-controller@04040000 {
19245 + compatible = "hisilicon,hisi-dmac";
19249 + clock-names = "apb_pclk";
19251 + reset-names = "dma-reset";
19252 + #dma-cells = <2>;
19256 + hiedmacv310_0: hiedma-controller@04040000 {
19263 + clock-names = "apb_pclk", "axi_aclk";
19264 + #clock-cells = <2>;
19266 + reset-names = "dma-reset";
19267 + dma-requests = <32>;
19268 + dma-channels = <8>;
19270 + #dma-cells = <2>;
19274 + hiedmacv310_1: hiedma-controller@04050000 {
19281 + clock-names = "apb_pclk", "axi_aclk";
19282 + #clock-cells = <2>;
19284 + reset-names = "dma-reset";
19285 + dma-requests = <32>;
19286 + dma-channels = <8>;
19288 + #dma-cells = <2>;
19292 + sysctrl: system-controller@00000000 {
19295 + #clock-cells = <1>;
19299 + compatible = "syscon-reboot";
19306 + misc_ctrl: misc-controller@04528000 {
19307 + compatible = "hisilicon,hisi-miscctrl", "syscon";
19312 + compatible = "hisilicon,hisi-ioconfig", "syscon";
19317 + compatible = "hisilicon,hisi-ioconfig", "syscon";
19322 + compatible = "hisilicon,hisi-ioconfig", "syscon";
19327 + compatible = "hisilicon,hisi-ioconfig", "syscon";
19332 + compatible = "hisilicon,hisi-usb-phy";
19334 + #phy-cells = <0>;
19339 + compatible = "generic-xhci";
19342 + usb2-lpm-disable;
19348 + compatible = "generic-xhci";
19351 + usb2-lpm-disable;
19360 + interrupt-names = "peripheral";
19361 + maximum-speed = "super-speed";
19373 + interrupt-names = "peripheral";
19374 + maximum-speed = "high-speed";
19379 + compatible = "arm,cci-400";
19380 + #address-cells = <1>;
19381 + #size-cells = <1>;
19385 + cci_control0: slave-if@4000 {
19386 + compatible = "arm,cci-400-ctrl-if";
19387 + interface-type = "ace";
19391 + cci_control1: slave-if@5000 {
19392 + compatible = "arm,cci-400-ctrl-if";
19393 + interface-type = "ace";
19400 + compatible = "hisilicon,hisi-gemac-mdio";
19404 + reset-names = "phy_reset";
19405 + #address-cells = <1>;
19406 + #size-cells = <0>;
19416 + clock-names = "higmac_clk",
19421 + reset-names = "port_reset",
19424 + mac-address = [00 00 00 00 00 00];
19427 + fmc: flash-memory-controller@10000000 {
19428 + compatible = "hisilicon,hisi-fmc";
19430 + reg-names = "control", "memory";
19432 + max-dma-size = <0x2000>;
19433 + #address-cells = <1>;
19434 + #size-cells = <0>;
19437 + compatible = "hisilicon,fmc-spi-nor";
19438 + assigned-clocks = <&clock HI3519AV100_FMC_CLK>;
19439 + assigned-clock-rates = <24000000>;
19440 + #address-cells = <1>;
19441 + #size-cells = <0>;
19445 + compatible = "hisilicon,fmc-spi-nand";
19446 + assigned-clocks = <&clock HI3519AV100_FMC_CLK>;
19447 + assigned-clock-rates = <24000000>;
19448 + #address-cells = <1>;
19449 + #size-cells = <0>;
19452 + hinfc:parallel-nand-controller {
19453 + compatible = "hisilicon,fmc-nand";
19454 + assigned-clocks = <&clock HI3519AV100_FMC_CLK>;
19455 + assigned-clock-rates = <200000000>;
19456 + #address-cells = <1>;
19457 + #size-cells = <0>;
19462 + compatible = "hisi-sdhci";
19466 + clock-names = "mmc_clk";
19468 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
19469 + max-frequency = <198000000>;
19471 + non-removable;
19472 + bus-width = <8>;
19473 + cap-mmc-highspeed;
19474 + mmc-hs400-1_8v;
19475 + mmc-hs400-enhanced-strobe;
19476 + cap-mmc-hw-reset;
19482 + compatible = "hisi-sdhci";
19486 + clock-names = "mmc_clk";
19488 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
19489 + max-frequency = <198000000>;
19493 + bus-width = <4>;
19494 + cap-sd-highspeed;
19495 + sd-uhs-sdr104;
19496 + full-pwr-cycle;
19497 + disable-wp;
19503 + compatible = "hisi-sdhci";
19507 + clock-names = "mmc_clk";
19509 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
19510 + max-frequency = <198000000>;
19514 + bus-width = <4>;
19515 + cap-sd-highspeed;
19516 + sd-uhs-sdr104;
19517 + full-pwr-cycle;
19518 + disable-wp;
19525 + compatible = "hisilicon,hisi-pcie";
19526 + #size-cells = <2>;
19527 + #address-cells = <3>;
19528 + #interrupt-cells = <1>;
19529 + bus-range = <0x0 0xff>;
19531 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
19532 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 102 0x4
19550 + compatible = "hisilicon,hisi-cipher";
19552 + reg-names = "cipher", "rsa";
19554 + interrupt-names = "cipher", "nonsec_cipher", "hash", "nonsec_hash", "rsa", "nonsec_rsa";
19564 + compatible = "hisilicon,hi35xx-rtc";
19578 + #address-cells = <1>;
19579 + #size-cells = <1>;
19580 + compatible = "simple-bus";
19581 + interrupt-parent = <&gic>;
19589 + compatible = "hisilicon,hisi-sys";
19592 + reg-names = "crg", "sys", "ddr", "misc";
19596 + compatible = "hisilicon,hisi-mipi";
19598 + reg-names = "mipi_rx", "slvs";
19600 + interrupt-names = "mipi_rx", "slvs";
19604 + compatible = "hisilicon,hisi-mipi_tx";
19606 + reg-names = "mipi_tx";
19608 + interrupt-names = "mipi_tx";
19612 + compatible = "hisilicon,hisi-vi";
19614 + reg-names = "VI_CAP0", "VI_PROC0";
19616 + interrupt-names = "VI_CAP0", "VI_PROC0";
19620 + compatible = "hisilicon,hisi-isp";
19622 + reg-names = "ISP";
19624 + interrupt-names = "ISP";
19628 + compatible = "hisilicon,hisi-vpss";
19630 + reg-names = "vpss0";
19632 + interrupt-names = "vpss0";
19636 + compatible = "hisilicon,hisi-vgs";
19638 + reg-names = "vgs0";
19640 + interrupt-names = "vgs0";
19644 + compatible = "hisilicon,hisi-vo";
19646 + reg-names = "vo";
19648 + interrupt-names = "vo";
19652 + compatible = "hisilicon,hisi-hifb";
19654 + reg-names = "hifb";
19656 + interrupt-names = "hifb";
19660 + compatible = "hisilicon,hisi-tde";
19662 + reg-names = "tde";
19664 + interrupt-names = "tde_osr_isr";
19668 + compatible = "hisilicon,hisi-avs";
19670 + reg-names = "avs";
19672 + interrupt-names = "avs";
19676 + compatible = "hisilicon,hisi-dis";
19678 + reg-names = "dis";
19680 + interrupt-names = "dis";
19684 + compatible = "hisilicon,hisi-gyro-dis";
19688 + compatible = "hisilicon,hisi-gdc";
19690 + reg-names = "gdc";
19692 + interrupt-names = "gdc";
19696 + compatible = "hisilicon,hisi-gzip";
19698 + reg-names = "gzip";
19700 + interrupt-names = "gzip";
19704 + compatible = "hisilicon,hisi-jpegd";
19706 + reg-names = "jpegd";
19708 + interrupt-names = "jpegd";
19712 + compatible = "hisilicon,hisi-vedu";
19714 + reg-names = "vedu0", "jpge";
19716 + interrupt-names = "vedu0","jpge";
19720 + compatible = "hisilicon,hisi-venc";
19724 + compatible = "hisilicon,hisi-vdh";
19726 + reg-names = "vdh_scd";
19728 + interrupt-names = "scd","vdh";
19732 + compatible = "hisilicon,hisi-hdmi";
19734 + reg-names = "hdmi0";
19738 + compatible = "hisilicon,hisi-aiao";
19740 + reg-names = "aiao","acodec","crg";
19742 + interrupt-names = "AIO","VOIE";
19746 + compatible = "hisilicon,hisi-nnie";
19748 + reg-names = "nnie0";
19750 + interrupt-names = "nnie0";
19754 + compatible = "hisilicon,hisi-dpu_rect";
19756 + reg-names = "dpu_rect";
19758 + interrupt-names = "rect";
19762 + compatible = "hisilicon,hisi-dpu_match";
19764 + reg-names = "dpu_match";
19766 + interrupt-names = "match";
19770 + compatible = "hisilicon,hisi-dsp";
19772 + reg-names = "dsp0";
19776 + compatible = "hisilicon,hisi-ive";
19778 + reg-names = "ive";
19780 + interrupt-names = "ive";
19784 + compatible = "hisilicon,hi3519av100-lsadc";
19788 + reset-names = "lsadc-crg";
19798 diff --git a/arch/arm/configs/hi3516a_full_defconfig b/arch/arm/configs/hi3516a_full_defconfig
19801 --- /dev/null
19803 @@ -0,0 +1,2737 @@
20034 +# GCOV-based kernel profiling
20657 +# Self-contained MTD device drivers
20668 +# Disk-On-Chip Device Drivers
20844 +# SCSI support type (disk, tape, CD-ROM)
21149 +# Non-8250 serial port support
21195 +# I2C system bus drivers (mostly embedded / system-on-chip)
21841 +# Microsoft Hyper-V guest support
22017 +# CD-ROM/DVD Filesystems
22029 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
22125 +CONFIG_NLS_DEFAULT="iso8859-1"
22189 +# Compile-time checks and compiler options
22322 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
22541 diff --git a/arch/arm/configs/hi3516a_mini_defconfig b/arch/arm/configs/hi3516a_mini_defconfig
22544 --- /dev/null
22546 @@ -0,0 +1,2335 @@
22777 +# GCOV-based kernel profiling
23379 +# Self-contained MTD device drivers
23390 +# Disk-On-Chip Device Drivers
23672 +# Host-side USB support is needed for USB Network Adapter support
23805 +# Non-8250 serial port support
23850 +# I2C system bus drivers (mostly embedded / system-on-chip)
24187 +# Microsoft Hyper-V guest support
24363 +# CD-ROM/DVD Filesystems
24375 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
24466 +CONFIG_NLS_DEFAULT="iso8859-1"
24530 +# Compile-time checks and compiler options
24663 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
24882 diff --git a/arch/arm/configs/hi3516a_spinand_defconfig b/arch/arm/configs/hi3516a_spinand_defconfig
24885 --- /dev/null
24887 @@ -0,0 +1,2733 @@
25118 +# GCOV-based kernel profiling
25741 +# Self-contained MTD device drivers
25752 +# Disk-On-Chip Device Drivers
25924 +# SCSI support type (disk, tape, CD-ROM)
26229 +# Non-8250 serial port support
26275 +# I2C system bus drivers (mostly embedded / system-on-chip)
26921 +# Microsoft Hyper-V guest support
27097 +# CD-ROM/DVD Filesystems
27109 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
27205 +CONFIG_NLS_DEFAULT="iso8859-1"
27269 +# Compile-time checks and compiler options
27402 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
27621 diff --git a/arch/arm/configs/hi3516a_spinand_mini_defconfig b/arch/arm/configs/hi3516a_spinand_min…
27624 --- /dev/null
27626 @@ -0,0 +1,2331 @@
27857 +# GCOV-based kernel profiling
28459 +# Self-contained MTD device drivers
28470 +# Disk-On-Chip Device Drivers
28748 +# Host-side USB support is needed for USB Network Adapter support
28881 +# Non-8250 serial port support
28926 +# I2C system bus drivers (mostly embedded / system-on-chip)
29263 +# Microsoft Hyper-V guest support
29439 +# CD-ROM/DVD Filesystems
29451 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
29542 +CONFIG_NLS_DEFAULT="iso8859-1"
29606 +# Compile-time checks and compiler options
29739 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
29958 diff --git a/arch/arm/configs/hi3516av300_emmc_smp_defconfig b/arch/arm/configs/hi3516av300_emmc_sm…
29961 --- /dev/null
29963 @@ -0,0 +1,3070 @@
29970 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
30458 +# General architecture-dependent options
30509 +# GCOV-based kernel profiling
30938 +# SCSI support type (disk, tape, CD-ROM)
31280 +# Non-8250 serial port support
31347 +# I2C system bus drivers (mostly embedded / system-on-chip)
31864 +# HD-Audio
32290 +# on-CPU RTC drivers
32315 +# Microsoft Hyper-V guest support
32515 +# CD-ROM/DVD Filesystems
32527 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
32593 +CONFIG_NLS_DEFAULT="iso8859-1"
32882 +# Compile-time checks and compiler options
33030 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
33034 diff --git a/arch/arm/configs/hi3516av300_smp_defconfig b/arch/arm/configs/hi3516av300_smp_defconfig
33037 --- /dev/null
33039 @@ -0,0 +1,3189 @@
33046 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
33534 +# General architecture-dependent options
33585 +# GCOV-based kernel profiling
33940 +# Self-contained MTD device drivers
33952 +# Disk-On-Chip Device Drivers
34112 +# SCSI support type (disk, tape, CD-ROM)
34454 +# Non-8250 serial port support
34521 +# I2C system bus drivers (mostly embedded / system-on-chip)
35038 +# HD-Audio
35464 +# on-CPU RTC drivers
35489 +# Microsoft Hyper-V guest support
35689 +# CD-ROM/DVD Filesystems
35701 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
35785 +CONFIG_NLS_DEFAULT="iso8859-1"
36077 +# Compile-time checks and compiler options
36225 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
36229 diff --git a/arch/arm/configs/hi3516cv200_full_defconfig b/arch/arm/configs/hi3516cv200_full_defcon…
36232 --- /dev/null
36234 @@ -0,0 +1,2641 @@
36465 +# GCOV-based kernel profiling
37017 +# Self-contained MTD device drivers
37028 +# Disk-On-Chip Device Drivers
37191 +# SCSI support type (disk, tape, CD-ROM)
37480 +# Non-8250 serial port support
37527 +# I2C system bus drivers (mostly embedded / system-on-chip)
38194 +# Microsoft Hyper-V guest support
38365 +# CD-ROM/DVD Filesystems
38377 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
38468 +CONFIG_NLS_DEFAULT="iso8859-1"
38532 +# Compile-time checks and compiler options
38665 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
38876 diff --git a/arch/arm/configs/hi3516cv500_emmc_smp_defconfig b/arch/arm/configs/hi3516cv500_emmc_sm…
38879 --- /dev/null
38881 @@ -0,0 +1,3070 @@
38888 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
39376 +# General architecture-dependent options
39427 +# GCOV-based kernel profiling
39856 +# SCSI support type (disk, tape, CD-ROM)
40198 +# Non-8250 serial port support
40265 +# I2C system bus drivers (mostly embedded / system-on-chip)
40782 +# HD-Audio
41208 +# on-CPU RTC drivers
41233 +# Microsoft Hyper-V guest support
41433 +# CD-ROM/DVD Filesystems
41445 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
41511 +CONFIG_NLS_DEFAULT="iso8859-1"
41800 +# Compile-time checks and compiler options
41948 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
41952 diff --git a/arch/arm/configs/hi3516cv500_smp_defconfig b/arch/arm/configs/hi3516cv500_smp_defconfig
41955 --- /dev/null
41957 @@ -0,0 +1,3189 @@
41964 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
42452 +# General architecture-dependent options
42503 +# GCOV-based kernel profiling
42858 +# Self-contained MTD device drivers
42870 +# Disk-On-Chip Device Drivers
43030 +# SCSI support type (disk, tape, CD-ROM)
43372 +# Non-8250 serial port support
43439 +# I2C system bus drivers (mostly embedded / system-on-chip)
43956 +# HD-Audio
44382 +# on-CPU RTC drivers
44407 +# Microsoft Hyper-V guest support
44607 +# CD-ROM/DVD Filesystems
44619 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
44703 +CONFIG_NLS_DEFAULT="iso8859-1"
44995 +# Compile-time checks and compiler options
45143 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
45147 diff --git a/arch/arm/configs/hi3516dv200_emmc_defconfig b/arch/arm/configs/hi3516dv200_emmc_defcon…
45150 --- /dev/null
45152 @@ -0,0 +1,3006 @@
45159 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
45609 +# General architecture-dependent options
45661 +# GCOV-based kernel profiling
45961 +# Self-contained MTD device drivers
45973 +# Disk-On-Chip Device Drivers
46135 +# SCSI support type (disk, tape, CD-ROM)
46440 +# Non-8250 serial port support
46499 +# I2C system bus drivers (mostly embedded / system-on-chip)
47021 +# HD-Audio
47449 +# on-CPU RTC drivers
47473 +# Microsoft Hyper-V guest support
47660 +# CD-ROM/DVD Filesystems
47674 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
47757 +CONFIG_NLS_DEFAULT="iso8859-1"
48039 +# Compile-time checks and compiler options
48155 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
48159 diff --git a/arch/arm/configs/hi3516dv200_full_defconfig b/arch/arm/configs/hi3516dv200_full_defcon…
48162 --- /dev/null
48164 @@ -0,0 +1,3006 @@
48171 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
48621 +# General architecture-dependent options
48673 +# GCOV-based kernel profiling
48973 +# Self-contained MTD device drivers
48985 +# Disk-On-Chip Device Drivers
49147 +# SCSI support type (disk, tape, CD-ROM)
49452 +# Non-8250 serial port support
49511 +# I2C system bus drivers (mostly embedded / system-on-chip)
50033 +# HD-Audio
50461 +# on-CPU RTC drivers
50485 +# Microsoft Hyper-V guest support
50672 +# CD-ROM/DVD Filesystems
50686 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
50769 +CONFIG_NLS_DEFAULT="iso8859-1"
51051 +# Compile-time checks and compiler options
51167 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
51171 diff --git a/arch/arm/configs/hi3516dv300_emmc_smp_defconfig b/arch/arm/configs/hi3516dv300_emmc_sm…
51174 --- /dev/null
51176 @@ -0,0 +1,3070 @@
51183 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
51671 +# General architecture-dependent options
51722 +# GCOV-based kernel profiling
52151 +# SCSI support type (disk, tape, CD-ROM)
52493 +# Non-8250 serial port support
52560 +# I2C system bus drivers (mostly embedded / system-on-chip)
53077 +# HD-Audio
53503 +# on-CPU RTC drivers
53528 +# Microsoft Hyper-V guest support
53728 +# CD-ROM/DVD Filesystems
53740 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
53806 +CONFIG_NLS_DEFAULT="iso8859-1"
54095 +# Compile-time checks and compiler options
54243 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
54247 diff --git a/arch/arm/configs/hi3516dv300_emmc_smp_hos_l2_defconfig b/arch/arm/configs/hi3516dv300_…
54250 --- /dev/null
54252 @@ -0,0 +1,3135 @@
54259 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
54775 +# General architecture-dependent options
54826 +# GCOV-based kernel profiling
55257 +# SCSI support type (disk, tape, CD-ROM)
55600 +# Non-8250 serial port support
55667 +# I2C system bus drivers (mostly embedded / system-on-chip)
56252 +# HD-Audio
56470 +# USB Type-C Multiplexer/DeMultiplexer Switch support
56475 +# USB Type-C Alternate Mode drivers
56608 +# on-CPU RTC drivers
56633 +# Microsoft Hyper-V guest support
56869 +# CD-ROM/DVD Filesystems
56881 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
56947 +CONFIG_NLS_DEFAULT="iso8859-1"
57027 +#CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init"
57258 +# Compile-time checks and compiler options
57388 diff --git a/arch/arm/configs/hi3516dv300_smp_defconfig b/arch/arm/configs/hi3516dv300_smp_defconfig
57391 --- /dev/null
57393 @@ -0,0 +1,3189 @@
57400 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
57888 +# General architecture-dependent options
57939 +# GCOV-based kernel profiling
58294 +# Self-contained MTD device drivers
58306 +# Disk-On-Chip Device Drivers
58466 +# SCSI support type (disk, tape, CD-ROM)
58808 +# Non-8250 serial port support
58875 +# I2C system bus drivers (mostly embedded / system-on-chip)
59392 +# HD-Audio
59818 +# on-CPU RTC drivers
59843 +# Microsoft Hyper-V guest support
60043 +# CD-ROM/DVD Filesystems
60055 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
60139 +CONFIG_NLS_DEFAULT="iso8859-1"
60431 +# Compile-time checks and compiler options
60579 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
60583 diff --git a/arch/arm/configs/hi3516ev200_emmc_defconfig b/arch/arm/configs/hi3516ev200_emmc_defcon…
60586 --- /dev/null
60588 @@ -0,0 +1,3006 @@
60595 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
61045 +# General architecture-dependent options
61097 +# GCOV-based kernel profiling
61397 +# Self-contained MTD device drivers
61409 +# Disk-On-Chip Device Drivers
61571 +# SCSI support type (disk, tape, CD-ROM)
61876 +# Non-8250 serial port support
61935 +# I2C system bus drivers (mostly embedded / system-on-chip)
62457 +# HD-Audio
62885 +# on-CPU RTC drivers
62909 +# Microsoft Hyper-V guest support
63096 +# CD-ROM/DVD Filesystems
63110 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
63193 +CONFIG_NLS_DEFAULT="iso8859-1"
63475 +# Compile-time checks and compiler options
63591 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
63595 diff --git a/arch/arm/configs/hi3516ev200_full_defconfig b/arch/arm/configs/hi3516ev200_full_defcon…
63598 --- /dev/null
63600 @@ -0,0 +1,3006 @@
63607 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
64057 +# General architecture-dependent options
64109 +# GCOV-based kernel profiling
64409 +# Self-contained MTD device drivers
64421 +# Disk-On-Chip Device Drivers
64583 +# SCSI support type (disk, tape, CD-ROM)
64888 +# Non-8250 serial port support
64947 +# I2C system bus drivers (mostly embedded / system-on-chip)
65469 +# HD-Audio
65897 +# on-CPU RTC drivers
65921 +# Microsoft Hyper-V guest support
66108 +# CD-ROM/DVD Filesystems
66122 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
66205 +CONFIG_NLS_DEFAULT="iso8859-1"
66487 +# Compile-time checks and compiler options
66603 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
66607 diff --git a/arch/arm/configs/hi3516ev200_mini_defconfig b/arch/arm/configs/hi3516ev200_mini_defcon…
66610 --- /dev/null
66612 @@ -0,0 +1,2067 @@
66619 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
67068 +# General architecture-dependent options
67120 +# GCOV-based kernel profiling
67400 +# Self-contained MTD device drivers
67412 +# Disk-On-Chip Device Drivers
67662 +# Host-side USB support is needed for USB Network Adapter support
67733 +# Non-8250 serial port support
67788 +# I2C system bus drivers (mostly embedded / system-on-chip)
68078 +# Microsoft Hyper-V guest support
68244 +# CD-ROM/DVD Filesystems
68308 +CONFIG_NLS_DEFAULT="iso8859-1"
68560 +# Compile-time checks and compiler options
68676 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
68680 diff --git a/arch/arm/configs/hi3516ev300_emmc_defconfig b/arch/arm/configs/hi3516ev300_emmc_defcon…
68683 --- /dev/null
68685 @@ -0,0 +1,3006 @@
68692 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
69142 +# General architecture-dependent options
69194 +# GCOV-based kernel profiling
69494 +# Self-contained MTD device drivers
69506 +# Disk-On-Chip Device Drivers
69668 +# SCSI support type (disk, tape, CD-ROM)
69973 +# Non-8250 serial port support
70032 +# I2C system bus drivers (mostly embedded / system-on-chip)
70554 +# HD-Audio
70982 +# on-CPU RTC drivers
71006 +# Microsoft Hyper-V guest support
71193 +# CD-ROM/DVD Filesystems
71207 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
71290 +CONFIG_NLS_DEFAULT="iso8859-1"
71572 +# Compile-time checks and compiler options
71688 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
71692 diff --git a/arch/arm/configs/hi3516ev300_full_defconfig b/arch/arm/configs/hi3516ev300_full_defcon…
71695 --- /dev/null
71697 @@ -0,0 +1,3006 @@
71704 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
72154 +# General architecture-dependent options
72206 +# GCOV-based kernel profiling
72506 +# Self-contained MTD device drivers
72518 +# Disk-On-Chip Device Drivers
72680 +# SCSI support type (disk, tape, CD-ROM)
72985 +# Non-8250 serial port support
73044 +# I2C system bus drivers (mostly embedded / system-on-chip)
73566 +# HD-Audio
73994 +# on-CPU RTC drivers
74018 +# Microsoft Hyper-V guest support
74205 +# CD-ROM/DVD Filesystems
74219 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
74302 +CONFIG_NLS_DEFAULT="iso8859-1"
74584 +# Compile-time checks and compiler options
74700 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
74704 diff --git a/arch/arm/configs/hi3518ev200_full_defconfig b/arch/arm/configs/hi3518ev200_full_defcon…
74707 --- /dev/null
74709 @@ -0,0 +1,2641 @@
74940 +# GCOV-based kernel profiling
75492 +# Self-contained MTD device drivers
75503 +# Disk-On-Chip Device Drivers
75666 +# SCSI support type (disk, tape, CD-ROM)
75955 +# Non-8250 serial port support
76002 +# I2C system bus drivers (mostly embedded / system-on-chip)
76669 +# Microsoft Hyper-V guest support
76840 +# CD-ROM/DVD Filesystems
76852 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
76943 +CONFIG_NLS_DEFAULT="iso8859-1"
77007 +# Compile-time checks and compiler options
77140 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
77351 diff --git a/arch/arm/configs/hi3518ev201_full_defconfig b/arch/arm/configs/hi3518ev201_full_defcon…
77354 --- /dev/null
77356 @@ -0,0 +1,2318 @@
77587 +# GCOV-based kernel profiling
78139 +# Self-contained MTD device drivers
78150 +# Disk-On-Chip Device Drivers
78289 +# SCSI support type (disk, tape, CD-ROM)
78425 +# Host-side USB support is needed for USB Network Adapter support
78569 +# Non-8250 serial port support
78616 +# I2C system bus drivers (mostly embedded / system-on-chip)
79002 +# Microsoft Hyper-V guest support
79174 +# CD-ROM/DVD Filesystems
79186 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
79272 +CONFIG_NLS_DEFAULT="iso8859-1"
79336 +# Compile-time checks and compiler options
79469 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
79675 diff --git a/arch/arm/configs/hi3518ev300_emmc_defconfig b/arch/arm/configs/hi3518ev300_emmc_defcon…
79678 --- /dev/null
79680 @@ -0,0 +1,3006 @@
79687 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
80137 +# General architecture-dependent options
80189 +# GCOV-based kernel profiling
80489 +# Self-contained MTD device drivers
80501 +# Disk-On-Chip Device Drivers
80663 +# SCSI support type (disk, tape, CD-ROM)
80968 +# Non-8250 serial port support
81027 +# I2C system bus drivers (mostly embedded / system-on-chip)
81549 +# HD-Audio
81977 +# on-CPU RTC drivers
82001 +# Microsoft Hyper-V guest support
82188 +# CD-ROM/DVD Filesystems
82202 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
82285 +CONFIG_NLS_DEFAULT="iso8859-1"
82567 +# Compile-time checks and compiler options
82683 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
82687 diff --git a/arch/arm/configs/hi3518ev300_full_defconfig b/arch/arm/configs/hi3518ev300_full_defcon…
82690 --- /dev/null
82692 @@ -0,0 +1,3006 @@
82699 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
83149 +# General architecture-dependent options
83201 +# GCOV-based kernel profiling
83501 +# Self-contained MTD device drivers
83513 +# Disk-On-Chip Device Drivers
83675 +# SCSI support type (disk, tape, CD-ROM)
83980 +# Non-8250 serial port support
84039 +# I2C system bus drivers (mostly embedded / system-on-chip)
84561 +# HD-Audio
84989 +# on-CPU RTC drivers
85013 +# Microsoft Hyper-V guest support
85200 +# CD-ROM/DVD Filesystems
85214 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
85297 +CONFIG_NLS_DEFAULT="iso8859-1"
85579 +# Compile-time checks and compiler options
85695 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
85699 diff --git a/arch/arm/configs/hi3518ev300_mini_defconfig b/arch/arm/configs/hi3518ev300_mini_defcon…
85702 --- /dev/null
85704 @@ -0,0 +1,1776 @@
85711 +# Compiler: arm-himix310-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
86159 +# General architecture-dependent options
86211 +# GCOV-based kernel profiling
86454 +# Self-contained MTD device drivers
86466 +# Disk-On-Chip Device Drivers
86667 +# Non-8250 serial port support
86722 +# I2C system bus drivers (mostly embedded / system-on-chip)
87011 +# Microsoft Hyper-V guest support
87177 +# CD-ROM/DVD Filesystems
87235 +CONFIG_NLS_DEFAULT="iso8859-1"
87361 +# Compile-time checks and compiler options
87477 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
87481 diff --git a/arch/arm/configs/hi3519av100_amp_defconfig b/arch/arm/configs/hi3519av100_amp_defconfig
87484 --- /dev/null
87486 @@ -0,0 +1,3048 @@
87493 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
87962 +# General architecture-dependent options
88013 +# GCOV-based kernel profiling
88343 +# Self-contained MTD device drivers
88355 +# Disk-On-Chip Device Drivers
88515 +# SCSI support type (disk, tape, CD-ROM)
88860 +# Non-8250 serial port support
88925 +# I2C system bus drivers (mostly embedded / system-on-chip)
89435 +# HD-Audio
89783 +# on-CPU RTC drivers
89807 +# Microsoft Hyper-V guest support
89993 +# CD-ROM/DVD Filesystems
90005 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
90093 +CONFIG_NLS_DEFAULT="iso8859-1"
90388 +# Compile-time checks and compiler options
90531 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
90535 diff --git a/arch/arm/configs/hi3519av100_amp_emmc_defconfig b/arch/arm/configs/hi3519av100_amp_emm…
90538 --- /dev/null
90540 @@ -0,0 +1,3015 @@
90547 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
91016 +# General architecture-dependent options
91067 +# GCOV-based kernel profiling
91399 +# Self-contained MTD device drivers
91410 +# Disk-On-Chip Device Drivers
91549 +# SCSI support type (disk, tape, CD-ROM)
91894 +# Non-8250 serial port support
91959 +# I2C system bus drivers (mostly embedded / system-on-chip)
92468 +# HD-Audio
92816 +# on-CPU RTC drivers
92840 +# Microsoft Hyper-V guest support
93035 +# CD-ROM/DVD Filesystems
93047 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
93114 +CONFIG_NLS_DEFAULT="iso8859-1"
93409 +# Compile-time checks and compiler options
93552 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
93556 diff --git a/arch/arm/configs/hi3519av100_amp_nand_defconfig b/arch/arm/configs/hi3519av100_amp_nan…
93559 --- /dev/null
93561 @@ -0,0 +1,3038 @@
93568 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
94037 +# General architecture-dependent options
94088 +# GCOV-based kernel profiling
94418 +# Self-contained MTD device drivers
94429 +# Disk-On-Chip Device Drivers
94586 +# SCSI support type (disk, tape, CD-ROM)
94931 +# Non-8250 serial port support
94996 +# I2C system bus drivers (mostly embedded / system-on-chip)
95506 +# HD-Audio
95854 +# on-CPU RTC drivers
95878 +# Microsoft Hyper-V guest support
96064 +# CD-ROM/DVD Filesystems
96076 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
96158 +CONFIG_NLS_DEFAULT="iso8859-1"
96453 +# Compile-time checks and compiler options
96596 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
96600 diff --git a/arch/arm/configs/hi3519av100_smp_defconfig b/arch/arm/configs/hi3519av100_smp_defconfig
96603 --- /dev/null
96605 @@ -0,0 +1,3500 @@
96612 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
97145 +# General architecture-dependent options
97196 +# GCOV-based kernel profiling
97555 +# Self-contained MTD device drivers
97568 +# Disk-On-Chip Device Drivers
97746 +# SCSI support type (disk, tape, CD-ROM)
98186 +# Non-8250 serial port support
98273 +# I2C system bus drivers (mostly embedded / system-on-chip)
98880 +# HD-Audio
99328 +# on-CPU RTC drivers
99354 +# Microsoft Hyper-V guest support
99565 +# CD-ROM/DVD Filesystems
99577 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
99661 +CONFIG_NLS_DEFAULT="iso8859-1"
99954 +# Compile-time checks and compiler options
100102 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
100106 diff --git a/arch/arm/configs/hi3519av100_smp_emmc_defconfig b/arch/arm/configs/hi3519av100_smp_emm…
100109 --- /dev/null
100111 @@ -0,0 +1,3465 @@
100118 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
100651 +# General architecture-dependent options
100702 +# GCOV-based kernel profiling
101061 +# Self-contained MTD device drivers
101073 +# Disk-On-Chip Device Drivers
101227 +# SCSI support type (disk, tape, CD-ROM)
101667 +# Non-8250 serial port support
101754 +# I2C system bus drivers (mostly embedded / system-on-chip)
102360 +# HD-Audio
102808 +# on-CPU RTC drivers
102834 +# Microsoft Hyper-V guest support
103045 +# CD-ROM/DVD Filesystems
103057 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
103134 +CONFIG_NLS_DEFAULT="iso8859-1"
103425 +# Compile-time checks and compiler options
103573 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
103577 diff --git a/arch/arm/configs/hi3519av100_smp_nand_defconfig b/arch/arm/configs/hi3519av100_smp_nan…
103580 --- /dev/null
103582 @@ -0,0 +1,3493 @@
103589 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
104121 +# General architecture-dependent options
104172 +# GCOV-based kernel profiling
104530 +# Self-contained MTD device drivers
104542 +# Disk-On-Chip Device Drivers
104717 +# SCSI support type (disk, tape, CD-ROM)
105157 +# Non-8250 serial port support
105244 +# I2C system bus drivers (mostly embedded / system-on-chip)
105851 +# HD-Audio
106299 +# on-CPU RTC drivers
106325 +# Microsoft Hyper-V guest support
106536 +# CD-ROM/DVD Filesystems
106548 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
106632 +CONFIG_NLS_DEFAULT="iso8859-1"
106925 +# Compile-time checks and compiler options
107072 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
107076 diff --git a/arch/arm/configs/hi3520dv300_full_defconfig b/arch/arm/configs/hi3520dv300_full_defcon…
107079 --- /dev/null
107081 @@ -0,0 +1,2628 @@
107313 +# GCOV-based kernel profiling
107956 +# Self-contained MTD device drivers
107967 +# Disk-On-Chip Device Drivers
108127 +# SCSI support type (disk, tape, CD-ROM)
108167 +# Controllers with non-SFF native interface
108436 +# Non-8250 serial port support
108482 +# I2C system bus drivers (mostly embedded / system-on-chip)
109002 +# Microsoft Hyper-V guest support
109180 +# CD-ROM/DVD Filesystems
109195 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
109299 +CONFIG_NLS_DEFAULT="iso8859-1"
109363 +# Compile-time checks and compiler options
109497 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
109710 diff --git a/arch/arm/configs/hi3520dv500_defconfig b/arch/arm/configs/hi3520dv500_defconfig
109713 --- /dev/null
109715 @@ -0,0 +1,3201 @@
109722 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
110194 +# General architecture-dependent options
110246 +# GCOV-based kernel profiling
110629 +# Self-contained MTD device drivers
110641 +# Disk-On-Chip Device Drivers
110803 +# SCSI support type (disk, tape, CD-ROM)
110843 +# Controllers with non-SFF native interface
111187 +# Non-8250 serial port support
111246 +# I2C system bus drivers (mostly embedded / system-on-chip)
111767 +# HD-Audio
112137 +# on-CPU RTC drivers
112187 +# Microsoft Hyper-V guest support
112371 +# CD-ROM/DVD Filesystems
112385 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
112468 +CONFIG_NLS_DEFAULT="iso8859-1"
112765 +# Compile-time checks and compiler options
112913 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
112917 diff --git a/arch/arm/configs/hi3520dv500_emmc_defconfig b/arch/arm/configs/hi3520dv500_emmc_defcon…
112920 --- /dev/null
112922 @@ -0,0 +1,3085 @@
112929 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
113401 +# General architecture-dependent options
113453 +# GCOV-based kernel profiling
113912 +# SCSI support type (disk, tape, CD-ROM)
113952 +# Controllers with non-SFF native interface
114296 +# Non-8250 serial port support
114355 +# I2C system bus drivers (mostly embedded / system-on-chip)
114876 +# HD-Audio
115246 +# on-CPU RTC drivers
115296 +# Microsoft Hyper-V guest support
115480 +# CD-ROM/DVD Filesystems
115494 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
115559 +CONFIG_NLS_DEFAULT="iso8859-1"
115856 +# Compile-time checks and compiler options
116004 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
116008 diff --git a/arch/arm/configs/hi3521a_full_defconfig b/arch/arm/configs/hi3521a_full_defconfig
116011 --- /dev/null
116013 @@ -0,0 +1,2628 @@
116245 +# GCOV-based kernel profiling
116888 +# Self-contained MTD device drivers
116899 +# Disk-On-Chip Device Drivers
117059 +# SCSI support type (disk, tape, CD-ROM)
117099 +# Controllers with non-SFF native interface
117368 +# Non-8250 serial port support
117414 +# I2C system bus drivers (mostly embedded / system-on-chip)
117934 +# Microsoft Hyper-V guest support
118112 +# CD-ROM/DVD Filesystems
118127 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
118231 +CONFIG_NLS_DEFAULT="iso8859-1"
118295 +# Compile-time checks and compiler options
118429 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
118642 diff --git a/arch/arm/configs/hi3521dv200_defconfig b/arch/arm/configs/hi3521dv200_defconfig
118645 --- /dev/null
118647 @@ -0,0 +1,3201 @@
118654 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
119126 +# General architecture-dependent options
119178 +# GCOV-based kernel profiling
119561 +# Self-contained MTD device drivers
119573 +# Disk-On-Chip Device Drivers
119735 +# SCSI support type (disk, tape, CD-ROM)
119775 +# Controllers with non-SFF native interface
120119 +# Non-8250 serial port support
120178 +# I2C system bus drivers (mostly embedded / system-on-chip)
120699 +# HD-Audio
121069 +# on-CPU RTC drivers
121119 +# Microsoft Hyper-V guest support
121303 +# CD-ROM/DVD Filesystems
121317 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
121400 +CONFIG_NLS_DEFAULT="iso8859-1"
121697 +# Compile-time checks and compiler options
121845 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
121849 diff --git a/arch/arm/configs/hi3521dv200_emmc_defconfig b/arch/arm/configs/hi3521dv200_emmc_defcon…
121852 --- /dev/null
121854 @@ -0,0 +1,3085 @@
121861 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
122333 +# General architecture-dependent options
122385 +# GCOV-based kernel profiling
122844 +# SCSI support type (disk, tape, CD-ROM)
122884 +# Controllers with non-SFF native interface
123228 +# Non-8250 serial port support
123287 +# I2C system bus drivers (mostly embedded / system-on-chip)
123808 +# HD-Audio
124178 +# on-CPU RTC drivers
124228 +# Microsoft Hyper-V guest support
124412 +# CD-ROM/DVD Filesystems
124426 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
124491 +CONFIG_NLS_DEFAULT="iso8859-1"
124788 +# Compile-time checks and compiler options
124936 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
124940 diff --git a/arch/arm/configs/hi3531a_full_defconfig b/arch/arm/configs/hi3531a_full_defconfig
124943 --- /dev/null
124945 @@ -0,0 +1,2873 @@
125184 +# GCOV-based kernel profiling
125843 +# Self-contained MTD device drivers
125855 +# Disk-On-Chip Device Drivers
126037 +# SCSI support type (disk, tape, CD-ROM)
126119 +# Controllers with non-SFF native interface
126438 +# Non-8250 serial port support
126506 +# I2C system bus drivers (mostly embedded / system-on-chip)
127070 +# Microsoft Hyper-V guest support
127274 +# CD-ROM/DVD Filesystems
127289 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
127374 +CONFIG_NLS_DEFAULT="iso8859-1"
127439 +# Compile-time checks and compiler options
127597 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
127819 diff --git a/arch/arm/configs/hi3531a_full_slave_defconfig b/arch/arm/configs/hi3531a_full_slave_de…
127822 --- /dev/null
127824 @@ -0,0 +1,2920 @@
128063 +# GCOV-based kernel profiling
128717 +# Self-contained MTD device drivers
128729 +# Disk-On-Chip Device Drivers
128911 +# SCSI support type (disk, tape, CD-ROM)
128993 +# Controllers with non-SFF native interface
129364 +# Non-8250 serial port support
129432 +# I2C system bus drivers (mostly embedded / system-on-chip)
129996 +# Microsoft Hyper-V guest support
130200 +# CD-ROM/DVD Filesystems
130215 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
130300 +CONFIG_NLS_DEFAULT="iso8859-1"
130365 +# Compile-time checks and compiler options
130523 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
130745 diff --git a/arch/arm/configs/hi3531a_spinand_defconfig b/arch/arm/configs/hi3531a_spinand_defconfig
130748 --- /dev/null
130750 @@ -0,0 +1,2868 @@
130989 +# GCOV-based kernel profiling
131648 +# Self-contained MTD device drivers
131660 +# Disk-On-Chip Device Drivers
131837 +# SCSI support type (disk, tape, CD-ROM)
131919 +# Controllers with non-SFF native interface
132238 +# Non-8250 serial port support
132306 +# I2C system bus drivers (mostly embedded / system-on-chip)
132870 +# Microsoft Hyper-V guest support
133074 +# CD-ROM/DVD Filesystems
133089 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
133174 +CONFIG_NLS_DEFAULT="iso8859-1"
133239 +# Compile-time checks and compiler options
133397 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
133619 diff --git a/arch/arm/configs/hi3531a_spinand_slave_defconfig b/arch/arm/configs/hi3531a_spinand_sl…
133622 --- /dev/null
133624 @@ -0,0 +1,2915 @@
133863 +# GCOV-based kernel profiling
134517 +# Self-contained MTD device drivers
134529 +# Disk-On-Chip Device Drivers
134706 +# SCSI support type (disk, tape, CD-ROM)
134788 +# Controllers with non-SFF native interface
135159 +# Non-8250 serial port support
135227 +# I2C system bus drivers (mostly embedded / system-on-chip)
135791 +# Microsoft Hyper-V guest support
135995 +# CD-ROM/DVD Filesystems
136010 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
136095 +CONFIG_NLS_DEFAULT="iso8859-1"
136160 +# Compile-time checks and compiler options
136318 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
136540 diff --git a/arch/arm/configs/hi3536dv100_full_defconfig b/arch/arm/configs/hi3536dv100_full_defcon…
136543 --- /dev/null
136545 @@ -0,0 +1,2746 @@
136776 +# GCOV-based kernel profiling
137388 +# Self-contained MTD device drivers
137396 +# Disk-On-Chip Device Drivers
137554 +# SCSI support type (disk, tape, CD-ROM)
137595 +# Controllers with non-SFF native interface
137616 +# PIO-only SFF controllers
137886 +# Non-8250 serial port support
137937 +# I2C system bus drivers (mostly embedded / system-on-chip)
138555 +# on-CPU RTC drivers
138581 +# Microsoft Hyper-V guest support
138763 +# CD-ROM/DVD Filesystems
138777 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
138874 +CONFIG_NLS_DEFAULT="iso8859-1"
138938 +# Compile-time checks and compiler options
139071 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
139292 diff --git a/arch/arm/configs/hi3556av100_amp_defconfig b/arch/arm/configs/hi3556av100_amp_defconfig
139295 --- /dev/null
139297 @@ -0,0 +1,3145 @@
139304 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
139775 +# General architecture-dependent options
139826 +# GCOV-based kernel profiling
140142 +# Self-contained MTD device drivers
140154 +# Disk-On-Chip Device Drivers
140314 +# SCSI support type (disk, tape, CD-ROM)
140663 +# Non-8250 serial port support
140728 +# I2C system bus drivers (mostly embedded / system-on-chip)
141238 +# HD-Audio
141672 +# on-CPU RTC drivers
141698 +# Microsoft Hyper-V guest support
141892 +# CD-ROM/DVD Filesystems
141904 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
141992 +CONFIG_NLS_DEFAULT="iso8859-1"
142296 +# Compile-time checks and compiler options
142439 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
142443 diff --git a/arch/arm/configs/hi3556av100_amp_emmc_defconfig b/arch/arm/configs/hi3556av100_amp_emm…
142446 --- /dev/null
142448 @@ -0,0 +1,2986 @@
142455 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
142926 +# General architecture-dependent options
142977 +# GCOV-based kernel profiling
143290 +# Self-contained MTD device drivers
143301 +# Disk-On-Chip Device Drivers
143440 +# SCSI support type (disk, tape, CD-ROM)
143789 +# Non-8250 serial port support
143854 +# I2C system bus drivers (mostly embedded / system-on-chip)
144362 +# HD-Audio
144715 +# Microsoft Hyper-V guest support
144911 +# CD-ROM/DVD Filesystems
144923 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
144998 +CONFIG_NLS_DEFAULT="iso8859-1"
145287 +# Compile-time checks and compiler options
145431 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
145435 diff --git a/arch/arm/configs/hi3556av100_amp_nand_defconfig b/arch/arm/configs/hi3556av100_amp_nan…
145438 --- /dev/null
145440 @@ -0,0 +1,3014 @@
145447 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
145918 +# General architecture-dependent options
145969 +# GCOV-based kernel profiling
146282 +# Self-contained MTD device drivers
146293 +# Disk-On-Chip Device Drivers
146450 +# SCSI support type (disk, tape, CD-ROM)
146799 +# Non-8250 serial port support
146864 +# I2C system bus drivers (mostly embedded / system-on-chip)
147373 +# HD-Audio
147726 +# Microsoft Hyper-V guest support
147922 +# CD-ROM/DVD Filesystems
147934 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
148016 +CONFIG_NLS_DEFAULT="iso8859-1"
148307 +# Compile-time checks and compiler options
148451 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
148455 diff --git a/arch/arm/configs/hi3556av100_amp_spi_defconfig b/arch/arm/configs/hi3556av100_amp_spi_…
148458 --- /dev/null
148460 @@ -0,0 +1,3042 @@
148467 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
148937 +# General architecture-dependent options
148988 +# GCOV-based kernel profiling
149302 +# Self-contained MTD device drivers
149314 +# Disk-On-Chip Device Drivers
149474 +# SCSI support type (disk, tape, CD-ROM)
149763 +# Non-8250 serial port support
149828 +# I2C system bus drivers (mostly embedded / system-on-chip)
150338 +# HD-Audio
150773 +# on-CPU RTC drivers
150799 +# Microsoft Hyper-V guest support
150983 +# CD-ROM/DVD Filesystems
150995 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
151060 +CONFIG_NLS_DEFAULT="iso8859-1"
151356 +# Compile-time checks and compiler options
151499 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
151503 diff --git a/arch/arm/configs/hi3556v200_amp_defconfig b/arch/arm/configs/hi3556v200_amp_defconfig
151506 --- /dev/null
151508 @@ -0,0 +1,2899 @@
151515 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
151982 +# General architecture-dependent options
152033 +# GCOV-based kernel profiling
152360 +# Self-contained MTD device drivers
152372 +# Disk-On-Chip Device Drivers
152514 +# SCSI support type (disk, tape, CD-ROM)
152762 +# Non-8250 serial port support
152829 +# I2C system bus drivers (mostly embedded / system-on-chip)
153344 +# HD-Audio
153687 +# on-CPU RTC drivers
153712 +# Microsoft Hyper-V guest support
153894 +# CD-ROM/DVD Filesystems
153906 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
153963 +CONFIG_NLS_DEFAULT="iso8859-1"
154260 +# Compile-time checks and compiler options
154404 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
154408 diff --git a/arch/arm/configs/hi3556v200_amp_emmc_defconfig b/arch/arm/configs/hi3556v200_amp_emmc_…
154411 --- /dev/null
154413 @@ -0,0 +1,2805 @@
154420 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
154887 +# General architecture-dependent options
154938 +# GCOV-based kernel profiling
155338 +# SCSI support type (disk, tape, CD-ROM)
155586 +# Non-8250 serial port support
155653 +# I2C system bus drivers (mostly embedded / system-on-chip)
156168 +# HD-Audio
156511 +# on-CPU RTC drivers
156536 +# Microsoft Hyper-V guest support
156720 +# CD-ROM/DVD Filesystems
156732 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
156774 +CONFIG_NLS_DEFAULT="iso8859-1"
157071 +# Compile-time checks and compiler options
157215 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
157219 diff --git a/arch/arm/configs/hi3556v200_amp_spinand_defconfig b/arch/arm/configs/hi3556v200_amp_sp…
157222 --- /dev/null
157224 @@ -0,0 +1,2902 @@
157231 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
157698 +# General architecture-dependent options
157749 +# GCOV-based kernel profiling
158076 +# Self-contained MTD device drivers
158087 +# Disk-On-Chip Device Drivers
158239 +# SCSI support type (disk, tape, CD-ROM)
158487 +# Non-8250 serial port support
158554 +# I2C system bus drivers (mostly embedded / system-on-chip)
159069 +# HD-Audio
159412 +# on-CPU RTC drivers
159437 +# Microsoft Hyper-V guest support
159619 +# CD-ROM/DVD Filesystems
159631 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
159682 +CONFIG_NLS_DEFAULT="iso8859-1"
159979 +# Compile-time checks and compiler options
160123 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
160127 diff --git a/arch/arm/configs/hi3556v200_emmc_smp_defconfig b/arch/arm/configs/hi3556v200_emmc_smp_…
160130 --- /dev/null
160132 @@ -0,0 +1,2866 @@
160139 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
160627 +# General architecture-dependent options
160678 +# GCOV-based kernel profiling
161086 +# SCSI support type (disk, tape, CD-ROM)
161330 +# Non-8250 serial port support
161397 +# I2C system bus drivers (mostly embedded / system-on-chip)
161914 +# HD-Audio
162255 +# on-CPU RTC drivers
162279 +# Microsoft Hyper-V guest support
162480 +# CD-ROM/DVD Filesystems
162492 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
162558 +CONFIG_NLS_DEFAULT="iso8859-1"
162847 +# Compile-time checks and compiler options
162995 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
162999 diff --git a/arch/arm/configs/hi3556v200_smp_defconfig b/arch/arm/configs/hi3556v200_smp_defconfig
163002 --- /dev/null
163004 @@ -0,0 +1,2985 @@
163011 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
163499 +# General architecture-dependent options
163550 +# GCOV-based kernel profiling
163885 +# Self-contained MTD device drivers
163897 +# Disk-On-Chip Device Drivers
164056 +# SCSI support type (disk, tape, CD-ROM)
164300 +# Non-8250 serial port support
164367 +# I2C system bus drivers (mostly embedded / system-on-chip)
164884 +# HD-Audio
165225 +# on-CPU RTC drivers
165249 +# Microsoft Hyper-V guest support
165450 +# CD-ROM/DVD Filesystems
165462 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
165546 +CONFIG_NLS_DEFAULT="iso8859-1"
165838 +# Compile-time checks and compiler options
165986 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
165990 diff --git a/arch/arm/configs/hi3559v200_amp_defconfig b/arch/arm/configs/hi3559v200_amp_defconfig
165993 --- /dev/null
165995 @@ -0,0 +1,2917 @@
166002 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
166469 +# General architecture-dependent options
166520 +# GCOV-based kernel profiling
166847 +# Self-contained MTD device drivers
166859 +# Disk-On-Chip Device Drivers
167001 +# SCSI support type (disk, tape, CD-ROM)
167249 +# Non-8250 serial port support
167316 +# I2C system bus drivers (mostly embedded / system-on-chip)
167831 +# HD-Audio
168192 +# on-CPU RTC drivers
168217 +# Microsoft Hyper-V guest support
168399 +# CD-ROM/DVD Filesystems
168411 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
168468 +CONFIG_NLS_DEFAULT="iso8859-1"
168765 +# Compile-time checks and compiler options
168909 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
168913 diff --git a/arch/arm/configs/hi3559v200_amp_emmc_defconfig b/arch/arm/configs/hi3559v200_amp_emmc_…
168916 --- /dev/null
168918 @@ -0,0 +1,2823 @@
168925 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
169392 +# General architecture-dependent options
169443 +# GCOV-based kernel profiling
169843 +# SCSI support type (disk, tape, CD-ROM)
170091 +# Non-8250 serial port support
170158 +# I2C system bus drivers (mostly embedded / system-on-chip)
170673 +# HD-Audio
171034 +# on-CPU RTC drivers
171059 +# Microsoft Hyper-V guest support
171243 +# CD-ROM/DVD Filesystems
171255 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
171297 +CONFIG_NLS_DEFAULT="iso8859-1"
171594 +# Compile-time checks and compiler options
171738 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
171742 diff --git a/arch/arm/configs/hi3559v200_amp_spinand_defconfig b/arch/arm/configs/hi3559v200_amp_sp…
171745 --- /dev/null
171747 @@ -0,0 +1,2920 @@
171754 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
172221 +# General architecture-dependent options
172272 +# GCOV-based kernel profiling
172599 +# Self-contained MTD device drivers
172610 +# Disk-On-Chip Device Drivers
172762 +# SCSI support type (disk, tape, CD-ROM)
173010 +# Non-8250 serial port support
173077 +# I2C system bus drivers (mostly embedded / system-on-chip)
173592 +# HD-Audio
173953 +# on-CPU RTC drivers
173978 +# Microsoft Hyper-V guest support
174160 +# CD-ROM/DVD Filesystems
174172 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
174223 +CONFIG_NLS_DEFAULT="iso8859-1"
174520 +# Compile-time checks and compiler options
174664 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
174668 diff --git a/arch/arm/configs/hi3559v200_emmc_smp_defconfig b/arch/arm/configs/hi3559v200_emmc_smp_…
174671 --- /dev/null
174673 @@ -0,0 +1,2866 @@
174680 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
175168 +# General architecture-dependent options
175219 +# GCOV-based kernel profiling
175627 +# SCSI support type (disk, tape, CD-ROM)
175871 +# Non-8250 serial port support
175938 +# I2C system bus drivers (mostly embedded / system-on-chip)
176455 +# HD-Audio
176796 +# on-CPU RTC drivers
176820 +# Microsoft Hyper-V guest support
177021 +# CD-ROM/DVD Filesystems
177033 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
177099 +CONFIG_NLS_DEFAULT="iso8859-1"
177388 +# Compile-time checks and compiler options
177536 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
177540 diff --git a/arch/arm/configs/hi3559v200_smp_defconfig b/arch/arm/configs/hi3559v200_smp_defconfig
177543 --- /dev/null
177545 @@ -0,0 +1,2985 @@
177552 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
178040 +# General architecture-dependent options
178091 +# GCOV-based kernel profiling
178426 +# Self-contained MTD device drivers
178438 +# Disk-On-Chip Device Drivers
178597 +# SCSI support type (disk, tape, CD-ROM)
178841 +# Non-8250 serial port support
178908 +# I2C system bus drivers (mostly embedded / system-on-chip)
179425 +# HD-Audio
179766 +# on-CPU RTC drivers
179790 +# Microsoft Hyper-V guest support
179991 +# CD-ROM/DVD Filesystems
180003 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
180087 +CONFIG_NLS_DEFAULT="iso8859-1"
180379 +# Compile-time checks and compiler options
180527 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
180531 diff --git a/arch/arm/configs/hi3562v100_amp_defconfig b/arch/arm/configs/hi3562v100_amp_defconfig
180534 --- /dev/null
180536 @@ -0,0 +1,2875 @@
180543 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
181008 +# General architecture-dependent options
181059 +# GCOV-based kernel profiling
181405 +# Self-contained MTD device drivers
181417 +# Disk-On-Chip Device Drivers
181560 +# SCSI support type (disk, tape, CD-ROM)
181832 +# Non-8250 serial port support
181899 +# I2C system bus drivers (mostly embedded / system-on-chip)
182695 +# on-CPU RTC drivers
182721 +# Microsoft Hyper-V guest support
182898 +# CD-ROM/DVD Filesystems
182910 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
182967 +CONFIG_NLS_DEFAULT="iso8859-1"
183264 +# Compile-time checks and compiler options
183408 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
183412 diff --git a/arch/arm/configs/hi3562v100_amp_emmc_defconfig b/arch/arm/configs/hi3562v100_amp_emmc_…
183415 --- /dev/null
183417 @@ -0,0 +1,2881 @@
183424 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
183889 +# General architecture-dependent options
183940 +# GCOV-based kernel profiling
184361 +# SCSI support type (disk, tape, CD-ROM)
184633 +# Non-8250 serial port support
184700 +# I2C system bus drivers (mostly embedded / system-on-chip)
185595 +# on-CPU RTC drivers
185621 +# Microsoft Hyper-V guest support
185800 +# CD-ROM/DVD Filesystems
185812 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
185854 +CONFIG_NLS_DEFAULT="iso8859-1"
186151 +# Compile-time checks and compiler options
186295 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
186299 diff --git a/arch/arm/configs/hi3562v100_amp_spinand_defconfig b/arch/arm/configs/hi3562v100_amp_sp…
186302 --- /dev/null
186304 @@ -0,0 +1,2978 @@
186311 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
186776 +# General architecture-dependent options
186827 +# GCOV-based kernel profiling
187174 +# Self-contained MTD device drivers
187185 +# Disk-On-Chip Device Drivers
187338 +# SCSI support type (disk, tape, CD-ROM)
187610 +# Non-8250 serial port support
187677 +# I2C system bus drivers (mostly embedded / system-on-chip)
188572 +# on-CPU RTC drivers
188598 +# Microsoft Hyper-V guest support
188775 +# CD-ROM/DVD Filesystems
188787 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
188838 +CONFIG_NLS_DEFAULT="iso8859-1"
189135 +# Compile-time checks and compiler options
189279 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
189283 diff --git a/arch/arm/configs/hi3566v100_amp_defconfig b/arch/arm/configs/hi3566v100_amp_defconfig
189286 --- /dev/null
189288 @@ -0,0 +1,2975 @@
189295 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
189760 +# General architecture-dependent options
189811 +# GCOV-based kernel profiling
190158 +# Self-contained MTD device drivers
190170 +# Disk-On-Chip Device Drivers
190313 +# SCSI support type (disk, tape, CD-ROM)
190585 +# Non-8250 serial port support
190652 +# I2C system bus drivers (mostly embedded / system-on-chip)
191547 +# on-CPU RTC drivers
191573 +# Microsoft Hyper-V guest support
191750 +# CD-ROM/DVD Filesystems
191762 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
191819 +CONFIG_NLS_DEFAULT="iso8859-1"
192116 +# Compile-time checks and compiler options
192260 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
192264 diff --git a/arch/arm/configs/hi3566v100_amp_emmc_defconfig b/arch/arm/configs/hi3566v100_amp_emmc_…
192267 --- /dev/null
192269 @@ -0,0 +1,2881 @@
192276 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
192741 +# General architecture-dependent options
192792 +# GCOV-based kernel profiling
193213 +# SCSI support type (disk, tape, CD-ROM)
193485 +# Non-8250 serial port support
193552 +# I2C system bus drivers (mostly embedded / system-on-chip)
194447 +# on-CPU RTC drivers
194473 +# Microsoft Hyper-V guest support
194652 +# CD-ROM/DVD Filesystems
194664 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
194706 +CONFIG_NLS_DEFAULT="iso8859-1"
195003 +# Compile-time checks and compiler options
195147 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
195151 diff --git a/arch/arm/configs/hi3566v100_amp_spinand_defconfig b/arch/arm/configs/hi3566v100_amp_sp…
195154 --- /dev/null
195156 @@ -0,0 +1,2978 @@
195163 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
195628 +# General architecture-dependent options
195679 +# GCOV-based kernel profiling
196026 +# Self-contained MTD device drivers
196037 +# Disk-On-Chip Device Drivers
196190 +# SCSI support type (disk, tape, CD-ROM)
196462 +# Non-8250 serial port support
196529 +# I2C system bus drivers (mostly embedded / system-on-chip)
197424 +# on-CPU RTC drivers
197450 +# Microsoft Hyper-V guest support
197627 +# CD-ROM/DVD Filesystems
197639 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
197690 +CONFIG_NLS_DEFAULT="iso8859-1"
197987 +# Compile-time checks and compiler options
198131 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
198135 diff --git a/arch/arm/configs/hi3568v100_amp_defconfig b/arch/arm/configs/hi3568v100_amp_defconfig
198138 --- /dev/null
198140 @@ -0,0 +1,3048 @@
198147 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
198616 +# General architecture-dependent options
198667 +# GCOV-based kernel profiling
198997 +# Self-contained MTD device drivers
199009 +# Disk-On-Chip Device Drivers
199169 +# SCSI support type (disk, tape, CD-ROM)
199514 +# Non-8250 serial port support
199579 +# I2C system bus drivers (mostly embedded / system-on-chip)
200089 +# HD-Audio
200437 +# on-CPU RTC drivers
200461 +# Microsoft Hyper-V guest support
200647 +# CD-ROM/DVD Filesystems
200659 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
200747 +CONFIG_NLS_DEFAULT="iso8859-1"
201042 +# Compile-time checks and compiler options
201185 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
201189 diff --git a/arch/arm/configs/hi3568v100_amp_emmc_defconfig b/arch/arm/configs/hi3568v100_amp_emmc_…
201192 --- /dev/null
201194 @@ -0,0 +1,3015 @@
201201 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
201670 +# General architecture-dependent options
201721 +# GCOV-based kernel profiling
202053 +# Self-contained MTD device drivers
202064 +# Disk-On-Chip Device Drivers
202203 +# SCSI support type (disk, tape, CD-ROM)
202548 +# Non-8250 serial port support
202613 +# I2C system bus drivers (mostly embedded / system-on-chip)
203122 +# HD-Audio
203470 +# on-CPU RTC drivers
203494 +# Microsoft Hyper-V guest support
203689 +# CD-ROM/DVD Filesystems
203701 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
203768 +CONFIG_NLS_DEFAULT="iso8859-1"
204063 +# Compile-time checks and compiler options
204206 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
204210 diff --git a/arch/arm/configs/hi3568v100_amp_nand_defconfig b/arch/arm/configs/hi3568v100_amp_nand_…
204213 --- /dev/null
204215 @@ -0,0 +1,3038 @@
204222 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
204691 +# General architecture-dependent options
204742 +# GCOV-based kernel profiling
205072 +# Self-contained MTD device drivers
205083 +# Disk-On-Chip Device Drivers
205240 +# SCSI support type (disk, tape, CD-ROM)
205585 +# Non-8250 serial port support
205650 +# I2C system bus drivers (mostly embedded / system-on-chip)
206160 +# HD-Audio
206508 +# on-CPU RTC drivers
206532 +# Microsoft Hyper-V guest support
206718 +# CD-ROM/DVD Filesystems
206730 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
206812 +CONFIG_NLS_DEFAULT="iso8859-1"
207107 +# Compile-time checks and compiler options
207250 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
207254 diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
207256 --- a/arch/arm/include/asm/mach/pci.h
207258 @@ -12,6 +12,7 @@
207266 @@ -19,7 +20,25 @@ struct pci_bus;
207292 @@ -36,12 +55,17 @@ struct hw_pci {
207301 * Per-controller structure
207309 u64 mem_offset; /* bus->cpu memory mapping offset */
207310 diff --git a/arch/arm/mach-hibvt/Kconfig b/arch/arm/mach-hibvt/Kconfig
207313 --- /dev/null
207314 +++ b/arch/arm/mach-hibvt/Kconfig
207315 @@ -0,0 +1,258 @@
207330 + bool "Hisilicon Hi3521DV200 Cortex-A7 family"
207339 + bool "Hisilicon Hi3520DV500 Cortex-A7 family"
207348 + bool "Hisilicon Hi3516A Cortex-A7(Single) family"
207358 + bool "Hisilicon Hi3516CV500 Cortex-A7 family"
207367 + bool "Hisilicon Hi3516DV300 Cortex-A7 family"
207376 + bool "Hisilicon Hi3516EV200 Cortex-A7 family"
207385 + bool "Hisilicon Hi3516EV300 Cortex-A7 family"
207394 + bool "Hisilicon Hi3518EV300 Cortex-A7 family"
207403 + bool "Hisilicon Hi3516DV200 Cortex-A7 family"
207411 + bool "Hisilicon Hi3556V200 Cortex-A7 family"
207420 + bool "Hisilicon Hi3559V200 Cortex-A7 family"
207437 + bool "Hisilicon Hi3536DV100 Cortex-A7(Single) family"
207467 + bool "Hisilicon Hi3556AV100 Cortex-a53 family" if ARCH_MULTI_V7
207481 + support power control for Hi3556AV100 Cortex-a53
207486 + bool "Hisilicon Hi3519AV100 Cortex-a53 family" if ARCH_MULTI_V7
207502 + support power control for Hi3519AV100 Cortex-a53
207507 + bool "Hisilicon Hi3568V100 Cortex-a53 family" if ARCH_MULTI_V7
207523 + support power control for Hi3568V100 Cortex-a53
207574 diff --git a/arch/arm/mach-hibvt/Makefile b/arch/arm/mach-hibvt/Makefile
207577 --- /dev/null
207578 +++ b/arch/arm/mach-hibvt/Makefile
207579 @@ -0,0 +1,27 @@
207584 +obj-$(CONFIG_ARCH_HI3521DV200) += mach-hi3521dv200.o
207585 +obj-$(CONFIG_ARCH_HI3520DV500) += mach-hi3521dv200.o
207586 +obj-$(CONFIG_ARCH_HI3516A) += mach-hi3516a.o
207587 +obj-$(CONFIG_ARCH_HI3516CV500) += mach-hi3516cv500.o
207588 +obj-$(CONFIG_ARCH_HI3516EV200) += mach-hi3516ev200.o
207589 +obj-$(CONFIG_ARCH_HI3516EV300) += mach-hi3516ev300.o
207590 +obj-$(CONFIG_ARCH_HI3518EV300) += mach-hi3518ev300.o
207591 +obj-$(CONFIG_ARCH_HI3516DV200) += mach-hi3516dv200.o
207592 +obj-$(CONFIG_ARCH_HI3516DV300) += mach-hi3516dv300.o
207593 +obj-$(CONFIG_ARCH_HI3556V200) += mach-hi3556v200.o
207594 +obj-$(CONFIG_ARCH_HI3559V200) += mach-hi3559v200.o
207595 +obj-$(CONFIG_ARCH_HI3562V100) += mach-hi3559v200.o
207596 +obj-$(CONFIG_ARCH_HI3566V100) += mach-hi3559v200.o
207597 +obj-$(CONFIG_ARCH_HI3518EV20X) += mach-hi3518ev20x.o
207598 +obj-$(CONFIG_ARCH_HI3536DV100) += mach-hi3536dv100.o
207599 +obj-$(CONFIG_ARCH_HI3521A) += mach-hi3521a.o
207600 +obj-$(CONFIG_ARCH_HI3531A) += mach-hi3531a.o
207601 +obj-$(CONFIG_ARCH_HI3556AV100) += mach-hi3556av100.o
207602 +obj-$(CONFIG_ARCH_HI3519AV100) += mach-hi3519av100.o
207603 +obj-$(CONFIG_ARCH_HI3568V100) += mach-hi3519av100.o
207606 +obj-$(CONFIG_SMP) += platsmp.o
207607 diff --git a/arch/arm/mach-hibvt/Makefile.boot b/arch/arm/mach-hibvt/Makefile.boot
207610 --- /dev/null
207611 +++ b/arch/arm/mach-hibvt/Makefile.boot
207612 @@ -0,0 +1,7 @@
207614 +zreladdr-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_AMP_ZRELADDR)
207616 +zreladdr-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_HI_ZRELADDR)
207618 +params_phys-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_HI_PARAMS_PHYS)
207619 +initrd_phys-$(CONFIG_ARCH_HISI_BVT) := $(CONFIG_HI_INITRD_PHYS)
207620 diff --git a/arch/arm/mach-hibvt/include/mach/hi3516a_io.h b/arch/arm/mach-hibvt/include/mach/hi351…
207623 --- /dev/null
207624 +++ b/arch/arm/mach-hibvt/include/mach/hi3516a_io.h
207625 @@ -0,0 +1,23 @@
207649 diff --git a/arch/arm/mach-hibvt/include/mach/hi3516cv500_io.h b/arch/arm/mach-hibvt/include/mach/h…
207652 --- /dev/null
207653 +++ b/arch/arm/mach-hibvt/include/mach/hi3516cv500_io.h
207654 @@ -0,0 +1,26 @@
207681 diff --git a/arch/arm/mach-hibvt/include/mach/hi3516cv500_platform.h b/arch/arm/mach-hibvt/include/…
207684 --- /dev/null
207685 +++ b/arch/arm/mach-hibvt/include/mach/hi3516cv500_platform.h
207686 @@ -0,0 +1,4 @@
207691 diff --git a/arch/arm/mach-hibvt/include/mach/hi3516dv300_io.h b/arch/arm/mach-hibvt/include/mach/h…
207694 --- /dev/null
207695 +++ b/arch/arm/mach-hibvt/include/mach/hi3516dv300_io.h
207696 @@ -0,0 +1,26 @@
207723 diff --git a/arch/arm/mach-hibvt/include/mach/hi3516dv300_platform.h b/arch/arm/mach-hibvt/include/…
207726 --- /dev/null
207727 +++ b/arch/arm/mach-hibvt/include/mach/hi3516dv300_platform.h
207728 @@ -0,0 +1,4 @@
207733 diff --git a/arch/arm/mach-hibvt/include/mach/hi3518ev20x_io.h b/arch/arm/mach-hibvt/include/mach/h…
207736 --- /dev/null
207737 +++ b/arch/arm/mach-hibvt/include/mach/hi3518ev20x_io.h
207738 @@ -0,0 +1,26 @@
207765 diff --git a/arch/arm/mach-hibvt/include/mach/hi3519av100_io.h b/arch/arm/mach-hibvt/include/mach/h…
207768 --- /dev/null
207769 +++ b/arch/arm/mach-hibvt/include/mach/hi3519av100_io.h
207770 @@ -0,0 +1,11 @@
207782 diff --git a/arch/arm/mach-hibvt/include/mach/hi3519av100_platform.h b/arch/arm/mach-hibvt/include/…
207785 --- /dev/null
207786 +++ b/arch/arm/mach-hibvt/include/mach/hi3519av100_platform.h
207787 @@ -0,0 +1,94 @@
207812 +/* bit[5:4:3]=000; bit[7]:SPI nor address mode; bit[7]=(0:3-Byte | 1:4-Byte) */
207814 +/* bit[5:4:3]=001; bit[7]: SPI nand I/O widthe; bit[7]=(0: 1-I/O | 1: 4-I/O */
207816 +/* bit[5:4:3]=10*; bit[7]: EMMC I/O widthe; bit[7]=(0: 4-I/O | 1: 8-I/O */
207840 + * 0x1-> init item1
207841 + * 0x2-> init item2
207842 + * 0x3->init item1 & item2
207848 +/*-----------------------------------------------------------------------
207850 + * ----------------------------------------------------------------------*/
207882 diff --git a/arch/arm/mach-hibvt/include/mach/hi3521a_io.h b/arch/arm/mach-hibvt/include/mach/hi352…
207885 --- /dev/null
207886 +++ b/arch/arm/mach-hibvt/include/mach/hi3521a_io.h
207887 @@ -0,0 +1,40 @@
207892 + * 0x1000_0000 <-----> 0xFE00_0000
207899 + * 0x1200_0000 <-----> 0xFE40_0000
207906 + * 0x1301_0000 <-----> 0xFE70_0000
207928 diff --git a/arch/arm/mach-hibvt/include/mach/hi3521a_platform.h b/arch/arm/mach-hibvt/include/mach…
207931 --- /dev/null
207932 +++ b/arch/arm/mach-hibvt/include/mach/hi3521a_platform.h
207933 @@ -0,0 +1,27 @@
207937 +/* -------------------------------------------------------------------- */
207939 +/* -------------------------------------------------------------------- */
207942 +/* -------------------------------------------------------------------- */
207944 +/* -------------------------------------------------------------------- */
207961 diff --git a/arch/arm/mach-hibvt/include/mach/hi3531a_io.h b/arch/arm/mach-hibvt/include/mach/hi353…
207964 --- /dev/null
207965 +++ b/arch/arm/mach-hibvt/include/mach/hi3531a_io.h
207966 @@ -0,0 +1,63 @@
207978 + * 0x1000_0000 <-----> 0xFE00_0000
207979 + * 0x1071_0000 <-----> 0xFE71_0000
207987 + * 0x1100_0000 <-----> 0xFE78_0000
207988 + * 0x1104_0000 <-----> 0xFE7C_0000
207996 + * 0x1200_0000 <-----> 0xFE80_0000
207997 + * 0x122F_0000 <-----> 0xFEAF_0000
208005 + * 0x1300_0000 <-----> 0xFEB0_0000
208006 + * 0x131A_0000 <-----> 0xFECA_0000
208030 diff --git a/arch/arm/mach-hibvt/include/mach/hi3531a_platform.h b/arch/arm/mach-hibvt/include/mach…
208033 --- /dev/null
208034 +++ b/arch/arm/mach-hibvt/include/mach/hi3531a_platform.h
208035 @@ -0,0 +1,65 @@
208039 +/* -------------------------------------------------------------------- */
208041 +/* -------------------------------------------------------------------- */
208058 +/* -------------------------------------------------------------------- */
208060 +/* -------------------------------------------------------------------- */
208063 +/* -------------------------------------------------------------------- */
208065 +/* -------------------------------------------------------------------- */
208068 +/* -------------------------------------------------------------------- */
208070 +/* -------------------------------------------------------------------- */
208076 +/* -------------------------------------------------------------------- */
208077 +/* CORTTX-A9 internal Register */
208078 +/* -------------------------------------------------------------------- */
208082 +/* -------------------------------------------------------------------- */
208085 +/* -------------------------------------------------------------------- */
208087 +/* -------------------------------------------------------------------- */
208101 diff --git a/arch/arm/mach-hibvt/include/mach/hi3536dv100_io.h b/arch/arm/mach-hibvt/include/mach/h…
208104 --- /dev/null
208105 +++ b/arch/arm/mach-hibvt/include/mach/hi3536dv100_io.h
208106 @@ -0,0 +1,44 @@
208111 + * 0x1100_0000 <-----> 0xFE00_0000
208112 + * 0x1104_0000 <-----> 0xFE04_0000
208119 + * 0x1200_0000 <-----> 0xFE10_0000
208120 + * 0x121B_0000 <-----> 0xFE2B_0000
208127 + * 0x1300_0000 <-----> 0xFE30_0000
208128 + * 0x1321_0000 <-----> 0xFE51_0000
208151 diff --git a/arch/arm/mach-hibvt/include/mach/hi3536dv100_platform.h b/arch/arm/mach-hibvt/include/…
208154 --- /dev/null
208155 +++ b/arch/arm/mach-hibvt/include/mach/hi3536dv100_platform.h
208156 @@ -0,0 +1,14 @@
208160 +/* -------------------------------------------------------------------- */
208162 +/* -------------------------------------------------------------------- */
208165 +/* -------------------------------------------------------------------- */
208167 +/* -------------------------------------------------------------------- */
208171 diff --git a/arch/arm/mach-hibvt/include/mach/hi3556av100_platform.h b/arch/arm/mach-hibvt/include/…
208174 --- /dev/null
208175 +++ b/arch/arm/mach-hibvt/include/mach/hi3556av100_platform.h
208176 @@ -0,0 +1,94 @@
208201 +/* bit[5:4:3]=000; bit[7]:SPI nor address mode; bit[7]=(0:3-Byte | 1:4-Byte) */
208203 +/* bit[5:4:3]=001; bit[7]: SPI nand I/O widthe; bit[7]=(0: 1-I/O | 1: 4-I/O */
208205 +/* bit[5:4:3]=10*; bit[7]: EMMC I/O widthe; bit[7]=(0: 4-I/O | 1: 8-I/O */
208229 + * 0x1-> init item1
208230 + * 0x2-> init item2
208231 + * 0x3->init item1 & item2
208237 +/*-----------------------------------------------------------------------
208239 + * ----------------------------------------------------------------------*/
208271 diff --git a/arch/arm/mach-hibvt/include/mach/hi3556v200_io.h b/arch/arm/mach-hibvt/include/mach/hi…
208274 --- /dev/null
208275 +++ b/arch/arm/mach-hibvt/include/mach/hi3556v200_io.h
208276 @@ -0,0 +1,26 @@
208303 diff --git a/arch/arm/mach-hibvt/include/mach/hi3556v200_platform.h b/arch/arm/mach-hibvt/include/m…
208306 --- /dev/null
208307 +++ b/arch/arm/mach-hibvt/include/mach/hi3556v200_platform.h
208308 @@ -0,0 +1,4 @@
208313 diff --git a/arch/arm/mach-hibvt/include/mach/hi3559v200_io.h b/arch/arm/mach-hibvt/include/mach/hi…
208316 --- /dev/null
208317 +++ b/arch/arm/mach-hibvt/include/mach/hi3559v200_io.h
208318 @@ -0,0 +1,26 @@
208345 diff --git a/arch/arm/mach-hibvt/include/mach/hi3559v200_platform.h b/arch/arm/mach-hibvt/include/m…
208348 --- /dev/null
208349 +++ b/arch/arm/mach-hibvt/include/mach/hi3559v200_platform.h
208350 @@ -0,0 +1,4 @@
208355 diff --git a/arch/arm/mach-hibvt/include/mach/io.h b/arch/arm/mach-hibvt/include/mach/io.h
208358 --- /dev/null
208359 +++ b/arch/arm/mach-hibvt/include/mach/io.h
208360 @@ -0,0 +1,52 @@
208413 diff --git a/arch/arm/mach-hibvt/include/mach/platform.h b/arch/arm/mach-hibvt/include/mach/platfor…
208416 --- /dev/null
208417 +++ b/arch/arm/mach-hibvt/include/mach/platform.h
208418 @@ -0,0 +1,52 @@
208471 diff --git a/arch/arm/mach-hibvt/mach-common.h b/arch/arm/mach-hibvt/mach-common.h
208474 --- /dev/null
208475 +++ b/arch/arm/mach-hibvt/mach-common.h
208476 @@ -0,0 +1,9 @@
208486 diff --git a/arch/arm/mach-hibvt/mach-hi3516a.c b/arch/arm/mach-hibvt/mach-hi3516a.c
208489 --- /dev/null
208490 +++ b/arch/arm/mach-hibvt/mach-hi3516a.c
208491 @@ -0,0 +1,64 @@
208493 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
208556 diff --git a/arch/arm/mach-hibvt/mach-hi3516cv500.c b/arch/arm/mach-hibvt/mach-hi3516cv500.c
208559 --- /dev/null
208560 +++ b/arch/arm/mach-hibvt/mach-hi3516cv500.c
208561 @@ -0,0 +1,68 @@
208563 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
208583 +#include "mach-common.h"
208597 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516cv500-clock");
208630 diff --git a/arch/arm/mach-hibvt/mach-hi3516dv200.c b/arch/arm/mach-hibvt/mach-hi3516dv200.c
208633 --- /dev/null
208634 +++ b/arch/arm/mach-hibvt/mach-hi3516dv200.c
208635 @@ -0,0 +1,67 @@
208657 +#include "mach-common.h"
208671 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv200-clock");
208700 +CPU_METHOD_OF_DECLARE(hi3516dv200_smp, "hisilicon,hi3516dv200-smp",
208703 diff --git a/arch/arm/mach-hibvt/mach-hi3516dv300.c b/arch/arm/mach-hibvt/mach-hi3516dv300.c
208706 --- /dev/null
208707 +++ b/arch/arm/mach-hibvt/mach-hi3516dv300.c
208708 @@ -0,0 +1,68 @@
208710 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
208730 +#include "mach-common.h"
208744 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516dv300-clock");
208777 diff --git a/arch/arm/mach-hibvt/mach-hi3516ev200.c b/arch/arm/mach-hibvt/mach-hi3516ev200.c
208780 --- /dev/null
208781 +++ b/arch/arm/mach-hibvt/mach-hi3516ev200.c
208782 @@ -0,0 +1,67 @@
208784 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
208804 +#include "mach-common.h"
208818 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516ev200-clock");
208847 +CPU_METHOD_OF_DECLARE(hi3516ev200_smp, "hisilicon,hi3516ev200-smp",
208850 diff --git a/arch/arm/mach-hibvt/mach-hi3516ev300.c b/arch/arm/mach-hibvt/mach-hi3516ev300.c
208853 --- /dev/null
208854 +++ b/arch/arm/mach-hibvt/mach-hi3516ev300.c
208855 @@ -0,0 +1,67 @@
208857 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
208877 +#include "mach-common.h"
208891 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3516ev300-clock");
208920 +CPU_METHOD_OF_DECLARE(hi3516ev300_smp, "hisilicon,hi3516ev300-smp",
208923 diff --git a/arch/arm/mach-hibvt/mach-hi3518ev20x.c b/arch/arm/mach-hibvt/mach-hi3518ev20x.c
208926 --- /dev/null
208927 +++ b/arch/arm/mach-hibvt/mach-hi3518ev20x.c
208928 @@ -0,0 +1,64 @@
208930 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
208993 diff --git a/arch/arm/mach-hibvt/mach-hi3518ev300.c b/arch/arm/mach-hibvt/mach-hi3518ev300.c
208996 --- /dev/null
208997 +++ b/arch/arm/mach-hibvt/mach-hi3518ev300.c
208998 @@ -0,0 +1,67 @@
209000 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209020 +#include "mach-common.h"
209034 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3518ev300-clock");
209063 +CPU_METHOD_OF_DECLARE(hi3518ev300_smp, "hisilicon,hi3518ev300-smp",
209066 diff --git a/arch/arm/mach-hibvt/mach-hi3519av100.c b/arch/arm/mach-hibvt/mach-hi3519av100.c
209069 --- /dev/null
209070 +++ b/arch/arm/mach-hibvt/mach-hi3519av100.c
209071 @@ -0,0 +1,88 @@
209073 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209157 +CPU_METHOD_OF_DECLARE(hi3519av100_smp, "hisilicon,hi3519av100-smp",
209160 diff --git a/arch/arm/mach-hibvt/mach-hi3521a.c b/arch/arm/mach-hibvt/mach-hi3521a.c
209163 --- /dev/null
209164 +++ b/arch/arm/mach-hibvt/mach-hi3521a.c
209165 @@ -0,0 +1,68 @@
209167 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209234 diff --git a/arch/arm/mach-hibvt/mach-hi3521dv200.c b/arch/arm/mach-hibvt/mach-hi3521dv200.c
209237 --- /dev/null
209238 +++ b/arch/arm/mach-hibvt/mach-hi3521dv200.c
209239 @@ -0,0 +1,110 @@
209241 + * Copyright (c) 2019-2020 HiSilicon Technologies Co., Ltd.
209261 +#include "mach-common.h"
209283 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3521dv200-clock");
209350 diff --git a/arch/arm/mach-hibvt/mach-hi3531a.c b/arch/arm/mach-hibvt/mach-hi3531a.c
209353 --- /dev/null
209354 +++ b/arch/arm/mach-hibvt/mach-hi3531a.c
209355 @@ -0,0 +1,185 @@
209357 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209386 +#include "mach-common.h"
209469 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3531a-clock");
209503 + * connected on the Cortex-A17 AXI master port support it.
209539 +CPU_METHOD_OF_DECLARE(hi3531a_smp, "hisilicon,hi3531a-smp", &hi35xx_smp_ops);
209541 diff --git a/arch/arm/mach-hibvt/mach-hi3536dv100.c b/arch/arm/mach-hibvt/mach-hi3536dv100.c
209544 --- /dev/null
209545 +++ b/arch/arm/mach-hibvt/mach-hi3536dv100.c
209546 @@ -0,0 +1,71 @@
209548 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209618 diff --git a/arch/arm/mach-hibvt/mach-hi3556av100.c b/arch/arm/mach-hibvt/mach-hi3556av100.c
209621 --- /dev/null
209622 +++ b/arch/arm/mach-hibvt/mach-hi3556av100.c
209623 @@ -0,0 +1,91 @@
209625 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209712 +CPU_METHOD_OF_DECLARE(hi3556av100_smp, "hisilicon,hi3556av100-smp",
209715 diff --git a/arch/arm/mach-hibvt/mach-hi3556v200.c b/arch/arm/mach-hibvt/mach-hi3556v200.c
209718 --- /dev/null
209719 +++ b/arch/arm/mach-hibvt/mach-hi3556v200.c
209720 @@ -0,0 +1,67 @@
209722 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209742 +#include "mach-common.h"
209756 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3556v200-clock");
209788 diff --git a/arch/arm/mach-hibvt/mach-hi3559v200.c b/arch/arm/mach-hibvt/mach-hi3559v200.c
209791 --- /dev/null
209792 +++ b/arch/arm/mach-hibvt/mach-hi3559v200.c
209793 @@ -0,0 +1,67 @@
209795 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
209815 +#include "mach-common.h"
209829 + np = of_find_compatible_node(NULL, NULL, "hisilicon,hi3559v200-clock");
209861 diff --git a/arch/arm/mach-hibvt/platsmp.c b/arch/arm/mach-hibvt/platsmp.c
209864 --- /dev/null
209865 +++ b/arch/arm/mach-hibvt/platsmp.c
209866 @@ -0,0 +1,62 @@
209870 + * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
209881 +#include "mach-common.h"
209913 + writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
209929 diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
209931 --- a/arch/arm/mm/dma-mapping.c
209932 +++ b/arch/arm/mm/dma-mapping.c
209933 @@ -284,7 +284,7 @@ static u64 get_coherent_dma_mask(struct device *dev)
209937 -static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag)
209942 @@ -313,6 +313,7 @@ static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag
209950 @@ -521,6 +522,12 @@ static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
209963 @@ -2403,3 +2410,10 @@ void arch_teardown_dma_ops(struct device *dev)
209964 /* Let arch_setup_dma_ops() start again from scratch upon re-probe */
209974 diff --git a/arch/arm/plat-hi3519av100/Makefile b/arch/arm/plat-hi3519av100/Makefile
209977 --- /dev/null
209978 +++ b/arch/arm/plat-hi3519av100/Makefile
209979 @@ -0,0 +1,7 @@
209980 +# arch/arm/plat-hi3519av100/Makefile
209985 +obj-$(CONFIG_HIEDMACV310) += pll-trainning.o
209987 diff --git a/arch/arm/plat-hi3519av100/pll-trainning.c b/arch/arm/plat-hi3519av100/pll-trainning.c
209990 --- /dev/null
209991 +++ b/arch/arm/plat-hi3519av100/pll-trainning.c
209992 @@ -0,0 +1,1187 @@
210019 +#include <linux/dma-mapping.h>
210233 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
210234 + pmx_reg_virt += pin->pinmx_reg_offset;
210237 + if ((val & 0xf) == pin->pinmx_func_num) {
210238 + pin->restored_val = val;
210241 + pin->pinmx_func_changed = 1;
210243 + pin->pinmx_func_changed = 0;
210252 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
210253 + pin = &pmx_ctrl->pins[i];
210272 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
210273 + pmx_reg_virt += pin->pinmx_reg_offset;
210275 + if (pin->pinmx_func_changed) {
210276 + writel(pin->restored_val, pmx_reg_virt);
210286 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
210287 + pin = &pmx_ctrl->pins[i];
210408 + val |= (1 << dev->clock_gate_bit);
210411 + val |= (1 << dev->reset_bit);
210414 + val &= ~(1 << dev->reset_bit);
210422 + if (dev->dev_clock_enable) {
210423 + dev->dev_clock_enable(dev);
210439 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x820); // dma src address
210448 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x868); // dma dest address
210453 + writel(0x7ff, dev->ctrlreg_base + 0x44);
210454 + writel(0x1, dev->ctrlreg_base + 0x24);
210455 + writel(0x0, dev->ctrlreg_base + 0x28);
210456 + writel(0x70, dev->ctrlreg_base + 0x2c);
210457 + writel(0x0, dev->ctrlreg_base + 0x34);
210458 + writel(0x40, dev->ctrlreg_base + 0x38);
210459 + writel(0x3, dev->ctrlreg_base + 0x48);
210461 + writel(0x381, dev->ctrlreg_base + 0x30);
210468 + if (dev->dev_clock_enable) {
210469 + dev->dev_clock_enable(dev);
210474 + * return: on -1, dma timeout;
210475 + * on -2, data err;
210486 + int ret = -1;
210495 + val |= ((dev->tx_dma_reqline_val << shift)
210496 + | (dev->rx_dma_reqline_val << (shift + 8)));
210501 + val |= ((dev->rx_dma_reqline_val << shift)
210502 + | (dev->tx_dma_reqline_val << (shift + 8)));
210506 + addr = dev->ctrlreg_base + UART_DR;
210508 + ret = -1;
210530 + return -1;
210541 + if (dev->dev_rx_dma_init) {
210542 + dev->dev_rx_dma_init(dev, i);
210547 + dev->dev_dma_exit(dev);
210554 + dev->dev_dma_exit(dev);
210559 + dev->dev_dma_exit(dev);
210572 + if (pt_dev->tx_trans_test) {
210573 + ret = pt_dev->tx_trans_test(pt_dev);
210577 + pt_dev->name, i);
210581 + if (pt_dev->rx_trans_test) {
210582 + ret = pt_dev->rx_trans_test(pt_dev);
210586 + pt_dev->name, i);
210599 + if (dev->dev_clock_enable) {
210600 + dev->dev_clock_enable(dev);
210618 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x820); // dma src address
210628 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x868); // dma dest address
210633 + writel(0x4, dev->ctrlreg_base + 0x10);
210634 + writel(0x1f, dev->ctrlreg_base);
210635 + writel(0x0, dev->ctrlreg_base + 0x14);
210636 + writel(0x2, dev->ctrlreg_base + 0x28);
210637 + writel(0x2, dev->ctrlreg_base + 0x2c);
210638 + writel(0x3, dev->ctrlreg_base + 0x24);
210644 + if (dev->dev_clock_enable) {
210645 + dev->dev_clock_enable(dev);
210658 + int ret = -1;
210667 + val |= ((dev->tx_dma_reqline_val << shift)
210668 + | (dev->rx_dma_reqline_val << (shift + 8)));
210673 + val |= ((dev->rx_dma_reqline_val << shift)
210674 + | (dev->tx_dma_reqline_val << (shift + 8)));
210678 + ret = -1;
210679 + writel(0x0, dev->ctrlreg_base + 0x4);
210687 + writel(0x3, dev->ctrlreg_base + 0x4);
210701 + return -1;
210712 + if (dev->dev_rx_dma_init) {
210713 + dev->dev_rx_dma_init(dev, i);
210718 + dev->dev_dma_exit(dev);
210725 + dev->dev_dma_exit(dev);
210730 + dev->dev_dma_exit(dev);
210904 + regulator->reg_virt = ioremap_nocache(regulator->reg_base, 0x1000);
210905 + val = readl(regulator->reg_virt);
210906 + regulator->curr = (val >> 16) & 0xff;
210908 + regulator->steps[0] = regulator->curr + 74;
210909 + regulator->steps[1] = regulator->curr + 37;
210910 + regulator->steps[2] = regulator->curr;
210911 + if (regulator->curr > 37) {
210912 + regulator->steps[3] = regulator->curr - 37;
210914 + regulator->steps[3] = 0;
210917 + if (regulator->curr > 74) {
210918 + regulator->steps[4] = regulator->curr - 74;
210920 + regulator->steps[4] = 0;
210923 + if (regulator->curr >= regulator->max) {
210924 + regulator->steps[0] = 0xffffffff;
210925 + regulator->steps[1] = 0xffffffff;
210929 + if (regulator->curr <= regulator->min) {
210930 + regulator->steps[3] = 0xffffffff;
210931 + regulator->steps[4] = 0xffffffff;
210935 + if ((regulator->curr + 37) >= regulator->max) {
210936 + regulator->steps[0] = 0xffffffff;
210937 + regulator->steps[1] = regulator->max;
210941 + if ((regulator->curr + 74) >= regulator->max) {
210942 + regulator->steps[0] = regulator->max;
210946 + if ((regulator->curr > 37) &&
210947 + ((regulator->curr - 37) <= regulator->min)) {
210948 + regulator->steps[4] = 0xffffffff;
210949 + regulator->steps[3] = regulator->min;
210952 + if ((regulator->curr > 74) &&
210953 + ((regulator->curr - 74) <= regulator->min)) {
210954 + regulator->steps[4] = regulator->min;
210958 + regulator->max = ((regulator->curr + 74) < regulator->max)
210959 + ? (regulator->curr + 74) : regulator->max;
210960 + regulator->min = ((regulator->curr - 74) > regulator->min)
210961 + ? (regulator->curr - 74) : regulator->min;
210964 + regulator->min, regulator->max);
210966 + pr_debug(" 0x%x ", regulator->steps[i]);
210975 + if (regulator->steps[step] == 0xffffffff) {
210976 + return -1;
210979 + val = readl(regulator->reg_virt);
210981 + val |= regulator->steps[step] << 16;
210983 + writel(val, regulator->reg_virt);
210990 + unsigned int val = readl(regulator->reg_virt);
210992 + val |= regulator->curr << 16;
210994 + writel(val, regulator->reg_virt);
210999 + iounmap(regulator->reg_virt);
211019 + unsigned int pll_reset_counts = PLL_TEST_NR - 1;
211029 + return -EINVAL;
211035 + return -EINVAL;
211042 + return -EINVAL;
211055 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
211060 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
211069 + (PLL_TEST_NR - pll_reset_counts));
211099 + } while (pll_reset_counts--);
211108 + pll_reset_counts = PLL_TEST_NR - 1;
211111 + (PLL_TEST_NR - pll_reset_counts));
211141 + } while (pll_reset_counts--);
211156 + iounmap(pt_dev->ctrlreg_base);
211161 + iounmap(pt_dev->ctrlreg_base);
211180 diff --git a/arch/arm/plat-hi3556av100/Makefile b/arch/arm/plat-hi3556av100/Makefile
211183 --- /dev/null
211184 +++ b/arch/arm/plat-hi3556av100/Makefile
211185 @@ -0,0 +1,7 @@
211186 +# arch/arm/plat-hi3556av100/Makefile
211191 +obj-$(CONFIG_HIEDMACV310) += pll-trainning.o
211193 diff --git a/arch/arm/plat-hi3556av100/pll-trainning.c b/arch/arm/plat-hi3556av100/pll-trainning.c
211196 --- /dev/null
211197 +++ b/arch/arm/plat-hi3556av100/pll-trainning.c
211198 @@ -0,0 +1,1179 @@
211225 +#include <linux/dma-mapping.h>
211439 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
211440 + pmx_reg_virt += pin->pinmx_reg_offset;
211443 + if ((val & 0xf) == pin->pinmx_func_num) {
211444 + pin->restored_val = val;
211447 + pin->pinmx_func_changed = 1;
211449 + pin->pinmx_func_changed = 0;
211458 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
211459 + pin = &pmx_ctrl->pins[i];
211478 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
211479 + pmx_reg_virt += pin->pinmx_reg_offset;
211481 + if (pin->pinmx_func_changed) {
211482 + writel(pin->restored_val, pmx_reg_virt);
211492 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
211493 + pin = &pmx_ctrl->pins[i];
211614 + val |= (1 << dev->clock_gate_bit);
211617 + val |= (1 << dev->reset_bit);
211620 + val &= ~(1 << dev->reset_bit);
211628 + if (dev->dev_clock_enable) {
211629 + dev->dev_clock_enable(dev);
211645 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x820);
211654 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x868);
211659 + writel(0x7ff, dev->ctrlreg_base + 0x44);
211660 + writel(0x1, dev->ctrlreg_base + 0x24);
211661 + writel(0x0, dev->ctrlreg_base + 0x28);
211662 + writel(0x70, dev->ctrlreg_base + 0x2c);
211663 + writel(0x0, dev->ctrlreg_base + 0x34);
211664 + writel(0x40, dev->ctrlreg_base + 0x38);
211665 + writel(0x3, dev->ctrlreg_base + 0x48);
211667 + writel(0x381, dev->ctrlreg_base + 0x30);
211674 + if (dev->dev_clock_enable) {
211675 + dev->dev_clock_enable(dev);
211680 + * return: on -1, dma timeout;
211681 + * on -2, data err;
211692 + int ret = -1;
211701 + val |= ((dev->tx_dma_reqline_val << shift)
211702 + | (dev->rx_dma_reqline_val << (shift + 8)));
211707 + val |= ((dev->rx_dma_reqline_val << shift)
211708 + | (dev->tx_dma_reqline_val << (shift + 8)));
211712 + addr = dev->ctrlreg_base + UART_DR;
211714 + ret = -1;
211736 + return -1;
211747 + if (dev->dev_rx_dma_init) {
211748 + dev->dev_rx_dma_init(dev, i);
211753 + dev->dev_dma_exit(dev);
211760 + dev->dev_dma_exit(dev);
211765 + dev->dev_dma_exit(dev);
211778 + if (pt_dev->tx_trans_test) {
211779 + ret = pt_dev->tx_trans_test(pt_dev);
211783 + pt_dev->name, i);
211787 + if (pt_dev->rx_trans_test) {
211788 + ret = pt_dev->rx_trans_test(pt_dev);
211792 + pt_dev->name, i);
211805 + if (dev->dev_clock_enable) {
211806 + dev->dev_clock_enable(dev);
211824 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x820);
211834 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x868);
211839 + writel(0x4, dev->ctrlreg_base + 0x10);
211840 + writel(0x1f, dev->ctrlreg_base);
211841 + writel(0x0, dev->ctrlreg_base + 0x14);
211842 + writel(0x2, dev->ctrlreg_base + 0x28);
211843 + writel(0x2, dev->ctrlreg_base + 0x2c);
211844 + writel(0x3, dev->ctrlreg_base + 0x24);
211850 + if (dev->dev_clock_enable) {
211851 + dev->dev_clock_enable(dev);
211864 + int ret = -1;
211873 + val |= ((dev->tx_dma_reqline_val << shift)
211874 + | (dev->rx_dma_reqline_val << (shift + 8)));
211879 + val |= ((dev->rx_dma_reqline_val << shift)
211880 + | (dev->tx_dma_reqline_val << (shift + 8)));
211884 + ret = -1;
211885 + writel(0x0, dev->ctrlreg_base + 0x4);
211893 + writel(0x3, dev->ctrlreg_base + 0x4);
211907 + return -1;
211918 + if (dev->dev_rx_dma_init) {
211919 + dev->dev_rx_dma_init(dev, i);
211924 + dev->dev_dma_exit(dev);
211931 + dev->dev_dma_exit(dev);
211936 + dev->dev_dma_exit(dev);
212110 + regulator->reg_virt = ioremap_nocache(regulator->reg_base, 0x1000);
212111 + val = readl(regulator->reg_virt);
212112 + regulator->curr = (val >> 16) & 0xff;
212114 + if (regulator->curr + 37 < regulator->max) {
212115 + regulator->steps[0] = regulator->curr + 37;
212117 + regulator->steps[0] = regulator->max;
212120 + regulator->steps[1] = regulator->curr;
212122 + if (regulator->curr > regulator->min + 37) {
212123 + regulator->steps[2] = regulator->curr - 37;
212125 + regulator->steps[2] = regulator->min;
212128 + if (regulator->curr > regulator->min + 74) {
212129 + regulator->steps[3] = regulator->curr - 74;
212131 + regulator->steps[3] = regulator->min;
212134 + if (regulator->curr > regulator->min + 111) {
212135 + regulator->steps[4] = regulator->curr - 111;
212137 + regulator->steps[4] = regulator->min;
212140 + if (regulator->steps[3] <= regulator->steps[4]) {
212141 + regulator->steps[4] = 0xffffffff;
212144 + if (regulator->steps[2] <= regulator->steps[3]) {
212145 + regulator->steps[3] = 0xffffffff;
212148 + if (regulator->steps[1] <= regulator->steps[2]) {
212149 + regulator->steps[2] = 0xffffffff;
212152 + if (regulator->steps[0] <= regulator->steps[1]) {
212153 + regulator->steps[0] = 0xffffffff;
212156 + regulator->max = ((regulator->curr + 37) < regulator->max)
212157 + ? (regulator->curr + 37) : regulator->max;
212158 + regulator->min = ((regulator->curr - 111) > regulator->min)
212159 + ? (regulator->curr - 111) : regulator->min;
212162 + regulator->min, regulator->max);
212164 + pr_warn(" 0x%x ", regulator->steps[i]);
212173 + if (regulator->steps[step] == 0xffffffff) {
212174 + return -1;
212177 + val = readl(regulator->reg_virt);
212179 + val |= regulator->steps[step] << 16;
212181 + writel(val, regulator->reg_virt);
212188 + unsigned int val = readl(regulator->reg_virt);
212190 + val |= regulator->curr << 16;
212192 + writel(val, regulator->reg_virt);
212197 + iounmap(regulator->reg_virt);
212217 + unsigned int pll_reset_counts = PLL_TEST_NR - 1;
212227 + return -EINVAL;
212233 + return -EINVAL;
212240 + return -EINVAL;
212253 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
212258 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
212267 + (PLL_TEST_NR - pll_reset_counts));
212297 + } while (pll_reset_counts--);
212306 + pll_reset_counts = PLL_TEST_NR - 1;
212309 + (PLL_TEST_NR - pll_reset_counts));
212339 + } while (pll_reset_counts--);
212354 + iounmap(pt_dev->ctrlreg_base);
212359 + iounmap(pt_dev->ctrlreg_base);
212378 diff --git a/arch/arm/plat-hi3568v100/Makefile b/arch/arm/plat-hi3568v100/Makefile
212381 --- /dev/null
212382 +++ b/arch/arm/plat-hi3568v100/Makefile
212383 @@ -0,0 +1,7 @@
212384 +# arch/arm/plat-hi3568v100/Makefile
212389 +obj-$(CONFIG_HIEDMACV310) += pll-trainning.o
212391 diff --git a/arch/arm/plat-hi3568v100/pll-trainning.c b/arch/arm/plat-hi3568v100/pll-trainning.c
212394 --- /dev/null
212395 +++ b/arch/arm/plat-hi3568v100/pll-trainning.c
212396 @@ -0,0 +1,1187 @@
212423 +#include <linux/dma-mapping.h>
212637 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
212638 + pmx_reg_virt += pin->pinmx_reg_offset;
212641 + if ((val & 0xf) == pin->pinmx_func_num) {
212642 + pin->restored_val = val;
212645 + pin->pinmx_func_changed = 1;
212647 + pin->pinmx_func_changed = 0;
212656 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
212657 + pin = &pmx_ctrl->pins[i];
212676 + void *pmx_reg_virt = ioremap_nocache(pin->pinmx_reg_base, 0x1000);
212677 + pmx_reg_virt += pin->pinmx_reg_offset;
212679 + if (pin->pinmx_func_changed) {
212680 + writel(pin->restored_val, pmx_reg_virt);
212690 + for (i = 0; i < pmx_ctrl->pinmux_nr; i++) {
212691 + pin = &pmx_ctrl->pins[i];
212812 + val |= (1 << dev->clock_gate_bit);
212815 + val |= (1 << dev->reset_bit);
212818 + val &= ~(1 << dev->reset_bit);
212826 + if (dev->dev_clock_enable) {
212827 + dev->dev_clock_enable(dev);
212843 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x820);
212852 + writel(dev->ctrlreg_phys, edma0_reg_base + 0x868);
212857 + writel(0x7ff, dev->ctrlreg_base + 0x44);
212858 + writel(0x1, dev->ctrlreg_base + 0x24);
212859 + writel(0x0, dev->ctrlreg_base + 0x28);
212860 + writel(0x70, dev->ctrlreg_base + 0x2c);
212861 + writel(0x0, dev->ctrlreg_base + 0x34);
212862 + writel(0x40, dev->ctrlreg_base + 0x38);
212863 + writel(0x3, dev->ctrlreg_base + 0x48);
212865 + writel(0x381, dev->ctrlreg_base + 0x30);
212872 + if (dev->dev_clock_enable) {
212873 + dev->dev_clock_enable(dev);
212878 + * return: on -1, dma timeout;
212879 + * on -2, data err;
212890 + int ret = -1;
212899 + val |= ((dev->tx_dma_reqline_val << shift)
212900 + | (dev->rx_dma_reqline_val << (shift + 8)));
212905 + val |= ((dev->rx_dma_reqline_val << shift)
212906 + | (dev->tx_dma_reqline_val << (shift + 8)));
212910 + addr = dev->ctrlreg_base + UART_DR;
212912 + ret = -1;
212934 + return -1;
212945 + if (dev->dev_rx_dma_init) {
212946 + dev->dev_rx_dma_init(dev, i);
212951 + dev->dev_dma_exit(dev);
212958 + dev->dev_dma_exit(dev);
212963 + dev->dev_dma_exit(dev);
212976 + if (pt_dev->tx_trans_test) {
212977 + ret = pt_dev->tx_trans_test(pt_dev);
212981 + pt_dev->name, i);
212985 + if (pt_dev->rx_trans_test) {
212986 + ret = pt_dev->rx_trans_test(pt_dev);
212990 + pt_dev->name, i);
213003 + if (dev->dev_clock_enable) {
213004 + dev->dev_clock_enable(dev);
213022 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x820);
213032 + writel(dev->ctrlreg_phys + 0x8, edma0_reg_base + 0x868);
213037 + writel(0x4, dev->ctrlreg_base + 0x10);
213038 + writel(0x1f, dev->ctrlreg_base);
213039 + writel(0x0, dev->ctrlreg_base + 0x14);
213040 + writel(0x2, dev->ctrlreg_base + 0x28);
213041 + writel(0x2, dev->ctrlreg_base + 0x2c);
213042 + writel(0x3, dev->ctrlreg_base + 0x24);
213048 + if (dev->dev_clock_enable) {
213049 + dev->dev_clock_enable(dev);
213062 + int ret = -1;
213071 + val |= ((dev->tx_dma_reqline_val << shift)
213072 + | (dev->rx_dma_reqline_val << (shift + 8)));
213077 + val |= ((dev->rx_dma_reqline_val << shift)
213078 + | (dev->tx_dma_reqline_val << (shift + 8)));
213082 + ret = -1;
213083 + writel(0x0, dev->ctrlreg_base + 0x4);
213091 + writel(0x3, dev->ctrlreg_base + 0x4);
213105 + return -1;
213116 + if (dev->dev_rx_dma_init) {
213117 + dev->dev_rx_dma_init(dev, i);
213122 + dev->dev_dma_exit(dev);
213129 + dev->dev_dma_exit(dev);
213134 + dev->dev_dma_exit(dev);
213308 + regulator->reg_virt = ioremap_nocache(regulator->reg_base, 0x1000);
213309 + val = readl(regulator->reg_virt);
213310 + regulator->curr = (val >> 16) & 0xff;
213312 + regulator->steps[0] = regulator->curr + 74;
213313 + regulator->steps[1] = regulator->curr + 37;
213314 + regulator->steps[2] = regulator->curr;
213315 + if (regulator->curr > 37) {
213316 + regulator->steps[3] = regulator->curr - 37;
213318 + regulator->steps[3] = 0;
213321 + if (regulator->curr > 74) {
213322 + regulator->steps[4] = regulator->curr - 74;
213324 + regulator->steps[4] = 0;
213327 + if (regulator->curr >= regulator->max) {
213328 + regulator->steps[0] = 0xffffffff;
213329 + regulator->steps[1] = 0xffffffff;
213333 + if (regulator->curr <= regulator->min) {
213334 + regulator->steps[3] = 0xffffffff;
213335 + regulator->steps[4] = 0xffffffff;
213339 + if ((regulator->curr + 37) >= regulator->max) {
213340 + regulator->steps[0] = 0xffffffff;
213341 + regulator->steps[1] = regulator->max;
213345 + if ((regulator->curr + 74) >= regulator->max) {
213346 + regulator->steps[0] = regulator->max;
213350 + if ((regulator->curr > 37) &&
213351 + ((regulator->curr - 37) <= regulator->min)) {
213352 + regulator->steps[4] = 0xffffffff;
213353 + regulator->steps[3] = regulator->min;
213356 + if ((regulator->curr > 74) &&
213357 + ((regulator->curr - 74) <= regulator->min)) {
213358 + regulator->steps[4] = regulator->min;
213362 + regulator->max = ((regulator->curr + 74) < regulator->max)
213363 + ? (regulator->curr + 74) : regulator->max;
213364 + regulator->min = ((regulator->curr - 74) > regulator->min)
213365 + ? (regulator->curr - 74) : regulator->min;
213368 + regulator->min, regulator->max);
213370 + pr_debug(" 0x%x ", regulator->steps[i]);
213379 + if (regulator->steps[step] == 0xffffffff) {
213380 + return -1;
213383 + val = readl(regulator->reg_virt);
213385 + val |= regulator->steps[step] << 16;
213387 + writel(val, regulator->reg_virt);
213394 + unsigned int val = readl(regulator->reg_virt);
213396 + val |= regulator->curr << 16;
213398 + writel(val, regulator->reg_virt);
213403 + iounmap(regulator->reg_virt);
213423 + unsigned int pll_reset_counts = PLL_TEST_NR - 1;
213433 + return -EINVAL;
213439 + return -EINVAL;
213446 + return -EINVAL;
213459 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
213464 + pt_dev->ctrlreg_base = ioremap_nocache(pt_dev->ctrlreg_phys, 0x1000);
213473 + (PLL_TEST_NR - pll_reset_counts));
213503 + } while (pll_reset_counts--);
213512 + pll_reset_counts = PLL_TEST_NR - 1;
213515 + (PLL_TEST_NR - pll_reset_counts));
213545 + } while (pll_reset_counts--);
213560 + iounmap(pt_dev->ctrlreg_base);
213565 + iounmap(pt_dev->ctrlreg_base);
213584 diff --git a/arch/arm/vdso/vgettimeofday.c b/arch/arm/vdso/vgettimeofday.c
213588 --- a/arch/arm/vdso/vgettimeofday.c
213590 @@ -115,7 +115,7 @@ static notrace int do_monotonic_coarse(struct timespec *ts,
213594 -#ifdef CONFIG_ARM_ARCH_TIMER
213599 diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
213601 --- a/arch/arm64/Makefile
213603 @@ -12,6 +12,7 @@
213605 LDFLAGS_vmlinux :=--no-undefined -X -z norelro
213606 CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET)
213607 +OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
213608 GZFLAGS :=-9
213611 diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile
213613 --- a/arch/arm64/boot/Makefile
213615 @@ -18,12 +18,28 @@ OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
213621 +dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(foreach d,$(dts-dirs), $(wildcar…
213627 +DTB_LIST := $(dtb-y)
213638 +$(obj)/Image-dtb: $(obj)/Image $(DTB_OBJS) FORCE
213644 @@ -36,10 +52,35 @@ $(obj)/Image.lzma: $(obj)/Image FORCE
213648 -install:
213649 +$(obj)/Image.gz-dtb: $(obj)/Image.gz $(DTB_OBJS) FORCE
213656 +if [ $(words $(UIMAGE_LOADADDR)) -ne 1 ]; then \
213664 + @rm -f $(obj)/uImage
213678 -zinstall:
213682 diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
213684 --- a/arch/arm64/boot/dts/Makefile
213686 @@ -26,3 +26,7 @@ subdir-y += synaptics
213687 subdir-y += ti
213688 subdir-y += xilinx
213689 subdir-y += zte
213693 +clean-files := dts/*.dtb *.dtb
213694 diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
213696 --- a/arch/arm64/boot/dts/hisilicon/Makefile
213698 @@ -5,3 +5,11 @@ dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
213699 dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
213700 dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
213701 dtb-$(CONFIG_ARCH_HISI) += hip07-d05.dtb
213702 +dtb-$(CONFIG_ARCH_HI3531DV200) += hi3531dv200-demb.dtb
213703 +dtb-$(CONFIG_ARCH_HI3535AV100) += hi3535av100-demb.dtb
213704 +dtb-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-demb-flash.dtb
213705 +dtb-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-demb-emmc.dtb
213706 +dtb-$(CONFIG_ARCH_HI3559AV100) += hi3559av100-demb-ufs.dtb
213707 +dtb-$(CONFIG_ARCH_HI3569V100) += hi3569v100-demb-flash.dtb
213708 +dtb-$(CONFIG_ARCH_HI3569V100) += hi3569v100-demb-emmc.dtb
213709 +dtb-$(CONFIG_ARCH_HI3569V100) += hi3569v100-demb-ufs.dtb
213710 diff --git a/arch/arm64/boot/dts/hisilicon/hi3531dv200-demb.dts b/arch/arm64/boot/dts/hisilicon/hi3…
213713 --- /dev/null
213714 +++ b/arch/arm64/boot/dts/hisilicon/hi3531dv200-demb.dts
213715 @@ -0,0 +1,338 @@
213733 +/dts-v1/;
213788 + linux,initrd-start = <0x60000040>;
213789 + linux,initrd-end = <0x61000000>;
213793 + #address-cells = <2>;
213794 + #size-cells = <0>;
213797 + compatible = "arm,cortex-a53";
213800 + enable-method = "psci";
213801 + //clock-latency = <100000>; /* From legacy driver */
213805 + compatible = "arm,cortex-a53";
213808 + enable-method = "psci";
213809 + //clock-latency = <200000>; /* From legacy driver */
213813 + compatible = "arm,cortex-a53";
213816 + enable-method = "psci";
213820 + compatible = "arm,cortex-a53";
213823 + enable-method = "psci";
213868 + pl022,com-mode = <0>;
213869 + spi-max-frequency = <25000000>;
213876 + pl022,com-mode = <0>;
213877 + spi-max-frequency = <25000000>;
213884 + pl022,com-mode = <0>;
213885 + spi-max-frequency = <25000000>;
213892 + pl022,com-mode = <0>;
213893 + spi-max-frequency = <25000000>;
214007 + compatible = "jedec,spi-nor";
214009 + spi-max-frequency = <160000000>;
214010 + m25p,fast-read;
214016 + compatible = "jedec,spi-nand";
214018 + spi-max-frequency = <160000000>;
214023 + ethphy: ethernet-phy@1 {
214028 + ethphy1: ethernet-phy@3 {
214034 + phy-handle = <ðphy>;
214035 + phy-mode = "rgmii";
214039 + phy-handle = <ðphy1>;
214040 + phy-mode = "rgmii";
214054 diff --git a/arch/arm64/boot/dts/hisilicon/hi3531dv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3531d…
214057 --- /dev/null
214059 @@ -0,0 +1,918 @@
214079 +#include <dt-bindings/clock/hi3531dv200-clock.h>
214080 +#include <dt-bindings/interrupt-controller/irq.h>
214081 +#include <dt-bindings/interrupt-controller/arm-gic.h>
214083 + #address-cells = <2>;
214084 + #size-cells = <2>;
214086 + interrupt-parent = <&gic>;
214088 + gic: interrupt-controller@12400000 {
214089 + compatible = "arm,gic-v3";
214090 + #interrupt-cells = <3>;
214091 + #address-cells = <0>;
214092 + interrupt-controller;
214098 + compatible = "arm,psci-0.2";
214103 + compatible = "arm,armv8-pmuv3";
214108 + compatible = "hisilicon,hi3531dv200-clock", "syscon";
214109 + #clock-cells = <1>;
214110 + #reset-cells = <2>;
214111 + #address-cells = <1>;
214112 + #size-cells = <1>;
214117 + #address-cells = <1>;
214118 + #size-cells = <1>;
214119 + compatible = "simple-bus";
214121 + //interrupt-parent = <&gic>;
214125 + compatible = "fixed-clock";
214126 + #clock-cells = <0>;
214127 + clock-frequency = <3000000>;
214131 + compatible = "arm,amba-bus";
214132 + #address-cells = <1>;
214133 + #size-cells = <1>;
214136 + arm-timer {
214137 + compatible = "arm,armv8-timer";
214140 + clock-frequency = <24000000>;
214141 + always-on;
214149 + clock-names = "apb_pclk";
214158 + clock-names = "apb_pclk";
214160 + //dma-names = "tx","rx";
214169 + clock-names = "apb_pclk";
214171 + //dma-names = "tx","rx";
214180 + clock-names = "apb_pclk";
214182 + //dma-names = "tx","rx";
214191 + clock-names = "apb_pclk";
214193 + //dma-names = "tx","rx";
214198 + compatible = "hisilicon,hibvt-i2c";
214203 + dma-names = "tx","rx";
214205 + clock-frequency = <100000>;
214210 + compatible = "hisilicon,hibvt-i2c";
214215 + dma-names = "tx","rx";
214217 + clock-frequency = <100000>;
214223 + arm,primecell-periphid = <0x00800022>;
214227 + clock-names = "apb_pclk";
214228 + #address-cells = <1>;
214229 + #size-cells = <0>;
214230 + num-cs = <4>;
214234 + dma-names = "tx","rx";*/
214242 + #gpio-cells = <2>;
214244 + clock-names = "apb_pclk";
214252 + #gpio-cells = <2>;
214254 + clock-names = "apb_pclk";
214262 + #gpio-cells = <2>;
214264 + clock-names = "apb_pclk";
214272 + #gpio-cells = <2>;
214274 + clock-names = "apb_pclk";
214282 + #gpio-cells = <2>;
214284 + clock-names = "apb_pclk";
214292 + #gpio-cells = <2>;
214294 + clock-names = "apb_pclk";
214302 + #gpio-cells = <2>;
214304 + clock-names = "apb_pclk";
214312 + #gpio-cells = <2>;
214314 + clock-names = "apb_pclk";
214322 + #gpio-cells = <2>;
214324 + clock-names = "apb_pclk";
214332 + #gpio-cells = <2>;
214334 + clock-names = "apb_pclk";
214342 + #gpio-cells = <2>;
214344 + clock-names = "apb_pclk";
214352 + #gpio-cells = <2>;
214354 + clock-names = "apb_pclk";
214362 + #gpio-cells = <2>;
214364 + clock-names = "apb_pclk";
214372 + #gpio-cells = <2>;
214374 + clock-names = "apb_pclk";
214382 + #gpio-cells = <2>;
214384 + clock-names = "apb_pclk";
214392 + #gpio-cells = <2>;
214394 + clock-names = "apb_pclk";
214402 + #gpio-cells = <2>;
214404 + clock-names = "apb_pclk";
214412 + #gpio-cells = <2>;
214414 + clock-names = "apb_pclk";
214422 + #gpio-cells = <2>;
214424 + clock-names = "apb_pclk";
214432 + #gpio-cells = <2>;
214434 + clock-names = "apb_pclk";
214442 + #gpio-cells = <2>;
214444 + clock-names = "apb_pclk";
214452 + #gpio-cells = <2>;
214454 + clock-names = "apb_pclk";
214462 + #gpio-cells = <2>;
214464 + clock-names = "apb_pclk";
214472 + #gpio-cells = <2>;
214474 + clock-names = "apb_pclk";
214482 + #gpio-cells = <2>;
214484 + clock-names = "apb_pclk";
214492 + #gpio-cells = <2>;
214494 + clock-names = "apb_pclk";
214499 + compatible = "hisilicon,hi35xx-rtc";
214507 + misc_ctrl: misc-controller@11024000 {
214508 + compatible = "hisilicon,hisi-miscctrl", "syscon";
214513 + compatible = "hisilicon,hisi-ioconfig", "syscon";
214518 + fmc: flash-memory-controller@10000000 {
214519 + compatible = "hisilicon,hisi-fmc";
214521 + reg-names = "control", "memory";
214523 + max-dma-size = <0x2000>;
214524 + #address-cells = <1>;
214525 + #size-cells = <0>;
214528 + compatible = "hisilicon,fmc-spi-nor";
214529 + assigned-clocks = <&clock HI3531DV200_FMC_CLK>;
214530 + assigned-clock-rates = <24000000>;
214531 + #address-cells = <1>;
214532 + #size-cells = <0>;
214536 + compatible = "hisilicon,fmc-spi-nand";
214537 + assigned-clocks = <&clock HI3531DV200_FMC_CLK>;
214538 + assigned-clock-rates = <24000000>;
214539 + #address-cells = <1>;
214540 + #size-cells = <0>;
214546 + compatible = "hisilicon,hisi-gemac-mdio";
214550 + reset-names = "phy_reset";
214552 + #address-cells = <1>;
214553 + #size-cells = <0>;
214557 + compatible = "hisilicon,hisi-gemac-mdio";
214561 + reset-names = "phy_reset";
214563 + #address-cells = <1>;
214564 + #size-cells = <0>;
214568 + compatible = "hisilicon,higmac-v5";
214577 + clock-names = "higmac_clk",
214582 + reset-names = "port_reset",
214585 + mac-address = [00 00 00 00 00 00];
214589 + compatible = "hisilicon,higmac-v5";
214598 + clock-names = "higmac_clk",
214603 + reset-names = "port_reset",
214606 + mac-address = [00 00 00 00 00 00];
214610 + compatible = "hisilicon,hisi-usb-phy";
214615 + compatible = "generic-xhci";
214618 + usb2-lpm-disable;
214622 + compatible = "generic-xhci";
214625 + usb2-lpm-disable;
214634 + clock-names = "mmc_clk";
214636 + reset-names = "crg_reset", "dll_reset";
214637 + max-frequency = <148500000>;
214640 + non-removable;
214641 + bus-width = <8>;
214642 + cap-mmc-highspeed;
214643 + mmc-hs200-1_8v;
214644 + mmc-hs400-1_8v;
214645 + mmc-hs400-enhanced-strobe;
214646 + cap-mmc-hw-reset;
214647 + mmc-cmd-queue;
214648 + no-sdio;
214649 + no-sd;
214659 + clock-names = "mmc_clk";
214661 + reset-names = "crg_reset", "dll_reset";
214662 + max-frequency = <196500000>;
214665 + bus-width = <4>;
214666 + cap-sd-highspeed;
214667 + sd-uhs-sdr104;
214668 + non-removable;
214675 + compatible = "hisilicon,hisi-pcie";
214676 + #size-cells = <2>;
214677 + #address-cells = <3>;
214678 + #interrupt-cells = <1>;
214679 + bus-range = <0x0 0xff>;
214682 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
214683 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH
214689 + interrupt-names = "msi";
214703 + compatible = "hisilicon,hisi-pcie";
214704 + #size-cells = <2>;
214705 + #address-cells = <3>;
214706 + #interrupt-cells = <1>;
214707 + bus-range = <0x0 0xff>;
214710 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
214711 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH
214718 + interrupt-names = "msi";
214746 + compatible = "hisilicon,hisi-sata-phy";
214749 + #phy-cells = <0>;
214753 + compatible = "hisilicon,hisi-ahci";
214757 + phy-names = "sata-phy";
214758 + #address-cells = <1>;
214759 + #size-cells = <0>;
214762 + hiedmacv310_0: hiedma-controller@10280000 {
214767 + clock-names = "apb_pclk", "axi_aclk";
214768 + #clock-cells = <2>;
214770 + reset-names = "dma-reset";
214771 + dma-requests = <32>;
214772 + dma-channels = <8>;
214774 + #dma-cells = <2>;
214779 + hiedmacv310_0: hiedma-controller@10280000 {
214784 + clock-names = "apb_pclk", "axi_aclk";
214785 + #clock-cells = <2>;
214787 + reset-names = "dma-reset";
214788 + dma-requests = <32>;
214789 + dma-channels = <8>;
214791 + #dma-cells = <2>;
214797 + compatible = "hisilicon,hisi-sys";
214802 + reg-names = "crg", "sys", "ddr", "misc";
214806 + compatible = "hisilicon,hisi-vi";
214809 + reg-names = "VI_CAP", "vi_timer";
214813 + interrupt-names = "VI_CAP", "vi_timer";
214817 + compatible = "hisilicon,hisi-mipi";
214819 + reg-names = "mipi_rx_phy", "mipi_rx_chn";
214821 + interrupt-names = "mipi_rx";
214825 + compatible = "hisilicon,hisi-vpss";
214827 + reg-names = "vpss0", "vpss1", "vpss2";
214831 + interrupt-names = "vpss0", "vpss1", "vpss2";
214835 + compatible = "hisilicon,hisi-vgs";
214837 + reg-names = "vgs0";
214839 + interrupt-names = "vgs0";
214843 + compatible = "hisilicon,hisi-vo";
214845 + reg-names = "vo";
214847 + interrupt-names = "vo";
214851 + compatible = "hisilicon,hisi-hifb";
214852 + reg-names = "hifb";
214854 + interrupt-names = "hifb";
214858 + compatible = "hisilicon,hisi-hdmi";
214860 + reg-names = "hdmi0","phy";
214864 + interrupt-names = "tx_aon","tx_pwd","tx_sec";
214868 + compatible = "hisilicon,hisi-vedu";
214870 + reg-names = "vedu0", "vedu1","vedu2","jpge";
214875 + interrupt-names = "vedu0","vedu1","vedu2","jpge";
214879 + compatible = "hisilicon,hisi-vdh";
214881 + reg-names = "vdh_scd";
214885 + interrupt-names = "vdh_bsp","vdh_pxp","scd";
214889 + compatible = "hisilicon,hisi-jpegd";
214891 + reg-names = "jpegd";
214893 + interrupt-names = "jpegd";
214896 + compatible = "hisilicon,hisi-vda";
214898 + reg-names = "vda";
214900 + interrupt-names = "vda";
214903 + compatible = "hisilicon,hisi-nnie";
214905 + reg-names = "nnie0";
214907 + interrupt-names = "nnie0";
214911 + compatible = "hisilicon,hisi-ive";
214913 + reg-names = "ive";
214915 + interrupt-names = "ive";
214919 + compatible = "hisilicon,hisi-mau";
214921 + reg-names = "mau0";
214923 + interrupt-names = "mau0";
214927 + compatible = "hisilicon,hisi-aiao";
214929 + reg-names = "acodec","aiao";
214932 + interrupt-names = "AIO","VOIE";
214936 + compatible = "hisilicon,hisi-tde";
214938 + reg-names = "tde";
214940 + interrupt-names = "tde_osr_isr";
214944 + compatible = "hisilicon,hisi-cipher";
214946 + reg-names = "cipher";
214951 + interrupt-names = "cipher","hash","nonsec_cipher","nonsec_hash";
214955 + compatible = "hisilicon,hisi-otp";
214957 + reg-names = "otp";
214961 + compatible = "hisilicon,hi-ir";
214963 + reg-names = "hi-ir";
214965 + interrupt-names = "hi-ir";
214969 + compatible = "hisilicon,hi-wdg";
214971 + reg-names = "hi-wdg0";
214973 + interrupt-names = "hi-wdg";
214978 diff --git a/arch/arm64/boot/dts/hisilicon/hi3535av100-demb.dts b/arch/arm64/boot/dts/hisilicon/hi3…
214981 --- /dev/null
214982 +++ b/arch/arm64/boot/dts/hisilicon/hi3535av100-demb.dts
214983 @@ -0,0 +1,334 @@
215001 +/dts-v1/;
215056 + linux,initrd-start = <0x60000040>;
215057 + linux,initrd-end = <0x61000000>;
215061 + #address-cells = <2>;
215062 + #size-cells = <0>;
215065 + compatible = "arm,cortex-a53";
215068 + enable-method = "psci";
215069 + //clock-latency = <100000>; /* From legacy driver */
215073 + compatible = "arm,cortex-a53";
215076 + enable-method = "psci";
215077 + //clock-latency = <200000>; /* From legacy driver */
215081 + compatible = "arm,cortex-a53";
215084 + enable-method = "psci";
215088 + compatible = "arm,cortex-a53";
215091 + enable-method = "psci";
215136 + pl022,com-mode = <0>;
215137 + spi-max-frequency = <25000000>;
215144 + pl022,com-mode = <0>;
215145 + spi-max-frequency = <25000000>;
215152 + pl022,com-mode = <0>;
215153 + spi-max-frequency = <25000000>;
215160 + pl022,com-mode = <0>;
215161 + spi-max-frequency = <25000000>;
215275 + compatible = "jedec,spi-nor";
215277 + spi-max-frequency = <160000000>;
215278 + m25p,fast-read;
215284 + compatible = "jedec,spi-nand";
215286 + spi-max-frequency = <160000000>;
215291 + ethphy: ethernet-phy@1 {
215296 + ethphy1: ethernet-phy@3 {
215302 + phy-handle = <ðphy>;
215303 + phy-mode = "rgmii";
215307 + phy-handle = <ðphy1>;
215308 + phy-mode = "rgmii";
215318 diff --git a/arch/arm64/boot/dts/hisilicon/hi3535av100.dtsi b/arch/arm64/boot/dts/hisilicon/hi3535a…
215321 --- /dev/null
215323 @@ -0,0 +1,856 @@
215342 +#include <dt-bindings/clock/hi3535av100-clock.h>
215343 +#include <dt-bindings/interrupt-controller/irq.h>
215344 +#include <dt-bindings/interrupt-controller/arm-gic.h>
215346 + #address-cells = <2>;
215347 + #size-cells = <2>;
215349 + interrupt-parent = <&gic>;
215351 + gic: interrupt-controller@12400000 {
215352 + compatible = "arm,gic-v3";
215353 + #interrupt-cells = <3>;
215354 + #address-cells = <0>;
215355 + interrupt-controller;
215361 + compatible = "arm,psci-0.2";
215366 + compatible = "arm,armv8-pmuv3";
215371 + compatible = "hisilicon,hi3535av100-clock", "syscon";
215372 + #clock-cells = <1>;
215373 + #reset-cells = <2>;
215374 + #address-cells = <1>;
215375 + #size-cells = <1>;
215380 + #address-cells = <1>;
215381 + #size-cells = <1>;
215382 + compatible = "simple-bus";
215384 + //interrupt-parent = <&gic>;
215388 + compatible = "fixed-clock";
215389 + #clock-cells = <0>;
215390 + clock-frequency = <3000000>;
215394 + compatible = "arm,amba-bus";
215395 + #address-cells = <1>;
215396 + #size-cells = <1>;
215399 + arm-timer {
215400 + compatible = "arm,armv8-timer";
215403 + clock-frequency = <24000000>;
215404 + always-on;
215412 + clock-names = "apb_pclk";
215421 + clock-names = "apb_pclk";
215423 + //dma-names = "tx","rx";
215432 + clock-names = "apb_pclk";
215434 + //dma-names = "tx","rx";
215443 + clock-names = "apb_pclk";
215445 + //dma-names = "tx","rx";
215454 + clock-names = "apb_pclk";
215456 + //dma-names = "tx","rx";
215461 + compatible = "hisilicon,hibvt-i2c";
215464 + clock-frequency = <100000>;
215469 + compatible = "hisilicon,hibvt-i2c";
215472 + clock-frequency = <100000>;
215478 + arm,primecell-periphid = <0x00800022>;
215482 + clock-names = "apb_pclk";
215483 + #address-cells = <1>;
215484 + #size-cells = <0>;
215485 + num-cs = <4>;
215489 + dma-names = "tx","rx";*/
215497 + #gpio-cells = <2>;
215499 + clock-names = "apb_pclk";
215507 + #gpio-cells = <2>;
215509 + clock-names = "apb_pclk";
215517 + #gpio-cells = <2>;
215519 + clock-names = "apb_pclk";
215527 + #gpio-cells = <2>;
215529 + clock-names = "apb_pclk";
215537 + #gpio-cells = <2>;
215539 + clock-names = "apb_pclk";
215547 + #gpio-cells = <2>;
215549 + clock-names = "apb_pclk";
215557 + #gpio-cells = <2>;
215559 + clock-names = "apb_pclk";
215567 + #gpio-cells = <2>;
215569 + clock-names = "apb_pclk";
215577 + #gpio-cells = <2>;
215579 + clock-names = "apb_pclk";
215587 + #gpio-cells = <2>;
215589 + clock-names = "apb_pclk";
215597 + #gpio-cells = <2>;
215599 + clock-names = "apb_pclk";
215607 + #gpio-cells = <2>;
215609 + clock-names = "apb_pclk";
215617 + #gpio-cells = <2>;
215619 + clock-names = "apb_pclk";
215627 + #gpio-cells = <2>;
215629 + clock-names = "apb_pclk";
215637 + #gpio-cells = <2>;
215639 + clock-names = "apb_pclk";
215647 + #gpio-cells = <2>;
215649 + clock-names = "apb_pclk";
215657 + #gpio-cells = <2>;
215659 + clock-names = "apb_pclk";
215667 + #gpio-cells = <2>;
215669 + clock-names = "apb_pclk";
215677 + #gpio-cells = <2>;
215679 + clock-names = "apb_pclk";
215687 + #gpio-cells = <2>;
215689 + clock-names = "apb_pclk";
215697 + #gpio-cells = <2>;
215699 + clock-names = "apb_pclk";
215707 + #gpio-cells = <2>;
215709 + clock-names = "apb_pclk";
215717 + #gpio-cells = <2>;
215719 + clock-names = "apb_pclk";
215727 + #gpio-cells = <2>;
215729 + clock-names = "apb_pclk";
215737 + #gpio-cells = <2>;
215739 + clock-names = "apb_pclk";
215747 + #gpio-cells = <2>;
215749 + clock-names = "apb_pclk";
215754 + compatible = "hisilicon,hi35xx-rtc";
215762 + misc_ctrl: misc-controller@11024000 {
215763 + compatible = "hisilicon,hisi-miscctrl", "syscon";
215768 + compatible = "hisilicon,hisi-ioconfig", "syscon";
215773 + fmc: flash-memory-controller@10000000 {
215774 + compatible = "hisilicon,hisi-fmc";
215776 + reg-names = "control", "memory";
215778 + max-dma-size = <0x2000>;
215779 + #address-cells = <1>;
215780 + #size-cells = <0>;
215783 + compatible = "hisilicon,fmc-spi-nor";
215784 + assigned-clocks = <&clock HI3535AV100_FMC_CLK>;
215785 + assigned-clock-rates = <24000000>;
215786 + #address-cells = <1>;
215787 + #size-cells = <0>;
215791 + compatible = "hisilicon,fmc-spi-nand";
215792 + assigned-clocks = <&clock HI3535AV100_FMC_CLK>;
215793 + assigned-clock-rates = <24000000>;
215794 + #address-cells = <1>;
215795 + #size-cells = <0>;
215801 + compatible = "hisilicon,hisi-gemac-mdio";
215805 + reset-names = "phy_reset";
215807 + #address-cells = <1>;
215808 + #size-cells = <0>;
215812 + compatible = "hisilicon,hisi-gemac-mdio";
215816 + reset-names = "phy_reset";
215818 + #address-cells = <1>;
215819 + #size-cells = <0>;
215823 + compatible = "hisilicon,higmac-v5";
215832 + clock-names = "higmac_clk",
215837 + reset-names = "port_reset",
215840 + mac-address = [00 00 00 00 00 00];
215844 + compatible = "hisilicon,higmac-v5";
215853 + clock-names = "higmac_clk",
215858 + reset-names = "port_reset",
215861 + mac-address = [00 00 00 00 00 00];
215865 + compatible = "hisilicon,hisi-usb-phy";
215870 + compatible = "generic-xhci";
215873 + usb2-lpm-disable;
215877 + compatible = "generic-xhci";
215880 + usb2-lpm-disable;
215889 + clock-names = "mmc_clk";
215891 + reset-names = "crg_reset", "dll_reset";
215892 + max-frequency = <148500000>;
215895 + non-removable;
215896 + bus-width = <8>;
215897 + cap-mmc-highspeed;
215898 + mmc-hs200-1_8v;
215899 + mmc-hs400-1_8v;
215900 + mmc-hs400-enhanced-strobe;
215901 + cap-mmc-hw-reset;
215902 + mmc-cmd-queue;
215903 + no-sdio;
215904 + no-sd;
215914 + clock-names = "mmc_clk";
215916 + reset-names = "crg_reset", "dll_reset";
215917 + max-frequency = <196500000>;
215920 + bus-width = <4>;
215921 + cap-sd-highspeed;
215922 + sd-uhs-sdr104;
215923 + non-removable;
215930 + compatible = "hisilicon,hisi-pcie";
215931 + #size-cells = <2>;
215932 + #address-cells = <3>;
215933 + #interrupt-cells = <1>;
215934 + bus-range = <0x0 0xff>;
215937 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
215938 + interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH
215944 + interrupt-names = "msi";
215968 + compatible = "hisilicon,hisi-sata-phy";
215971 + #phy-cells = <0>;
215975 + compatible = "hisilicon,hisi-ahci";
215979 + phy-names = "sata-phy";
215980 + #address-cells = <1>;
215981 + #size-cells = <0>;
215984 + hiedmacv310_0: hiedma-controller@10280000 {
215989 + clock-names = "apb_pclk", "axi_aclk";
215990 + #clock-cells = <2>;
215992 + reset-names = "dma-reset";
215993 + dma-requests = <32>;
215994 + dma-channels = <8>;
215996 + #dma-cells = <2>;
216002 + compatible = "hisilicon,hisi-sys";
216007 + reg-names = "crg", "sys", "ddr", "misc";
216011 + compatible = "hisilicon,hisi-vi";
216014 + reg-names = "VI_CAP", "vi_timer";
216018 + interrupt-names = "VI_CAP", "vi_timer";
216022 + compatible = "hisilicon,hisi-mipi";
216024 + reg-names = "mipi_rx_phy", "mipi_rx_sys", "mipi_rx_chn";
216026 + interrupt-names = "mipi_rx";
216030 + compatible = "hisilicon,hisi-vpss";
216032 + reg-names = "vpss0", "vpss1";
216035 + interrupt-names = "vpss0", "vpss1";
216039 + compatible = "hisilicon,hisi-vgs";
216041 + reg-names = "vgs0";
216043 + interrupt-names = "vgs0";
216047 + compatible = "hisilicon,hisi-vo";
216049 + reg-names = "vo";
216051 + interrupt-names = "vo";
216055 + compatible = "hisilicon,hisi-hifb";
216056 + reg-names = "hifb";
216058 + interrupt-names = "hifb";
216062 + compatible = "hisilicon,hisi-hdmi";
216064 + reg-names = "hdmi0","phy";
216068 + interrupt-names = "tx_aon","tx_pwd","tx_sec";
216072 + compatible = "hisilicon,hisi-vedu";
216074 + reg-names = "vedu0", "jpge";
216077 + interrupt-names = "vedu0","jpge";
216081 + compatible = "hisilicon,hisi-vdh";
216083 + reg-names = "vdh_scd";
216087 + interrupt-names = "vdh_bsp","vdh_pxp","scd";
216091 + compatible = "hisilicon,hisi-jpegd";
216093 + reg-names = "jpegd";
216095 + interrupt-names = "jpegd";
216098 + compatible = "hisilicon,hisi-vda";
216100 + reg-names = "vda";
216102 + interrupt-names = "vda";
216105 + compatible = "hisilicon,hisi-nnie";
216107 + reg-names = "nnie0";
216109 + interrupt-names = "nnie0";
216113 + compatible = "hisilicon,hisi-ive";
216115 + reg-names = "ive";
216117 + interrupt-names = "ive";
216121 + compatible = "hisilicon,hisi-mau";
216123 + reg-names = "mau0";
216125 + interrupt-names = "mau0";
216129 + compatible = "hisilicon,hisi-aiao";
216131 + reg-names = "acodec","aiao";
216134 + interrupt-names = "AIO","VOIE";
216138 + compatible = "hisilicon,hisi-tde";
216140 + reg-names = "tde";
216142 + interrupt-names = "tde_osr_isr";
216146 + compatible = "hisilicon,hisi-cipher";
216148 + reg-names = "cipher";
216153 + interrupt-names = "cipher","hash","nonsec_cipher","nonsec_hash";
216157 + compatible = "hisilicon,hisi-otp";
216159 + reg-names = "otp";
216163 + compatible = "hisilicon,hi-ir";
216165 + reg-names = "hi-ir";
216167 + interrupt-names = "hi-ir";
216171 + compatible = "hisilicon,hi-wdg";
216173 + reg-names = "hi-wdg0";
216175 + interrupt-names = "hi-wdg";
216180 diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-amp.dts b/arch/arm64/boot/dts/hisilicon…
216183 --- /dev/null
216184 +++ b/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-amp.dts
216185 @@ -0,0 +1,596 @@
216203 +/dts-v1/;
216280 + linux,initrd-start = <0x60000040>;
216281 + linux,initrd-end = <0x61000000>;
216285 + #address-cells = <2>;
216286 + #size-cells = <0>;
216289 + compatible = "arm,cortex-a53";
216292 + enable-method = "psci";
216293 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
216297 + compatible = "arm,cortex-a53";
216300 + enable-method = "psci";
216301 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
216304 + compatible = "arm,cortex-a73";
216307 + enable-method = "psci";
216308 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
216311 + compatible = "arm,cortex-a73";
216314 + enable-method = "psci";
216315 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
216457 + pl022,com-mode = <0>;
216458 + spi-max-frequency = <24750000>;
216465 + pl022,com-mode = <0>;
216466 + spi-max-frequency = <24750000>;
216477 + pl022,com-mode = <0>;
216478 + spi-max-frequency = <24750000>;
216485 + pl022,com-mode = <0>;
216486 + spi-max-frequency = <24750000>;
216497 + pl022,com-mode = <0>;
216498 + spi-max-frequency = <24750000>;
216505 + pl022,com-mode = <0>;
216506 + spi-max-frequency = <24750000>;
216517 + pl022,com-mode = <0>;
216518 + spi-max-frequency = <24750000>;
216525 + pl022,com-mode = <0>;
216526 + spi-max-frequency = <24750000>;
216537 + pl022,com-mode = <0>;
216538 + spi-max-frequency = <24750000>;
216545 + pl022,com-mode = <0>;
216546 + spi-max-frequency = <24750000>;
216553 + pl022,com-mode = <0>;
216554 + spi-max-frequency = <24750000>;
216561 + pl022,com-mode = <0>;
216562 + spi-max-frequency = <24750000>;
216573 + pl022,com-mode = <0>;
216574 + spi-max-frequency = <48000000>;
216581 + pl022,com-mode = <0>;
216582 + spi-max-frequency = <48000000>;
216588 + pl022,com-mode = <0>;
216589 + spi-max-frequency = <48000000>;
216600 + pl022,com-mode = <0>;
216601 + spi-max-frequency = <48000000>;
216608 + pl022,com-mode = <0>;
216609 + spi-max-frequency = <48000000>;
216615 + pl022,com-mode = <0>;
216616 + spi-max-frequency = <48000000>;
216627 + pl022,com-mode = <0>;
216628 + spi-max-frequency = <48000000>;
216714 + compatible = "jedec,spi-nor";
216716 + spi-max-frequency = <160000000>;
216717 + m25p,fast-read;
216723 + compatible = "jedec,spi-nand";
216725 + spi-max-frequency = <160000000>;
216733 + nand-max-frequency = <200000000>;
216738 + ethphy: ethernet-phy@1 {
216745 + ethphy1: ethernet-phy@3 {
216752 + phy-handle = <ðphy>;
216753 + phy-mode = "rgmii";
216758 + phy-handle = <ðphy1>;
216759 + phy-mode = "rgmii";
216782 diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-emmc.dts b/arch/arm64/boot/dts/hisilico…
216785 --- /dev/null
216786 +++ b/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-emmc.dts
216787 @@ -0,0 +1,32 @@
216807 +#include "hi3559av100-demb-amp.dts"
216809 +#include "hi3559av100-demb.dts"
216820 diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-flash.dts b/arch/arm64/boot/dts/hisilic…
216823 --- /dev/null
216824 +++ b/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-flash.dts
216825 @@ -0,0 +1,32 @@
216845 +#include "hi3559av100-demb-amp.dts"
216847 +#include "hi3559av100-demb.dts"
216858 diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-ufs.dts b/arch/arm64/boot/dts/hisilicon…
216861 --- /dev/null
216862 +++ b/arch/arm64/boot/dts/hisilicon/hi3559av100-demb-ufs.dts
216863 @@ -0,0 +1,32 @@
216883 +#include "hi3559av100-demb-amp.dts"
216885 +#include "hi3559av100-demb.dts"
216896 diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100-demb.dts b/arch/arm64/boot/dts/hisilicon/hi3…
216899 --- /dev/null
216900 +++ b/arch/arm64/boot/dts/hisilicon/hi3559av100-demb.dts
216901 @@ -0,0 +1,655 @@
216919 +/dts-v1/;
216996 + linux,initrd-start = <0x60000040>;
216997 + linux,initrd-end = <0x61000000>;
217001 + #address-cells = <2>;
217002 + #size-cells = <0>;
217005 + compatible = "arm,cortex-a53";
217008 + enable-method = "psci";
217009 + clock-latency = <100000>; /* From legacy driver */
217010 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
217014 + compatible = "arm,cortex-a53";
217017 + enable-method = "psci";
217018 + clock-latency = <200000>; /* From legacy driver */
217019 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
217022 + compatible = "arm,cortex-a73";
217025 + enable-method = "psci";
217026 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
217027 + vcc-supply = <&a73_regulator>;
217030 + compatible = "arm,cortex-a73";
217033 + enable-method = "psci";
217034 + operating-points = <
217043 + clock-names = "a73_mux","24m","apll","1000m";
217044 + clock-latency = <400000>; /* From legacy driver */
217045 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
217046 + vcc-supply = <&a73_regulator>;
217053 + avs-num = <3>;
217054 + avs-name-array = "cpu-avs","media-avs","gpu-avs";
217056 + avs-name = "cpu-avs";
217057 + opp-num = <6>;
217058 + opp-freq = <1250000 1150000 1000000 930000 792000 594000 >;
217059 + opp-volt-min = <870000 870000 800000 800000 740000 740000>;
217060 + opp-hpm = <310 310 280 280 250 250>;
217061 + opp-div = <24 22 19 18 15 11>;
217062 + opp-volt-max = <1060000>;
217066 + avs-name = "media-avs";
217067 + opp-num = <4>;
217068 + opp-prof-num = <2>;
217069 + opp-temp-num = <2>;
217070 + opp-temp = <50 200>;
217071 + opp-freq = <1 2 3 4>;
217072 + opp-volt-min = <
217077 + opp-hpm = <
217082 + opp-div = <3 3 3 3>;
217083 + opp-volt-max = <
217091 + avs-name = "gpu-avs";
217232 + pl022,com-mode = <0>;
217233 + spi-max-frequency = <24750000>;
217240 + pl022,com-mode = <0>;
217241 + spi-max-frequency = <24750000>;
217252 + pl022,com-mode = <0>;
217253 + spi-max-frequency = <24750000>;
217260 + pl022,com-mode = <0>;
217261 + spi-max-frequency = <24750000>;
217272 + pl022,com-mode = <0>;
217273 + spi-max-frequency = <24750000>;
217280 + pl022,com-mode = <0>;
217281 + spi-max-frequency = <24750000>;
217292 + pl022,com-mode = <0>;
217293 + spi-max-frequency = <24750000>;
217300 + pl022,com-mode = <0>;
217301 + spi-max-frequency = <24750000>;
217312 + pl022,com-mode = <0>;
217313 + spi-max-frequency = <24750000>;
217320 + pl022,com-mode = <0>;
217321 + spi-max-frequency = <24750000>;
217328 + pl022,com-mode = <0>;
217329 + spi-max-frequency = <24750000>;
217336 + pl022,com-mode = <0>;
217337 + spi-max-frequency = <24750000>;
217348 + pl022,com-mode = <0>;
217349 + spi-max-frequency = <48000000>;
217356 + pl022,com-mode = <0>;
217357 + spi-max-frequency = <48000000>;
217363 + pl022,com-mode = <0>;
217364 + spi-max-frequency = <48000000>;
217375 + pl022,com-mode = <0>;
217376 + spi-max-frequency = <48000000>;
217383 + pl022,com-mode = <0>;
217384 + spi-max-frequency = <48000000>;
217390 + pl022,com-mode = <0>;
217391 + spi-max-frequency = <48000000>;
217402 + pl022,com-mode = <0>;
217403 + spi-max-frequency = <48000000>;
217489 + compatible = "jedec,spi-nor";
217491 + spi-max-frequency = <160000000>;
217492 + m25p,fast-read;
217498 + compatible = "jedec,spi-nand";
217500 + spi-max-frequency = <160000000>;
217508 + nand-max-frequency = <200000000>;
217513 + ethphy: ethernet-phy@1 {
217519 + ethphy1: ethernet-phy@3 {
217525 + phy-handle = <ðphy>;
217526 + phy-mode = "rgmii";
217530 + phy-handle = <ðphy1>;
217531 + phy-mode = "rgmii";
217557 diff --git a/arch/arm64/boot/dts/hisilicon/hi3559av100.dtsi b/arch/arm64/boot/dts/hisilicon/hi3559a…
217560 --- /dev/null
217562 @@ -0,0 +1,1374 @@
217581 +#include <dt-bindings/clock/hi3559av100-clock.h>
217584 + #address-cells = <2>;
217585 + #size-cells = <2>;
217587 + interrupt-parent = <&gic>;
217589 + gic: interrupt-controller@1F100000 {
217590 + compatible = "arm,gic-400";
217591 + #interrupt-cells = <3>;
217592 + #address-cells = <0>;
217593 + interrupt-controller;
217599 + compatible = "arm,psci-0.2";
217604 + compatible = "arm,armv8-pmuv3";
217612 + compatible = "hisilicon,hi3559av100-clock", "syscon";
217613 + #clock-cells = <1>;
217614 + #reset-cells = <2>;
217615 + #address-cells = <1>;
217616 + #size-cells = <1>;
217620 + compatible = "hisilicon,hi3559av100-shub-clock";
217621 + #clock-cells = <1>;
217622 + #reset-cells = <2>;
217623 + #address-cells = <1>;
217624 + #size-cells = <1>;
217628 + idle-states {
217629 + entry-method = "arm,psci";
217631 + CPU_POWERDOWN: cpu-powerdown {
217632 + compatible = "arm,idle-state";
217633 + local-timer-stop;
217634 + arm,psci-suspend-param = <0x0010000>;
217635 + entry-latency-us = <20>;
217636 + exit-latency-us = <40>;
217637 + min-residency-us = <80>;
217639 + CPU_STANDBY: cpu-standby {
217640 + compatible = "arm,idle-state";
217641 + arm,psci-suspend-param = <0x0000000>;
217642 + entry-latency-us = <0x3fffffff>;
217643 + exit-latency-us = <0x40000000>;
217644 + min-residency-us = <0xffffffff>;
217648 + compatible = "hisilicon,ipcm-interrupt";
217649 + interrupt-parent = <&gic>;
217655 + #address-cells = <1>;
217656 + #size-cells = <1>;
217657 + compatible = "simple-bus";
217659 + interrupt-parent = <&gic>;
217663 + compatible = "fixed-clock";
217664 + #clock-cells = <0>;
217665 + clock-frequency = <3000000>;
217669 + compatible = "arm,amba-bus";
217670 + #address-cells = <1>;
217671 + #size-cells = <1>;
217675 + arm-timer {
217676 + compatible = "arm,armv8-timer";
217679 + clock-frequency = <50000000>;
217694 + clock-names = "apb_pclk";
217702 + clock-names = "apb_pclk";
217711 + clock-names = "apb_pclk";
217720 + clock-names = "apb_pclk";
217729 + clock-names = "apb_pclk";
217738 + clock-names = "apb_pclk";
217746 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
217747 + assigned-clock-rates = <24000000>;
217749 + clock-names = "apb_pclk";
217751 + dma-names = "tx","rx";
217759 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
217760 + assigned-clock-rates = <24000000>;
217762 + clock-names = "apb_pclk";
217764 + dma-names = "tx","rx";
217772 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
217773 + assigned-clock-rates = <24000000>;
217775 + clock-names = "apb_pclk";
217777 + dma-names = "tx","rx";
217785 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
217786 + assigned-clock-rates = <24000000>;
217788 + clock-names = "apb_pclk";
217790 + dma-names = "tx","rx";
217798 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
217799 + assigned-clock-rates = <24000000>;
217801 + clock-names = "apb_pclk";
217803 + dma-names = "tx","rx";
217808 + compatible = "hisilicon,hibvt-i2c";
217811 + clock-frequency = <100000>;
217814 + dma-names = "tx","rx";
217818 + compatible = "hisilicon,hibvt-i2c";
217821 + clock-frequency = <100000>;
217823 + dma-names = "tx","rx";
217828 + compatible = "hisilicon,hibvt-i2c";
217831 + clock-frequency = <100000>;
217833 + dma-names = "tx","rx";
217838 + compatible = "hisilicon,hibvt-i2c";
217841 + clock-frequency = <100000>;
217843 + dma-names = "tx","rx";
217848 + compatible = "hisilicon,hibvt-i2c";
217851 + clock-frequency = <100000>;
217853 + dma-names = "tx","rx";
217858 + compatible = "hisilicon,hibvt-i2c";
217861 + clock-frequency = <100000>;
217863 + dma-names = "tx","rx";
217868 + compatible = "hisilicon,hibvt-i2c";
217871 + clock-frequency = <100000>;
217873 + dma-names = "tx","rx";
217878 + compatible = "hisilicon,hibvt-i2c";
217881 + clock-frequency = <100000>;
217883 + dma-names = "tx","rx";
217888 + compatible = "hisilicon,hibvt-i2c";
217891 + clock-frequency = <100000>;
217893 + dma-names = "tx","rx";
217898 + compatible = "hisilicon,hibvt-i2c";
217901 + clock-frequency = <100000>;
217903 + dma-names = "tx","rx";
217908 + compatible = "hisilicon,hibvt-i2c";
217911 + clock-frequency = <100000>;
217913 + dma-names = "tx","rx";
217918 + compatible = "hisilicon,hibvt-i2c";
217921 + clock-frequency = <100000>;
217923 + dma-names = "tx","rx";
217928 + compatible = "hisilicon,hibvt-i2c";
217931 + clock-frequency = <100000>;
217936 + compatible = "hisilicon,hibvt-i2c";
217939 + clock-frequency = <100000>;
217944 + compatible = "hisilicon,hibvt-i2c";
217947 + clock-frequency = <100000>;
217952 + compatible = "hisilicon,hibvt-i2c";
217955 + clock-frequency = <100000>;
217960 + compatible = "hisilicon,hibvt-i2c";
217963 + clock-frequency = <100000>;
217968 + compatible = "hisilicon,hibvt-i2c";
217971 + clock-frequency = <100000>;
217976 + compatible = "hisilicon,hibvt-i2c";
217979 + clock-frequency = <100000>;
217984 + compatible = "hisilicon,hibvt-i2c";
217987 + clock-frequency = <100000>;
217993 + arm,primecell-periphid = <0x00800022>;
217997 + clock-names = "apb_pclk";
217998 + #address-cells = <1>;
217999 + #size-cells = <0>;
218001 + num-cs = <2>;
218008 + arm,primecell-periphid = <0x00800022>;
218012 + clock-names = "apb_pclk";
218013 + #address-cells = <1>;
218014 + #size-cells = <0>;
218016 + num-cs = <2>;
218023 + arm,primecell-periphid = <0x00800022>;
218027 + clock-names = "apb_pclk";
218028 + #address-cells = <1>;
218029 + #size-cells = <0>;
218031 + num-cs = <2>;
218038 + arm,primecell-periphid = <0x00800022>;
218042 + clock-names = "apb_pclk";
218043 + #address-cells = <1>;
218044 + #size-cells = <0>;
218046 + num-cs = <2>;
218053 + arm,primecell-periphid = <0x00800022>;
218057 + clock-names = "apb_pclk";
218058 + #address-cells = <1>;
218059 + #size-cells = <0>;
218061 + num-cs = <4>;
218068 + arm,primecell-periphid = <0x00800022>;
218072 + clock-names = "apb_pclk";
218073 + #address-cells = <1>;
218074 + #size-cells = <0>;
218076 + num-cs = <3>;
218078 + dma-names = "tx","rx";
218085 + arm,primecell-periphid = <0x00800022>;
218089 + clock-names = "apb_pclk";
218090 + #address-cells = <1>;
218091 + #size-cells = <0>;
218093 + num-cs = <3>;
218095 + dma-names = "tx","rx";
218102 + arm,primecell-periphid = <0x00800022>;
218106 + clock-names = "apb_pclk";
218107 + #address-cells = <1>;
218108 + #size-cells = <0>;
218110 + num-cs = <1>;
218112 + dma-names = "tx","rx";
218121 + #gpio-cells = <2>;
218123 + clock-names = "apb_pclk";
218131 + #gpio-cells = <2>;
218133 + clock-names = "apb_pclk";
218141 + #gpio-cells = <2>;
218143 + clock-names = "apb_pclk";
218151 + #gpio-cells = <2>;
218153 + clock-names = "apb_pclk";
218161 + #gpio-cells = <2>;
218163 + clock-names = "apb_pclk";
218171 + #gpio-cells = <2>;
218173 + clock-names = "apb_pclk";
218181 + #gpio-cells = <2>;
218183 + clock-names = "apb_pclk";
218191 + #gpio-cells = <2>;
218193 + clock-names = "apb_pclk";
218201 + #gpio-cells = <2>;
218203 + clock-names = "apb_pclk";
218211 + #gpio-cells = <2>;
218213 + clock-names = "apb_pclk";
218221 + #gpio-cells = <2>;
218223 + clock-names = "apb_pclk";
218231 + #gpio-cells = <2>;
218233 + clock-names = "apb_pclk";
218241 + #gpio-cells = <2>;
218243 + clock-names = "apb_pclk";
218251 + #gpio-cells = <2>;
218253 + clock-names = "apb_pclk";
218261 + #gpio-cells = <2>;
218263 + clock-names = "apb_pclk";
218271 + #gpio-cells = <2>;
218273 + clock-names = "apb_pclk";
218281 + #gpio-cells = <2>;
218283 + clock-names = "apb_pclk";
218291 + #gpio-cells = <2>;
218293 + clock-names = "apb_pclk";
218301 + #gpio-cells = <2>;
218303 + clock-names = "apb_pclk";
218308 + compatible = "hisilicon,hi35xx-rtc";
218315 + compatible = "hisilicon,hisi-sys";
218318 + reg-names = "crg", "sys", "ddr", "misc";
218325 + sysctrl: system-controller@00000000 {
218328 + reboot-offset = <0x4>;
218331 + misc_ctrl: misc-controller@12030000 {
218332 + compatible = "hisilicon,hisi-miscctrl", "syscon";
218336 + shub_sysctrl: shubsystem-controller@18030000 {
218342 + compatible = "hisilicon,hisi-ioconfig", "syscon";
218347 + fmc: flash-memory-controller@10000000 {
218348 + compatible = "hisilicon,hisi-fmc";
218350 + reg-names = "control", "memory";
218352 + max-dma-size = <0x2000>;
218353 + #address-cells = <1>;
218354 + #size-cells = <0>;
218357 + compatible = "hisilicon,fmc-spi-nor";
218358 + assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
218359 + assigned-clock-rates = <24000000>;
218360 + #address-cells = <1>;
218361 + #size-cells = <0>;
218365 + compatible = "hisilicon,fmc-spi-nand";
218366 + assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
218367 + assigned-clock-rates = <24000000>;
218368 + #address-cells = <1>;
218369 + #size-cells = <0>;
218372 + hinfc:parallel-nand-controller {
218373 + compatible = "hisilicon,fmc-nand";
218374 + assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
218375 + assigned-clock-rates = <200000000>;
218376 + #address-cells = <1>;
218377 + #size-cells = <0>;
218385 + skip-info = <1>;
218386 + lanes-per-direction = <2>;
218387 + power-mode = <1>; /* 1:F 2:S 4:FA 5:SA */
218390 + cd-gpio = <&gpio_chip0 4 0>; /* card detect pin */
218391 + update-xfer-length;
218397 + compatible = "hisilicon,hisi-gemac-mdio";
218401 + reset-names = "phy_reset";
218402 + #address-cells = <1>;
218403 + #size-cells = <0>;
218408 + compatible = "hisilicon,hisi-gemac-mdio";
218412 + reset-names = "phy_reset";
218413 + #address-cells = <1>;
218414 + #size-cells = <0>;
218424 + clock-names = "higmac_clk",
218429 + reset-names = "port_reset",
218432 + mac-address = [00 00 00 00 00 00];
218442 + clock-names = "higmac_clk",
218447 + reset-names = "port_reset",
218450 + mac-address = [00 00 00 00 00 00];
218456 + compatible = "hisilicon,hisi-usb3-phy_0";
218462 + compatible = "hisilicon,hisi-usb3-phy_1";
218469 + compatible = "generic-xhci";
218472 + usb2-lpm-disable;
218477 + compatible = "generic-xhci";
218480 + usb2-lpm-disable;
218489 + interrupt-names = "peripheral";
218490 + maximum-speed = "super-speed";
218502 + interrupt-names = "peripheral";
218503 + maximum-speed = "super-speed";
218515 + clock-names = "mmc_clk";
218517 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
218518 + max-frequency = <198000000>;
218520 + non-removable;
218521 + bus-width = <8>;
218522 + cap-mmc-highspeed;
218523 + mmc-hs200-1_8v;
218524 + mmc-hs400-1_8v;
218525 + mmc-hs400-enhanced-strobe;
218526 + cap-mmc-hw-reset;
218536 + clock-names = "mmc_clk";
218538 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
218539 + max-frequency = <198000000>;
218543 + bus-width = <4>;
218544 + cap-sd-highspeed;
218545 + sd-uhs-sdr104;
218546 + full-pwr-cycle;
218547 + disable-wp;
218557 + clock-names = "mmc_clk";
218559 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
218560 + max-frequency = <49500000>;
218564 + bus-width = <4>;
218565 + cap-sd-highspeed;
218566 + full-pwr-cycle;
218567 + disable-wp;
218573 + compatible = "hisi-sdhci";
218577 + clock-names = "mmc_clk";
218579 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
218580 + max-frequency = <198000000>;
218584 + bus-width = <4>;
218585 + cap-mmc-highspeed;
218586 + sd-uhs-sdr104;
218593 + compatible = "hisilicon,hisi-pcie";
218594 + #size-cells = <2>;
218595 + #address-cells = <3>;
218596 + #interrupt-cells = <1>;
218597 + bus-range = <0x0 0xff>;
218600 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
218601 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 143 0x4
218606 + interrupt-names = "msi";
218618 + hivdmac: hivdma-controller@1f010000 {
218619 + compatible = "hisilicon,hisi-vdmac";
218623 + clock-names = "apb_pclk";
218625 + reset-names = "dma-reset";
218626 + #dma-cells = <2>;
218630 + hiedmacv310_1: hiedma-controller@10040000 {
218637 + clock-names = "apb_pclk", "axi_aclk";
218638 + #clock-cells = <2>;
218640 + reset-names = "dma-reset";
218641 + dma-requests = <32>;
218642 + dma-channels = <8>;
218644 + #dma-cells = <2>;
218649 + hiedmacv310_2: hiedma-controller@180f0000 {
218656 + clock-names = "apb_pclk", "axi_aclk";
218657 + #clock-cells = <2>;
218659 + reset-names = "dma-reset";
218660 + dma-requests = <32>;
218661 + dma-channels = <8>;
218663 + #dma-cells = <2>;
218669 + compatible = "hisilicon,hisi-vi";
218671 + reg-names = "VI_CAP0", "VI_PROC0", "VI_PROC1";
218673 + interrupt-names = "VI_CAP0", "VI_PROC0", "VI_PROC1";
218677 + compatible = "hisilicon,hisi-isp";
218679 + reg-names = "ISP";
218681 + interrupt-names = "ISP";
218685 + compatible = "hisilicon,hisi-mipi";
218687 + reg-names = "SLVS_EC0", "MIPI0";
218689 + interrupt-names = "SLVS_EC0", "MIPI0";
218693 + compatible = "hisilicon,hisi-vpss";
218695 + reg-names = "vpss0", "vpss1";
218697 + interrupt-names = "vpss0", "vpss1";
218701 + compatible = "hisilicon,hisi-vgs";
218703 + reg-names = "vgs0", "vgs1";
218705 + interrupt-names = "vgs0", "vgs1";
218709 + compatible = "hisilicon,hisi-gdc";
218711 + reg-names = "gdc0", "gdc1";
218713 + interrupt-names = "gdc0", "gdc1";
218717 + compatible = "hisilicon,hisi-dis";
218719 + reg-names = "dis";
218721 + interrupt-names = "dis";
218725 + compatible = "hisilicon,hisi-avs";
218727 + reg-names = "avs";
218729 + interrupt-names = "avs";
218733 + compatible = "hisilicon,hisi-vo";
218735 + reg-names = "vo";
218737 + interrupt-names = "vo";
218740 + compatible = "hisilicon,hisi-hifb";
218742 + reg-names = "hifb";
218744 + interrupt-names = "hifb";
218747 + compatible = "hisilicon,hisi-mipi_tx";
218749 + reg-names = "mipi_tx";
218751 + interrupt-names = "mipi_tx";
218754 + compatible = "hisilicon,hisi-hdmi";
218756 + reg-names = "hdmi0", "crg", "timer";
218758 + interrupt-names = "timer";
218762 + compatible = "hisilicon,hisi-vedu";
218764 + reg-names = "vedu0", "vedu1","vedu2","jpge";
218766 + interrupt-names = "vedu0", "vedu1","vedu2","jpge";
218770 + compatible = "hisilicon,hisi-venc";
218774 + compatible = "hisilicon,hisi-vdh";
218776 + reg-names = "vdh_scd" ;
218778 + interrupt-names = "vdh_olp","vdh_ilp","scd";
218782 + compatible = "hisilicon,hisi-jpegd";
218784 + reg-names = "jpegd";
218786 + interrupt-names = "jpegd";
218790 + compatible = "hisilicon,hisi-nnie";
218792 + reg-names = "nnie0", "nnie1";
218794 + interrupt-names = "nnie0", "nnie1";
218797 + compatible = "hisilicon,hisi-dpu_rect";
218799 + reg-names = "dpu_rect";
218801 + interrupt-names = "rect";
218804 + compatible = "hisilicon,hisi-dpu_match";
218806 + reg-names = "dpu_match";
218808 + interrupt-names = "match";
218811 + compatible = "hisilicon,hisi-dsp";
218813 + reg-names = "dsp0","dsp1","dsp2","dsp3";
218816 + compatible = "hisilicon,hisi-ive";
218818 + reg-names = "ive";
218820 + interrupt-names = "ive";
218823 + compatible = "hisilicon,hisi-fd";
218825 + reg-names = "fd";
218827 + interrupt-names = "fd";
218830 + compatible = "hisilicon,hisi-aiao";
218832 + reg-names = "acodec","aiao","crg";
218834 + interrupt-names = "AIO","VOIE";
218838 + compatible = "hisilicon,hisi-tde";
218840 + reg-names = "tde";
218842 + interrupt-names = "tde_osr_isr";
218846 + compatible = "hisilicon,hi3559a-volt";
218848 + reg-names = "base-address";
218849 + regulator-name = "vdd-gpu";
218850 + regulator-min-microvolt = <600000>;
218851 + regulator-max-microvolt = <940000>;
218852 + regulator-always-on;
218859 + regulator-num = <3>;
218860 + regulator-name-array = "regulator-a73","regulator-gpu","regulator-media";
218863 + regulator-name = "regulator-a73";
218864 + regulator-min-microvolt = <597000>;
218865 + regulator-max-microvolt = <1078000>;
218866 + regulator-always-on;
218871 + regulator-name = "regulator-gpu";
218872 + regulator-min-microvolt = <603000>;
218873 + regulator-max-microvolt = <943000>;
218874 + regulator-always-on;
218879 + regulator-name = "regulator-media";
218880 + regulator-min-microvolt = <603000>;
218881 + regulator-max-microvolt = <935000>;
218882 + regulator-always-on;
218889 + compatible = "arm,malit6xx", "arm,mali-midgard";
218892 + interrupt-names = "JOB", "MMU", "GPU";
218895 + clock-names = "clk_mali";
218896 + mali-supply = <&vddgpu>;
218897 + operating-points = <
218907 + compatible = "hisilicon,hisi-cipher";
218909 + reg-names = "cipher","rsa";
218911 + interrupt-names = "cipher","hash","rsa";
218915 + compatible = "hisilicon,hi-ir";
218917 + reg-names = "hi-ir";
218919 + interrupt-names = "hi-ir";
218922 + compatible = "hisilicon,hi-wdg";
218924 + reg-names = "hi-wdg0","hi-wdg1","hi-wdg2";
218926 + interrupt-names = "hi-wdg";
218931 + reg-names = "VI_CAP0", "VI_PROC0", "VI_PROC1", "ISP", "vp…
218933 + interrupt-names = "VI_CAP0","VI_PROC0","VI_PROC1","ISP", "vpss0", "vpss1", "vgs0", "v…
218938 diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-amp.dts b/arch/arm64/boot/dts/hisilicon/…
218941 --- /dev/null
218942 +++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-amp.dts
218943 @@ -0,0 +1,596 @@
218961 +/dts-v1/;
219038 + linux,initrd-start = <0x60000040>;
219039 + linux,initrd-end = <0x61000000>;
219043 + #address-cells = <2>;
219044 + #size-cells = <0>;
219047 + compatible = "arm,cortex-a53";
219050 + enable-method = "psci";
219051 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219055 + compatible = "arm,cortex-a53";
219058 + enable-method = "psci";
219059 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219062 + compatible = "arm,cortex-a73";
219065 + enable-method = "psci";
219066 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219069 + compatible = "arm,cortex-a73";
219072 + enable-method = "psci";
219073 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219215 + pl022,com-mode = <0>;
219216 + spi-max-frequency = <24750000>;
219223 + pl022,com-mode = <0>;
219224 + spi-max-frequency = <24750000>;
219235 + pl022,com-mode = <0>;
219236 + spi-max-frequency = <24750000>;
219243 + pl022,com-mode = <0>;
219244 + spi-max-frequency = <24750000>;
219255 + pl022,com-mode = <0>;
219256 + spi-max-frequency = <24750000>;
219263 + pl022,com-mode = <0>;
219264 + spi-max-frequency = <24750000>;
219275 + pl022,com-mode = <0>;
219276 + spi-max-frequency = <24750000>;
219283 + pl022,com-mode = <0>;
219284 + spi-max-frequency = <24750000>;
219295 + pl022,com-mode = <0>;
219296 + spi-max-frequency = <24750000>;
219303 + pl022,com-mode = <0>;
219304 + spi-max-frequency = <24750000>;
219311 + pl022,com-mode = <0>;
219312 + spi-max-frequency = <24750000>;
219319 + pl022,com-mode = <0>;
219320 + spi-max-frequency = <24750000>;
219331 + pl022,com-mode = <0>;
219332 + spi-max-frequency = <48000000>;
219339 + pl022,com-mode = <0>;
219340 + spi-max-frequency = <48000000>;
219346 + pl022,com-mode = <0>;
219347 + spi-max-frequency = <48000000>;
219358 + pl022,com-mode = <0>;
219359 + spi-max-frequency = <48000000>;
219366 + pl022,com-mode = <0>;
219367 + spi-max-frequency = <48000000>;
219373 + pl022,com-mode = <0>;
219374 + spi-max-frequency = <48000000>;
219385 + pl022,com-mode = <0>;
219386 + spi-max-frequency = <48000000>;
219472 + compatible = "jedec,spi-nor";
219474 + spi-max-frequency = <160000000>;
219475 + m25p,fast-read;
219481 + compatible = "jedec,spi-nand";
219483 + spi-max-frequency = <160000000>;
219491 + nand-max-frequency = <200000000>;
219496 + ethphy: ethernet-phy@1 {
219503 + ethphy1: ethernet-phy@3 {
219510 + phy-handle = <ðphy>;
219511 + phy-mode = "rgmii";
219516 + phy-handle = <ðphy1>;
219517 + phy-mode = "rgmii";
219540 diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-emmc.dts b/arch/arm64/boot/dts/hisilicon…
219543 --- /dev/null
219544 +++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-emmc.dts
219545 @@ -0,0 +1,32 @@
219565 +#include "hi3569v100-demb-amp.dts"
219567 +#include "hi3569v100-demb.dts"
219578 diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-flash.dts b/arch/arm64/boot/dts/hisilico…
219581 --- /dev/null
219582 +++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-flash.dts
219583 @@ -0,0 +1,32 @@
219603 +#include "hi3569v100-demb-amp.dts"
219605 +#include "hi3569v100-demb.dts"
219616 diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-ufs.dts b/arch/arm64/boot/dts/hisilicon/…
219619 --- /dev/null
219620 +++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb-ufs.dts
219621 @@ -0,0 +1,32 @@
219641 +#include "hi3569v100-demb-amp.dts"
219643 +#include "hi3569v100-demb.dts"
219654 diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100-demb.dts b/arch/arm64/boot/dts/hisilicon/hi35…
219657 --- /dev/null
219658 +++ b/arch/arm64/boot/dts/hisilicon/hi3569v100-demb.dts
219659 @@ -0,0 +1,655 @@
219677 +/dts-v1/;
219754 + linux,initrd-start = <0x60000040>;
219755 + linux,initrd-end = <0x61000000>;
219759 + #address-cells = <2>;
219760 + #size-cells = <0>;
219763 + compatible = "arm,cortex-a53";
219766 + enable-method = "psci";
219767 + clock-latency = <100000>; /* From legacy driver */
219768 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219772 + compatible = "arm,cortex-a53";
219775 + enable-method = "psci";
219776 + clock-latency = <200000>; /* From legacy driver */
219777 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219780 + compatible = "arm,cortex-a73";
219783 + enable-method = "psci";
219784 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219785 + vcc-supply = <&a73_regulator>;
219788 + compatible = "arm,cortex-a73";
219791 + enable-method = "psci";
219792 + operating-points = <
219801 + clock-names = "a73_mux","24m","apll","1000m";
219802 + clock-latency = <400000>; /* From legacy driver */
219803 + cpu-idle-states = <&CPU_POWERDOWN &CPU_STANDBY>;
219804 + vcc-supply = <&a73_regulator>;
219811 + avs-num = <3>;
219812 + avs-name-array = "cpu-avs","media-avs","gpu-avs";
219814 + avs-name = "cpu-avs";
219815 + opp-num = <6>;
219816 + opp-freq = <1250000 1150000 1000000 930000 792000 594000 >;
219817 + opp-volt-min = <870000 870000 800000 800000 740000 740000>;
219818 + opp-hpm = <310 310 280 280 250 250>;
219819 + opp-div = <24 22 19 18 15 11>;
219820 + opp-volt-max = <1060000>;
219824 + avs-name = "media-avs";
219825 + opp-num = <4>;
219826 + opp-prof-num = <2>;
219827 + opp-temp-num = <2>;
219828 + opp-temp = <50 200>;
219829 + opp-freq = <1 2 3 4>;
219830 + opp-volt-min = <
219835 + opp-hpm = <
219840 + opp-div = <3 3 3 3>;
219841 + opp-volt-max = <
219849 + avs-name = "gpu-avs";
219990 + pl022,com-mode = <0>;
219991 + spi-max-frequency = <24750000>;
219998 + pl022,com-mode = <0>;
219999 + spi-max-frequency = <24750000>;
220010 + pl022,com-mode = <0>;
220011 + spi-max-frequency = <24750000>;
220018 + pl022,com-mode = <0>;
220019 + spi-max-frequency = <24750000>;
220030 + pl022,com-mode = <0>;
220031 + spi-max-frequency = <24750000>;
220038 + pl022,com-mode = <0>;
220039 + spi-max-frequency = <24750000>;
220050 + pl022,com-mode = <0>;
220051 + spi-max-frequency = <24750000>;
220058 + pl022,com-mode = <0>;
220059 + spi-max-frequency = <24750000>;
220070 + pl022,com-mode = <0>;
220071 + spi-max-frequency = <24750000>;
220078 + pl022,com-mode = <0>;
220079 + spi-max-frequency = <24750000>;
220086 + pl022,com-mode = <0>;
220087 + spi-max-frequency = <24750000>;
220094 + pl022,com-mode = <0>;
220095 + spi-max-frequency = <24750000>;
220106 + pl022,com-mode = <0>;
220107 + spi-max-frequency = <48000000>;
220114 + pl022,com-mode = <0>;
220115 + spi-max-frequency = <48000000>;
220121 + pl022,com-mode = <0>;
220122 + spi-max-frequency = <48000000>;
220133 + pl022,com-mode = <0>;
220134 + spi-max-frequency = <48000000>;
220141 + pl022,com-mode = <0>;
220142 + spi-max-frequency = <48000000>;
220148 + pl022,com-mode = <0>;
220149 + spi-max-frequency = <48000000>;
220160 + pl022,com-mode = <0>;
220161 + spi-max-frequency = <48000000>;
220247 + compatible = "jedec,spi-nor";
220249 + spi-max-frequency = <160000000>;
220250 + m25p,fast-read;
220256 + compatible = "jedec,spi-nand";
220258 + spi-max-frequency = <160000000>;
220266 + nand-max-frequency = <200000000>;
220271 + ethphy: ethernet-phy@1 {
220277 + ethphy1: ethernet-phy@3 {
220283 + phy-handle = <ðphy>;
220284 + phy-mode = "rgmii";
220288 + phy-handle = <ðphy1>;
220289 + phy-mode = "rgmii";
220315 diff --git a/arch/arm64/boot/dts/hisilicon/hi3569v100.dtsi b/arch/arm64/boot/dts/hisilicon/hi3569v1…
220318 --- /dev/null
220320 @@ -0,0 +1,1364 @@
220339 +#include <dt-bindings/clock/hi3559av100-clock.h>
220342 + #address-cells = <2>;
220343 + #size-cells = <2>;
220345 + interrupt-parent = <&gic>;
220347 + gic: interrupt-controller@1F100000 {
220348 + compatible = "arm,gic-400";
220349 + #interrupt-cells = <3>;
220350 + #address-cells = <0>;
220351 + interrupt-controller;
220357 + compatible = "arm,psci-0.2";
220362 + compatible = "arm,armv8-pmuv3";
220370 + compatible = "hisilicon,hi3559av100-clock", "syscon";
220371 + #clock-cells = <1>;
220372 + #reset-cells = <2>;
220373 + #address-cells = <1>;
220374 + #size-cells = <1>;
220378 + compatible = "hisilicon,hi3559av100-shub-clock";
220379 + #clock-cells = <1>;
220380 + #reset-cells = <2>;
220381 + #address-cells = <1>;
220382 + #size-cells = <1>;
220386 + idle-states {
220387 + entry-method = "arm,psci";
220389 + CPU_POWERDOWN: cpu-powerdown {
220390 + compatible = "arm,idle-state";
220391 + local-timer-stop;
220392 + arm,psci-suspend-param = <0x0010000>;
220393 + entry-latency-us = <20>;
220394 + exit-latency-us = <40>;
220395 + min-residency-us = <80>;
220397 + CPU_STANDBY: cpu-standby {
220398 + compatible = "arm,idle-state";
220399 + arm,psci-suspend-param = <0x0000000>;
220400 + entry-latency-us = <0x3fffffff>;
220401 + exit-latency-us = <0x40000000>;
220402 + min-residency-us = <0xffffffff>;
220406 + compatible = "hisilicon,ipcm-interrupt";
220407 + interrupt-parent = <&gic>;
220413 + #address-cells = <1>;
220414 + #size-cells = <1>;
220415 + compatible = "simple-bus";
220417 + interrupt-parent = <&gic>;
220421 + compatible = "fixed-clock";
220422 + #clock-cells = <0>;
220423 + clock-frequency = <3000000>;
220427 + compatible = "arm,amba-bus";
220428 + #address-cells = <1>;
220429 + #size-cells = <1>;
220433 + arm-timer {
220434 + compatible = "arm,armv8-timer";
220437 + clock-frequency = <50000000>;
220452 + clock-names = "apb_pclk";
220460 + clock-names = "apb_pclk";
220469 + clock-names = "apb_pclk";
220478 + clock-names = "apb_pclk";
220487 + clock-names = "apb_pclk";
220496 + clock-names = "apb_pclk";
220504 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
220505 + assigned-clock-rates = <24000000>;
220507 + clock-names = "apb_pclk";
220509 + dma-names = "tx","rx";
220517 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
220518 + assigned-clock-rates = <24000000>;
220520 + clock-names = "apb_pclk";
220522 + dma-names = "tx","rx";
220530 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
220531 + assigned-clock-rates = <24000000>;
220533 + clock-names = "apb_pclk";
220535 + dma-names = "tx","rx";
220543 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
220544 + assigned-clock-rates = <24000000>;
220546 + clock-names = "apb_pclk";
220548 + dma-names = "tx","rx";
220556 + assigned-clocks = <&clock_shub HI3559AV100_SHUB_UART_SOURCE_CLK>;
220557 + assigned-clock-rates = <24000000>;
220559 + clock-names = "apb_pclk";
220561 + dma-names = "tx","rx";
220566 + compatible = "hisilicon,hibvt-i2c";
220569 + clock-frequency = <100000>;
220572 + dma-names = "tx","rx";
220576 + compatible = "hisilicon,hibvt-i2c";
220579 + clock-frequency = <100000>;
220581 + dma-names = "tx","rx";
220586 + compatible = "hisilicon,hibvt-i2c";
220589 + clock-frequency = <100000>;
220591 + dma-names = "tx","rx";
220596 + compatible = "hisilicon,hibvt-i2c";
220599 + clock-frequency = <100000>;
220601 + dma-names = "tx","rx";
220606 + compatible = "hisilicon,hibvt-i2c";
220609 + clock-frequency = <100000>;
220611 + dma-names = "tx","rx";
220616 + compatible = "hisilicon,hibvt-i2c";
220619 + clock-frequency = <100000>;
220621 + dma-names = "tx","rx";
220626 + compatible = "hisilicon,hibvt-i2c";
220629 + clock-frequency = <100000>;
220631 + dma-names = "tx","rx";
220636 + compatible = "hisilicon,hibvt-i2c";
220639 + clock-frequency = <100000>;
220641 + dma-names = "tx","rx";
220646 + compatible = "hisilicon,hibvt-i2c";
220649 + clock-frequency = <100000>;
220651 + dma-names = "tx","rx";
220656 + compatible = "hisilicon,hibvt-i2c";
220659 + clock-frequency = <100000>;
220661 + dma-names = "tx","rx";
220666 + compatible = "hisilicon,hibvt-i2c";
220669 + clock-frequency = <100000>;
220671 + dma-names = "tx","rx";
220676 + compatible = "hisilicon,hibvt-i2c";
220679 + clock-frequency = <100000>;
220681 + dma-names = "tx","rx";
220686 + compatible = "hisilicon,hibvt-i2c";
220689 + clock-frequency = <100000>;
220694 + compatible = "hisilicon,hibvt-i2c";
220697 + clock-frequency = <100000>;
220702 + compatible = "hisilicon,hibvt-i2c";
220705 + clock-frequency = <100000>;
220710 + compatible = "hisilicon,hibvt-i2c";
220713 + clock-frequency = <100000>;
220718 + compatible = "hisilicon,hibvt-i2c";
220721 + clock-frequency = <100000>;
220726 + compatible = "hisilicon,hibvt-i2c";
220729 + clock-frequency = <100000>;
220734 + compatible = "hisilicon,hibvt-i2c";
220737 + clock-frequency = <100000>;
220742 + compatible = "hisilicon,hibvt-i2c";
220745 + clock-frequency = <100000>;
220751 + arm,primecell-periphid = <0x00800022>;
220755 + clock-names = "apb_pclk";
220756 + #address-cells = <1>;
220757 + #size-cells = <0>;
220759 + num-cs = <2>;
220766 + arm,primecell-periphid = <0x00800022>;
220770 + clock-names = "apb_pclk";
220771 + #address-cells = <1>;
220772 + #size-cells = <0>;
220774 + num-cs = <2>;
220781 + arm,primecell-periphid = <0x00800022>;
220785 + clock-names = "apb_pclk";
220786 + #address-cells = <1>;
220787 + #size-cells = <0>;
220789 + num-cs = <2>;
220796 + arm,primecell-periphid = <0x00800022>;
220800 + clock-names = "apb_pclk";
220801 + #address-cells = <1>;
220802 + #size-cells = <0>;
220804 + num-cs = <2>;
220811 + arm,primecell-periphid = <0x00800022>;
220815 + clock-names = "apb_pclk";
220816 + #address-cells = <1>;
220817 + #size-cells = <0>;
220819 + num-cs = <4>;
220826 + arm,primecell-periphid = <0x00800022>;
220830 + clock-names = "apb_pclk";
220831 + #address-cells = <1>;
220832 + #size-cells = <0>;
220834 + num-cs = <3>;
220836 + dma-names = "tx","rx";
220843 + arm,primecell-periphid = <0x00800022>;
220847 + clock-names = "apb_pclk";
220848 + #address-cells = <1>;
220849 + #size-cells = <0>;
220851 + num-cs = <3>;
220853 + dma-names = "tx","rx";
220860 + arm,primecell-periphid = <0x00800022>;
220864 + clock-names = "apb_pclk";
220865 + #address-cells = <1>;
220866 + #size-cells = <0>;
220868 + num-cs = <1>;
220870 + dma-names = "tx","rx";
220879 + #gpio-cells = <2>;
220881 + clock-names = "apb_pclk";
220889 + #gpio-cells = <2>;
220891 + clock-names = "apb_pclk";
220899 + #gpio-cells = <2>;
220901 + clock-names = "apb_pclk";
220909 + #gpio-cells = <2>;
220911 + clock-names = "apb_pclk";
220919 + #gpio-cells = <2>;
220921 + clock-names = "apb_pclk";
220929 + #gpio-cells = <2>;
220931 + clock-names = "apb_pclk";
220939 + #gpio-cells = <2>;
220941 + clock-names = "apb_pclk";
220949 + #gpio-cells = <2>;
220951 + clock-names = "apb_pclk";
220959 + #gpio-cells = <2>;
220961 + clock-names = "apb_pclk";
220969 + #gpio-cells = <2>;
220971 + clock-names = "apb_pclk";
220979 + #gpio-cells = <2>;
220981 + clock-names = "apb_pclk";
220989 + #gpio-cells = <2>;
220991 + clock-names = "apb_pclk";
220999 + #gpio-cells = <2>;
221001 + clock-names = "apb_pclk";
221009 + #gpio-cells = <2>;
221011 + clock-names = "apb_pclk";
221019 + #gpio-cells = <2>;
221021 + clock-names = "apb_pclk";
221029 + #gpio-cells = <2>;
221031 + clock-names = "apb_pclk";
221039 + #gpio-cells = <2>;
221041 + clock-names = "apb_pclk";
221049 + #gpio-cells = <2>;
221051 + clock-names = "apb_pclk";
221059 + #gpio-cells = <2>;
221061 + clock-names = "apb_pclk";
221066 + compatible = "hisilicon,hi35xx-rtc";
221073 + compatible = "hisilicon,hisi-sys";
221076 + reg-names = "crg", "sys", "ddr", "misc";
221083 + sysctrl: system-controller@00000000 {
221086 + reboot-offset = <0x4>;
221089 + misc_ctrl: misc-controller@12030000 {
221090 + compatible = "hisilicon,hisi-miscctrl", "syscon";
221094 + shub_sysctrl: shubsystem-controller@18030000 {
221100 + compatible = "hisilicon,hisi-ioconfig", "syscon";
221105 + fmc: flash-memory-controller@10000000 {
221106 + compatible = "hisilicon,hisi-fmc";
221108 + reg-names = "control", "memory";
221110 + max-dma-size = <0x2000>;
221111 + #address-cells = <1>;
221112 + #size-cells = <0>;
221115 + compatible = "hisilicon,fmc-spi-nor";
221116 + assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
221117 + assigned-clock-rates = <24000000>;
221118 + #address-cells = <1>;
221119 + #size-cells = <0>;
221123 + compatible = "hisilicon,fmc-spi-nand";
221124 + assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
221125 + assigned-clock-rates = <24000000>;
221126 + #address-cells = <1>;
221127 + #size-cells = <0>;
221130 + hinfc:parallel-nand-controller {
221131 + compatible = "hisilicon,fmc-nand";
221132 + assigned-clocks = <&clock HI3559AV100_FMC_CLK>;
221133 + assigned-clock-rates = <200000000>;
221134 + #address-cells = <1>;
221135 + #size-cells = <0>;
221144 + clock-names = "clk";
221145 + lanes-per-direction = <2>;
221146 + power-mode = <1>; /* 1:F 2:S 4:FA 5:SA */
221149 + cd-gpio = <&gpio_chip0 4 0>; /* card detect pin */
221150 + update-xfer-length;
221155 + compatible = "hisilicon,hisi-gemac-mdio";
221159 + reset-names = "phy_reset";
221160 + #address-cells = <1>;
221161 + #size-cells = <0>;
221166 + compatible = "hisilicon,hisi-gemac-mdio";
221170 + reset-names = "phy_reset";
221171 + #address-cells = <1>;
221172 + #size-cells = <0>;
221182 + clock-names = "higmac_clk",
221187 + reset-names = "port_reset",
221190 + mac-address = [00 00 00 00 00 00];
221200 + clock-names = "higmac_clk",
221205 + reset-names = "port_reset",
221208 + mac-address = [00 00 00 00 00 00];
221214 + compatible = "hisilicon,hisi-usb3-phy_0";
221220 + compatible = "hisilicon,hisi-usb3-phy_1";
221227 + compatible = "generic-xhci";
221230 + usb2-lpm-disable;
221235 + compatible = "generic-xhci";
221238 + usb2-lpm-disable;
221247 + interrupt-names = "peripheral";
221248 + maximum-speed = "super-speed";
221260 + interrupt-names = "peripheral";
221261 + maximum-speed = "super-speed";
221269 + compatible = "hisi-sdhci";
221273 + clock-names = "mmc_clk";
221275 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
221276 + max-frequency = <198000000>;
221278 + non-removable;
221279 + bus-width = <8>;
221280 + cap-mmc-highspeed;
221281 + mmc-hs400-1_8v;
221282 + mmc-hs400-enhanced-strobe;
221283 + cap-mmc-hw-reset;
221289 + compatible = "hisi-sdhci";
221293 + clock-names = "mmc_clk";
221295 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
221296 + max-frequency = <198000000>;
221300 + bus-width = <4>;
221301 + cap-sd-highspeed;
221302 + sd-uhs-sdr104;
221303 + full-pwr-cycle;
221304 + disable-wp;
221310 + compatible = "hisi-sdhci";
221314 + clock-names = "mmc_clk";
221316 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
221317 + max-frequency = <49500000>;
221321 + bus-width = <4>;
221322 + cap-sd-highspeed;
221323 + full-pwr-cycle;
221324 + disable-wp;
221330 + compatible = "hisi-sdhci";
221334 + clock-names = "mmc_clk";
221336 + reset-names = "crg_reset", "dll_reset", "sampl_reset";
221337 + max-frequency = <198000000>;
221341 + bus-width = <4>;
221342 + cap-mmc-highspeed;
221343 + sd-uhs-sdr104;
221350 + compatible = "hisilicon,hisi-pcie";
221351 + #size-cells = <2>;
221352 + #address-cells = <3>;
221353 + #interrupt-cells = <1>;
221354 + bus-range = <0x0 0xff>;
221357 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
221358 + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 143 0x4
221363 + interrupt-names = "msi";
221375 + hivdmac: hivdma-controller@1f010000 {
221376 + compatible = "hisilicon,hisi-vdmac";
221380 + clock-names = "apb_pclk";
221382 + reset-names = "dma-reset";
221383 + #dma-cells = <2>;
221387 + hiedmacv310_1: hiedma-controller@10040000 {
221394 + clock-names = "apb_pclk", "axi_aclk";
221395 + #clock-cells = <2>;
221397 + reset-names = "dma-reset";
221398 + dma-requests = <32>;
221399 + dma-channels = <8>;
221401 + #dma-cells = <2>;
221406 + hiedmacv310_2: hiedma-controller@180f0000 {
221413 + clock-names = "apb_pclk", "axi_aclk";
221414 + #clock-cells = <2>;
221416 + reset-names = "dma-reset";
221417 + dma-requests = <32>;
221418 + dma-channels = <8>;
221420 + #dma-cells = <2>;
221426 + compatible = "hisilicon,hisi-vi";
221428 + reg-names = "VI_CAP0", "VI_PROC0", "VI_PROC1";
221430 + interrupt-names = "VI_CAP0", "VI_PROC0", "VI_PROC1";
221434 + compatible = "hisilicon,hisi-isp";
221436 + reg-names = "ISP";
221438 + interrupt-names = "ISP";
221442 + compatible = "hisilicon,hisi-mipi";
221444 + reg-names = "SLVS_EC0", "MIPI0";
221446 + interrupt-names = "SLVS_EC0", "MIPI0";
221450 + compatible = "hisilicon,hisi-vpss";
221452 + reg-names = "vpss0", "vpss1";
221454 + interrupt-names = "vpss0", "vpss1";
221458 + compatible = "hisilicon,hisi-vgs";
221460 + reg-names = "vgs0", "vgs1";
221462 + interrupt-names = "vgs0", "vgs1";
221466 + compatible = "hisilicon,hisi-gdc";
221468 + reg-names = "gdc0", "gdc1";
221470 + interrupt-names = "gdc0", "gdc1";
221474 + compatible = "hisilicon,hisi-dis";
221476 + reg-names = "dis";
221478 + interrupt-names = "dis";
221482 + compatible = "hisilicon,hisi-avs";
221484 + reg-names = "avs";
221486 + interrupt-names = "avs";
221490 + compatible = "hisilicon,hisi-vo";
221492 + reg-names = "vo";
221494 + interrupt-names = "vo";
221497 + compatible = "hisilicon,hisi-hifb";
221499 + reg-names = "hifb";
221501 + interrupt-names = "hifb";
221504 + compatible = "hisilicon,hisi-mipi_tx";
221506 + reg-names = "mipi_tx";
221508 + interrupt-names = "mipi_tx";
221511 + compatible = "hisilicon,hisi-hdmi";
221513 + reg-names = "hdmi0", "crg", "timer";
221515 + interrupt-names = "timer";
221519 + compatible = "hisilicon,hisi-vedu";
221521 + reg-names = "vedu0", "vedu1","vedu2","jpge";
221523 + interrupt-names = "vedu0", "vedu1","vedu2","jpge";
221527 + compatible = "hisilicon,hisi-venc";
221531 + compatible = "hisilicon,hisi-vdh";
221533 + reg-names = "vdh_scd" ;
221535 + interrupt-names = "vdh_olp","vdh_ilp","scd";
221539 + compatible = "hisilicon,hisi-jpegd";
221541 + reg-names = "jpegd";
221543 + interrupt-names = "jpegd";
221547 + compatible = "hisilicon,hisi-nnie";
221549 + reg-names = "nnie0", "nnie1";
221551 + interrupt-names = "nnie0", "nnie1";
221554 + compatible = "hisilicon,hisi-dpu_rect";
221556 + reg-names = "dpu_rect";
221558 + interrupt-names = "rect";
221561 + compatible = "hisilicon,hisi-dpu_match";
221563 + reg-names = "dpu_match";
221565 + interrupt-names = "match";
221568 + compatible = "hisilicon,hisi-dsp";
221570 + reg-names = "dsp0","dsp1","dsp2","dsp3";
221573 + compatible = "hisilicon,hisi-ive";
221575 + reg-names = "ive";
221577 + interrupt-names = "ive";
221580 + compatible = "hisilicon,hisi-fd";
221582 + reg-names = "fd";
221584 + interrupt-names = "fd";
221587 + compatible = "hisilicon,hisi-aiao";
221589 + reg-names = "acodec","aiao","crg";
221591 + interrupt-names = "AIO","VOIE";
221595 + compatible = "hisilicon,hisi-tde";
221597 + reg-names = "tde";
221599 + interrupt-names = "tde_osr_isr";
221603 + compatible = "hisilicon,hi3559a-volt";
221605 + reg-names = "base-address";
221606 + regulator-name = "vdd-gpu";
221607 + regulator-min-microvolt = <600000>;
221608 + regulator-max-microvolt = <940000>;
221609 + regulator-always-on;
221616 + regulator-num = <3>;
221617 + regulator-name-array = "regulator-a73","regulator-gpu","regulator-media";
221620 + regulator-name = "regulator-a73";
221621 + regulator-min-microvolt = <597000>;
221622 + regulator-max-microvolt = <1078000>;
221623 + regulator-always-on;
221628 + regulator-name = "regulator-gpu";
221629 + regulator-min-microvolt = <603000>;
221630 + regulator-max-microvolt = <943000>;
221631 + regulator-always-on;
221636 + regulator-name = "regulator-media";
221637 + regulator-min-microvolt = <603000>;
221638 + regulator-max-microvolt = <935000>;
221639 + regulator-always-on;
221646 + compatible = "arm,malit6xx", "arm,mali-midgard";
221649 + interrupt-names = "JOB", "MMU", "GPU";
221652 + clock-names = "clk_mali";
221653 + mali-supply = <&vddgpu>;
221654 + operating-points = <
221661 + compatible = "hisilicon,hisi-cipher";
221663 + reg-names = "cipher","rsa";
221665 + interrupt-names = "cipher","hash","rsa";
221669 + compatible = "hisilicon,hi-ir";
221671 + reg-names = "hi-ir";
221673 + interrupt-names = "hi-ir";
221676 + compatible = "hisilicon,hi-wdg";
221678 + reg-names = "hi-wdg0","hi-wdg1","hi-wdg2";
221680 + interrupt-names = "hi-wdg";
221685 diff --git a/arch/arm64/configs/hi3531dv200_defconfig b/arch/arm64/configs/hi3531dv200_defconfig
221688 --- /dev/null
221690 @@ -0,0 +1,3458 @@
221697 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
222071 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
222072 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3531dv200-demb"
222148 +# General architecture-dependent options
222206 +# GCOV-based kernel profiling
222665 +# Self-contained MTD device drivers
222678 +# Disk-On-Chip Device Drivers
222856 +# SCSI support type (disk, tape, CD-ROM)
222937 +# Controllers with non-SFF native interface
223305 +# Non-8250 serial port support
223397 +# I2C system bus drivers (mostly embedded / system-on-chip)
224299 +# on-CPU RTC drivers
224351 +# Microsoft Hyper-V guest support
224583 +# CD-ROM/DVD Filesystems
224597 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
224692 +CONFIG_NLS_DEFAULT="iso8859-1"
224990 +# Compile-time checks and compiler options
225149 diff --git a/arch/arm64/configs/hi3531dv200_emmc_defconfig b/arch/arm64/configs/hi3531dv200_emmc_de…
225152 --- /dev/null
225154 @@ -0,0 +1,3491 @@
225161 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
225535 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
225536 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3531dv200-demb"
225612 +# General architecture-dependent options
225670 +# GCOV-based kernel profiling
226129 +# Self-contained MTD device drivers
226142 +# Disk-On-Chip Device Drivers
226318 +# SCSI support type (disk, tape, CD-ROM)
226399 +# Controllers with non-SFF native interface
226767 +# Non-8250 serial port support
226859 +# I2C system bus drivers (mostly embedded / system-on-chip)
227796 +# on-CPU RTC drivers
227848 +# Microsoft Hyper-V guest support
228080 +# CD-ROM/DVD Filesystems
228094 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
228189 +CONFIG_NLS_DEFAULT="iso8859-1"
228487 +# Compile-time checks and compiler options
228646 diff --git a/arch/arm64/configs/hi3535av100_defconfig b/arch/arm64/configs/hi3535av100_defconfig
228649 --- /dev/null
228651 @@ -0,0 +1,3458 @@
228658 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
229032 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
229033 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3535av100-demb"
229109 +# General architecture-dependent options
229167 +# GCOV-based kernel profiling
229626 +# Self-contained MTD device drivers
229639 +# Disk-On-Chip Device Drivers
229817 +# SCSI support type (disk, tape, CD-ROM)
229898 +# Controllers with non-SFF native interface
230266 +# Non-8250 serial port support
230358 +# I2C system bus drivers (mostly embedded / system-on-chip)
231260 +# on-CPU RTC drivers
231312 +# Microsoft Hyper-V guest support
231544 +# CD-ROM/DVD Filesystems
231558 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
231653 +CONFIG_NLS_DEFAULT="iso8859-1"
231951 +# Compile-time checks and compiler options
232110 diff --git a/arch/arm64/configs/hi3535av100_emmc_defconfig b/arch/arm64/configs/hi3535av100_emmc_de…
232113 --- /dev/null
232115 @@ -0,0 +1,3491 @@
232122 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B017_20190910) 7.3.0
232496 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
232497 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3535av100-demb"
232573 +# General architecture-dependent options
232631 +# GCOV-based kernel profiling
233090 +# Self-contained MTD device drivers
233103 +# Disk-On-Chip Device Drivers
233279 +# SCSI support type (disk, tape, CD-ROM)
233360 +# Controllers with non-SFF native interface
233728 +# Non-8250 serial port support
233820 +# I2C system bus drivers (mostly embedded / system-on-chip)
234757 +# on-CPU RTC drivers
234809 +# Microsoft Hyper-V guest support
235041 +# CD-ROM/DVD Filesystems
235055 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
235150 +CONFIG_NLS_DEFAULT="iso8859-1"
235448 +# Compile-time checks and compiler options
235607 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_amp_defconfig b/arch/arm64/configs/hi3…
235610 --- /dev/null
235612 @@ -0,0 +1,3530 @@
235619 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
235997 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
235998 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-flash"
236074 +# General architecture-dependent options
236132 +# GCOV-based kernel profiling
236591 +# Self-contained MTD device drivers
236604 +# Disk-On-Chip Device Drivers
236782 +# SCSI support type (disk, tape, CD-ROM)
237210 +# Non-8250 serial port support
237302 +# I2C system bus drivers (mostly embedded / system-on-chip)
238290 +# on-CPU RTC drivers
238314 +# Microsoft Hyper-V guest support
238578 +# CD-ROM/DVD Filesystems
238592 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
238687 +CONFIG_NLS_DEFAULT="iso8859-1"
238983 +# Compile-time checks and compiler options
239143 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_defconfig b/arch/arm64/configs/hi3559a…
239146 --- /dev/null
239148 @@ -0,0 +1,3530 @@
239155 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
239533 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
239534 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-flash"
239610 +# General architecture-dependent options
239668 +# GCOV-based kernel profiling
240127 +# Self-contained MTD device drivers
240140 +# Disk-On-Chip Device Drivers
240318 +# SCSI support type (disk, tape, CD-ROM)
240746 +# Non-8250 serial port support
240838 +# I2C system bus drivers (mostly embedded / system-on-chip)
241826 +# on-CPU RTC drivers
241850 +# Microsoft Hyper-V guest support
242114 +# CD-ROM/DVD Filesystems
242128 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
242223 +CONFIG_NLS_DEFAULT="iso8859-1"
242519 +# Compile-time checks and compiler options
242679 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_emmc_amp_defconfig b/arch/arm64/config…
242682 --- /dev/null
242684 @@ -0,0 +1,3530 @@
242691 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
243069 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
243070 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-emmc"
243146 +# General architecture-dependent options
243204 +# GCOV-based kernel profiling
243663 +# Self-contained MTD device drivers
243676 +# Disk-On-Chip Device Drivers
243854 +# SCSI support type (disk, tape, CD-ROM)
244282 +# Non-8250 serial port support
244374 +# I2C system bus drivers (mostly embedded / system-on-chip)
245362 +# on-CPU RTC drivers
245386 +# Microsoft Hyper-V guest support
245650 +# CD-ROM/DVD Filesystems
245664 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
245759 +CONFIG_NLS_DEFAULT="iso8859-1"
246055 +# Compile-time checks and compiler options
246215 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_emmc_defconfig b/arch/arm64/configs/hi…
246218 --- /dev/null
246220 @@ -0,0 +1,3530 @@
246227 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
246605 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
246606 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-emmc"
246682 +# General architecture-dependent options
246740 +# GCOV-based kernel profiling
247199 +# Self-contained MTD device drivers
247212 +# Disk-On-Chip Device Drivers
247390 +# SCSI support type (disk, tape, CD-ROM)
247818 +# Non-8250 serial port support
247910 +# I2C system bus drivers (mostly embedded / system-on-chip)
248898 +# on-CPU RTC drivers
248922 +# Microsoft Hyper-V guest support
249186 +# CD-ROM/DVD Filesystems
249200 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
249295 +CONFIG_NLS_DEFAULT="iso8859-1"
249591 +# Compile-time checks and compiler options
249751 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_emmc_hos_l2_defconfig b/arch/arm64/con…
249754 --- /dev/null
249756 @@ -0,0 +1,3643 @@
249763 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
250141 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
250142 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-emmc"
250218 +# General architecture-dependent options
250276 +# GCOV-based kernel profiling
250735 +# Self-contained MTD device drivers
250748 +# Disk-On-Chip Device Drivers
250926 +# SCSI support type (disk, tape, CD-ROM)
251354 +# Non-8250 serial port support
251446 +# I2C system bus drivers (mostly embedded / system-on-chip)
252505 +# on-CPU RTC drivers
252529 +# Microsoft Hyper-V guest support
252811 +# CD-ROM/DVD Filesystems
252825 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
252920 +CONFIG_NLS_DEFAULT="iso8859-1"
253000 +#CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/sbin/tomoyo-init"
253240 +# Compile-time checks and compiler options
253400 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_nand_amp_defconfig b/arch/arm64/config…
253403 --- /dev/null
253405 @@ -0,0 +1,3526 @@
253412 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
253790 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
253791 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-flash"
253867 +# General architecture-dependent options
253925 +# GCOV-based kernel profiling
254384 +# Self-contained MTD device drivers
254396 +# Disk-On-Chip Device Drivers
254571 +# SCSI support type (disk, tape, CD-ROM)
254999 +# Non-8250 serial port support
255091 +# I2C system bus drivers (mostly embedded / system-on-chip)
256079 +# on-CPU RTC drivers
256103 +# Microsoft Hyper-V guest support
256367 +# CD-ROM/DVD Filesystems
256381 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
256476 +CONFIG_NLS_DEFAULT="iso8859-1"
256772 +# Compile-time checks and compiler options
256932 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_nand_defconfig b/arch/arm64/configs/hi…
256935 --- /dev/null
256937 @@ -0,0 +1,3526 @@
256944 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
257322 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
257323 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-flash"
257399 +# General architecture-dependent options
257457 +# GCOV-based kernel profiling
257916 +# Self-contained MTD device drivers
257928 +# Disk-On-Chip Device Drivers
258103 +# SCSI support type (disk, tape, CD-ROM)
258531 +# Non-8250 serial port support
258623 +# I2C system bus drivers (mostly embedded / system-on-chip)
259611 +# on-CPU RTC drivers
259635 +# Microsoft Hyper-V guest support
259899 +# CD-ROM/DVD Filesystems
259913 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
260008 +CONFIG_NLS_DEFAULT="iso8859-1"
260304 +# Compile-time checks and compiler options
260464 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_ufs_amp_defconfig b/arch/arm64/configs…
260467 --- /dev/null
260469 @@ -0,0 +1,3497 @@
260476 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
260854 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
260855 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-ufs"
260931 +# General architecture-dependent options
260989 +# GCOV-based kernel profiling
261448 +# Self-contained MTD device drivers
261461 +# Disk-On-Chip Device Drivers
261639 +# SCSI support type (disk, tape, CD-ROM)
262071 +# Non-8250 serial port support
262163 +# I2C system bus drivers (mostly embedded / system-on-chip)
263116 +# on-CPU RTC drivers
263140 +# Microsoft Hyper-V guest support
263402 +# CD-ROM/DVD Filesystems
263416 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
263511 +CONFIG_NLS_DEFAULT="iso8859-1"
263807 +# Compile-time checks and compiler options
263967 diff --git a/arch/arm64/configs/hi3559av100_arm64_big_little_ufs_defconfig b/arch/arm64/configs/hi3…
263970 --- /dev/null
263972 @@ -0,0 +1,3497 @@
263979 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
264357 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb"
264358 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3559av100-demb-ufs"
264434 +# General architecture-dependent options
264492 +# GCOV-based kernel profiling
264951 +# Self-contained MTD device drivers
264964 +# Disk-On-Chip Device Drivers
265142 +# SCSI support type (disk, tape, CD-ROM)
265574 +# Non-8250 serial port support
265666 +# I2C system bus drivers (mostly embedded / system-on-chip)
266619 +# on-CPU RTC drivers
266643 +# Microsoft Hyper-V guest support
266905 +# CD-ROM/DVD Filesystems
266919 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
267014 +CONFIG_NLS_DEFAULT="iso8859-1"
267310 +# Compile-time checks and compiler options
267470 diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_amp_defconfig b/arch/arm64/configs/hi35…
267473 --- /dev/null
267475 @@ -0,0 +1,3530 @@
267482 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
267860 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
267861 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
267937 +# General architecture-dependent options
267995 +# GCOV-based kernel profiling
268454 +# Self-contained MTD device drivers
268467 +# Disk-On-Chip Device Drivers
268645 +# SCSI support type (disk, tape, CD-ROM)
269073 +# Non-8250 serial port support
269165 +# I2C system bus drivers (mostly embedded / system-on-chip)
270153 +# on-CPU RTC drivers
270177 +# Microsoft Hyper-V guest support
270441 +# CD-ROM/DVD Filesystems
270455 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
270550 +CONFIG_NLS_DEFAULT="iso8859-1"
270846 +# Compile-time checks and compiler options
271006 diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_defconfig b/arch/arm64/configs/hi3569v1…
271009 --- /dev/null
271011 @@ -0,0 +1,3530 @@
271018 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
271396 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
271397 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
271473 +# General architecture-dependent options
271531 +# GCOV-based kernel profiling
271990 +# Self-contained MTD device drivers
272003 +# Disk-On-Chip Device Drivers
272181 +# SCSI support type (disk, tape, CD-ROM)
272609 +# Non-8250 serial port support
272701 +# I2C system bus drivers (mostly embedded / system-on-chip)
273689 +# on-CPU RTC drivers
273713 +# Microsoft Hyper-V guest support
273977 +# CD-ROM/DVD Filesystems
273991 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
274086 +CONFIG_NLS_DEFAULT="iso8859-1"
274382 +# Compile-time checks and compiler options
274542 diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_amp_defconfig b/arch/arm64/configs…
274545 --- /dev/null
274547 @@ -0,0 +1,3530 @@
274554 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
274932 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
274933 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-emmc"
275009 +# General architecture-dependent options
275067 +# GCOV-based kernel profiling
275526 +# Self-contained MTD device drivers
275539 +# Disk-On-Chip Device Drivers
275717 +# SCSI support type (disk, tape, CD-ROM)
276145 +# Non-8250 serial port support
276237 +# I2C system bus drivers (mostly embedded / system-on-chip)
277225 +# on-CPU RTC drivers
277249 +# Microsoft Hyper-V guest support
277513 +# CD-ROM/DVD Filesystems
277527 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
277622 +CONFIG_NLS_DEFAULT="iso8859-1"
277918 +# Compile-time checks and compiler options
278078 diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_emmc_defconfig b/arch/arm64/configs/hi3…
278081 --- /dev/null
278083 @@ -0,0 +1,3530 @@
278090 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
278468 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
278469 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-emmc"
278545 +# General architecture-dependent options
278603 +# GCOV-based kernel profiling
279062 +# Self-contained MTD device drivers
279075 +# Disk-On-Chip Device Drivers
279253 +# SCSI support type (disk, tape, CD-ROM)
279681 +# Non-8250 serial port support
279773 +# I2C system bus drivers (mostly embedded / system-on-chip)
280761 +# on-CPU RTC drivers
280785 +# Microsoft Hyper-V guest support
281049 +# CD-ROM/DVD Filesystems
281063 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
281158 +CONFIG_NLS_DEFAULT="iso8859-1"
281454 +# Compile-time checks and compiler options
281614 diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_nand_amp_defconfig b/arch/arm64/configs…
281617 --- /dev/null
281619 @@ -0,0 +1,3526 @@
281626 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
282004 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
282005 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
282081 +# General architecture-dependent options
282139 +# GCOV-based kernel profiling
282598 +# Self-contained MTD device drivers
282610 +# Disk-On-Chip Device Drivers
282785 +# SCSI support type (disk, tape, CD-ROM)
283213 +# Non-8250 serial port support
283305 +# I2C system bus drivers (mostly embedded / system-on-chip)
284293 +# on-CPU RTC drivers
284317 +# Microsoft Hyper-V guest support
284581 +# CD-ROM/DVD Filesystems
284595 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
284690 +CONFIG_NLS_DEFAULT="iso8859-1"
284986 +# Compile-time checks and compiler options
285146 diff --git a/arch/arm64/configs/hi3569v100_arm64_big_little_nand_defconfig b/arch/arm64/configs/hi3…
285149 --- /dev/null
285151 @@ -0,0 +1,3526 @@
285158 +# Compiler: aarch64-himix200-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
285536 +CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image-dtb"
285537 +CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="hisilicon/hi3569v100-demb-flash"
285613 +# General architecture-dependent options
285671 +# GCOV-based kernel profiling
286130 +# Self-contained MTD device drivers
286142 +# Disk-On-Chip Device Drivers
286317 +# SCSI support type (disk, tape, CD-ROM)
286745 +# Non-8250 serial port support
286837 +# I2C system bus drivers (mostly embedded / system-on-chip)
287825 +# on-CPU RTC drivers
287849 +# Microsoft Hyper-V guest support
288113 +# CD-ROM/DVD Filesystems
288127 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
288222 +CONFIG_NLS_DEFAULT="iso8859-1"
288518 +# Compile-time checks and compiler options
288678 diff --git a/arch/arm64/include/mach/platform-hi3559av100.h b/arch/arm64/include/mach/platform-hi35…
288681 --- /dev/null
288682 +++ b/arch/arm64/include/mach/platform-hi3559av100.h
288683 @@ -0,0 +1,24 @@
288708 diff --git a/arch/arm64/include/mach/platform.h b/arch/arm64/include/mach/platform.h
288711 --- /dev/null
288713 @@ -0,0 +1,25 @@
288735 +#include "platform-hi3559av100.h"
288739 diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
288741 --- a/arch/arm64/kernel/pci.c
288743 @@ -33,6 +33,18 @@ int pcibios_alloc_irq(struct pci_dev *dev)
288754 + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
288762 diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
288764 --- a/arch/arm64/mm/init.c
288766 @@ -223,8 +223,18 @@ static void __init reserve_elfcorehdr(void)
288785 diff --git a/drivers/Kconfig b/drivers/Kconfig
288787 --- a/drivers/Kconfig
288789 @@ -219,4 +219,12 @@ source "drivers/siox/Kconfig"
288802 diff --git a/drivers/Makefile b/drivers/Makefile
288804 --- a/drivers/Makefile
288806 @@ -186,3 +186,7 @@ obj-$(CONFIG_MULTIPLEXER) += mux/
288807 obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/
288808 obj-$(CONFIG_SIOX) += siox/
288809 obj-$(CONFIG_GNSS) += gnss/
288810 +obj-$(CONFIG_HI_DMAC) += hidmac/
288811 +obj-$(CONFIG_HIEDMAC) += hiedmac/
288812 +obj-$(CONFIG_ARCH_HISI_BVT) += hisilicon/
288813 +obj-$(CONFIG_HI_VDMA_V100) += hi_vdmav100/
288814 diff --git a/drivers/acpi/acpi_configfs.c b/drivers/acpi/acpi_configfs.c
288816 --- a/drivers/acpi/acpi_configfs.c
288818 @@ -14,6 +14,7 @@
288826 @@ -31,7 +32,10 @@ static ssize_t acpi_table_aml_write(struct config_item *cfg,
288830 - int ret;
288838 diff --git a/drivers/android/binder.c b/drivers/android/binder.c
288840 --- a/drivers/android/binder.c
288842 @@ -2829,7 +2829,7 @@ static void binder_transaction(struct binder_proc *proc,
288844 return_error_param = -EINVAL;
288846 - goto err_invalid_target_handle;
288851 diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
288853 --- a/drivers/ata/Kconfig
288855 @@ -2,6 +2,7 @@
288863 diff --git a/drivers/ata/Kconfig.hiahci b/drivers/ata/Kconfig.hiahci
288866 --- /dev/null
288868 @@ -0,0 +1,44 @@
288887 + int "Hisi sata FIS-Based switching"
288892 + FBS is FIS-Based switching.
288913 diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
288915 --- a/drivers/ata/Makefile
288917 @@ -1,6 +1,7 @@
288918 # SPDX-License-Identifier: GPL-2.0
288920 obj-$(CONFIG_ATA) += libata.o
288921 +obj-$(CONFIG_HISI_SATA) += hisi_sata_dbg.o
288923 # non-SFF interface
288924 obj-$(CONFIG_SATA_AHCI) += ahci.o libahci.o
288925 diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
288927 --- a/drivers/ata/ahci.h
288929 @@ -240,6 +240,9 @@ enum {
288930 error-handling stage) */
288938 AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
288939 @@ -354,6 +357,13 @@ struct ahci_host_priv {
288953 diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
288955 --- a/drivers/ata/ahci_platform.c
288957 @@ -26,6 +26,16 @@
288974 @@ -63,8 +73,21 @@ static int ahci_probe(struct platform_device *pdev)
288975 of_property_read_u32(dev->of_node,
288976 "ports-implemented", &hpriv->force_port_map);
288979 + hpriv->type = ORI_AHCI;
288980 + hpriv->force_port_map = sata_port_map;
288982 + hpriv->flags |= AHCI_HFLAG_NO_SXS;
288987 + hpriv->flags |= AHCI_HFLAG_NO_NCQ;
288990 if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
288991 hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
288996 diff --git a/drivers/ata/hisi_sata_dbg.c b/drivers/ata/hisi_sata_dbg.c
288999 --- /dev/null
289001 @@ -0,0 +1,174 @@
289003 + * Copyright (c) 2009-2014 HiSilicon Technologies Co., Ltd.
289074 + pp = link->ap->private_data;
289080 + hisi_sata_phys_mem_dump((unsigned int)(pp->rx_fis_dma),
289095 + tf->flags, tf->protocol, tf->command, tf->device, tf->ctl);
289097 + tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
289099 + tf->hob_feature, tf->hob_nsect, tf->hob_lbal,
289100 + tf->hob_lbam, tf->hob_lbah);
289133 + pr_debug("dmac tx fifo:count-0x%x-empty-%x-ful-%x\n",
289136 + pr_debug("dmac rx fifo:count-0x%x-empty-%x-ful-%x\n",
289157 + pr_debug("link tx fifo:count-0x%x-empty-%x-ful-%x\n",
289160 + pr_debug("link rx fifo:count-0x%x-empty-%x-ful-%x\n",
289163 + pr_debug("link df fifo:count-0x%x-empty-%x-ful-%x\n\n",
289176 diff --git a/drivers/ata/hisi_sata_dbg.h b/drivers/ata/hisi_sata_dbg.h
289179 --- /dev/null
289181 @@ -0,0 +1,58 @@
289183 + * Copyright (c) 2009-2014 HiSilicon Technologies Co., Ltd.
289215 + pr_debug("------------------[ Start ]--------------------\n"); \
289218 + pr_debug("------------------[ End ]--------------------\n"); \
289240 diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
289242 --- a/drivers/ata/libahci.c
289244 @@ -47,6 +47,7 @@
289252 @@ -58,6 +59,33 @@ MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)
289286 @@ -509,6 +537,13 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
289291 + if ((cap & HOST_CAP_SXS) && (hpriv->flags & AHCI_HFLAG_NO_SXS)) {
289297 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
289298 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
289299 port_map, hpriv->force_port_map);
289300 @@ -1407,8 +1442,28 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
289305 + unsigned int port_num = ap->port_no;
289312 + (link->pmp == SATA_PMP_CTRL_PORT) &&
289313 + (hpriv->type == ORI_AHCI)) {
289314 + struct ahci_port_priv *pp = ap->private_data;
289316 + if (pp->fbs_enabled == false)
289326 /* prepare for SRST (AHCI-1.1 10.4.1) */
289328 if (rc && rc != -EOPNOTSUPP)
289329 @@ -1437,6 +1492,10 @@ int ahci_do_softreset(struct ata_link *link, unsigned int *class,
289331 rc = -EIO;
289334 + hisi_sata_reset_rxtx_assert(ap->port_no);
289335 + hisi_sata_reset_rxtx_deassert(ap->port_no);
289340 @@ -1634,6 +1693,68 @@ static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
289341 struct ata_port *ap = qc->ap;
289342 struct ahci_port_priv *pp = ap->private_data;
289345 + struct ahci_host_priv *hpriv = ap->host->private_data;
289346 + int is_atapi = ata_is_atapi(qc->tf.protocol);
289348 + unsigned int port_num = ap->port_no;
289352 + (ap->link.pmp == SATA_PMP_CTRL_PORT) &&
289353 + (hpriv->type == ORI_AHCI)) {
289354 + if (is_atapi || fbs_ctrl[ap->port_no].fbs_cmd_issue_flag) {
289368 + fbs_ctrl[ap->port_no].
289374 + if (pp->fbs_enabled == true)
289377 + ap->excl_link = NULL;
289378 + ap->nr_active_links = 0;
289381 + fbs_ctrl[ap->port_no].fbs_cmd_issue_flag = 0;
289398 + if (pp->fbs_enabled == false)
289406 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
289409 @@ -1680,6 +1801,7 @@ static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
289416 struct ahci_port_priv *pp = ap->private_data;
289417 @@ -1703,6 +1825,7 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
289419 dev_err(ap->host->dev, "failed to clear device error\n");
289425 @@ -1810,7 +1933,9 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
289435 @@ -2211,7 +2336,9 @@ static void ahci_enable_fbs(struct ata_port *ap)
289440 dev_info(ap->host->dev, "FBS is enabled\n");
289442 pp->fbs_enabled = true;
289443 pp->fbs_last_dev = -1; /* initialization */
289445 @@ -2251,6 +2378,9 @@ static void ahci_disable_fbs(struct ata_port *ap)
289448 hpriv->start_engine(ap);
289455 @@ -2259,12 +2389,24 @@ static void ahci_pmp_attach(struct ata_port *ap)
289456 struct ahci_port_priv *pp = ap->private_data;
289460 + struct ahci_host_priv *hpriv = ap->host->private_data;
289461 + unsigned int port_num = ap->port_no;
289471 + if (hpriv->type == ORI_AHCI) {
289477 pp->intr_mask |= PORT_IRQ_BAD_PMP;
289480 @@ -2333,6 +2475,32 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
289488 + unsigned int port_num = ap->port_no;
289490 + if (ap->link.pmp == SATA_PMP_CTRL_PORT) {
289499 + struct ata_port *ap = ata_fbs_ctrl_ptr->ap;
289512 struct ahci_host_priv *hpriv = ap->host->private_data;
289513 @@ -2426,6 +2594,19 @@ static int ahci_port_start(struct ata_port *ap)
289515 ap->private_data = pp;
289518 + if (hpriv->type == ORI_AHCI) {
289519 + fbs_ctrl[ap->port_no].fbs_enable_ctrl = fbs_en;
289520 + fbs_ctrl[ap->port_no].fbs_enable_flag = 0;
289521 + fbs_ctrl[ap->port_no].fbs_disable_flag = 0;
289522 + fbs_ctrl[ap->port_no].fbs_cmd_issue_flag = 0;
289523 + fbs_ctrl[ap->port_no].ap = ap;
289525 + timer_setup(&fbs_ctrl[ap->port_no].poll_timer, ahci_poll_timerout, 0);
289526 + fbs_ctrl[ap->port_no].poll_timer.expires = jiffies + AHCI_POLL_TIMER;
289533 diff --git a/drivers/block/paride/pcd.c b/drivers/block/paride/pcd.c
289535 --- a/drivers/block/paride/pcd.c
289537 @@ -983,8 +983,14 @@ static int __init pcd_init(void)
289541 - for (unit = 0, cd = pcd; unit < PCD_UNITS; unit++, cd++)
289543 + if (!cd->disk)
289546 + blk_cleanup_queue(cd->disk->queue);
289547 + blk_mq_free_tag_set(&cd->tag_set);
289548 put_disk(cd->disk);
289550 return -EBUSY;
289553 @@ -1005,6 +1011,9 @@ static void __exit pcd_exit(void)
289557 + if (!cd->disk)
289560 if (cd->present) {
289561 del_gendisk(cd->disk);
289562 pi_release(cd->pi);
289563 diff --git a/drivers/block/paride/pf.c b/drivers/block/paride/pf.c
289565 --- a/drivers/block/paride/pf.c
289567 @@ -998,8 +998,13 @@ static int __init pf_init(void)
289571 - for (pf = units, unit = 0; unit < PF_UNITS; pf++, unit++)
289573 + if (!pf->disk)
289575 + blk_cleanup_queue(pf->disk->queue);
289576 + blk_mq_free_tag_set(&pf->tag_set);
289577 put_disk(pf->disk);
289579 return -EBUSY;
289582 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
289584 --- a/drivers/clk/Makefile
289586 @@ -70,6 +70,7 @@ obj-$(CONFIG_ARCH_BERLIN) += berlin/
289587 obj-$(CONFIG_ARCH_DAVINCI) += davinci/
289588 obj-$(CONFIG_H8300) += h8300/
289589 obj-$(CONFIG_ARCH_HISI) += hisilicon/
289590 +obj-$(CONFIG_ARCH_HISI_BVT) += hisilicon/
289591 obj-y += imgtec/
289592 obj-$(CONFIG_ARCH_MXC) += imx/
289593 obj-$(CONFIG_MACH_INGENIC) += ingenic/
289594 diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
289596 --- a/drivers/clk/hisilicon/Kconfig
289598 @@ -21,6 +21,38 @@ config COMMON_CLK_HI3660
289637 @@ -29,6 +61,166 @@ config COMMON_CLK_HI3798CV200
289804 @@ -38,7 +230,7 @@ config COMMON_CLK_HI6220
289808 - depends on ARCH_HISI || COMPILE_TEST
289813 diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
289815 --- a/drivers/clk/hisilicon/Makefile
289817 @@ -13,6 +13,30 @@ obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
289818 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
289819 obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
289820 obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
289821 +obj-$(CONFIG_COMMON_CLK_HI3531DV200) += clk-hi3531dv200.o
289822 +obj-$(CONFIG_COMMON_CLK_HI3535AV100) += clk-hi3535av100.o
289823 +obj-$(CONFIG_COMMON_CLK_HI3521DV200) += clk-hi3521dv200.o
289824 +obj-$(CONFIG_COMMON_CLK_HI3520DV500) += clk-hi3521dv200.o
289825 +obj-$(CONFIG_COMMON_CLK_HI3516A) += clk-hi3516a.o
289826 +obj-$(CONFIG_COMMON_CLK_HI3516CV500) += clk-hi3516cv500.o
289827 +obj-$(CONFIG_COMMON_CLK_HI3516DV300) += clk-hi3516dv300.o
289828 +obj-$(CONFIG_COMMON_CLK_HI3556V200) += clk-hi3556v200.o
289829 +obj-$(CONFIG_COMMON_CLK_HI3559V200) += clk-hi3559v200.o
289830 +obj-$(CONFIG_COMMON_CLK_HI3562V100) += clk-hi3559v200.o
289831 +obj-$(CONFIG_COMMON_CLK_HI3566V100) += clk-hi3559v200.o
289832 +obj-$(CONFIG_COMMON_CLK_HI3518EV20X) += clk-hi3518ev20x.o
289833 +obj-$(CONFIG_COMMON_CLK_HI3536DV100) += clk-hi3536dv100.o
289834 +obj-$(CONFIG_COMMON_CLK_HI3521A) += clk-hi3521a.o
289835 +obj-$(CONFIG_COMMON_CLK_HI3531A) += clk-hi3531a.o
289836 +obj-$(CONFIG_COMMON_CLK_HI3556AV100) += clk-hi3556av100.o
289837 +obj-$(CONFIG_COMMON_CLK_HI3519AV100) += clk-hi3519av100.o
289838 +obj-$(CONFIG_COMMON_CLK_HI3568V100) += clk-hi3519av100.o
289839 +obj-$(CONFIG_COMMON_CLK_HI3516EV200) += clk-hi3516ev200.o
289840 +obj-$(CONFIG_COMMON_CLK_HI3516EV300) += clk-hi3516ev300.o
289841 +obj-$(CONFIG_COMMON_CLK_HI3518EV300) += clk-hi3518ev300.o
289842 +obj-$(CONFIG_COMMON_CLK_HI3516DV200) += clk-hi3516dv200.o
289843 +obj-$(CONFIG_COMMON_CLK_HI3559AV100) += clk-hi3559av100.o
289844 +obj-$(CONFIG_COMMON_CLK_HI3569V100) += clk-hi3559av100.o
289845 obj-$(CONFIG_RESET_HISI) += reset.o
289846 obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
289847 obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o
289848 diff --git a/drivers/clk/hisilicon/clk-hi3516a.c b/drivers/clk/hisilicon/clk-hi3516a.c
289851 --- /dev/null
289852 +++ b/drivers/clk/hisilicon/clk-hi3516a.c
289853 @@ -0,0 +1,525 @@
289857 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
289874 +#include <dt-bindings/clock/hi3516a-clock.h>
289875 +#include <linux/clk-provider.h>
290142 + val = readl_relaxed(clk->ctrl_reg1);
290143 + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
290144 + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
290145 + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
290147 + val |= frac_val << clk->frac_shift;
290148 + val |= postdiv1_val << clk->postdiv1_shift;
290149 + val |= postdiv2_val << clk->postdiv2_shift;
290150 + writel_relaxed(val, clk->ctrl_reg1);
290152 + val = readl_relaxed(clk->ctrl_reg2);
290153 + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
290154 + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
290156 + val |= fbdiv_val << clk->fbdiv_shift;
290157 + val |= refdiv_val << clk->refdiv_shift;
290158 + writel_relaxed(val, clk->ctrl_reg2);
290171 + val = readl_relaxed(clk->ctrl_reg1);
290172 + val = val >> clk->frac_shift;
290173 + val &= ((1 << clk->frac_width) - 1);
290176 + val = readl_relaxed(clk->ctrl_reg2);
290177 + val = val >> clk->fbdiv_shift;
290178 + val &= ((1 << clk->fbdiv_width) - 1);
290181 + val = readl_relaxed(clk->ctrl_reg2);
290182 + val = val >> clk->refdiv_shift;
290183 + val &= ((1 << clk->refdiv_width) - 1);
290198 + return req->rate;
290210 + void __iomem *base = data->base;
290220 + return -1;
290229 + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
290230 + p_clk->frac_shift = clks[i].frac_shift;
290231 + p_clk->frac_width = clks[i].frac_width;
290232 + p_clk->postdiv1_shift = clks[i].postdiv1_shift;
290233 + p_clk->postdiv1_width = clks[i].postdiv1_width;
290234 + p_clk->postdiv2_shift = clks[i].postdiv2_shift;
290235 + p_clk->postdiv2_width = clks[i].postdiv2_width;
290237 + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
290238 + p_clk->fbdiv_shift = clks[i].fbdiv_shift;
290239 + p_clk->fbdiv_width = clks[i].fbdiv_width;
290240 + p_clk->refdiv_shift = clks[i].refdiv_shift;
290241 + p_clk->refdiv_width = clks[i].refdiv_width;
290242 + p_clk->hw.init = &init;
290244 + clk = clk_register(NULL, &p_clk->hw);
290252 + data->clk_data.clks[clks[i].id] = clk;
290296 + of_clk_src_onecell_get, &clk_data->clk_data);
290300 + if (!of_property_read_u32(np, "#reset-cells", &count) && (count == 2))
290322 +CLK_OF_DECLARE(hi3516a_clk_crg, "hisilicon,hi3516a-clock",
290363 + __func__, np->name);
290371 + __func__, np->name);
290379 diff --git a/drivers/clk/hisilicon/clk-hi3516cv500.c b/drivers/clk/hisilicon/clk-hi3516cv500.c
290382 --- /dev/null
290383 +++ b/drivers/clk/hisilicon/clk-hi3516cv500.c
290384 @@ -0,0 +1,261 @@
290386 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
290403 +#include <dt-bindings/clock/hi3516cv500-clock.h>
290404 +#include <linux/clk-provider.h>
290643 +CLK_OF_DECLARE(hi3516cv500_clk, "hisilicon,hi3516cv500-clock",
290646 diff --git a/drivers/clk/hisilicon/clk-hi3516dv200.c b/drivers/clk/hisilicon/clk-hi3516dv200.c
290649 --- /dev/null
290650 +++ b/drivers/clk/hisilicon/clk-hi3516dv200.c
290651 @@ -0,0 +1,251 @@
290672 +#include <dt-bindings/clock/hi3516dv200-clock.h>
290673 +#include <linux/clk-provider.h>
290900 +CLK_OF_DECLARE(hi3516dv200_clk, "hisilicon,hi3516dv200-clock",
290903 diff --git a/drivers/clk/hisilicon/clk-hi3516dv300.c b/drivers/clk/hisilicon/clk-hi3516dv300.c
290906 --- /dev/null
290907 +++ b/drivers/clk/hisilicon/clk-hi3516dv300.c
290908 @@ -0,0 +1,271 @@
290910 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
290927 +#include <dt-bindings/clock/hi3516dv300-clock.h>
290928 +#include <linux/clk-provider.h>
291177 +CLK_OF_DECLARE(hi3516dv300_clk, "hisilicon,hi3516dv300-clock",
291180 diff --git a/drivers/clk/hisilicon/clk-hi3516ev200.c b/drivers/clk/hisilicon/clk-hi3516ev200.c
291183 --- /dev/null
291184 +++ b/drivers/clk/hisilicon/clk-hi3516ev200.c
291185 @@ -0,0 +1,244 @@
291189 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
291206 +#include <dt-bindings/clock/hi3516ev200-clock.h>
291207 +#include <linux/clk-provider.h>
291428 +CLK_OF_DECLARE(hi3516ev200_clk, "hisilicon,hi3516ev200-clock",
291430 diff --git a/drivers/clk/hisilicon/clk-hi3516ev300.c b/drivers/clk/hisilicon/clk-hi3516ev300.c
291433 --- /dev/null
291434 +++ b/drivers/clk/hisilicon/clk-hi3516ev300.c
291435 @@ -0,0 +1,241 @@
291439 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
291456 +#include <dt-bindings/clock/hi3516ev300-clock.h>
291457 +#include <linux/clk-provider.h>
291674 +CLK_OF_DECLARE(hi3516ev300_clk, "hisilicon,hi3516ev300-clock",
291677 diff --git a/drivers/clk/hisilicon/clk-hi3518ev20x.c b/drivers/clk/hisilicon/clk-hi3518ev20x.c
291680 --- /dev/null
291681 +++ b/drivers/clk/hisilicon/clk-hi3518ev20x.c
291682 @@ -0,0 +1,291 @@
291686 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
291703 +#include <dt-bindings/clock/hi3518ev20x-clock.h>
291704 +#include <linux/clk-provider.h>
291892 + of_clk_src_onecell_get, &clk_data->clk_data);
291896 + if (!of_property_read_u32(np, "#reset-cells", &count) && (count == 2))
291918 +CLK_OF_DECLARE(hi3518ev20x_clk_crg, "hisilicon,hi3518ev20x-clock",
291959 + __func__, np->name);
291967 + __func__, np->name);
291974 diff --git a/drivers/clk/hisilicon/clk-hi3518ev300.c b/drivers/clk/hisilicon/clk-hi3518ev300.c
291977 --- /dev/null
291978 +++ b/drivers/clk/hisilicon/clk-hi3518ev300.c
291979 @@ -0,0 +1,240 @@
291983 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
292000 +#include <dt-bindings/clock/hi3518ev300-clock.h>
292001 +#include <linux/clk-provider.h>
292218 +CLK_OF_DECLARE(hi3518ev300_clk, "hisilicon,hi3518ev300-clock",
292220 diff --git a/drivers/clk/hisilicon/clk-hi3519av100.c b/drivers/clk/hisilicon/clk-hi3519av100.c
292223 --- /dev/null
292224 +++ b/drivers/clk/hisilicon/clk-hi3519av100.c
292225 @@ -0,0 +1,559 @@
292229 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
292247 +#include <dt-bindings/clock/hi3519av100-clock.h>
292636 + val = readl_relaxed(clk->ctrl_reg1);
292637 + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
292638 + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
292639 + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
292641 + val |= frac_val << clk->frac_shift;
292642 + val |= postdiv1_val << clk->postdiv1_shift;
292643 + val |= postdiv2_val << clk->postdiv2_shift;
292644 + writel_relaxed(val, clk->ctrl_reg1);
292646 + val = readl_relaxed(clk->ctrl_reg2);
292647 + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
292648 + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
292650 + val |= fbdiv_val << clk->fbdiv_shift;
292651 + val |= refdiv_val << clk->refdiv_shift;
292652 + writel_relaxed(val, clk->ctrl_reg2);
292666 + val = readl_relaxed(clk->ctrl_reg1);
292667 + val = val >> clk->frac_shift;
292668 + val &= ((1 << clk->frac_width) - 1);
292671 + val = readl_relaxed(clk->ctrl_reg2);
292672 + val = val >> clk->fbdiv_shift;
292673 + val &= ((1 << clk->fbdiv_width) - 1);
292676 + val = readl_relaxed(clk->ctrl_reg2);
292677 + val = val >> clk->refdiv_shift;
292678 + val &= ((1 << clk->refdiv_width) - 1);
292697 + return req->rate;
292715 + base = data->base;
292732 + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
292733 + p_clk->frac_shift = clks[i].frac_shift;
292734 + p_clk->frac_width = clks[i].frac_width;
292735 + p_clk->postdiv1_shift = clks[i].postdiv1_shift;
292736 + p_clk->postdiv1_width = clks[i].postdiv1_width;
292737 + p_clk->postdiv2_shift = clks[i].postdiv2_shift;
292738 + p_clk->postdiv2_width = clks[i].postdiv2_width;
292740 + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
292741 + p_clk->fbdiv_shift = clks[i].fbdiv_shift;
292742 + p_clk->fbdiv_width = clks[i].fbdiv_width;
292743 + p_clk->refdiv_shift = clks[i].refdiv_shift;
292744 + p_clk->refdiv_width = clks[i].refdiv_width;
292745 + p_clk->hw.init = &init;
292747 + clk = clk_register(NULL, &p_clk->hw);
292755 + data->clk_data.clks[clks[i].id] = clk;
292783 +CLK_OF_DECLARE(hi3519av100_clk, "hisilicon,hi3519av100-clock",
292785 diff --git a/drivers/clk/hisilicon/clk-hi3521a.c b/drivers/clk/hisilicon/clk-hi3521a.c
292788 --- /dev/null
292789 +++ b/drivers/clk/hisilicon/clk-hi3521a.c
292790 @@ -0,0 +1,288 @@
292794 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
292811 +#include <dt-bindings/clock/hi3521a-clock.h>
292812 +#include <linux/clk-provider.h>
292973 + of_clk_src_onecell_get, &clk_data->clk_data);
292977 + if (!of_property_read_u32(np, "#reset-cells", &count) && (count == 2))
292999 +CLK_OF_DECLARE(hi3521a_clk_crg, "hisilicon,hi3521a-clock",
293064 + __func__, np->name);
293072 + __func__, np->name);
293079 diff --git a/drivers/clk/hisilicon/clk-hi3521dv200.c b/drivers/clk/hisilicon/clk-hi3521dv200.c
293082 --- /dev/null
293083 +++ b/drivers/clk/hisilicon/clk-hi3521dv200.c
293084 @@ -0,0 +1,255 @@
293088 + * Copyright (c) 2019-2020 HiSilicon Technologies Co., Ltd.
293105 +#include <dt-bindings/clock/hi3521dv200-clock.h>
293106 +#include <linux/clk-provider.h>
293337 +CLK_OF_DECLARE(hi3521dv200_clk, "hisilicon,hi3521dv200-clock",
293340 diff --git a/drivers/clk/hisilicon/clk-hi3531a.c b/drivers/clk/hisilicon/clk-hi3531a.c
293343 --- /dev/null
293344 +++ b/drivers/clk/hisilicon/clk-hi3531a.c
293345 @@ -0,0 +1,323 @@
293349 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
293366 +#include <dt-bindings/clock/hi3531a-clock.h>
293367 +#include <linux/clk-provider.h>
293563 + of_clk_src_onecell_get, &clk_data->clk_data);
293567 + if (!of_property_read_u32(np, "#reset-cells", &count) && (count == 2))
293589 +CLK_OF_DECLARE(hi3531a_clk_crg, "hisilicon,hi3531a-clock",
293654 + __func__, np->name);
293662 + __func__, np->name);
293669 diff --git a/drivers/clk/hisilicon/clk-hi3531dv200.c b/drivers/clk/hisilicon/clk-hi3531dv200.c
293672 --- /dev/null
293673 +++ b/drivers/clk/hisilicon/clk-hi3531dv200.c
293674 @@ -0,0 +1,578 @@
293678 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
293695 +#include <dt-bindings/clock/hi3531dv200-clock.h>
293696 +#include <linux/clk-provider.h>
293992 + val = readl_relaxed(clk->ctrl_reg1);
293993 + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
293994 + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
293995 + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
293997 + val |= frac_val << clk->frac_shift;
293998 + val |= postdiv1_val << clk->postdiv1_shift;
293999 + val |= postdiv2_val << clk->postdiv2_shift;
294000 + writel_relaxed(val, clk->ctrl_reg1);
294002 + val = readl_relaxed(clk->ctrl_reg2);
294003 + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
294004 + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
294006 + val |= fbdiv_val << clk->fbdiv_shift;
294007 + val |= refdiv_val << clk->refdiv_shift;
294008 + writel_relaxed(val, clk->ctrl_reg2);
294021 + val = readl_relaxed(clk->ctrl_reg1);
294022 + val = val >> clk->frac_shift;
294023 + val &= ((1 << clk->frac_width) - 1);
294026 + val = readl_relaxed(clk->ctrl_reg2);
294027 + val = val >> clk->fbdiv_shift;
294028 + val &= ((1 << clk->fbdiv_width) - 1);
294031 + val = readl_relaxed(clk->ctrl_reg2);
294032 + val = val >> clk->refdiv_shift;
294033 + val &= ((1 << clk->refdiv_width) - 1);
294048 + return req->rate;
294060 + void __iomem *base = data->base;
294079 + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
294080 + p_clk->frac_shift = clks[i].frac_shift;
294081 + p_clk->frac_width = clks[i].frac_width;
294082 + p_clk->postdiv1_shift = clks[i].postdiv1_shift;
294083 + p_clk->postdiv1_width = clks[i].postdiv1_width;
294084 + p_clk->postdiv2_shift = clks[i].postdiv2_shift;
294085 + p_clk->postdiv2_width = clks[i].postdiv2_width;
294087 + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
294088 + p_clk->fbdiv_shift = clks[i].fbdiv_shift;
294089 + p_clk->fbdiv_width = clks[i].fbdiv_width;
294090 + p_clk->refdiv_shift = clks[i].refdiv_shift;
294091 + p_clk->refdiv_width = clks[i].refdiv_width;
294092 + p_clk->hw.init = &init;
294094 + clk = clk_register(NULL, &p_clk->hw);
294102 + data->clk_data.clks[clks[i].id] = clk;
294114 + return ERR_PTR(-ENOMEM);
294141 + ret = of_clk_add_provider(pdev->dev.of_node,
294142 + of_clk_src_onecell_get, &clk_data->clk_data);
294168 + of_clk_del_provider(pdev->dev.of_node);
294171 + ARRAY_SIZE(hi3531dv200_gate_clks), crg->clk_data);
294173 + ARRAY_SIZE(hi3531dv200_mux_clks_crg), crg->clk_data);
294175 + ARRAY_SIZE(hi3531dv200_fixed_factor_clks), crg->clk_data);
294177 + ARRAY_SIZE(hi3531dv200_fixed_rate_clks_crg), crg->clk_data);
294188 + .compatible = "hisilicon,hi3531dv200-clock",
294199 + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
294201 + return -ENOMEM;
294203 + crg->funcs = of_device_get_match_data(&pdev->dev);
294204 + if (!crg->funcs)
294205 + return -ENOENT;
294207 + crg->rstc = hisi_reset_init(pdev);
294208 + if (!crg->rstc)
294209 + return -ENOMEM;
294211 + crg->clk_data = crg->funcs->register_clks(pdev);
294212 + if (IS_ERR(crg->clk_data)) {
294213 + hisi_reset_exit(crg->rstc);
294214 + return PTR_ERR(crg->clk_data);
294225 + hisi_reset_exit(crg->rstc);
294226 + crg->funcs->unregister_clks(pdev);
294234 + .name = "hi3531dv200-clock",
294253 diff --git a/drivers/clk/hisilicon/clk-hi3535av100.c b/drivers/clk/hisilicon/clk-hi3535av100.c
294256 --- /dev/null
294257 +++ b/drivers/clk/hisilicon/clk-hi3535av100.c
294258 @@ -0,0 +1,570 @@
294262 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
294279 +#include <dt-bindings/clock/hi3535av100-clock.h>
294280 +#include <linux/clk-provider.h>
294570 + val = readl_relaxed(clk->ctrl_reg1);
294571 + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
294572 + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
294573 + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
294575 + val |= frac_val << clk->frac_shift;
294576 + val |= postdiv1_val << clk->postdiv1_shift;
294577 + val |= postdiv2_val << clk->postdiv2_shift;
294578 + writel_relaxed(val, clk->ctrl_reg1);
294580 + val = readl_relaxed(clk->ctrl_reg2);
294581 + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
294582 + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
294584 + val |= fbdiv_val << clk->fbdiv_shift;
294585 + val |= refdiv_val << clk->refdiv_shift;
294586 + writel_relaxed(val, clk->ctrl_reg2);
294599 + val = readl_relaxed(clk->ctrl_reg1);
294600 + val = val >> clk->frac_shift;
294601 + val &= ((1 << clk->frac_width) - 1);
294604 + val = readl_relaxed(clk->ctrl_reg2);
294605 + val = val >> clk->fbdiv_shift;
294606 + val &= ((1 << clk->fbdiv_width) - 1);
294609 + val = readl_relaxed(clk->ctrl_reg2);
294610 + val = val >> clk->refdiv_shift;
294611 + val &= ((1 << clk->refdiv_width) - 1);
294626 + return req->rate;
294638 + void __iomem *base = data->base;
294657 + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
294658 + p_clk->frac_shift = clks[i].frac_shift;
294659 + p_clk->frac_width = clks[i].frac_width;
294660 + p_clk->postdiv1_shift = clks[i].postdiv1_shift;
294661 + p_clk->postdiv1_width = clks[i].postdiv1_width;
294662 + p_clk->postdiv2_shift = clks[i].postdiv2_shift;
294663 + p_clk->postdiv2_width = clks[i].postdiv2_width;
294665 + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
294666 + p_clk->fbdiv_shift = clks[i].fbdiv_shift;
294667 + p_clk->fbdiv_width = clks[i].fbdiv_width;
294668 + p_clk->refdiv_shift = clks[i].refdiv_shift;
294669 + p_clk->refdiv_width = clks[i].refdiv_width;
294670 + p_clk->hw.init = &init;
294672 + clk = clk_register(NULL, &p_clk->hw);
294680 + data->clk_data.clks[clks[i].id] = clk;
294692 + return ERR_PTR(-ENOMEM);
294717 + ret = of_clk_add_provider(pdev->dev.of_node,
294718 + of_clk_src_onecell_get, &clk_data->clk_data);
294743 + of_clk_del_provider(pdev->dev.of_node);
294746 + ARRAY_SIZE(hi3535av100_gate_clks), crg->clk_data);
294748 + ARRAY_SIZE(hi3535av100_mux_clks_crg), crg->clk_data);
294750 + ARRAY_SIZE(hi3535av100_fixed_factor_clks), crg->clk_data);
294752 + ARRAY_SIZE(hi3535av100_fixed_rate_clks_crg), crg->clk_data);
294763 + .compatible = "hisilicon,hi3535av100-clock",
294774 + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
294776 + return -ENOMEM;
294778 + crg->funcs = of_device_get_match_data(&pdev->dev);
294779 + if (!crg->funcs)
294780 + return -ENOENT;
294782 + crg->rstc = hisi_reset_init(pdev);
294783 + if (!crg->rstc)
294784 + return -ENOMEM;
294786 + crg->clk_data = crg->funcs->register_clks(pdev);
294787 + if (IS_ERR(crg->clk_data)) {
294788 + hisi_reset_exit(crg->rstc);
294789 + return PTR_ERR(crg->clk_data);
294800 + hisi_reset_exit(crg->rstc);
294801 + crg->funcs->unregister_clks(pdev);
294809 + .name = "hi3535av100-clock",
294829 diff --git a/drivers/clk/hisilicon/clk-hi3536dv100.c b/drivers/clk/hisilicon/clk-hi3536dv100.c
294832 --- /dev/null
294833 +++ b/drivers/clk/hisilicon/clk-hi3536dv100.c
294834 @@ -0,0 +1,270 @@
294838 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
294855 +#include <dt-bindings/clock/hi3536dv100-clock.h>
294856 +#include <linux/clk-provider.h>
294999 + of_clk_src_onecell_get, &clk_data->clk_data);
295003 + if (!of_property_read_u32(np, "#reset-cells", &count) && (count == 2))
295025 +CLK_OF_DECLARE(hi3536dv100_clk_crg, "hisilicon,hi3536dv100-clock",
295090 + __func__, np->name);
295098 + __func__, np->name);
295105 diff --git a/drivers/clk/hisilicon/clk-hi3556av100.c b/drivers/clk/hisilicon/clk-hi3556av100.c
295108 --- /dev/null
295109 +++ b/drivers/clk/hisilicon/clk-hi3556av100.c
295110 @@ -0,0 +1,566 @@
295114 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
295132 +#include <dt-bindings/clock/hi3556av100-clock.h>
295528 + val = readl_relaxed(clk->ctrl_reg1);
295529 + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
295530 + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
295531 + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
295533 + val |= frac_val << clk->frac_shift;
295534 + val |= postdiv1_val << clk->postdiv1_shift;
295535 + val |= postdiv2_val << clk->postdiv2_shift;
295536 + writel_relaxed(val, clk->ctrl_reg1);
295538 + val = readl_relaxed(clk->ctrl_reg2);
295539 + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
295540 + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
295542 + val |= fbdiv_val << clk->fbdiv_shift;
295543 + val |= refdiv_val << clk->refdiv_shift;
295544 + writel_relaxed(val, clk->ctrl_reg2);
295558 + val = readl_relaxed(clk->ctrl_reg1);
295559 + val = val >> clk->frac_shift;
295560 + val &= ((1 << clk->frac_width) - 1);
295563 + val = readl_relaxed(clk->ctrl_reg2);
295564 + val = val >> clk->fbdiv_shift;
295565 + val &= ((1 << clk->fbdiv_width) - 1);
295568 + val = readl_relaxed(clk->ctrl_reg2);
295569 + val = val >> clk->refdiv_shift;
295570 + val &= ((1 << clk->refdiv_width) - 1);
295589 + return req->rate;
295607 + base = data->base;
295624 + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
295625 + p_clk->frac_shift = clks[i].frac_shift;
295626 + p_clk->frac_width = clks[i].frac_width;
295627 + p_clk->postdiv1_shift = clks[i].postdiv1_shift;
295628 + p_clk->postdiv1_width = clks[i].postdiv1_width;
295629 + p_clk->postdiv2_shift = clks[i].postdiv2_shift;
295630 + p_clk->postdiv2_width = clks[i].postdiv2_width;
295632 + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
295633 + p_clk->fbdiv_shift = clks[i].fbdiv_shift;
295634 + p_clk->fbdiv_width = clks[i].fbdiv_width;
295635 + p_clk->refdiv_shift = clks[i].refdiv_shift;
295636 + p_clk->refdiv_width = clks[i].refdiv_width;
295637 + p_clk->hw.init = &init;
295639 + clk = clk_register(NULL, &p_clk->hw);
295647 + data->clk_data.clks[clks[i].id] = clk;
295675 +CLK_OF_DECLARE(hi3556av100_clk, "hisilicon,hi3556av100-clock",
295677 diff --git a/drivers/clk/hisilicon/clk-hi3556v200.c b/drivers/clk/hisilicon/clk-hi3556v200.c
295680 --- /dev/null
295681 +++ b/drivers/clk/hisilicon/clk-hi3556v200.c
295682 @@ -0,0 +1,274 @@
295684 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
295701 +#include <dt-bindings/clock/hi3556v200-clock.h>
295702 +#include <linux/clk-provider.h>
295955 +CLK_OF_DECLARE(hi3556v200_clk, "hisilicon,hi3556v200-clock",
295957 diff --git a/drivers/clk/hisilicon/clk-hi3559av100.c b/drivers/clk/hisilicon/clk-hi3559av100.c
295960 --- /dev/null
295961 +++ b/drivers/clk/hisilicon/clk-hi3559av100.c
295962 @@ -0,0 +1,882 @@
295966 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
295983 +#include <dt-bindings/clock/hi3559av100-clock.h>
295984 +#include <linux/clk-provider.h>
296359 + val = readl_relaxed(clk->ctrl_reg1);
296360 + val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
296361 + val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
296362 + val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
296364 + val |= frac_val << clk->frac_shift;
296365 + val |= postdiv1_val << clk->postdiv1_shift;
296366 + val |= postdiv2_val << clk->postdiv2_shift;
296367 + writel_relaxed(val, clk->ctrl_reg1);
296369 + val = readl_relaxed(clk->ctrl_reg2);
296370 + val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
296371 + val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
296373 + val |= fbdiv_val << clk->fbdiv_shift;
296374 + val |= refdiv_val << clk->refdiv_shift;
296375 + writel_relaxed(val, clk->ctrl_reg2);
296389 + val = readl_relaxed(clk->ctrl_reg1);
296390 + val = val >> clk->frac_shift;
296391 + val &= ((1 << clk->frac_width) - 1);
296394 + val = readl_relaxed(clk->ctrl_reg1);
296395 + val = val >> clk->postdiv1_shift;
296396 + val &= ((1 << clk->postdiv1_width) - 1);
296399 + val = readl_relaxed(clk->ctrl_reg1);
296400 + val = val >> clk->postdiv2_shift;
296401 + val &= ((1 << clk->postdiv2_width) - 1);
296404 + val = readl_relaxed(clk->ctrl_reg2);
296405 + val = val >> clk->fbdiv_shift;
296406 + val &= ((1 << clk->fbdiv_width) - 1);
296409 + val = readl_relaxed(clk->ctrl_reg2);
296410 + val = val >> clk->refdiv_shift;
296411 + val &= ((1 << clk->refdiv_width) - 1);
296431 + return req->rate;
296443 + void __iomem *base = data->base;
296465 + p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
296466 + p_clk->frac_shift = clks[i].frac_shift;
296467 + p_clk->frac_width = clks[i].frac_width;
296468 + p_clk->postdiv1_shift = clks[i].postdiv1_shift;
296469 + p_clk->postdiv1_width = clks[i].postdiv1_width;
296470 + p_clk->postdiv2_shift = clks[i].postdiv2_shift;
296471 + p_clk->postdiv2_width = clks[i].postdiv2_width;
296473 + p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
296474 + p_clk->fbdiv_shift = clks[i].fbdiv_shift;
296475 + p_clk->fbdiv_width = clks[i].fbdiv_width;
296476 + p_clk->refdiv_shift = clks[i].refdiv_shift;
296477 + p_clk->refdiv_width = clks[i].refdiv_width;
296478 + p_clk->hw.init = &init;
296480 + clk = clk_register(NULL, &p_clk->hw);
296488 + data->clk_data.clks[clks[i].id] = clk;
296500 + return ERR_PTR(-ENOMEM);
296525 + ret = of_clk_add_provider(pdev->dev.of_node,
296526 + of_clk_src_onecell_get, &clk_data->clk_data);
296551 + of_clk_del_provider(pdev->dev.of_node);
296554 + ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
296556 + ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
296558 + ARRAY_SIZE(hi3559av100_fixed_factor_clks), crg->clk_data);
296560 + ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
296704 + return ERR_PTR(-ENOMEM);
296726 + ret = of_clk_add_provider(pdev->dev.of_node,
296727 + of_clk_src_onecell_get, &clk_data->clk_data);
296752 + of_clk_del_provider(pdev->dev.of_node);
296755 + ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
296757 + ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
296759 + ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
296761 + ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);
296773 + .compatible = "hisilicon,hi3559av100-clock",
296778 + .compatible = "hisilicon,hi3559av100-shub-clock",
296790 + crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
296792 + return -ENOMEM;
296794 + crg->funcs = of_device_get_match_data(&pdev->dev);
296795 + if (!crg->funcs)
296796 + return -ENOENT;
296798 + crg->rstc = hisi_reset_init(pdev);
296799 + if (!crg->rstc)
296800 + return -ENOMEM;
296802 + crg->clk_data = crg->funcs->register_clks(pdev);
296803 + if (IS_ERR(crg->clk_data)) {
296804 + hisi_reset_exit(crg->rstc);
296805 + return PTR_ERR(crg->clk_data);
296816 + hisi_reset_exit(crg->rstc);
296817 + crg->funcs->unregister_clks(pdev);
296825 + .name = "hi3559av100-clock",
296845 diff --git a/drivers/clk/hisilicon/clk-hi3559v200.c b/drivers/clk/hisilicon/clk-hi3559v200.c
296848 --- /dev/null
296849 +++ b/drivers/clk/hisilicon/clk-hi3559v200.c
296850 @@ -0,0 +1,271 @@
296852 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
296869 +#include <dt-bindings/clock/hi3559v200-clock.h>
296870 +#include <linux/clk-provider.h>
297120 +CLK_OF_DECLARE(hi3559v200_clk, "hisilicon,hi3559v200-clock",
297122 diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c
297124 --- a/drivers/clk/hisilicon/clk-hisi-phase.c
297125 +++ b/drivers/clk/hisilicon/clk-hisi-phase.c
297126 @@ -77,7 +77,7 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
297128 val = clk_readl(phase->reg);
297129 val &= ~phase->mask;
297130 - val |= regval << phase->shift;
297131 + val |= (unsigned int)regval << phase->shift;
297132 clk_writel(val, phase->reg);
297134 spin_unlock_irqrestore(phase->lock, flags);
297135 diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c
297137 --- a/drivers/clk/hisilicon/clk.c
297139 @@ -96,6 +96,10 @@ struct hisi_clock_data *hisi_clk_init(struct device_node *np,
297140 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
297150 diff --git a/drivers/clk/hisilicon/crg.h b/drivers/clk/hisilicon/crg.h
297152 --- a/drivers/clk/hisilicon/crg.h
297154 @@ -22,7 +22,7 @@ struct hisi_reset_controller;
297158 - void (*unregister_clks)(struct platform_device *pdev);
297163 diff --git a/drivers/clk/hisilicon/reset.c b/drivers/clk/hisilicon/reset.c
297165 --- a/drivers/clk/hisilicon/reset.c
297167 @@ -99,6 +99,36 @@ static const struct reset_control_ops hisi_reset_ops = {
297179 + return -ENOMEM;
297181 + rstc->membase = of_iomap(np, 0);
297182 + if (!rstc->membase){
297184 + return -EINVAL;
297187 + spin_lock_init(&rstc->lock);
297189 + rstc->rcdev.owner = THIS_MODULE;
297190 + rstc->rcdev.nr_resets = nr_rsts;
297191 + rstc->rcdev.ops = &hisi_reset_ops;
297192 + rstc->rcdev.of_node = np;
297193 + rstc->rcdev.of_reset_n_cells = 2;
297194 + rstc->rcdev.of_xlate = hisi_reset_of_xlate;
297196 + return reset_controller_register(&rstc->rcdev);
297204 diff --git a/drivers/clk/hisilicon/reset.h b/drivers/clk/hisilicon/reset.h
297206 --- a/drivers/clk/hisilicon/reset.h
297208 @@ -23,6 +23,9 @@ struct hisi_reset_controller;
297218 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
297220 --- a/drivers/clocksource/Kconfig
297222 @@ -334,6 +334,14 @@ config ARM_ARCH_TIMER_EVTSTREAM
297235 bool "Workaround for Freescale/NXP Erratum A-008585"
297237 @@ -389,6 +397,12 @@ config ARM_TIMER_SP804
297250 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
297252 --- a/drivers/clocksource/Makefile
297254 @@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
297255 obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
297256 obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o
297257 obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o
297258 +obj-$(CONFIG_TIMER_HISP804) += timer-hisp804.o
297259 obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o
297260 obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o
297261 obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o
297262 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
297264 --- a/drivers/clocksource/arm_arch_timer.c
297266 @@ -628,7 +628,8 @@ static bool arch_timer_this_cpu_has_cntvct_wa(void)
297270 -#define arch_timer_this_cpu_has_cntvct_wa() ({false;})
297276 diff --git a/drivers/clocksource/timer-hisp804.c b/drivers/clocksource/timer-hisp804.c
297279 --- /dev/null
297280 +++ b/drivers/clocksource/timer-hisp804.c
297281 @@ -0,0 +1,356 @@
297289 + * http://www.apache.org/licenses/LICENSE-2.0
297373 + hisp804_clocksource_enable(to_hiclksrc(cs)->base);
297383 + return ~(cycle_t)readl_relaxed(to_hiclksrc(cs)->base + TIMER_VALUE);
297409 + writel(0, hiclkevt->base + TIMER_CTRL);
297420 + writel(TIMER_CTRL_32BIT, hiclkevt->base + TIMER_CTRL);
297422 + writel(next, hiclkevt->base + TIMER_LOAD);
297423 + writel(next, hiclkevt->base + TIMER_LOAD);
297429 + writel(ctrl, hiclkevt->base + TIMER_CTRL);
297439 + writel(TIMER_CTRL_32BIT, hiclkevt->base + TIMER_CTRL);
297441 + writel(hiclkevt->reload, hiclkevt->base + TIMER_LOAD);
297442 + writel(hiclkevt->reload, hiclkevt->base + TIMER_LOAD);
297448 + writel(ctrl, hiclkevt->base + TIMER_CTRL);
297459 + writel(1, hiclkevt->base + TIMER_INTCLR);
297461 + clkevt->event_handler(clkevt);
297468 + struct clock_event_device *clkevt = &hiclkevt->clkevt;
297470 + writel(0, hiclkevt->base + TIMER_CTRL);
297472 + BUG_ON(setup_irq(clkevt->irq, &hiclkevt->action));
297474 + irq_force_affinity(clkevt->irq, clkevt->cpumask);
297476 + clockevents_config_and_register(clkevt, hiclkevt->rate, 0xf,
297484 + struct clock_event_device *clkevt = &hiclkevt->clkevt;
297486 + pr_info("disable IRQ%d cpu #%d\n", clkevt->irq, smp_processor_id());
297488 + disable_irq(clkevt->irq);
297490 + remove_irq(clkevt->irq, &hiclkevt->action);
297492 + clkevt->set_state_shutdown(clkevt);
297527 + hiclkevt->base = base;
297528 + hiclkevt->rate = rate;
297529 + hiclkevt->reload = reload;
297530 + snprintf(hiclkevt->name, sizeof(hiclkevt->name), "clockevent %d", cpu);
297532 + clkevt = &hiclkevt->clkevt;
297534 + clkevt->name = hiclkevt->name;
297535 + clkevt->cpumask = cpumask_of(cpu);
297536 + clkevt->irq = irq;
297537 + clkevt->set_next_event = hisp804_clockevent_set_next_event;
297538 + clkevt->set_state_shutdown = hisp804_clockevent_shutdown;
297539 + clkevt->set_state_periodic = sp804_clockevent_set_periodic;
297540 + clkevt->features = CLOCK_EVT_FEAT_PERIODIC |
297543 + clkevt->rating = 400;
297545 + action = &hiclkevt->action;
297547 + action->name = hiclkevt->name;
297548 + action->dev_id = hiclkevt;
297549 + action->irq = irq;
297550 + action->flags = IRQF_TIMER | IRQF_NOBALANCING;
297551 + action->handler = hisp804_clockevent_timer_interrupt;
297577 + if (of_count_phandle_with_args(node, "clocks", "#clock-cells") == 3) {
297580 + pr_err("hisp804: %s clock not found: %d\n", node->name,
297602 + while (--ix >= 0)
297603 + iounmap(per_cpu_ptr(hisp804_clkevt, ix)->base);
297631 + iounmap(per_cpu_ptr(hisp804_clkevt, ix)->base);
297635 + return -ENODEV;
297639 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
297641 --- a/drivers/dma/Kconfig
297643 @@ -312,6 +312,20 @@ config K3_DMA
297653 + The Direction Memory Access(EDMA) is a high-speed data transfer
297664 @@ -619,7 +633,6 @@ config ZX_DMA
297668 -
297672 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
297674 --- a/drivers/dma/Makefile
297676 @@ -72,7 +72,7 @@ obj-$(CONFIG_TIMB_DMA) += timb_dma.o
297677 obj-$(CONFIG_XGENE_DMA) += xgene-dma.o
297678 obj-$(CONFIG_ZX_DMA) += zx_dma.o
297679 obj-$(CONFIG_ST_FDMA) += st_fdma.o
297680 -
297681 +obj-$(CONFIG_HIEDMACV310) += hiedmacv310.o
297682 obj-y += mediatek/
297683 obj-y += qcom/
297684 obj-y += ti/
297685 diff --git a/drivers/dma/hiedmacv310.c b/drivers/dma/hiedmacv310.c
297688 --- /dev/null
297690 @@ -0,0 +1,1443 @@
297720 +#include <linux/dma-mapping.h>
297736 +#include "virt-dma.h"
297861 + list_for_each_entry(edmac_dma_chan, &hiedmac->slave.channels,
297863 + if (edmac_dma_chan->id == request_num)
297864 + return &edmac_dma_chan->virt_chan.chan;
297872 + struct hiedmacv310_driver_data *hiedmac = ofdma->of_dma_data;
297883 + misc = hiedmac->misc_regmap;
297885 + if (dma_spec->args_count != 2) { /* check num of dts node args */
297890 + request_num = dma_spec->args[0];
297891 + signal = dma_spec->args[1];
297893 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "host->id = %d,signal = %d, request_num = %d\n",
297894 + hiedmac->id, signal, request_num);
297898 + offset = hiedmac->misc_ctrl_base;
297902 + offset = hiedmac->misc_ctrl_base + (request_num & (~0x3));
297920 + edmac_dma_chan->signal = request_num;
297926 + struct platform_device *platdev = hiedmac->dev;
297929 + hiedmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk");
297930 + if (IS_ERR(hiedmac->clk)) {
297931 + return PTR_ERR(hiedmac->clk);
297934 + hiedmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk");
297935 + if (IS_ERR(hiedmac->axi_clk)) {
297936 + return PTR_ERR(hiedmac->axi_clk);
297939 + hiedmac->irq = platform_get_irq(platdev, 0);
297940 + if (unlikely(hiedmac->irq < 0))
297941 + return -ENODEV;
297943 + hiedmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset");
297944 + if (IS_ERR(hiedmac->rstc))
297945 + return PTR_ERR(hiedmac->rstc);
297950 + return -ENODEV;
297953 + hiedmac->base = devm_ioremap_resource(&(platdev->dev), res);
297954 + if (IS_ERR(hiedmac->base))
297955 + return PTR_ERR(hiedmac->base);
297961 + struct platform_device *platdev = hiedmac->dev;
297962 + struct device_node *np = platdev->dev.of_node;
297967 + hiedmac->misc_regmap = 0;
297969 + hiedmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap");
297970 + if (IS_ERR(hiedmac->misc_regmap))
297971 + return PTR_ERR(hiedmac->misc_regmap);
297973 + ret = of_property_read_u32(np, "misc_ctrl_base", &(hiedmac->misc_ctrl_base));
297975 + hiedmacv310_error("get dma-misc_ctrl_base fail\n");
297976 + return -ENODEV;
297979 + ret = of_property_read_u32(np, "devid", &(hiedmac->id));
297982 + return -ENODEV;
297984 + ret = of_property_read_u32(np, "dma-channels", &(hiedmac->channels));
297986 + hiedmacv310_error("get dma-channels fail\n");
297987 + return -ENODEV;
297989 + ret = of_property_read_u32(np, "dma-requests", &(hiedmac->slave_requests));
297991 + hiedmacv310_error("get dma-requests fail\n");
297992 + return -ENODEV;
297994 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "dma-channels = %d, dma-requests = %d\n",
297995 + hiedmac->channels, hiedmac->slave_requests);
298001 + struct platform_device *platdev = hiedmac->dev;
298014 + return of_dma_controller_register(platdev->dev.of_node,
298029 + struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
298031 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298034 + next_lli = (hiedmacv310_readl(hiedmac->base + hiedmac_cx_lli_l(phychan->id)) &
298035 + (~(HIEDMAC_LLI_ALIGN - 1)));
298036 + next_lli |= ((u64)(hiedmacv310_readl(hiedmac->base + hiedmac_cx_lli_h(
298037 + phychan->id)) & 0xffffffff) << BITS_PER_HALF_WORD);
298038 + bytes = hiedmacv310_readl(hiedmac->base + hiedmac_cx_curr_cnt0(
298039 + phychan->id));
298042 + bytes += tsf_desc->size;
298043 + index = (next_lli - tsf_desc->llis_busaddr) / sizeof(*plli);
298044 + plli = (hiedmac_lli *)(tsf_desc->llis_vaddr);
298046 + bytes -= plli[i].count;
298067 + if (edmac_dma_chan->state == HIEDMAC_CHAN_PAUSED && ret == DMA_IN_PROGRESS) {
298072 + spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
298073 + vd = vchan_find_desc(&edmac_dma_chan->virt_chan, cookie);
298076 + tsf_desc = to_edmac_transfer_desc(&vd->tx);
298077 + bytes = tsf_desc->size;
298080 + tsf_desc = edmac_dma_chan->at;
298082 + if (!(edmac_dma_chan->phychan) || !tsf_desc) {
298083 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298088 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298101 + for (i = 0; i < hiedmac->channels; i++) {
298102 + ch = &hiedmac->phy_chans[i];
298104 + spin_lock_irqsave(&ch->lock, flags);
298106 + if (!ch->serving) {
298107 + ch->serving = edmac_dma_chan;
298108 + spin_unlock_irqrestore(&ch->lock, flags);
298111 + spin_unlock_irqrestore(&ch->lock, flags);
298114 + if (i == hiedmac->channels) {
298125 + hiedmac_lli *plli = (hiedmac_lli *)tsf_desc->llis_vaddr;
298127 + if (plli->next_lli != 0x0)
298128 + hiedmacv310_writel((plli->next_lli & 0xffffffff) | HIEDMAC_LLI_ENABLE,
298129 + hiedmac->base + hiedmac_cx_lli_l(phychan->id));
298131 + hiedmacv310_writel((plli->next_lli & 0xffffffff),
298132 + hiedmac->base + hiedmac_cx_lli_l(phychan->id));
298134 + hiedmacv310_writel(((plli->next_lli >> 32) & 0xffffffff),
298135 + hiedmac->base + hiedmac_cx_lli_h(phychan->id));
298136 + hiedmacv310_writel(plli->count, hiedmac->base + hiedmac_cx_cnt0(phychan->id));
298137 + hiedmacv310_writel(plli->src_addr & 0xffffffff,
298138 + hiedmac->base + hiedmac_cx_src_addr_l(phychan->id));
298139 + hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff,
298140 + hiedmac->base + hiedmac_cx_src_addr_h(phychan->id));
298141 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
298142 + hiedmac->base + hiedmac_cx_dest_addr_l(phychan->id));
298143 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
298144 + hiedmac->base + hiedmac_cx_dest_addr_h(phychan->id));
298145 + hiedmacv310_writel(plli->config,
298146 + hiedmac->base + hiedmac_cx_config(phychan->id));
298151 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298152 + struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
298153 + struct virt_dma_desc *vd = vchan_next_desc(&edmac_dma_chan->virt_chan);
298154 + struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx);
298156 + list_del(&tsf_desc->virt_desc.node);
298157 + edmac_dma_chan->at = tsf_desc;
298159 + val = hiedmacv310_readl(hiedmac->base + hiedmac_cx_config(phychan->id));
298162 + hiedmac->base + hiedmac_cx_config(phychan->id));
298167 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298172 + edmac_dma_chan->state = HIEDMAC_CHAN_WAITING;
298175 + edmac_dma_chan->phychan = ch;
298176 + edmac_dma_chan->state = HIEDMAC_CHAN_RUNNING;
298184 + spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
298185 + if (vchan_issue_pending(&edmac_dma_chan->virt_chan)) {
298186 + if (!edmac_dma_chan->phychan && edmac_dma_chan->state != HIEDMAC_CHAN_WAITING)
298189 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298195 + vchan_get_all_descriptors(&edmac_dma_chan->virt_chan, &head);
298196 + vchan_dma_desc_free_list(&edmac_dma_chan->virt_chan, &head);
298203 + if (!edmac_dma_chan->slave) {
298205 + return -EINVAL;
298207 + edmac_dma_chan->cfg = *config;
298213 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298214 + struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
298218 + val = hiedmacv310_readl(hiedmac->base + hiedmac_cx_config(phychan->id));
298220 + hiedmacv310_writel(val, hiedmac->base + hiedmac_cx_config(phychan->id));
298222 + for (timeout = 2000; timeout > 0; timeout--) {
298223 + if (!((0x1 << phychan->id) & hiedmacv310_readl(hiedmac->base + HIEDMAC_CH_STAT)))
298225 + hiedmacv310_writel(val, hiedmac->base + hiedmac_cx_config(phychan->id));
298230 + phychan->id, timeout);
298238 + spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
298239 + if (!edmac_dma_chan->phychan) {
298240 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298244 + edmac_dma_chan->state = HIEDMAC_CHAN_PAUSED;
298245 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298251 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298252 + struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
298254 + val = hiedmacv310_readl(hiedmac->base + hiedmac_cx_config(phychan->id));
298256 + hiedmacv310_writel(val, hiedmac->base + hiedmac_cx_config(phychan->id));
298264 + spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
298266 + if (!edmac_dma_chan->phychan) {
298267 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298272 + edmac_dma_chan->state = HIEDMAC_CHAN_RUNNING;
298273 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298285 + spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags);
298286 + if (!edmac_dma_chan->phychan && !edmac_dma_chan->at) {
298287 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298291 + edmac_dma_chan->state = HIEDMAC_CHAN_IDLE;
298293 + if (edmac_dma_chan->phychan)
298295 + if (edmac_dma_chan->at) {
298296 + hiedmac_desc_free(&edmac_dma_chan->at->virt_desc);
298297 + edmac_dma_chan->at = NULL;
298300 + spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags);
298339 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", config);
298344 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "edmac_dma_chan->signal = %d\n", signal);
298364 + *slave_addr = edmac_dma_chan->cfg.dst_addr;
298365 + addr_width = edmac_dma_chan->cfg.dst_addr_width;
298366 + maxburst = edmac_dma_chan->cfg.dst_maxburst;
298368 + *slave_addr = edmac_dma_chan->cfg.src_addr;
298369 + addr_width = edmac_dma_chan->cfg.src_addr_width;
298370 + maxburst = edmac_dma_chan->cfg.src_maxburst;
298378 + burst |= (HIEDMAC_MAX_BURST_WIDTH - 1);
298382 + burst |= (maxburst - 1);
298384 + tsf_desc->ccfg = hiedmac_set_config_value(direction, addr_width,
298385 + burst, edmac_dma_chan->signal);
298386 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", tsf_desc->ccfg);
298398 + return -ENOMEM;
298401 + plli = (hiedmac_lli*)(tsf_desc->llis_vaddr);
298404 + plli[num].src_addr = dsg->src_addr;
298405 + plli[num].dest_addr = dsg->dst_addr;
298406 + plli[num].config = tsf_desc->ccfg;
298408 + tsf_desc->size += length;
298411 + plli[num - 1].next_lli = (tsf_desc->llis_busaddr + (num) * sizeof(
298412 + *plli)) & (~(HIEDMAC_LLI_ALIGN - 1));
298413 + plli[num - 1].next_lli |= HIEDMAC_LLI_ENABLE;
298424 + list_del(&dsg->node);
298437 + return -ENOMEM;
298444 + return -ENOMEM;
298447 + list_add_tail(&dsg->node, sg_head);
298448 + dsg->src_addr = src;
298449 + dsg->dst_addr = dst;
298450 + dsg->len = len;
298469 + return -ENOMEM;
298486 + return -ENOMEM;
298516 + trans_bytes = min(period_len, buf_len - count_in_sg);
298537 + unsigned short width = get_max_width(tsf_desc->ccfg);
298539 + while (dsg->len != 0) {
298542 + lli_len = min(lli_len, dsg->len);
298547 + if (tsf_desc->ccfg & HIEDMAC_CONFIG_SRC_INC)
298548 + dsg->src_addr += lli_len;
298549 + if (tsf_desc->ccfg & HIEDMAC_CONFIG_DST_INC)
298550 + dsg->dst_addr += lli_len;
298551 + dsg->len -= lli_len;
298571 + if (tsf_desc->cyclic) {
298572 + last_plli = (hiedmac_lli *)((uintptr_t)tsf_desc->llis_vaddr +
298573 + (lli_count - 1) * sizeof(*last_plli));
298574 + last_plli->next_lli = tsf_desc->llis_busaddr | HIEDMAC_LLI_ENABLE;
298576 + last_plli = (hiedmac_lli *)((uintptr_t)tsf_desc->llis_vaddr +
298577 + (lli_count - 1) * sizeof(*last_plli));
298578 + last_plli->next_lli = 0;
298580 + dump_lli(tsf_desc->llis_vaddr, lli_count);
298590 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298604 + tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT,
298605 + &tsf_desc->llis_busaddr);
298606 + if (!tsf_desc->llis_vaddr) {
298618 + return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
298621 + dma_pool_free(hiedmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr);
298632 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298647 + tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT,
298648 + &tsf_desc->llis_busaddr);
298649 + if (!tsf_desc->llis_vaddr) {
298657 + config |= (HIEDMAC_MAX_BURST_WIDTH - 1) << HIEDMAC_CONFIG_SRC_BURST_SHIFT;
298658 + config |= (HIEDMAC_MAX_BURST_WIDTH - 1) << HIEDMAC_CONFIG_DST_BURST_SHIFT;
298661 + tsf_desc->ccfg = config;
298669 + return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
298672 + dma_pool_free(hiedmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr);
298685 + struct hiedmacv310_driver_data *hiedmac = edmac_dma_chan->host;
298695 + tsf_desc->llis_vaddr = dma_pool_alloc(hiedmac->pool, GFP_NOWAIT,
298696 + &tsf_desc->llis_busaddr);
298697 + if (!tsf_desc->llis_vaddr) {
298702 + tsf_desc->cyclic = true;
298710 + return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags);
298713 + dma_pool_free(hiedmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr);
298722 + phy_chan->serving = chan;
298723 + chan->phychan = phy_chan;
298724 + chan->state = HIEDMAC_CHAN_RUNNING;
298733 + struct hiedmacv310_phy_chan *phychan = edmac_dma_chan->phychan;
298735 + val = 0x1 << phychan->id;
298736 + hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_TC1_RAW);
298737 + hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
298738 + hiedmacv310_writel(val, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
298743 + struct hiedmacv310_driver_data *hiedmac = chan->host;
298747 + list_for_each_entry(p, &hiedmac->memcpy.channels, virt_chan.chan.device_node) {
298748 + if (p->state == HIEDMAC_CHAN_WAITING) {
298755 + list_for_each_entry(p, &hiedmac->slave.channels, virt_chan.chan.device_node) {
298756 + if (p->state == HIEDMAC_CHAN_WAITING) {
298765 + spin_lock(&next->virt_chan.lock);
298766 + hiedmac_phy_reassign(chan->phychan, next);
298767 + spin_unlock(&next->virt_chan.lock);
298769 + chan->phychan->serving = NULL;
298772 + chan->phychan = NULL;
298773 + chan->state = HIEDMAC_CHAN_IDLE;
298783 + phy_chan = &hiedmac->phy_chans[chan_id];
298784 + chan = phy_chan->serving;
298789 + tsf_desc = chan->at;
298791 + channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC1_RAW);
298794 + hiedmacv310_writel(channel_tc_status << chan_id, hiedmac->base + HIEDMAC_INT_TC1_RAW);
298796 + channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC2);
298799 + hiedmacv310_writel(channel_tc_status << chan_id, hiedmac->base + HIEDMAC_INT_TC2_RAW);
298800 + channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
298801 + channel_err_status[1] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR2);
298802 + channel_err_status[2] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR3);
298807 + hiedmacv310_writel(1 << chan_id, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
298808 + hiedmacv310_writel(1 << chan_id, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
298809 + hiedmacv310_writel(1 << chan_id, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
298812 + spin_lock(&chan->virt_chan.lock);
298814 + if (tsf_desc->cyclic) {
298815 + vchan_cyclic_callback(&tsf_desc->virt_desc);
298816 + spin_unlock(&chan->virt_chan.lock);
298819 + chan->at = NULL;
298820 + tsf_desc->done = true;
298821 + vchan_cookie_complete(&tsf_desc->virt_desc);
298823 + if (vchan_next_desc(&chan->virt_chan))
298827 + spin_unlock(&chan->virt_chan.lock);
298837 + channel_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_STAT);
298843 + for (i = 0; i < hiedmac->channels; i++) {
298853 + chan->slave = true;
298858 + struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx);
298859 + struct hiedmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(vd->tx.chan);
298860 + dma_descriptor_unmap(&vd->tx);
298861 + dma_pool_free(edmac_dma_chan->host->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr);
298871 + INIT_LIST_HEAD(&dmadev->channels);
298877 + return -1;
298880 + chan->host = hiedmac;
298881 + chan->state = HIEDMAC_CHAN_IDLE;
298882 + chan->signal = -1;
298885 + chan->id = i;
298888 + chan->virt_chan.desc_free = hiedmac_desc_free;
298889 + vchan_init(&chan->virt_chan, dmadev);
298899 + list_for_each_entry_safe(chan, next, &dmadev->channels, virt_chan.chan.device_node) {
298900 + list_del(&chan->virt_chan.chan.device_node);
298908 + dma_cap_set(DMA_MEMCPY, hiedmac->memcpy.cap_mask);
298909 + hiedmac->memcpy.dev = &pdev->dev;
298910 + hiedmac->memcpy.device_free_chan_resources = hiedmac_free_chan_resources;
298911 + hiedmac->memcpy.device_prep_dma_memcpy = hiedmac_prep_dma_m2m_copy;
298912 + hiedmac->memcpy.device_tx_status = hiedmac_tx_status;
298913 + hiedmac->memcpy.device_issue_pending = hiedmac_issue_pending;
298914 + hiedmac->memcpy.device_config = hiedmac_config;
298915 + hiedmac->memcpy.device_pause = hiedmac_pause;
298916 + hiedmac->memcpy.device_resume = hiedmac_resume;
298917 + hiedmac->memcpy.device_terminate_all = hiedmac_terminate_all;
298918 + hiedmac->memcpy.directions = BIT(DMA_MEM_TO_MEM);
298919 + hiedmac->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
298921 + dma_cap_set(DMA_SLAVE, hiedmac->slave.cap_mask);
298922 + dma_cap_set(DMA_CYCLIC, hiedmac->slave.cap_mask);
298923 + hiedmac->slave.dev = &pdev->dev;
298924 + hiedmac->slave.device_free_chan_resources = hiedmac_free_chan_resources;
298925 + hiedmac->slave.device_tx_status = hiedmac_tx_status;
298926 + hiedmac->slave.device_issue_pending = hiedmac_issue_pending;
298927 + hiedmac->slave.device_prep_slave_sg = hiedmac_prep_slave_sg;
298928 + hiedmac->slave.device_prep_dma_cyclic = hiedmac_prep_dma_cyclic;
298929 + hiedmac->slave.device_config = hiedmac_config;
298930 + hiedmac->slave.device_resume = hiedmac_resume;
298931 + hiedmac->slave.device_pause = hiedmac_pause;
298932 + hiedmac->slave.device_terminate_all = hiedmac_terminate_all;
298933 + hiedmac->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
298934 + hiedmac->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
298940 + hiedmac->phy_chans = kzalloc((hiedmac->channels * sizeof(
298943 + if (!hiedmac->phy_chans) {
298945 + return -ENOMEM;
298948 + for (i = 0; i < hiedmac->channels; i++) {
298949 + struct hiedmacv310_phy_chan *phy_ch = &hiedmac->phy_chans[i];
298950 + phy_ch->id = i;
298951 + phy_ch->base = hiedmac->base + hiedmac_cx_base(i);
298952 + spin_lock_init(&phy_ch->lock);
298953 + phy_ch->serving = NULL;
298956 + ret = hiedmac_init_virt_channels(hiedmac, &hiedmac->memcpy, hiedmac->channels,
298963 + ret = hiedmac_init_virt_channels(hiedmac, &hiedmac->slave, hiedmac->slave_requests,
298972 + hiedmac_free_virt_channels(&hiedmac->memcpy);
298974 + kfree(hiedmac->phy_chans);
298975 + return -ENOMEM;
298980 + hiedmac_free_virt_channels(&hiedmac->slave);
298981 + hiedmac_free_virt_channels(&hiedmac->memcpy);
298982 + kfree(hiedmac->phy_chans);
298987 + clk_prepare_enable(hiedmac->clk);
298988 + clk_prepare_enable(hiedmac->axi_clk);
298989 + reset_control_deassert(hiedmac->rstc);
298991 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC1_RAW);
298992 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC2_RAW);
298993 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
298994 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
298995 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
298997 + hiedmac->base + HIEDMAC_INT_TC1_MASK);
298999 + hiedmac->base + HIEDMAC_INT_TC2_MASK);
299001 + hiedmac->base + HIEDMAC_INT_ERR1_MASK);
299003 + hiedmac->base + HIEDMAC_INT_ERR2_MASK);
299005 + hiedmac->base + HIEDMAC_INT_ERR3_MASK);
299014 + ret = dma_set_mask_and_coherent(&(pdev->dev), DMA_BIT_MASK(64));
299024 + hiedmac->dev = pdev;
299033 + hiedmac->max_transfer_size = MAX_TRANSFER_BYTES;
299036 + hiedmac->pool = dma_pool_create(DRIVER_NAME, &(pdev->dev),
299038 + if (!hiedmac->pool) {
299050 + dma_pool_destroy(hiedmac->pool);
299059 + dma_pool_destroy(hiedmac->pool);
299070 + return -ENOMEM;
299073 + ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
299079 + ret = dma_async_device_register(&hiedmac->memcpy);
299081 + hiedmacv310_error("%s failed to register memcpy as an async device - %d\n", __func__, ret);
299085 + ret = dma_async_device_register(&hiedmac->slave);
299087 + hiedmacv310_error("%s failed to register slave as an async device - %d\n", __func__, ret);
299093 + dma_async_device_unregister(&hiedmac->memcpy);
299095 + free_irq(hiedmac->irq, hiedmac);
299098 + return -ENOMEM;
299134 diff --git a/drivers/dma/hiedmacv310.h b/drivers/dma/hiedmacv310.h
299137 --- /dev/null
299139 @@ -0,0 +1,153 @@
299293 diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c
299295 --- a/drivers/firmware/efi/efi.c
299297 @@ -31,6 +31,7 @@
299305 @@ -241,6 +242,11 @@ static void generic_ops_unregister(void)
299317 diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
299319 --- a/drivers/gpio/gpio-pl061.c
299320 +++ b/drivers/gpio/gpio-pl061.c
299321 @@ -209,6 +209,25 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
299333 + pending = readb(pl061->base + GPIOMIS);
299334 + writeb(pending, pl061->base + GPIOIC);
299337 + generic_handle_irq(irq_find_mapping(gc->irq.domain,
299347 @@ -228,6 +247,7 @@ static void pl061_irq_handler(struct irq_desc *desc)
299355 @@ -287,6 +307,9 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
299356 struct device *dev = &adev->dev;
299365 @@ -302,7 +325,20 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
299366 pl061->gc.free = gpiochip_generic_free;
299370 + if (dev->of_node) {
299371 + gpio_idx = of_alias_get_id(dev->of_node, "gpio");
299373 + return -ENOMEM;
299374 + pl061->gc.base = gpio_idx * PL061_GPIO_NR;
299377 + if (pl061->gc.base < 0)
299378 + pl061->gc.base = -1;
299380 pl061->gc.base = -1;
299383 pl061->gc.get_direction = pl061_get_direction;
299384 pl061->gc.direction_input = pl061_direction_input;
299385 pl061->gc.direction_output = pl061_direction_output;
299386 @@ -342,8 +378,21 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
299387 dev_info(&adev->dev, "could not add irqchip\n");
299392 + dev_name(dev), &pl061->gc);
299399 + for (gpio_idx = 0; gpio_idx < pl061->gc.ngpio; gpio_idx++)
299400 + irq_set_parent(irq_find_mapping(pl061->gc.irq.domain, gpio_idx), irq);
299402 gpiochip_set_chained_irqchip(&pl061->gc, &pl061->irq_chip,
299407 dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
299408 diff --git a/drivers/gpu/drm/hisilicon/Kconfig b/drivers/gpu/drm/hisilicon/Kconfig
299410 --- a/drivers/gpu/drm/hisilicon/Kconfig
299412 @@ -4,3 +4,4 @@
299417 diff --git a/drivers/gpu/drm/hisilicon/Makefile b/drivers/gpu/drm/hisilicon/Makefile
299419 --- a/drivers/gpu/drm/hisilicon/Makefile
299421 @@ -4,3 +4,4 @@
299423 obj-$(CONFIG_DRM_HISI_HIBMC) += hibmc/
299424 obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/
299425 +obj-$(CONFIG_DRM_HISI_HISMART) += hismart/
299426 diff --git a/drivers/gpu/drm/hisilicon/hismart/Kconfig b/drivers/gpu/drm/hisilicon/hismart/Kconfig
299429 --- /dev/null
299431 @@ -0,0 +1,8 @@
299440 diff --git a/drivers/gpu/drm/hisilicon/hismart/Makefile b/drivers/gpu/drm/hisilicon/hismart/Makefile
299443 --- /dev/null
299445 @@ -0,0 +1,27 @@
299449 +EXTRA_CFLAGS += -I$(SDK_ROOT_DIR)/mpp/cbb/vo/vo_dev/drm_hal \
299450 + -I$(SDK_ROOT_DIR)/mpp/component/hifb/drm_hal \
299451 + -I$(SDK_ROOT_DIR)/mpp/component/hdmi/src/mkp/drm_hal \
299452 + -I$(SDK_ROOT_DIR)/mpp/cbb/include \
299453 + -I$(SDK_ROOT_DIR)/mpp/cbb/include/adapt \
299454 + -I$(SDK_ROOT_DIR)/mpp/cbb/based/arch/hi3516cv500/include/hi3516cv500 \
299455 + -I$(SDK_ROOT_DIR)/mpp/cbb/vo/vo_dev/include \
299456 + -I$(SDK_ROOT_DIR)/mpp/cbb/vo/vo_dev/include/adapt \
299457 + -I$(SDK_ROOT_DIR)/mpp/cbb/vo/include/adapt \
299458 + -I$(SDK_ROOT_DIR)/mpp/cbb/vo/include \
299459 + -I$(SDK_ROOT_DIR)/osal/include
299461 +hi_drm-y := \
299471 +obj-y += hi_drm.o
299473 diff --git a/drivers/gpu/drm/hisilicon/hismart/drm_hal_mipitx.h b/drivers/gpu/drm/hisilicon/hismart…
299476 --- /dev/null
299478 @@ -0,0 +1,91 @@
299480 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
299483 + * Create: 2020-7-29
299505 + OUTPUT_800X600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */
299506 + OUTPUT_1024X768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */
299507 + OUTPUT_1280X1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */
299508 + OUTPUT_1366X768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */
299509 + OUTPUT_1440X900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */
299511 + OUTPUT_1600X1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */
299512 + OUTPUT_1680X1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */
299513 + OUTPUT_1920X1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking)…
299514 + OUTPUT_640X480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */
299515 + OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced) */
299516 + OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced) */
299536 + OUTPUT_720X1280_60, /* For MIPI DSI Tx 720 x1280 at 60 Hz */
299537 + OUTPUT_1080X1920_60, /* For MIPI DSI Tx 1080x1920 at 60 Hz */
299570 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_adp_crtc.c b/drivers/gpu/drm/hisilicon/hismart/hi…
299573 --- /dev/null
299575 @@ -0,0 +1,775 @@
299577 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
299580 + * Create: 2020-7-29
299638 + if (g_hi_crtcs->disp_dev != NULL) {
299639 + return g_hi_crtcs->disp_dev;
299642 + ret = drm_get_export_func(MOD_ID_DISP, (hi_void **)&g_hi_crtcs->disp_dev);
299647 + return (struct drm_hal_disp_dev *)g_hi_crtcs->disp_dev;
299654 + if (g_hi_crtcs->gfx_dev != NULL) {
299655 + return g_hi_crtcs->gfx_dev;
299658 + ret = drm_get_export_func(MOD_ID_GFX, (hi_void **)&g_hi_crtcs->gfx_dev);
299663 + return (struct drm_hal_gfx_dev *)g_hi_crtcs->gfx_dev;
299668 + cap->layer_cap[DRM_HAL_GFX_G0].available = 1;
299669 + cap->layer_cap[DRM_HAL_GFX_G0].connected_disp_chn = DRM_HAL_DISP_0;
299670 + cap->layer_cap[DRM_HAL_GFX_G0].max_w = 1920; /* 1920 max width */
299671 + cap->layer_cap[DRM_HAL_GFX_G0].max_h = 1080; /* 1080 max height */
299672 + cap->layer_cap[DRM_HAL_GFX_G0].format_num = 2; /* 2:support 2 color format */
299673 + cap->layer_cap[DRM_HAL_GFX_G0].formats[0] = DRM_HAL_FMT_ARGB8888;
299674 + cap->layer_cap[DRM_HAL_GFX_G0].formats[1] = DRM_HAL_FMT_ARGB1555;
299676 + cap->layer_cap[DRM_HAL_GFX_G1].available = 0;
299678 + cap->layer_cap[DRM_HAL_GFX_G2].available = 0;
299680 + cap->layer_cap[DRM_HAL_GFX_G3].available = 1;
299681 + cap->layer_cap[DRM_HAL_GFX_G3].connected_disp_chn = DRM_HAL_DISP_0;
299682 + cap->layer_cap[DRM_HAL_GFX_G3].max_w = 256; /* 256 max width */
299683 + cap->layer_cap[DRM_HAL_GFX_G3].max_h = 256; /* 256 max height */
299684 + cap->layer_cap[DRM_HAL_GFX_G3].format_num = 2; /* 2:support 2 color format */
299685 + cap->layer_cap[DRM_HAL_GFX_G3].formats[0] = DRM_HAL_FMT_ARGB8888;
299686 + cap->layer_cap[DRM_HAL_GFX_G3].formats[1] = DRM_HAL_FMT_ARGB1555;
299703 + return -1;
299708 + return -1;
299715 + cap.layer_cap[i].connected_disp_chn == hi_crtc->id) {
299720 + hi_crtc->primary[index].id = i;
299721 + hi_crtc->primary[index].root_hi_crtc = hi_crtc;
299722 + *plane = &hi_crtc->primary[index].base;
299734 + HI_DRM_CHECK_PTR_RETURN(disp_dev->get_csc);
299735 + HI_DRM_CHECK_PTR_RETURN(disp_dev->set_csc);
299737 + ret = disp_dev->get_csc(DRM_HAL_GFX_G0, &csc);
299739 + HI_DRM_ERR("disp_dev->get_csc error, ret=%#x\n", ret);
299744 + ret = disp_dev->set_csc(DRM_HAL_GFX_G0, &csc);
299746 + HI_DRM_ERR("disp_dev->set_csc error, ret=%#x\n", ret);
299760 + drm_connector_list_iter_begin(plane->dev, &conn_iter);
299762 + if (connector->connector_type == DRM_MODE_CONNECTOR_DSI) {
299763 + mipi_status = connector->status;
299764 + } else if (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA) {
299765 + hdmi_status = connector->status;
299783 + HI_DRM_CHECK_PTR_RETURN(gfx_dev->open);
299784 + HI_DRM_CHECK_PTR_RETURN(gfx_dev->enable);
299785 + HI_DRM_CHECK_PTR_RETURN(gfx_dev->close);
299788 + if (hi_plane->status == 1) {
299792 + ret = hi_adp_crtc_open(&hi_plane->root_hi_crtc->base);
299794 + return -1;
299797 + ret = gfx_dev->open(hi_plane->id);
299802 + ret = gfx_dev->enable(hi_plane->id);
299806 + hi_plane->status = 1;
299811 + gfx_dev->close(hi_plane->id);
299813 + hi_adp_crtc_close(&hi_plane->root_hi_crtc->base);
299825 + HI_DRM_CHECK_PTR_RETURN(gfx_dev->disable);
299826 + HI_DRM_CHECK_PTR_RETURN(gfx_dev->close);
299829 + if (hi_plane->status == 0) {
299833 + ret = gfx_dev->disable(hi_plane->id);
299835 + return -1;
299838 + ret = gfx_dev->close(hi_plane->id);
299840 + return -1;
299842 + hi_plane->status = 0;
299855 + /* fall-through */
299866 + /* fall-through */
299880 + struct drm_plane_state *state = plane->state;
299881 + struct drm_framebuffer *fb = state->fb;
299891 + if (fb == NULL || IS_ERR_OR_NULL(hi_plane) || IS_ERR_OR_NULL(hi_plane->root_hi_crtc) ||
299892 + IS_ERR_OR_NULL(gfx_dev) || IS_ERR_OR_NULL(gfx_dev->set_attr) || IS_ERR_OR_NULL(gfx_dev->re…
299893 + hi_plane->root_hi_crtc->status == 0) {
299908 + hal_rect.w = fb->width;
299909 + hal_rect.h = fb->height;
299910 + ret = gfx_dev->set_attr(hi_plane->id, DRM_HAL_GFX_ATTR_SIZE, &hal_rect);
299916 + adp_format_translate(fb->format->format, &hal_fmt);
299917 + ret = gfx_dev->set_attr(hi_plane->id, DRM_HAL_GFX_ATTR_FORMAT, &hal_fmt);
299923 + ret = gfx_dev->set_attr(hi_plane->id, DRM_HAL_GFX_ATTR_STRIDE, &fb->pitches[0]);
299929 + ret = gfx_dev->set_attr(hi_plane->id, DRM_HAL_GFX_ATTR_BUFFER, &cma_gem->paddr);
299935 + ret = gfx_dev->refresh(hi_plane->id);
299948 + return -ENOMEM;
299959 + if (gfx_dev->deinit != NULL) {
299960 + gfx_dev->deinit();
299962 + if (disp_dev->deinit != NULL) {
299963 + disp_dev->deinit();
299975 + cap->crtc_num = 1;
299984 + return -1;
299988 + *crtc = &g_hi_crtcs->crtcs[index].base;
299992 + g_hi_crtcs->crtcs[index].id = DRM_HAL_DISP_0;
299995 + g_hi_crtcs->crtcs[index].id = DRM_HAL_DISP_1;
299998 + return -1;
300011 + HI_DRM_CHECK_PTR_RETURN(disp_dev->open);
300012 + HI_DRM_CHECK_PTR_RETURN(disp_dev->enable);
300013 + HI_DRM_CHECK_PTR_RETURN(disp_dev->close);
300015 + if (hi_crtc->status >= 1) {
300020 + HI_DRM_INFO("prepare to open display: %d\n", hi_crtc->id);
300022 + ret = disp_dev->open(hi_crtc->id);
300024 + HI_DRM_ERR("disp_dev->open error, ret=%#x\n", ret);
300028 + ret = disp_dev->enable(hi_crtc->id);
300030 + HI_DRM_ERR("disp_dev->enable error, ret=%#x\n", ret);
300034 + hi_crtc->status = 1;
300035 + hi_crtc->vb_enable = false;
300039 + (void)disp_dev->close(hi_crtc->id);
300053 + HI_DRM_CHECK_PTR_RETURN(disp_dev->disable);
300054 + HI_DRM_CHECK_PTR_RETURN(disp_dev->close);
300056 + if (hi_crtc->status == 0) {
300061 + ret = disp_dev->disable(hi_crtc->id);
300063 + HI_DRM_ERR("disp_dev->disable error, ret=%#x\n", ret);
300068 + if (hi_crtc->primary[i].status == 1) {
300069 + (void)adp_plane_close(&hi_crtc->primary[i].base);
300073 + if (hi_crtc->cursor.status == 1) {
300074 + (void)adp_plane_close(&hi_crtc->cursor.base);
300077 + ret |= disp_dev->close(hi_crtc->id);
300079 + HI_DRM_ERR("disp_dev->close error, ret=%#x\n", ret);
300081 + hi_crtc->status = 0;
300095 + HI_DRM_CHECK_PTR_RETURN(disp_dev->set_attr);
300097 + timing.clock = mode->clock;
300098 + timing.hdisplay = mode->hdisplay;
300099 + timing.hskew = mode->hskew;
300100 + timing.hsync_end = mode->hsync_end;
300101 + timing.hsync_start = mode->hsync_start;
300102 + timing.htotal = mode->htotal;
300103 + timing.vdisplay = mode->vdisplay;
300104 + timing.vscan = mode->vscan;
300105 + timing.vsync_end = mode->vsync_end;
300106 + timing.vsync_start = mode->vsync_start;
300107 + timing.vtotal = mode->vtotal;
300110 + ret = disp_dev->set_attr(hi_crtc->id, DRM_HAL_DISP_ATTR_TIMING, (void *)&fmt);
300112 + HI_DRM_ERR("disp_dev->set_attr timing error, ret=%#x\n", ret);
300129 + HI_DRM_CHECK_PTR_RETURN(disp_dev->attach_user_intf_sync);
300131 + HI_DRM_CHECK_PTR_RETURN(disp_dev->attach_user_intf_sync);
300141 + ret = disp_dev->attach_user_intf_sync(hi_crtc->id, &intf_sync_attr, 0);
300157 + HI_DRM_CHECK_PTR_RETURN(disp_dev->attach_intf);
300159 + ret = disp_dev->attach_intf(hi_crtc->id, intf_type, (void *)(&intf_id));
300161 + HI_DRM_ERR("dd->attach_intf error, ret=%#x\n", ret);
300175 + HI_DRM_CHECK_PTR_RETURN(disp_dev->detach_intf);
300177 + ret = disp_dev->detach_intf(hi_crtc->id, intf_type, (void *)(&intf_id));
300179 + HI_DRM_ERR("dd->detach_intf error, ret=%#x\n", ret);
300194 + HI_DRM_CHECK_PTR_RETURN(disp_dev->attach_user_intf_sync);
300195 + ret = disp_dev->attach_user_intf_sync(hi_crtc->id, intf_sync_attr, (void *)(&intf_id));
300220 + if (g_hi_crtcs->crtcs[i].id == cap.layer_cap[layer].connected_disp_chn) {
300221 + return &g_hi_crtcs->crtcs[i];
300233 + if (type == DRM_HAL_GFX_CB_INTR_100 && hi_crtc->adp_crtc_cb != NULL && hi_crtc->status != 0) {
300234 + return hi_crtc->adp_crtc_cb(&hi_crtc->base, HI_ADP_CRTC_VBLANK, para);
300243 + struct drm_plane *primary = crtc->primary;
300248 + IS_ERR_OR_NULL(gfx_dev) || IS_ERR_OR_NULL(gfx_dev->register_cb)) {
300249 + return -1;
300253 + if (hi_crtc->adp_crtc_cb != NULL) {
300260 + ret = gfx_dev->register_cb(hi_plane->id, DRM_HAL_GFX_CB_INTR_100, hi_adp_disp_cb);
300265 + hi_crtc->adp_crtc_cb = cb;
300272 + hi_crtc->vb_enable = enable;
300325 + if (g_adp_crtc_timing_map[i].timing.clock == timing->clock &&
300326 + g_adp_crtc_timing_map[i].timing.hdisplay == timing->hdisplay &&
300327 + g_adp_crtc_timing_map[i].timing.hsync_start == timing->hsync_start &&
300328 + g_adp_crtc_timing_map[i].timing.hsync_end == timing->hsync_end &&
300329 + g_adp_crtc_timing_map[i].timing.htotal == timing->htotal &&
300330 + g_adp_crtc_timing_map[i].timing.hskew == timing->hskew &&
300331 + g_adp_crtc_timing_map[i].timing.vdisplay == timing->vdisplay &&
300332 + g_adp_crtc_timing_map[i].timing.vsync_start == timing->vsync_start &&
300333 + g_adp_crtc_timing_map[i].timing.vsync_end == timing->vsync_end &&
300334 + g_adp_crtc_timing_map[i].timing.vtotal == timing->vtotal &&
300335 + g_adp_crtc_timing_map[i].timing.vscan == timing->vscan) {
300344 + HI_DRM_ERR("org timing: %d %d %d %d %d %d %d %d %d %d %d\n", timing->clock, timing->hdispl…
300345 + timing->hsync_start, timing->hsync_end, timing->htotal, timing->hskew, timing->vdispla…
300346 + timing->vsync_start, timing->vsync_end, timing->vtotal, timing->vscan);
300351 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_adp_crtc.h b/drivers/gpu/drm/hisilicon/hismart/hi…
300354 --- /dev/null
300356 @@ -0,0 +1,69 @@
300358 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
300361 + * Create: 2020-7-29
300426 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_adp_hdmitx.c b/drivers/gpu/drm/hisilicon/hismart/…
300429 --- /dev/null
300431 @@ -0,0 +1,345 @@
300433 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
300436 + * Create: 2020-7-29
300487 + if (g_hi_hdmitx->hdmi_dev != NULL) {
300488 + return g_hi_hdmitx->hdmi_dev;
300491 + ret = drm_get_export_func(MOD_ID_HDMI, (hi_void **)&g_hi_hdmitx->hdmi_dev);
300496 + return (struct drm_hal_hdmitx_dev *)g_hi_hdmitx->hdmi_dev;
300506 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->open);
300508 + if (hdmitx->open == 1) {
300512 + ret = hdmi_dev->open(hdmitx->hi_hdmi_id);
300517 + hdmitx->open = 1;
300528 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->close);
300530 + if (hdmitx->open == 0) {
300534 + ret = hdmi_dev->close(hdmitx->hi_hdmi_id);
300539 + hdmitx->open = 0;
300550 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->enable);
300552 + if (hdmitx->enable == 1) {
300556 + ret = hdmi_dev->enable(hdmitx->hi_hdmi_id);
300561 + hdmitx->enable = 1;
300572 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->disable);
300574 + if (hdmitx->enable == 0) {
300578 + ret = hdmi_dev->disable(hdmitx->hi_hdmi_id);
300583 + hdmitx->enable = 0;
300596 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->read_edid);
300603 + ret = hdmi_dev->read_edid(hi_hdmitx->hi_hdmi_id, edid, len);
300605 + return -1;
300619 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->get_status);
300626 + ret = hdmi_dev->get_status(hi_hdmitx->hi_hdmi_id, DRM_HAL_HDMITX_STAT_CONNECTOR, &stat);
300698 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->get_attr);
300699 + HI_DRM_CHECK_PTR_RETURN(hdmi_dev->set_attr);
300706 + if (hi_hdmitx->enable == 1) {
300711 + ret = hi_adp_crtc_set_mode(conn_state->crtc, mode);
300717 + ret = hi_adp_crtc_add_intf(conn_state->crtc, DRM_HAL_DISP_INTF_HDMITX, hi_hdmitx->hi_hdmi_id);
300722 + ret = hdmi_dev->get_attr(hi_hdmitx->hi_hdmi_id, &hdmi_attr);
300727 + timing.clock = mode->clock;
300728 + timing.hdisplay = mode->hdisplay;
300729 + timing.hskew = mode->hskew;
300730 + timing.hsync_end = mode->hsync_end;
300731 + timing.hsync_start = mode->hsync_start;
300732 + timing.htotal = mode->htotal;
300733 + timing.vdisplay = mode->vdisplay;
300734 + timing.vscan = mode->vscan;
300735 + timing.vsync_end = mode->vsync_end;
300736 + timing.vsync_start = mode->vsync_start;
300737 + timing.vtotal = mode->vtotal;
300739 + ret = hdmi_dev->set_attr(hi_hdmitx->hi_hdmi_id, &hdmi_attr);
300752 + return -1;
300755 + g_hi_hdmitx->hdmitx[0].drm_hdmi_id = drm_hdmi_id;
300756 + g_hi_hdmitx->hdmitx[0].hi_hdmi_id = DRM_HAL_HDMITX_0;
300757 + *conn = &g_hi_hdmitx->hdmitx[0].conn;
300758 + *encoder = &g_hi_hdmitx->hdmitx[0].encoder;
300766 + return -ENOMEM;
300777 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_adp_hdmitx.h b/drivers/gpu/drm/hisilicon/hismart/…
300780 --- /dev/null
300782 @@ -0,0 +1,28 @@
300784 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
300787 + * Create: 2020-7-29
300811 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_adp_mipitx.c b/drivers/gpu/drm/hisilicon/hismart/…
300814 --- /dev/null
300816 @@ -0,0 +1,300 @@
300818 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
300821 + * Create: 2020-7-29
300890 + if (g_hi_mipitx->mipi_dev != NULL) {
300891 + return g_hi_mipitx->mipi_dev;
300894 + g_hi_mipitx->mipi_dev = GetDispOps();
300895 + if (IS_ERR_OR_NULL(g_hi_mipitx->mipi_dev) || IS_ERR_OR_NULL(g_hi_mipitx->mipi_dev->init)) {
300900 + ret = g_hi_mipitx->mipi_dev->init(DRM_HAL_GFX_G0);
300906 + return (struct DispOperations *)g_hi_mipitx->mipi_dev;
300913 + mode = drm_mode_duplicate(connector->dev, &default_mode);
300916 + return -ENOMEM;
300920 + connector->display_info.width_mm = MIPI_PHYSICAL_WIDTH;
300921 + connector->display_info.height_mm = MIPI_PHYSICAL_HEIGHT;
300933 + if (hi_mipitx->enable == 1) {
300937 + ret = hi_adp_crtc_add_user_intf(conn_state->crtc);
300942 + ret = hi_adp_crtc_set_mode(conn_state->crtc, mode);
300948 + ret = hi_adp_crtc_add_intf(conn_state->crtc, DRM_HAL_DISP_INTF_MIPITX, hi_mipitx->drm_mipi_id);
300963 + HI_DRM_CHECK_PTR_RETURN(mipi_dev->setBacklight);
300965 + if (hi_mipitx->enable == 1) {
300969 + ret = mipi_dev->on(DRM_HAL_GFX_G0);
300975 + hi_mipitx->enable = 1;
300987 + HI_DRM_CHECK_PTR_RETURN(mipi_dev->off);
300989 + if (hi_mipitx->enable == 0) {
300993 + ret = mipi_dev->off(DRM_HAL_GFX_G0);
300999 + hi_mipitx->enable = 0;
301007 + if (property == hi_mipitx->private.tv_brightness_property) {
301008 + state->tv.brightness = val;
301010 + HI_DRM_ERR("[CONNECTOR:%d:%s] unknown property [PROP:%d%s]\n", connector->base.id,
301011 + connector->name, property->base.id, property->name);
301012 + return -EINVAL;
301022 + if (property == hi_mipitx->private.tv_brightness_property) {
301023 + *val = state->tv.brightness;
301025 + HI_DRM_ERR("[CONNECTOR:%d:%s] unknown property [PROP:%d%s]\n", connector->base.id,
301026 + connector->name, property->base.id, property->name);
301027 + return -EINVAL;
301040 + HI_DRM_CHECK_PTR_RETURN(mipi_dev->setBacklight);
301048 + ret = mipi_dev->setBacklight(DRM_HAL_GFX_G0, brightness);
301060 + hi_mipitx->private.tv_brightness_property = drm_property_create_range(dev, 0, "brightness", 0,…
301061 + if (hi_mipitx->private.tv_brightness_property == NULL) {
301063 + return -ENOMEM;
301065 + drm_object_attach_property(&connector->base, hi_mipitx->private.tv_brightness_property, DEFAUL…
301073 + if (hi_mipitx->private.tv_brightness_property != NULL) {
301074 + drm_property_destroy(dev, hi_mipitx->private.tv_brightness_property);
301075 + hi_mipitx->private.tv_brightness_property = NULL;
301085 + return -1;
301088 + g_hi_mipitx->mipitx.drm_mipi_id = drm_mipi_id;
301089 + *conn = &g_hi_mipitx->mipitx.conn;
301090 + *encoder = &g_hi_mipitx->mipitx.encoder;
301097 + int ret = -1;
301101 + return -ENOMEM;
301117 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_adp_mipitx.h b/drivers/gpu/drm/hisilicon/hismart/…
301120 --- /dev/null
301122 @@ -0,0 +1,32 @@
301124 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
301127 + * Create: 2020-7-29
301155 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_crtc.c b/drivers/gpu/drm/hisilicon/hismart/hi…
301158 --- /dev/null
301160 @@ -0,0 +1,388 @@
301162 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
301165 + * Create: 2020-7-29
301294 + struct drm_pending_vblank_event *event = crtc->state->event;
301300 + crtc->state->event = NULL;
301301 + spin_lock_irq(&crtc->dev->event_lock);
301307 + spin_unlock_irq(&crtc->dev->event_lock);
301318 + crtc->state->mode.clock,
301319 + crtc->state->mode.hdisplay,
301320 + crtc->state->mode.hsync_start,
301321 + crtc->state->mode.hsync_end,
301322 + crtc->state->mode.htotal,
301323 + crtc->state->mode.hskew,
301324 + crtc->state->mode.vdisplay,
301325 + crtc->state->mode.vsync_start,
301326 + crtc->state->mode.vsync_end,
301327 + crtc->state->mode.vtotal,
301328 + crtc->state->mode.vscan);
301331 + mode->clock,
301332 + mode->hdisplay,
301333 + mode->hsync_start,
301334 + mode->hsync_end,
301335 + mode->htotal,
301336 + mode->hskew,
301337 + mode->vdisplay,
301338 + mode->vsync_start,
301339 + mode->vsync_end,
301340 + mode->vtotal,
301341 + mode->vscan);
301368 + return -1;
301372 + return -1;
301463 + HI_DRM_INFO("crtc %p index %d, plane id %d\n", crtc, crtc->index, primary->index);
301478 + hi_drm_plane_destroy(crtc->primary);
301549 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_crtc.h b/drivers/gpu/drm/hisilicon/hismart/hi…
301552 --- /dev/null
301554 @@ -0,0 +1,17 @@
301556 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
301559 + * Create: 2020-7-29
301572 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_drv.c b/drivers/gpu/drm/hisilicon/hismart/hi_…
301575 --- /dev/null
301577 @@ -0,0 +1,393 @@
301579 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
301582 + * Create: 2020-7-29
301651 + ret = drm_gem_prime_fd_to_handle(dev, file, arg->fd, &handle);
301653 + HI_DRM_ERR("fd %d to handle failed", arg->fd);
301654 + return -1;
301658 + HI_DRM_ERR("gem object not finde fd %d, handle 0x%x", arg->fd, handle);
301659 + return -1;
301665 + return -1;
301667 + page = sg_page(sgt->sgl);
301668 + arg->phyaddr = PFN_PHYS(page_to_pfn(page));
301672 + sgt = ERR_PTR(-ENOMEM);
301687 + temp_start = p->phys_addr;
301688 + temp_end = p->phys_addr + p->size;
301693 + HI_DRM_ERR("drm_check_dumb_phy_addr, addr_start-addr_end [0x%llx-0x%llx]\n", addr_start, addr_…
301694 + return -1;
301719 + gem_obj = drm_gem_object_lookup(file_priv, args->handle);
301721 + HI_DRM_ERR("gem object not finde handle 0x%x", args->handle);
301723 + return -1;
301730 + return -1;
301732 + page = sg_page(sgt->sgl);
301733 + node->phys_addr = PFN_PHYS(page_to_pfn(page));
301734 + node->size = args->size;
301736 + osal_list_add(&node->list, &g_phys_addr);
301739 + sgt = ERR_PTR(-ENOMEM);
301755 + page = sg_page(sgt->sgl);
301761 + sgt = ERR_PTR(-ENOMEM);
301763 + if (p->phys_addr == phyaddr) {
301764 + osal_list_del(&p->list);
301812 + if ((connector->connector_type == DRM_MODE_CONNECTOR_DSI) &&
301813 + (old_connector_state->tv.brightness != new_connector_state->tv.brightness)) {
301814 + adp_mipi_set_brightness(connector, new_connector_state->tv.brightness);
301828 + dev->mode_config.min_width = 0;
301829 + dev->mode_config.min_height = 0;
301830 + dev->mode_config.max_width = HI_DRM_MAX_WIDTH;
301831 + dev->mode_config.max_height = HI_DRM_MAX_HEIGHT;
301832 + dev->mode_config.funcs = &hi_drm_mode_config_funcs;
301856 + ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
301862 + drm->irq_enabled = true;
301894 + struct device *dev = &pdev->dev;
301904 + private = devm_kzalloc(drm_dev->dev, sizeof(struct hi_drm_private), GFP_KERNEL);
301906 + ret = -ENOMEM;
301910 + drm_dev->dev_private = private;
301931 + devm_kfree(drm_dev->dev, drm_dev->dev_private);
301932 + drm_dev->dev_private = NULL;
301940 + devm_kfree(drm_dev->dev, drm_dev->dev_private);
301941 + drm_dev->dev_private = NULL;
301953 + { .compatible = "hisilicon,hi-drm", },
301961 + .name = "hi-drm",
301971 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_drv.h b/drivers/gpu/drm/hisilicon/hismart/hi_…
301974 --- /dev/null
301976 @@ -0,0 +1,29 @@
301978 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
301981 + * Create: 2020-7-29
301997 + return -PTR_ERR(ptr); \
302006 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_func_ext.c b/drivers/gpu/drm/hisilicon/hismar…
302009 --- /dev/null
302011 @@ -0,0 +1,43 @@
302013 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
302016 + * Create: 2020-7-29
302032 + return -1;
302045 + return -1;
302056 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_func_ext.h b/drivers/gpu/drm/hisilicon/hismar…
302059 --- /dev/null
302061 @@ -0,0 +1,27 @@
302063 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
302066 + * Create: 2020-7-29
302089 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_hdmitx.c b/drivers/gpu/drm/hisilicon/hismart/…
302092 --- /dev/null
302094 @@ -0,0 +1,232 @@
302096 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
302099 + * Create: 2020-7-29
302131 + return -ENOMEM;
302180 + crtc_state->mode.clock,
302181 + crtc_state->mode.hdisplay,
302182 + crtc_state->mode.hsync_start,
302183 + crtc_state->mode.hsync_end,
302184 + crtc_state->mode.htotal,
302185 + crtc_state->mode.hskew,
302186 + crtc_state->mode.vdisplay,
302187 + crtc_state->mode.vsync_start,
302188 + crtc_state->mode.vsync_end,
302189 + crtc_state->mode.vtotal,
302190 + crtc_state->mode.vscan);
302191 + hi_adp_hdmitx_set_mode(encoder, &crtc_state->mode, conn_state);
302272 + encoder->possible_crtcs = 1; /* 1: dhd0 */
302274 + encoder->possible_crtcs = 2; /* 2: dhd1 */
302327 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_hdmitx.h b/drivers/gpu/drm/hisilicon/hismart/…
302330 --- /dev/null
302332 @@ -0,0 +1,16 @@
302334 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
302337 + * Create: 2020-7-29
302349 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_mipitx.c b/drivers/gpu/drm/hisilicon/hismart/…
302352 --- /dev/null
302354 @@ -0,0 +1,188 @@
302356 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
302359 + * Create: 2020-7-29
302414 + hi_adp_mipitx_set_mode(encoder, &crtc_state->mode, conn_state);
302476 + encoder->possible_crtcs = 1; /* 1: dhd0 */
302478 + encoder->possible_crtcs = 2; /* 2: dhd1 */
302543 diff --git a/drivers/gpu/drm/hisilicon/hismart/hi_drm_mipitx.h b/drivers/gpu/drm/hisilicon/hismart/…
302546 --- /dev/null
302548 @@ -0,0 +1,17 @@
302550 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
302553 + * Create: 2020-7-29
302566 diff --git a/drivers/gpu/drm/hisilicon/hismart/hisilicon_drm.h b/drivers/gpu/drm/hisilicon/hismart/…
302569 --- /dev/null
302571 @@ -0,0 +1,31 @@
302573 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2016-2019. All rights reserved.
302603 diff --git a/drivers/hi_vdmav100/Kconfig b/drivers/hi_vdmav100/Kconfig
302606 --- /dev/null
302608 @@ -0,0 +1,26 @@
302635 diff --git a/drivers/hi_vdmav100/Makefile b/drivers/hi_vdmav100/Makefile
302638 --- /dev/null
302640 @@ -0,0 +1,2 @@
302641 +obj-$(CONFIG_HI_VDMA_V100) += hi_vdmav100.o
302642 +obj-$(CONFIG_HI_VDMA_MISC_DEV) += hi_vdmav100_misc.o
302643 diff --git a/drivers/hi_vdmav100/hi_vdma.h b/drivers/hi_vdmav100/hi_vdma.h
302646 --- /dev/null
302648 @@ -0,0 +1,41 @@
302690 diff --git a/drivers/hi_vdmav100/hi_vdmav100.c b/drivers/hi_vdmav100/hi_vdmav100.c
302693 --- /dev/null
302695 @@ -0,0 +1,534 @@
302736 +#include <linux/dma-mapping.h>
302779 + return -1;
302814 + -DMAC_CHN_CONFIG_ERROR;
302881 + return -EINVAL;
302886 + mm = current->mm;
302891 + if (mm->pgd == NULL)
302892 + return -EINVAL;
302895 + reg[channel] = __pa(mm->pgd);
303012 + -DMAC_CHN_CONFIG_ERROR;
303013 + return -DMAC_CHN_CONFIG_ERROR;
303019 + return -1;
303023 + return -1;
303041 + return -1;
303054 + ret = -1;
303059 + ret = -1;
303075 + return -1;
303079 + return -1;
303083 + return -1;
303085 + if (abs((uintptr_t)dst - (uintptr_t)src) < PAGE_SIZE) {
303086 + return -1;
303105 + dma = devm_kzalloc(&platdev->dev, sizeof(*dma), GFP_KERNEL);
303107 + return -ENOMEM;
303112 + dev_err(&platdev->dev, "no mmio resource\n");
303113 + return -ENODEV;
303116 + dma->regbase = devm_ioremap_resource(&platdev->dev, res);
303117 + if (IS_ERR(dma->regbase)) {
303118 + return PTR_ERR(dma->regbase);
303121 + dma->clk = devm_clk_get(&platdev->dev, NULL);
303122 + if (IS_ERR(dma->clk)) {
303123 + return PTR_ERR(dma->clk);
303126 + clk_prepare_enable(dma->clk);
303128 + dma->rstc = devm_reset_control_get(&platdev->dev, "dma-reset");
303129 + if (IS_ERR(dma->rstc)) {
303130 + return PTR_ERR(dma->rstc);
303133 + dma->irq = platform_get_irq(platdev, 0);
303134 + if (unlikely(dma->irq < 0)) {
303135 + return -ENODEV;
303137 + hi_reg_vdma_base_va = dma->regbase;
303139 + dma->dev = &platdev->dev;
303143 + return -ENODEV;
303162 + clk_disable_unprepare(dma->clk);
303180 + clk_prepare_enable(dma->clk);
303186 + clk_disable_unprepare(dma->clk);
303210 + {.compatible = "hisilicon,hisi-vdmac"},
303217 + .name = "hisi-vdmac",
303230 diff --git a/drivers/hi_vdmav100/hi_vdmav100.h b/drivers/hi_vdmav100/hi_vdmav100.h
303233 --- /dev/null
303235 @@ -0,0 +1,122 @@
303358 diff --git a/drivers/hi_vdmav100/hi_vdmav100_misc.c b/drivers/hi_vdmav100/hi_vdmav100_misc.c
303361 --- /dev/null
303363 @@ -0,0 +1,109 @@
303416 + return -EINVAL;
303425 + ret = -1;
303473 diff --git a/drivers/hidmac/Kconfig b/drivers/hidmac/Kconfig
303476 --- /dev/null
303478 @@ -0,0 +1,21 @@
303487 + The Direction Memory Access(DMA) is a high-speed data transfer
303500 diff --git a/drivers/hidmac/Makefile b/drivers/hidmac/Makefile
303503 --- /dev/null
303505 @@ -0,0 +1,6 @@
303510 +obj-$(CONFIG_HI_DMAC) += hi_pl08x.o
303512 diff --git a/drivers/hidmac/hi_pl08x.c b/drivers/hidmac/hi_pl08x.c
303515 --- /dev/null
303517 @@ -0,0 +1,1303 @@
303548 +#include <linux/dma-mapping.h>
303628 + dmac_readw(dma->regbase + DMAC_INTSTATUS, channel_status);
303634 + dmac_readw(dma->regbase + DMAC_INTTCSTATUS, channel_tc_status);
303635 + dmac_readw(dma->regbase + DMAC_INTERRORSTATUS, channel_err_status);
303640 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR,
303644 + dmac_writew(dma->regbase + DMAC_INTERRCLR,
303653 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, (0x01 << i));
303655 + g_channel_status[i] = -DMAC_CHN_ERROR;
303656 + dmac_writew(dma->regbase + DMAC_INTERRCLR, (0x01 << i));
303701 + g_channel_status[i] = -DMAC_CHN_ERROR;
303709 + g_channel_status[i] = -DMAC_CHN_TIMEOUT;
303724 + if (-DMAC_CHN_ERROR == g_channel_status[channel]) {
303728 + status = -DMAC_CHN_ERROR;
303735 + } else if (-DMAC_CHN_TIMEOUT == g_channel_status[channel]) {
303737 + status = -DMAC_CHN_TIMEOUT;
303744 + status = -DMAC_CHN_ERROR;
303784 + return -EINVAL;
303790 + if (channel > CHANNEL_NUM - 1) {
303792 + return -1;
303797 + return -1;
303818 + return -EINVAL;
303839 + return -1;
303852 + clk_prepare_enable(dma->clk);
303853 + reset_control_deassert(dma->rstc);
303855 + dmac_readw(dma->regbase + DMAC_CONFIG, tempvalue);
303857 + dmac_writew(dma->regbase + DMAC_CONFIG,
303859 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
303860 + dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
303862 + dmac_writew(dma->regbase + DMAC_CxCONFIG(i),
303872 + return -1;
303875 + if (request_irq(dma->irq, dmac_isr, 0, "hi_dma", dma)) {
303876 + dma_err("DMA Irq %d request failed\n", dma->irq);
303878 + return -1;
303900 + return -1;
303942 + return -EINVAL;
303950 + return -EFAULT;
303975 + return -EINVAL;
303996 + return -1;
304001 + if (ret_result == -DMAC_CHN_ERROR) {
304003 + ret = -1;
304013 + } else if (ret_result == -DMAC_CHN_TIMEOUT) {
304017 + ret = -1;
304053 + if (j == (lli_num - 1)) {
304063 + if (j == (lli_num - 1)) {
304113 + if (j == (lli_num - 1)) {
304123 + if ((j == (lli_num - 1)) && (last_lli == 0))
304128 + else if ((j == (lli_num - 1)) && (last_lli == 1))
304159 + return -EINVAL;
304190 + return -1;
304209 + return -EFAULT;
304217 + return -EINVAL;
304262 + return -EINVAL;
304269 + return -EINVAL;
304320 + return -EINVAL;
304327 + return -EFAULT;
304334 + * even number-->TX, odd number-->RX */
304341 + return -EINVAL;
304382 + return -EINVAL;
304389 + return -EFAULT;
304396 + * even number-->TX, odd number-->RX */
304403 + return -EINVAL;
304444 + left_size -= (dma_size << 2);
304456 + return -1;
304461 + return -1;
304471 + return -1;
304475 + return -1;
304496 + return -1;
304503 + left_size -= (dma_size << uwwidth);
304508 + return -1;
304512 + return -1;
304517 + return -1;
304529 + return -1;
304533 + return -1;
304554 + return -1;
304561 + left_size -= (dma_size << uwwidth);
304566 + return -1;
304570 + return -1;
304575 + return -1;
304587 + return -1;
304591 + return -1;
304619 + return -1;
304624 + return -1;
304629 + return -1;
304645 + return -1;
304649 + if (ret == -1) {
304651 + return -1;
304660 + int ret = -1;
304666 + return -1;
304670 + if (ret == -1) {
304672 + return -1;
304689 + dma = devm_kzalloc(&platdev->dev, sizeof(*dma), GFP_KERNEL);
304691 + return -ENOMEM;
304696 + dev_err(&platdev->dev, "no mmio resource\n");
304697 + return -ENODEV;
304700 + dma->regbase = devm_ioremap_resource(&platdev->dev, res);
304701 + if (IS_ERR(dma->regbase)) {
304702 + return PTR_ERR(dma->regbase);
304705 + dma->clk = devm_clk_get(&platdev->dev, NULL);
304706 + if (IS_ERR(dma->clk)) {
304707 + return PTR_ERR(dma->clk);
304710 + dma->rstc = devm_reset_control_get(&platdev->dev, "dma-reset");
304711 + if (IS_ERR(dma->rstc)) {
304712 + return PTR_ERR(dma->rstc);
304715 + dma->irq = platform_get_irq(platdev, 0);
304716 + if (unlikely(dma->irq < 0)) {
304717 + return -ENODEV;
304720 + dma_regbase = dma->regbase;
304724 + return -ENODEV;
304733 + dev_info(&platdev->dev, "hidmac probe!\n");
304742 + clk_disable_unprepare(dma->clk);
304759 + clk_prepare_enable(dma->clk);
304765 + clk_disable_unprepare(dma->clk);
304776 + clk_prepare_enable(dma->clk);
304777 + reset_control_deassert(dma->rstc);
304779 + dmac_readw(dma->regbase + DMAC_CONFIG, tempvalue);
304781 + dmac_writew(dma->regbase + DMAC_CONFIG,
304783 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
304784 + dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
304786 + dmac_writew(dma->regbase + DMAC_CxCONFIG(i),
304800 + { .compatible = "hisilicon,hisi-dmac" },
304807 + .name = "hisi-dmac",
304821 diff --git a/drivers/hidmac/hi_pl08x.h b/drivers/hidmac/hi_pl08x.h
304824 --- /dev/null
304826 @@ -0,0 +1,90 @@
304828 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
304917 diff --git a/drivers/hidmac/hidmac_hi3516a.h b/drivers/hidmac/hidmac_hi3516a.h
304920 --- /dev/null
304922 @@ -0,0 +1,176 @@
304961 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305099 diff --git a/drivers/hidmac/hidmac_hi3518ev20x.h b/drivers/hidmac/hidmac_hi3518ev20x.h
305102 --- /dev/null
305104 @@ -0,0 +1,168 @@
305106 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
305144 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305273 diff --git a/drivers/hidmac/hidmac_hi3521a.h b/drivers/hidmac/hidmac_hi3521a.h
305276 --- /dev/null
305278 @@ -0,0 +1,151 @@
305318 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305430 diff --git a/drivers/hidmac/hidmac_hi3531a.h b/drivers/hidmac/hidmac_hi3531a.h
305433 --- /dev/null
305435 @@ -0,0 +1,166 @@
305475 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305602 diff --git a/drivers/hidmac/hidmac_hi3536dv100.h b/drivers/hidmac/hidmac_hi3536dv100.h
305605 --- /dev/null
305607 @@ -0,0 +1,131 @@
305609 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
305646 +#define DMAC_MAXTRANSFERSIZE 0x0fff /* the max length is denoted by 0-11bit */
305739 diff --git a/drivers/hiedmac/Kconfig b/drivers/hiedmac/Kconfig
305742 --- /dev/null
305744 @@ -0,0 +1,29 @@
305753 + The Direction Memory Access(EDMA) is a high-speed data transfer
305774 diff --git a/drivers/hiedmac/Makefile b/drivers/hiedmac/Makefile
305777 --- /dev/null
305779 @@ -0,0 +1,4 @@
305783 +obj-$(CONFIG_HIEDMAC) += hiedmacv310.o
305784 diff --git a/drivers/hiedmac/hiedma_hi3516cv500.h b/drivers/hiedmac/hiedma_hi3516cv500.h
305787 --- /dev/null
305789 @@ -0,0 +1,107 @@
305791 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
305897 diff --git a/drivers/hiedmac/hiedma_hi3516ev200.h b/drivers/hiedmac/hiedma_hi3516ev200.h
305900 --- /dev/null
305902 @@ -0,0 +1,83 @@
305904 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
305986 diff --git a/drivers/hiedmac/hiedma_hi3519av100.h b/drivers/hiedmac/hiedma_hi3519av100.h
305989 --- /dev/null
305991 @@ -0,0 +1,156 @@
305993 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
306148 diff --git a/drivers/hiedmac/hiedma_hi3521dv200.h b/drivers/hiedmac/hiedma_hi3521dv200.h
306151 --- /dev/null
306153 @@ -0,0 +1,140 @@
306155 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
306294 diff --git a/drivers/hiedmac/hiedma_hi3531dv200.h b/drivers/hiedmac/hiedma_hi3531dv200.h
306297 --- /dev/null
306299 @@ -0,0 +1,90 @@
306301 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
306390 diff --git a/drivers/hiedmac/hiedma_hi3559av100.h b/drivers/hiedmac/hiedma_hi3559av100.h
306393 --- /dev/null
306395 @@ -0,0 +1,140 @@
306397 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
306536 diff --git a/drivers/hiedmac/hiedmacv310.c b/drivers/hiedmac/hiedmacv310.c
306539 --- /dev/null
306541 @@ -0,0 +1,946 @@
306543 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
306573 +#include <linux/dma-mapping.h>
306645 + return -1;
306694 + g_channel_status[i] = -DMAC_CHN_ERROR;
306704 + g_channel_status[i] = -DMAC_CHN_TIMEOUT;
306717 + if (channel < 0 || channel > HIEDMAC_CHANNEL_NUM - 1) {
306719 + return -EINVAL;
306750 + return -1;
306767 + return -1;
306771 + if (ret_result == -DMAC_CHN_ERROR) {
306773 + ret = -1;
306783 + } else if (ret_result == -DMAC_CHN_TIMEOUT) {
306788 + ret = -1;
306811 + if (-1 == ulchnn)
306812 + return -1;
306818 + return -1;
306867 + if (-1 == ulchnn)
306868 + return -1;
306874 + return -1;
306920 + return -1;
306924 + if (ret == -1) {
306926 + return -1;
306936 + int ret = -1;
306942 + return -1;
306946 + if (ret == -1) {
306948 + return -1;
306970 + return -EINVAL;
306988 + plli->next_lli = (phy_address + (j + 1) * sizeof(dmac_lli)) &
306989 + (~(HIEDMAC_LLI_ALIGN - 1));
306990 + if (j < lli_num - 1) {
306991 + plli->next_lli |= HIEDMAC_LLI_ENABLE;
306992 + plli->count = uwnumtransfers;
306994 + plli->next_lli |= HIEDMAC_LLI_DISABLE;
306995 + plli->count = totaltransfersize % uwnumtransfers;
306998 + plli->src_addr = psource;
306999 + plli->dest_addr = pdest;
307000 + plli->config = HIEDMAC_CxCONFIG_M2M_LLI;
307020 + hiedmacv310_trace(4, "plli.src_addr: 0x%lx\n", plli->src_addr);
307021 + hiedmacv310_trace(4, "plli.dst_addr: 0x%lx\n", plli->dest_addr);
307022 + hiedmacv310_trace(4, "plli.next_lli: 0x%lx\n", plli->next_lli);
307023 + hiedmacv310_trace(4, "plli.count: 0x%d\n", plli->count);
307025 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
307028 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
307031 + hiedmacv310_writel(plli->count, dma_regbase + HIEDMAC_Cx_CNT0(i));
307033 + hiedmacv310_writel(plli->src_addr & 0xffffffff,
307036 + hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff,
307039 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
307042 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
307045 + hiedmacv310_writel(plli->config | EDMA_CH_ENABLE,
307062 + return -EINVAL;
307110 + return -EINVAL;
307128 + return -1;
307130 + left_size -= dma_size;
307155 + ret = -1;
307163 + ret = -ENOMEM;
307170 + ret = -EIO;
307176 + ret = -EIO;
307202 + return -1;
307208 + if (dma_phys & (HIEDMAC_LLI_ALIGN - 1)) {
307209 + return -1;
307219 + struct regmap *misc = hiedmac->misc_regmap;
307226 + if (peripheral_info[i].host_sel == hiedmac->id) {
307229 + return -1;
307232 + offset = hiedmac->misc_ctrl_base + (count & (~0x3));
307249 + struct platform_device *platdev = hiedmac->pdev;
307250 + struct device_node *np = platdev->dev.of_node;
307253 + ret = of_property_read_u32((&platdev->dev)->of_node,
307254 + "devid", &(hiedmac->id));
307257 + return -ENODEV;
307260 + hiedmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk");
307261 + if (IS_ERR(hiedmac->clk)) {
307263 + return PTR_ERR(hiedmac->clk);
307266 + hiedmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk");
307267 + if (IS_ERR(hiedmac->axi_clk)) {
307269 + return PTR_ERR(hiedmac->axi_clk);
307272 + hiedmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset");
307273 + if (IS_ERR(hiedmac->rstc)) {
307275 + return PTR_ERR(hiedmac->rstc);
307281 + return -ENODEV;
307284 + hiedmac->base = devm_ioremap_resource(&(platdev->dev), res);
307285 + if (IS_ERR(hiedmac->base)) {
307287 + return PTR_ERR(hiedmac->base);
307291 + hiedmac->misc_regmap = 0;
307293 + hiedmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap");
307294 + if (IS_ERR(hiedmac->misc_regmap)) {
307296 + return PTR_ERR(hiedmac->misc_regmap);
307299 + ret = of_property_read_u32((&platdev->dev)->of_node,
307300 + "misc_ctrl_base", &(hiedmac->misc_ctrl_base));
307302 + hiedmacv310_error("get dma-misc_ctrl_base fail\n");
307303 + return -ENODEV;
307306 + hiedmac->irq = platform_get_irq(platdev, 0);
307307 + if (unlikely(hiedmac->irq < 0))
307308 + return -ENODEV;
307310 + ret = of_property_read_u32((&platdev->dev)->of_node,
307311 + "dma-channels", &(hiedmac->channels));
307313 + hiedmacv310_error("get dma-channels fail\n");
307314 + return -ENODEV;
307316 + ret = of_property_read_u32((&platdev->dev)->of_node,
307317 + "dma-requests", &(hiedmac->slave_requests));
307319 + hiedmacv310_error("get dma-requests fail\n");
307320 + return -ENODEV;
307322 + hiedmacv310_trace(2, "dma-channels = %d, dma-requests = %d\n",
307323 + hiedmac->channels, hiedmac->slave_requests);
307341 + channel_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_STAT);
307347 + for (i = 0; i < hiedmac->channels; i++) {
307350 + channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC1_RAW);
307353 + hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC1_RAW);
307355 + channel_tc_status = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_TC2);
307358 + hiedmacv310_writel(channel_tc_status << i, hiedmac->base + HIEDMAC_INT_TC2_RAW);
307360 + channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
307362 + channel_err_status[1] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR2);
307364 + channel_err_status[2] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR3);
307370 + hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
307371 + hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
307372 + hiedmacv310_writel(1 << i, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
307396 + ret = -ENOMEM;
307399 + hiedmac->pdev = pdev;
307407 + clk_prepare_enable(hiedmac->clk);
307408 + clk_prepare_enable(hiedmac->axi_clk);
307410 + reset_control_deassert(hiedmac->rstc);
307412 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC1_RAW);
307413 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_TC2_RAW);
307414 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR1_RAW);
307415 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR2_RAW);
307416 + hiedmacv310_writel(HIEDMAC_ALL_CHAN_CLR, hiedmac->base + HIEDMAC_INT_ERR3_RAW);
307419 + hiedmac->base + HIEDMAC_INT_TC1_MASK);
307421 + hiedmac->base + HIEDMAC_INT_TC2_MASK);
307423 + hiedmac->base + HIEDMAC_INT_ERR1_MASK);
307425 + hiedmac->base + HIEDMAC_INT_ERR2_MASK);
307427 + hiedmac->base + HIEDMAC_INT_ERR3_MASK);
307432 + dma_regbase = hiedmac->base;
307434 + ret = allocate_dmalli_space(&(hiedmac->pdev->dev), pllihead,
307441 + ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
307488 diff --git a/drivers/hiedmac/hiedmacv310.h b/drivers/hiedmac/hiedmacv310.h
307491 --- /dev/null
307493 @@ -0,0 +1,184 @@
307495 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
307523 +#define HIEDMAC_TRANS_MAXSIZE (64 * 1024 - 1)
307657 +#define DMAC_NOT_USE (-1)
307678 diff --git a/drivers/hisilicon/Kconfig b/drivers/hisilicon/Kconfig
307681 --- /dev/null
307683 @@ -0,0 +1,4 @@
307688 diff --git a/drivers/hisilicon/Makefile b/drivers/hisilicon/Makefile
307691 --- /dev/null
307693 @@ -0,0 +1 @@
307694 +obj-$(CONFIG_CMA) += cma/
307695 diff --git a/drivers/hisilicon/cma/Kconfig b/drivers/hisilicon/cma/Kconfig
307698 --- /dev/null
307700 @@ -0,0 +1,16 @@
307717 diff --git a/drivers/hisilicon/cma/Makefile b/drivers/hisilicon/cma/Makefile
307720 --- /dev/null
307722 @@ -0,0 +1,2 @@
307724 +obj-$(CONFIG_CMA) += hi_cma.o
307725 diff --git a/drivers/hisilicon/cma/hi_cma.c b/drivers/hisilicon/cma/hi_cma.c
307728 --- /dev/null
307730 @@ -0,0 +1,199 @@
307798 + strncpy(tmpline, s, sizeof(tmpline) - 1);
307799 + tmpline[sizeof(tmpline) - 1] = '\0';
307928 +RESERVEDMEM_OF_DECLARE(cma, "hisi-mmz", hisi_mmz_setup);
307930 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
307932 --- a/drivers/i2c/busses/Kconfig
307934 @@ -593,6 +593,16 @@ config I2C_GPIO_FAULT_INJECTOR
307935 faults to an I2C bus, so another bus master can be stress-tested.
307946 + will be called i2c-hibvt.
307951 @@ -1361,4 +1371,20 @@ config I2C_FSI
307953 called as i2c-fsi.
307970 + because DMA for 0xFFC one-time largest data transfers;
307972 diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
307974 --- a/drivers/i2c/busses/Makefile
307976 @@ -58,6 +58,7 @@ obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
307977 obj-$(CONFIG_I2C_EMEV2) += i2c-emev2.o
307978 obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
307979 obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
307980 +obj-$(CONFIG_I2C_HIBVT) += i2c-hibvt.o
307981 obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
307982 obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o
307983 obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
307984 diff --git a/drivers/i2c/busses/i2c-hibvt.c b/drivers/i2c/busses/i2c-hibvt.c
307987 --- /dev/null
307988 +++ b/drivers/i2c/busses/i2c-hibvt.c
307989 @@ -0,0 +1,1451 @@
308017 +#include <linux/dma-mapping.h>
308052 + * I2C Global Config Register -- HIBVT_I2C_GLB
308060 + * I2C Timing CMD Register -- HIBVT_I2C_CMD_BASE + n * 4 (n = 0, 1, 2, ... 31)
308079 + * I2C Control Register 1 -- HIBVT_I2C_CTRL1
308087 + * I2C Status Register -- HIBVT_I2C_STAT
308093 + * I2C Interrupt status and mask Register --
308155 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308161 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308167 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308174 + dev_err(i2c->dev, "wait Timeout!\n");
308178 + val = readl(i2c->base + HIBVT_I2C_CTRL2);
308183 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308186 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308192 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308196 + writel(val, i2c->base + HIBVT_I2C_CTRL2);
308203 + val = readl(i2c->base + HIBVT_I2C_GLB);
308205 + writel(val, i2c->base + HIBVT_I2C_GLB);
308212 + val = readl(i2c->base + HIBVT_I2C_GLB);
308214 + writel(val, i2c->base + HIBVT_I2C_GLB);
308220 + writel(flag, i2c->base + HIBVT_I2C_INTR_EN);
308228 + val = readl(i2c->base + HIBVT_I2C_INTR_EN);
308230 + writel(val, i2c->base + HIBVT_I2C_INTR_EN);
308237 + val = readl(i2c->base + HIBVT_I2C_INTR_STAT);
308238 + writel(INTR_ALL_MASK, i2c->base + HIBVT_I2C_INTR_RAW);
308246 + dev_dbg(i2c->dev, "hii2c reg: offset=0x%x, cmd=0x%x...\n",
308248 + writel(cmd, i2c->base + HIBVT_I2C_CMD_BASE + *offset * 4);
308257 + struct i2c_msg *msg = i2c->msg;
308260 + if (msg->flags & I2C_M_TEN) {
308262 + addr = ((msg->addr & 0x300) << 1) | 0xf000;
308263 + if (msg->flags & I2C_M_RD)
308267 + addr |= msg->addr & 0xff;
308269 + addr = (msg->addr & 0x7f) << 1;
308270 + if (msg->flags & I2C_M_RD)
308274 + writel(addr, i2c->base + HIBVT_I2C_DATA1);
308284 + val = readl(i2c->base + HIBVT_I2C_CTRL1);
308286 + writel(val, i2c->base + HIBVT_I2C_CTRL1);
308295 + val = readl(i2c->base + HIBVT_I2C_STAT);
308304 + dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
308305 + readl(i2c->base + HIBVT_I2C_INTR_RAW), val);
308306 + return -EIO;
308315 + val = readl(i2c->base + HIBVT_I2C_STAT);
308324 + dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
308325 + readl(i2c->base + HIBVT_I2C_INTR_RAW), val);
308326 + return -EIO;
308335 + val = readl(i2c->base + HIBVT_I2C_INTR_RAW);
308337 + dev_err(i2c->dev, "wait idle abort!, RIS: 0x%x\n",
308339 + return -EIO;
308350 + dev_err(i2c->dev, "wait idle timeout, RIS: 0x%x, SR: 0x%x\n",
308351 + val, readl(i2c->base + HIBVT_I2C_STAT));
308353 + return -EIO;
308362 + freq = i2c->freq;
308363 + clk_rate = clk_get_rate(i2c->clk);
308367 + i2c->freq = max_freq;
308368 + freq = i2c->freq;
308382 + writel(val, i2c->base + HIBVT_I2C_SCL_H);
308383 + writel(val, i2c->base + HIBVT_I2C_SCL_L);
308390 + writel(val, i2c->base + HIBVT_I2C_SCL_H);
308392 + writel(val, i2c->base + HIBVT_I2C_SCL_L);
308395 + val = readl(i2c->base + HIBVT_I2C_GLB);
308398 + writel(val, i2c->base + HIBVT_I2C_GLB);
308406 + writel(I2C_TXF_WATER, i2c->base + HIBVT_I2C_TX_WATER);
308407 + writel(I2C_RXF_WATER, i2c->base + HIBVT_I2C_RX_WATER);
308422 + * hibvt_i2c_cfg_cmd - config i2c controller command sequence
308430 + struct i2c_msg *msg = i2c->msg;
308433 + if (i2c->msg_idx == 0)
308438 + if (msg->flags & I2C_M_TEN) {
308439 + if (i2c->msg_idx == 0) {
308449 + if (msg->flags & I2C_M_IGNORE_NAK)
308454 + if (msg->flags & I2C_M_RD) {
308455 + if (msg->len >= 2) {
308456 + writel(offset, i2c->base + HIBVT_I2C_DST1);
308457 + writel(msg->len - 2, i2c->base + HIBVT_I2C_LOOP1);
308465 + writel(offset, i2c->base + HIBVT_I2C_DST1);
308466 + writel(msg->len - 1, i2c->base + HIBVT_I2C_LOOP1);
308470 + if (msg->flags & I2C_M_IGNORE_NAK)
308478 + if ((i2c->msg_idx == (i2c->msg_num - 1)) || (msg->flags & I2C_M_STOP)) {
308479 + dev_dbg(i2c->dev, "run to %s %d...TX STOP\n",
308489 + struct i2c_msg *msg = i2c->msg;
308493 + if (i2c->msg_idx == 0) {
308499 + if (msg->flags & I2C_M_TEN) {
308500 + if (i2c->msg_idx == 0) {
308510 + if (msg->flags & I2C_M_IGNORE_NAK) {
308516 + if (msg->flags & I2C_M_RD) {
308517 + if (msg->len >= 2) {
308518 + writel(offset, i2c->base + HIBVT_I2C_DST1);
308519 + writel(msg->len - 2, i2c->base + HIBVT_I2C_LOOP1);
308527 + for(i = 0; i < reg_data_width - 1; i++){
308538 + if(((msg->len / reg_data_width) - 1) > 0){
308539 + writel(0, i2c->base + HIBVT_I2C_DST2);
308540 + writel((msg->len / reg_data_width) - 1, i2c->base + HIBVT_I2C_LOOP2);
308549 + val = readl(i2c->base + HIBVT_I2C_GLB);
308562 + if (chan == -1)
308574 + if (chan == -1)
308585 + struct i2c_msg *msg = i2c->msg;
308589 + writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
308596 + chan = dma_to_i2c(dma_dst_addr, (i2c->phybase + HIBVT_I2C_TXF),
308597 + msg->len);
308598 + if (chan == -1) {
308599 + status = -1;
308603 + val = readl(i2c->base + HIBVT_I2C_CTRL1);
308606 + writel(val, i2c->base + HIBVT_I2C_CTRL1);
308609 + status = -1;
308627 + struct i2c_msg *msg = i2c->msg;
308632 + writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
308639 + chan = dma_to_i2c(dma_dst_addr, (i2c->phybase + HIBVT_I2C_TXF),
308640 + msg->len);
308641 + if (chan == -1) {
308642 + status = -1;
308646 + val = readl(i2c->base + HIBVT_I2C_CTRL1);
308649 + writel(val, i2c->base + HIBVT_I2C_CTRL1);
308660 + struct i2c_msg *msg = i2c->msg;
308664 + writel(0x0, i2c->base + HIBVT_I2C_RX_WATER);
308671 + chan = i2c_to_dma((i2c->phybase + HIBVT_I2C_RXF),
308672 + dma_dst_addr, msg->len);
308673 + if (chan == -1) {
308674 + status = -1;
308678 + val = readl(i2c->base + HIBVT_I2C_CTRL1);
308681 + writel(val, i2c->base + HIBVT_I2C_CTRL1);
308684 + status = -1;
308700 + if (should_copy_to_continuous_mem(i2c->msg->buf)) {
308701 + i2c->msg->highmem_buf = i2c->msg->buf;
308702 + i2c->msg->buf = kmalloc(i2c->msg->len, GFP_KERNEL | __GFP_ATOMIC);
308703 + if (i2c->msg->buf == NULL) {
308704 + i2c->msg->buf = i2c->msg->highmem_buf;
308705 + dev_err(i2c->dev, "Allocate continuous memory fail.\n");
308706 + return -EINVAL;
308709 + i2c->msg->highmem_buf = NULL;
308717 + struct i2c_msg *msg = i2c->msg;
308720 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308721 + __func__, __LINE__, msg->flags, msg->len);
308724 + return -EINVAL;
308726 + if (msg->flags & I2C_M_RD) {
308728 + dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
308729 + msg->len, DMA_FROM_DEVICE);
308730 + status = dma_mapping_error(i2c->dev, dma_dst_addr);
308732 + dev_err(i2c->dev, "DMA mapping failed\n");
308738 + dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_FROM_DEVICE);
308740 + if (i2c->msg->highmem_buf)
308741 + memcpy(msg->highmem_buf, msg->buf, msg->len);
308743 + if (i2c->msg->highmem_buf)
308744 + memcpy(msg->buf, msg->highmem_buf, msg->len);
308746 + dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
308747 + msg->len, DMA_TO_DEVICE);
308748 + status = dma_mapping_error(i2c->dev, dma_dst_addr);
308750 + dev_err(i2c->dev, "DMA mapping failed\n");
308755 + dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_TO_DEVICE);
308760 + if (i2c->msg->highmem_buf) {
308761 + kfree(msg->buf);
308762 + msg->buf = msg->highmem_buf;
308763 + msg->highmem_buf = NULL;
308777 + struct i2c_msg *msg = i2c->msg;
308781 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308782 + __func__, __LINE__, msg->flags, msg->len);
308785 + return -EINVAL;
308787 + if (msg->flags & I2C_M_RD) {
308789 + dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
308790 + msg->len, DMA_FROM_DEVICE);
308791 + status = dma_mapping_error(i2c->dev, dma_dst_addr);
308793 + dev_err(i2c->dev, "DMA mapping failed\n");
308799 + dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_FROM_DEVICE);
308801 + if (i2c->msg->highmem_buf)
308802 + memcpy(msg->highmem_buf, msg->buf, msg->len);
308804 + if (i2c->msg->highmem_buf)
308805 + memcpy(msg->buf, msg->highmem_buf, msg->len);
308807 + dma_dst_addr = dma_map_single(i2c->dev, msg->buf,
308808 + msg->len, DMA_TO_DEVICE);
308809 + status = dma_mapping_error(i2c->dev, dma_dst_addr);
308811 + dev_err(i2c->dev, "DMA mapping failed\n");
308816 + dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_TO_DEVICE);
308821 + if (i2c->msg->highmem_buf) {
308822 + kfree(msg->buf);
308823 + msg->buf = msg->highmem_buf;
308824 + msg->highmem_buf = NULL;
308833 + struct i2c_msg *msg = i2c->msg;
308835 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308836 + __func__, __LINE__, msg->flags, msg->len);
308845 + i2c->msg_buf_ptr = 0;
308847 + if (msg->flags & I2C_M_RD) {
308848 + while (i2c->msg_buf_ptr < msg->len) {
308853 + val = readl(i2c->base + HIBVT_I2C_RXF);
308854 + msg->buf[i2c->msg_buf_ptr] = val;
308855 + i2c->msg_buf_ptr++;
308858 + while (i2c->msg_buf_ptr < msg->len) {
308863 + val = msg->buf[i2c->msg_buf_ptr];
308864 + writel(val, i2c->base + HIBVT_I2C_TXF);
308865 + i2c->msg_buf_ptr++;
308880 + struct i2c_msg *msg = i2c->msg;
308882 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308883 + __func__, __LINE__, msg->flags, msg->len);
308892 + i2c->msg_buf_ptr = 0;
308894 + if (msg->flags & I2C_M_RD) {
308895 + while (i2c->msg_buf_ptr < msg->len) {
308901 + val = readl(i2c->base + HIBVT_I2C_RXF);
308902 + msg->buf[i2c->msg_buf_ptr] = val;
308903 + i2c->msg_buf_ptr++;
308907 + while (i2c->msg_buf_ptr < msg->len) {
308913 + val = msg->buf[i2c->msg_buf_ptr];
308914 + writel(val, i2c->base + HIBVT_I2C_TXF);
308915 + i2c->msg_buf_ptr++;
308927 + struct i2c_msg *msg = i2c->msg;
308929 + spin_lock(&i2c->lock);
308932 + dev_dbg(i2c->dev, "%s RIS: 0x%x\n", __func__, irq_status);
308935 + dev_dbg(i2c->dev, "no irq\n");
308940 + dev_err(i2c->dev, "irq handle abort, RIS: 0x%x\n",
308942 + i2c->status = -EIO;
308945 + complete(&i2c->msg_complete);
308949 + if (msg->flags & I2C_M_RD) {
308950 + while ((readl(i2c->base + HIBVT_I2C_STAT) & STAT_RXF_NOE_MASK)
308951 + && (i2c->msg_buf_ptr < msg->len)) {
308952 + msg->buf[i2c->msg_buf_ptr] =
308953 + readl(i2c->base + HIBVT_I2C_RXF);
308954 + i2c->msg_buf_ptr++;
308957 + while ((readl(i2c->base + HIBVT_I2C_STAT) & STAT_TXF_NOF_MASK)
308958 + && (i2c->msg_buf_ptr < msg->len)) {
308959 + writel(msg->buf[i2c->msg_buf_ptr],
308960 + i2c->base + HIBVT_I2C_TXF);
308961 + i2c->msg_buf_ptr++;
308965 + if (i2c->msg_buf_ptr >= msg->len)
308969 + dev_dbg(i2c->dev, "cmd done\n");
308970 + i2c->status = 0;
308973 + complete(&i2c->msg_complete);
308977 + spin_unlock(&i2c->lock);
308985 + struct i2c_msg *msg = i2c->msg;
308989 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
308990 + __func__, __LINE__, msg->flags, msg->len);
308992 + reinit_completion(&i2c->msg_complete);
308993 + i2c->msg_buf_ptr = 0;
308994 + i2c->status = -EIO;
308996 + spin_lock_irqsave(&i2c->lock, flags);
309000 + if (msg->flags & I2C_M_RD)
309008 + spin_unlock_irqrestore(&i2c->lock, flags);
309010 + timeout = wait_for_completion_timeout(&i2c->msg_complete,
309013 + spin_lock_irqsave(&i2c->lock, flags);
309016 + status = -EIO;
309017 + dev_err(i2c->dev, "%s timeout\n",
309018 + msg->flags & I2C_M_RD ? "rx" : "tx");
309020 + status = i2c->status;
309025 + spin_unlock_irqrestore(&i2c->lock, flags);
309036 + int status = -EINVAL;
309040 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
309041 + return -EINVAL;
309044 + spin_lock_irqsave(&i2c->lock, flags);
309046 + i2c->msg = msgs;
309047 + i2c->msg_num = num;
309048 + i2c->msg_idx = 0;
309050 + while (i2c->msg_idx < i2c->msg_num) {
309052 + if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) &&
309053 + (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) {
309057 + } else if (i2c->irq >= 0) {
309059 + if (i2c->irq >= 0) {
309061 + spin_unlock_irqrestore(&i2c->lock, flags);
309063 + spin_lock_irqsave(&i2c->lock, flags);
309071 + i2c->msg++;
309072 + i2c->msg_idx++;
309075 + if (!status || i2c->msg_idx > 0)
309076 + status = i2c->msg_idx;
309078 + spin_unlock_irqrestore(&i2c->lock, flags);
309090 + int status = -EINVAL;
309093 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
309094 + return -EINVAL;
309096 + spin_lock_irqsave(&i2c->lock, flags);
309097 + i2c->msg = msgs;
309098 + i2c->msg_num = num;
309099 + i2c->msg_idx = 0;
309100 + while (i2c->msg_idx < i2c->msg_num) {
309102 + if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) &&
309103 + (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) {
309113 + i2c->msg++;
309114 + i2c->msg_idx++;
309116 + if (!status || i2c->msg_idx > 0)
309117 + status = i2c->msg_idx;
309118 + spin_unlock_irqrestore(&i2c->lock, flags);
309126 + int status = -EINVAL;
309129 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
309130 + return -EINVAL;
309132 + spin_lock_irqsave(&i2c->lock, flags);
309133 + i2c->msg = msgs;
309134 + i2c->msg_num = num;
309135 + i2c->msg_idx = 0;
309136 + while (i2c->msg_idx < i2c->msg_num) {
309137 + if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN) && (i…
309150 + i2c->msg++;
309151 + i2c->msg_idx++;
309153 + if (!status || i2c->msg_idx > 0) {
309154 + status = i2c->msg_idx;
309156 + spin_unlock_irqrestore(&i2c->lock, flags);
309160 + * hi_i2c_master_recv - issue a single I2C message in master receive mode
309173 + return -EIO;
309178 + * hi_i2c_master_send - issue a single I2C message in master transmit mode
309192 + if ((client == NULL) || (buf == NULL) || (client->adapter == NULL) ||
309195 + return -EINVAL;
309198 + if ((client->addr > 0x3ff) ||
309199 + (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
309201 + return -EINVAL;
309204 + adap = client->adapter;
309205 + msg.addr = client->addr;
309206 + msg.flags = client->flags;
309213 + return (msgs_count == 1) ? count : -EIO;
309221 + struct i2c_adapter *adap = client->adapter;
309225 + if ((client->addr > 0x3ff)
309226 + || (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
309228 + return -EINVAL;
309231 + msg.addr = client->addr;
309232 + msg.flags = client->flags;
309237 + return -EINVAL;
309243 + return (msgs_count == 1) ? count : -EIO;
309247 + * hi_i2c_transfer - execute a single or combined I2C message
309265 + return -EINVAL;
309271 + return -EINVAL;
309277 + return -EINVAL;
309308 + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
309310 + return -ENOMEM;
309313 + i2c->dev = &pdev->dev;
309314 + spin_lock_init(&i2c->lock);
309315 + init_completion(&i2c->msg_complete);
309319 + dev_err(i2c->dev, "Invalid mem resource./n");
309320 + return -ENODEV;
309323 + i2c->phybase = res->start;
309324 + i2c->base = devm_ioremap_resource(&pdev->dev, res);
309325 + if (IS_ERR(i2c->base)) {
309326 + dev_err(i2c->dev, "cannot ioremap resource\n");
309327 + return -ENOMEM;
309330 + i2c->clk = devm_clk_get(&pdev->dev, NULL);
309331 + if (IS_ERR(i2c->clk)) {
309332 + dev_err(i2c->dev, "cannot get clock\n");
309333 + return -ENOENT;
309335 + clk_prepare_enable(i2c->clk);
309337 + if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
309338 + &i2c->freq)) {
309339 + dev_warn(i2c->dev, "setting default clock-frequency@%dHz\n",
309341 + i2c->freq = I2C_DEFAULT_FREQUENCY;
309347 + i2c->irq = platform_get_irq(pdev, 0);
309348 + status = devm_request_irq(&pdev->dev, i2c->irq, hibvt_i2c_isr,
309349 + IRQF_SHARED, dev_name(&pdev->dev), i2c);
309351 + dev_dbg(i2c->dev, "falling back to polling mode");
309352 + i2c->irq = -1;
309355 + adap = &i2c->adap;
309357 + adap->owner = THIS_MODULE;
309358 + strlcpy(adap->name, "hibvt-i2c", sizeof(adap->name));
309359 + adap->dev.parent = &pdev->dev;
309360 + adap->dev.of_node = pdev->dev.of_node;
309361 + adap->algo = &hibvt_i2c_algo;
309366 + dev_err(i2c->dev, "failed to add bus to i2c core\n");
309370 + dev_info(i2c->dev, "%s%d@%dhz registered\n",
309371 + adap->name, adap->nr, i2c->freq);
309376 + clk_disable_unprepare(i2c->clk);
309384 + clk_disable_unprepare(i2c->clk);
309385 + i2c_del_adapter(&i2c->adap);
309395 + i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
309396 + clk_disable_unprepare(i2c->clk);
309397 + i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
309406 + i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
309407 + clk_prepare_enable(i2c->clk);
309409 + i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
309419 + { .compatible = "hisilicon,hibvt-i2c" },
309420 + { .compatible = "hisilicon,hi3516cv300-i2c" },
309421 + { .compatible = "hisilicon,hi3536dv100-i2c" },
309428 + .name = "hibvt-i2c",
309441 diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c
309443 --- a/drivers/i2c/i2c-dev.c
309444 +++ b/drivers/i2c/i2c-dev.c
309445 @@ -239,7 +239,42 @@ static int i2cdev_check_addr(struct i2c_adapter *adapter, unsigned int addr)
309459 + return -EFAULT;
309461 + if(client->flags & I2C_M_16BIT_REG)
309466 + if(client->flags & I2C_M_16BIT_DATA)
309477 + return -EINVAL;
309488 @@ -487,6 +522,24 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long ar…
309490 client->adapter->timeout = msecs_to_jiffies(arg * 10);
309494 + client->flags |= I2C_M_16BIT_REG;
309496 + client->flags &= ~I2C_M_16BIT_REG;
309499 + client->flags |= I2C_M_16BIT_DATA;
309501 + client->flags &= ~I2C_M_16BIT_DATA;
309504 + client->flags |= I2C_M_DMA;
309506 + client->flags &= ~I2C_M_DMA;
309513 diff --git a/drivers/infiniband/hw/hfi1/mmu_rb.c b/drivers/infiniband/hw/hfi1/mmu_rb.c
309515 --- a/drivers/infiniband/hw/hfi1/mmu_rb.c
309517 @@ -1,4 +1,5 @@
309520 * Copyright(c) 2016 - 2017 Intel Corporation.
309523 @@ -48,23 +49,11 @@
309532 -struct mmu_rb_handler {
309533 - struct mmu_notifier mn;
309534 - struct rb_root_cached root;
309535 - void *ops_arg;
309536 - spinlock_t lock; /* protect the RB tree */
309537 - struct mmu_rb_ops *ops;
309538 - struct mm_struct *mm;
309539 - struct list_head lru_list;
309540 - struct work_struct del_work;
309541 - struct list_head del_list;
309542 - struct workqueue_struct *wq;
309543 -};
309544 -
309548 @@ -94,37 +83,36 @@ static unsigned long mmu_node_last(struct mmu_rb_node *node)
309549 return PAGE_ALIGN(node->addr + node->len) - 1;
309552 -int hfi1_mmu_rb_register(void *ops_arg, struct mm_struct *mm,
309558 - struct mmu_rb_handler *handlr;
309562 - handlr = kmalloc(sizeof(*handlr), GFP_KERNEL);
309563 - if (!handlr)
309566 return -ENOMEM;
309568 - handlr->root = RB_ROOT_CACHED;
309569 - handlr->ops = ops;
309570 - handlr->ops_arg = ops_arg;
309571 - INIT_HLIST_NODE(&handlr->mn.hlist);
309572 - spin_lock_init(&handlr->lock);
309573 - handlr->mn.ops = &mn_opts;
309574 - handlr->mm = mm;
309575 - INIT_WORK(&handlr->del_work, handle_remove);
309576 - INIT_LIST_HEAD(&handlr->del_list);
309577 - INIT_LIST_HEAD(&handlr->lru_list);
309578 - handlr->wq = wq;
309579 -
309580 - ret = mmu_notifier_register(&handlr->mn, handlr->mm);
309581 + h->root = RB_ROOT_CACHED;
309582 + h->ops = ops;
309583 + h->ops_arg = ops_arg;
309584 + INIT_HLIST_NODE(&h->mn.hlist);
309585 + spin_lock_init(&h->lock);
309586 + h->mn.ops = &mn_opts;
309587 + INIT_WORK(&h->del_work, handle_remove);
309588 + INIT_LIST_HEAD(&h->del_list);
309589 + INIT_LIST_HEAD(&h->lru_list);
309590 + h->wq = wq;
309592 + ret = mmu_notifier_register(&h->mn, current->mm);
309594 - kfree(handlr);
309599 - *handler = handlr;
309604 @@ -136,7 +124,7 @@ void hfi1_mmu_rb_unregister(struct mmu_rb_handler *handler)
309608 - mmu_notifier_unregister(&handler->mn, handler->mm);
309609 + mmu_notifier_unregister(&handler->mn, handler->mn.mm);
309613 @@ -168,6 +156,10 @@ int hfi1_mmu_rb_insert(struct mmu_rb_handler *handler,
309616 trace_hfi1_mmu_rb_insert(mnode->addr, mnode->len);
309618 + if (current->mm != handler->mn.mm)
309619 + return -EPERM;
309621 spin_lock_irqsave(&handler->lock, flags);
309622 node = __mmu_rb_search(handler, mnode->addr, mnode->len);
309624 @@ -182,6 +174,7 @@ int hfi1_mmu_rb_insert(struct mmu_rb_handler *handler,
309625 __mmu_int_rb_remove(mnode, &handler->root);
309626 list_del(&mnode->list); /* remove from LRU list */
309628 + mnode->handler = handler;
309630 spin_unlock_irqrestore(&handler->lock, flags);
309632 @@ -219,6 +212,9 @@ bool hfi1_mmu_rb_remove_unless_exact(struct mmu_rb_handler *handler,
309636 + if (current->mm != handler->mn.mm)
309639 spin_lock_irqsave(&handler->lock, flags);
309642 @@ -241,6 +237,9 @@ void hfi1_mmu_rb_evict(struct mmu_rb_handler *handler, void *evict_arg)
309646 + if (current->mm != handler->mn.mm)
309651 spin_lock_irqsave(&handler->lock, flags);
309652 @@ -274,6 +273,9 @@ void hfi1_mmu_rb_remove(struct mmu_rb_handler *handler,
309656 + if (current->mm != handler->mn.mm)
309660 trace_hfi1_mmu_rb_remove(node->addr, node->len);
309661 spin_lock_irqsave(&handler->lock, flags);
309662 diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c
309664 --- a/drivers/input/mousedev.c
309666 @@ -872,7 +872,7 @@ static struct mousedev *mousedev_create(struct input_dev *dev,
309669 dev_set_name(&mousedev->dev, "mice");
309670 -
309671 + mousedev->open = 1;
309672 mousedev->open_device = mixdev_open_devices;
309673 mousedev->close_device = mixdev_close_devices;
309675 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
309677 --- a/drivers/irqchip/irq-gic.c
309678 +++ b/drivers/irqchip/irq-gic.c
309679 @@ -122,6 +122,24 @@ static DEFINE_RAW_SPINLOCK(cpu_map_lock);
309704 @@ -342,6 +360,29 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
309734 @@ -363,6 +404,15 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
309750 @@ -474,7 +524,31 @@ static void gic_cpu_if_up(struct gic_chip_data *gic)
309755 +#include "irq-map-hi3559av100.h"
309761 + unsigned int gic_irqs = gic->gic_irqs;
309782 @@ -497,6 +571,7 @@ static void gic_dist_init(struct gic_chip_data *gic)
309790 @@ -1086,7 +1161,9 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
309794 -
309798 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
309799 /* Frankein-GIC without banked registers... */
309801 @@ -1166,7 +1243,25 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start,
309805 - gic_dist_init(gic);
309828 diff --git a/drivers/irqchip/irq-map-hi3559av100.h b/drivers/irqchip/irq-map-hi3559av100.h
309831 --- /dev/null
309832 +++ b/drivers/irqchip/irq-map-hi3559av100.h
309833 @@ -0,0 +1,115 @@
309893 + /* USB 0 USB 1 SLVS-EC res */
309945 +}; /* [32 - 255] */
309947 +#error "should not include irq-map-hi3559av100.h twice"
309949 diff --git a/drivers/media/usb/gspca/ov519.c b/drivers/media/usb/gspca/ov519.c
309951 --- a/drivers/media/usb/gspca/ov519.c
309953 @@ -3492,6 +3492,11 @@ static void ov511_mode_init_regs(struct sd *sd)
309957 + if (alt->desc.bNumEndpoints < 1) {
309958 + sd->gspca_dev.usb_err = -ENODEV;
309962 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
309965 @@ -3623,6 +3628,11 @@ static void ov518_mode_init_regs(struct sd *sd)
309969 + if (alt->desc.bNumEndpoints < 1) {
309970 + sd->gspca_dev.usb_err = -ENODEV;
309974 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
309977 diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
309979 --- a/drivers/mfd/Kconfig
309981 @@ -457,6 +457,17 @@ config MFD_HI655X_PMIC
309999 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
310001 --- a/drivers/mfd/Makefile
310003 @@ -199,6 +199,7 @@ obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
310004 obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o
310005 obj-$(CONFIG_MFD_ATMEL_HLCDC) += atmel-hlcdc.o
310006 obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o
310007 +obj-$(CONFIG_MFD_HISI_FMC) += hisi_fmc.o
310008 obj-$(CONFIG_MFD_INTEL_LPSS) += intel-lpss.o
310009 obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o
310010 obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o
310011 diff --git a/drivers/mfd/hisi_fmc.c b/drivers/mfd/hisi_fmc.c
310014 --- /dev/null
310016 @@ -0,0 +1,134 @@
310037 +#include <linux/dma-mapping.h>
310050 +/* ------------------------------------------------------------------------ */
310054 + .of_compatible = "hisilicon,fmc-spi-nor",
310058 + .of_compatible = "hisilicon,fmc-spi-nand",
310062 + .of_compatible = "hisilicon,fmc-nand",
310070 + struct device *dev = &pdev->dev;
310075 + return -ENOMEM;
310078 + fmc->regbase = devm_ioremap_resource(dev, res);
310079 + if (IS_ERR(fmc->regbase))
310080 + return PTR_ERR(fmc->regbase);
310083 + fmc->iobase = devm_ioremap_resource(dev, res);
310084 + if (IS_ERR(fmc->iobase))
310085 + return PTR_ERR(fmc->iobase);
310087 + fmc->clk = devm_clk_get(dev, NULL);
310088 + if (IS_ERR(fmc->clk))
310089 + return PTR_ERR(fmc->clk);
310091 + if (of_property_read_u32(dev->of_node, "max-dma-size", &fmc->dma_len)) {
310092 + dev_err(dev, "Please set the suitable max-dma-size value !!!\n");
310093 + return -ENOMEM;
310102 + fmc->buffer = dmam_alloc_coherent(dev, fmc->dma_len,
310103 + &fmc->dma_buffer, GFP_KERNEL);
310104 + if (IS_ERR(fmc->buffer))
310105 + return PTR_ERR(fmc->buffer);
310107 + mutex_init(&fmc->lock);
310125 + dmam_free_coherent(&pdev->dev, fmc->dma_len,
310126 + fmc->buffer, fmc->dma_buffer);
310127 + mfd_remove_devices(&pdev->dev);
310128 + mutex_destroy(&fmc->lock);
310134 + {.compatible = "hisilicon,hisi-fmc"},
310151 diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c
310153 --- a/drivers/mmc/core/block.c
310155 @@ -492,7 +492,7 @@ static int card_busy_detect(struct mmc_card *card, unsigned int timeout_ms,
310159 - struct mmc_command cmd = {}, sbc = {};
310164 @@ -569,15 +569,10 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md,
310167 if (idata->rpmb) {
310168 - sbc.opcode = MMC_SET_BLOCK_COUNT;
310169 - /*
310170 - * We don't do any blockcount validation because the max size
310171 - * may be increased by a future standard. We just copy the
310172 - * 'Reliable Write' bit here.
310173 - */
310174 - sbc.arg = data.blocks | (idata->ic.write_flag & BIT(31));
310175 - sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
310176 - mrq.sbc = &sbc;
310178 + idata->ic.write_flag & (1 << 31));
310184 diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
310186 --- a/drivers/mmc/core/core.c
310188 @@ -1701,6 +1701,9 @@ void mmc_power_off(struct mmc_host *host)
310192 + if (host->type == MMC_HOST_TYPE_MMC)
310198 @@ -2653,16 +2656,27 @@ void mmc_rescan(struct work_struct *work)
310202 + host->card_status = MMC_CARD_UNINIT;
310203 if (mmc_card_is_removable(host) && host->ops->get_cd &&
310204 host->ops->get_cd(host) == 0) {
310206 + if (host->ops->card_info_save)
310207 + host->ops->card_info_save(host);
310213 - if (!mmc_rescan_try_freq(host, max(freqs[i], host->f_min)))
310214 + if (!mmc_rescan_try_freq(host, max(freqs[i], host->f_min))) {
310215 + host->card_status = MMC_CARD_INIT;
310216 + if (host->ops->card_info_save)
310217 + host->ops->card_info_save(host);
310219 + } else if ((i == (ARRAY_SIZE(freqs) - 1)) ||
310220 + (freqs[i] <= host->f_min)) {
310221 + host->card_status = MMC_CARD_INIT_FAIL;
310224 if (freqs[i] <= host->f_min)
310227 diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
310229 --- a/drivers/mmc/core/mmc.c
310231 @@ -1401,7 +1401,9 @@ static int mmc_select_hs400es(struct mmc_card *card)
310235 -
310240 host->ios.enhanced_strobe = true;
310241 if (host->ops->hs400_enhanced_strobe)
310242 @@ -1499,7 +1501,8 @@ static int mmc_select_timing(struct mmc_card *card)
310246 - if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES)
310247 + if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES &&
310248 + card->host->caps & MMC_CAP_8_BIT_DATA)
310250 else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200)
310252 @@ -2206,6 +2209,7 @@ int mmc_attach_mmc(struct mmc_host *host)
310256 + host->type = MMC_HOST_TYPE_MMC;
310258 if (host->ocr_avail_mmc)
310259 host->ocr_avail = host->ocr_avail_mmc;
310260 diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
310262 --- a/drivers/mmc/core/sd.c
310264 @@ -1262,6 +1262,7 @@ int mmc_attach_sd(struct mmc_host *host)
310268 + host->type = MMC_HOST_TYPE_SD;
310270 if (host->ocr_avail_sd)
310271 host->ocr_avail = host->ocr_avail_sd;
310272 diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
310274 --- a/drivers/mmc/core/sdio.c
310276 @@ -31,6 +31,10 @@
310287 @@ -162,15 +166,19 @@ static int sdio_read_cccr(struct mmc_card *card, u32 ocr)
310288 if (mmc_host_uhs(card->host)) {
310290 card->sw_caps.sd3_bus_mode
310291 - |= SD_MODE_UHS_DDR50;
310296 card->sw_caps.sd3_bus_mode
310297 - |= SD_MODE_UHS_SDR50;
310302 card->sw_caps.sd3_bus_mode
310303 - |= SD_MODE_UHS_SDR104;
310310 @@ -1107,6 +1115,7 @@ int mmc_attach_sdio(struct mmc_host *host)
310314 + host->type = MMC_HOST_TYPE_SDIO;
310316 if (host->ocr_avail_sdio)
310317 host->ocr_avail = host->ocr_avail_sdio;
310318 @@ -1220,3 +1229,40 @@ int mmc_attach_sdio(struct mmc_host *host)
310328 + struct mmc_host *host = card->host;
310336 + mmc_set_clock(host, host->f_min);
310342 + err = -EINVAL;
310359 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
310361 --- a/drivers/mmc/host/Kconfig
310363 @@ -209,6 +209,21 @@ config MMC_SDHCI_CNS3XXX
310376 + This selects the SDHCI support for Hi35xx System-on-Chip devices.
310385 @@ -945,3 +960,18 @@ config MMC_SDHCI_OMAP
310405 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
310407 --- a/drivers/mmc/host/Makefile
310409 @@ -84,6 +84,21 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
310410 obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
310411 obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
310412 obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
310413 +obj-$(CONFIG_MMC_SDHCI_HISI) += sdhci-of-hisi.o
310414 +sdhci-of-hisi-objs := sdhci-hisi.o mci_proc.o
310415 +sdhci-of-hisi-$(CONFIG_ARCH_HI3531DV200) += sdhci-hi3531dv200.o
310416 +sdhci-of-hisi-$(CONFIG_ARCH_HI3535AV100) += sdhci-hi3531dv200.o
310417 +sdhci-of-hisi-$(CONFIG_ARCH_HI3521DV200) += sdhci-hi3521dv200.o
310418 +sdhci-of-hisi-$(CONFIG_ARCH_HI3520DV500) += sdhci-hi3521dv200.o
310419 +sdhci-of-hisi-$(CONFIG_ARCH_HI3559AV100) += sdhci-hi3559av100.o
310420 +sdhci-of-hisi-$(CONFIG_ARCH_HI3556AV100) += sdhci-hi3556av100.o
310421 +sdhci-of-hisi-$(CONFIG_ARCH_HI3519AV100) += sdhci-hi3556av100.o
310422 +sdhci-of-hisi-$(CONFIG_ARCH_HI3516EV200) += sdhci-hi3516ev200.o
310423 +sdhci-of-hisi-$(CONFIG_ARCH_HI3516EV300) += sdhci-hi3516ev300.o
310424 +sdhci-of-hisi-$(CONFIG_ARCH_HI3518EV300) += sdhci-hi3518ev300.o
310425 +sdhci-of-hisi-$(CONFIG_ARCH_HI3516DV200) += sdhci-hi3516dv200.o
310426 +sdhci-of-hisi-$(CONFIG_ARCH_HI3568V100) += sdhci-hi3556av100.o
310427 +sdhci-of-hisi-$(CONFIG_ARCH_HI3569V100) += sdhci-hi3559av100.o
310428 obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
310429 obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
310430 obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
310431 @@ -99,3 +114,5 @@ endif
310433 obj-$(CONFIG_MMC_SDHCI_XENON) += sdhci-xenon-driver.o
310434 sdhci-xenon-driver-y += sdhci-xenon.o sdhci-xenon-phy.o
310436 +obj-$(CONFIG_HIMCI) += himci/
310437 diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
310439 --- a/drivers/mmc/host/cqhci.c
310441 @@ -54,6 +54,11 @@ static inline u8 *get_link_desc(struct cqhci_host *cq_host, u8 tag)
310445 + if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT)
310446 + return cq_host->trans_desc_dma_base +
310447 + (cq_host->mmc->max_segs * tag * 2 *
310448 + cq_host->trans_desc_len);
310450 return cq_host->trans_desc_dma_base +
310451 (cq_host->mmc->max_segs * tag *
310452 cq_host->trans_desc_len);
310453 @@ -61,6 +66,11 @@ static inline dma_addr_t get_trans_desc_dma(struct cqhci_host *cq_host, u8 tag)
310457 + if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT)
310458 + return cq_host->trans_desc_base +
310459 + (cq_host->trans_desc_len *
310460 + cq_host->mmc->max_segs * 2 * tag);
310462 return cq_host->trans_desc_base +
310463 (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag);
310465 @@ -201,8 +211,12 @@ static int cqhci_host_alloc_tdl(struct cqhci_host *cq_host)
310467 cq_host->desc_size = cq_host->slot_sz * cq_host->num_slots;
310469 - cq_host->data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs *
310470 - cq_host->mmc->cqe_qdepth;
310471 + if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT)
310472 + cq_host->data_size = cq_host->trans_desc_len *
310473 + cq_host->mmc->max_segs * 2 * cq_host->mmc->cqe_qdepth;
310475 + cq_host->data_size = cq_host->trans_desc_len *
310476 + cq_host->mmc->max_segs * cq_host->mmc->cqe_qdepth;
310478 pr_debug("%s: cqhci: desc_size: %zu data_sz: %zu slot-sz: %d\n",
310479 mmc_hostname(cq_host->mmc), cq_host->desc_size, cq_host->data_size,
310480 @@ -275,14 +289,14 @@ static void __cqhci_enable(struct cqhci_host *cq_host)
310482 cqhci_writel(cq_host, cq_host->rca, CQHCI_SSC2);
310492 - mmc->cqe_on = true;
310493 -
310494 if (cq_host->ops->enable)
310495 cq_host->ops->enable(mmc);
310497 @@ -302,21 +316,19 @@ static void __cqhci_disable(struct cqhci_host *cq_host)
310501 - cq_host->mmc->cqe_on = false;
310502 -
310503 cq_host->activated = false;
310506 -int cqhci_suspend(struct mmc_host *mmc)
310509 struct cqhci_host *cq_host = mmc->cqe_private;
310511 - if (cq_host->enabled)
310512 + if (cq_host->enabled && cq_host->activated)
310517 -EXPORT_SYMBOL(cqhci_suspend);
310522 @@ -379,6 +391,8 @@ static void cqhci_off(struct mmc_host *mmc)
310525 mmc->cqe_on = false;
310531 @@ -448,7 +462,7 @@ static int cqhci_dma_map(struct mmc_host *host, struct mmc_request *mrq)
310535 -static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end,
310540 @@ -470,6 +484,27 @@ static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end,
310549 + if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT &&
310554 + desc_len = (SYNOPSYS_DMA_LIMIT - addr % SYNOPSYS_DMA_LIMIT);
310557 + *desc = *desc + cq_host->trans_desc_len;
310558 + len -= desc_len;
310568 @@ -496,7 +531,7 @@ static int cqhci_prep_tran_desc(struct mmc_request *mrq,
310572 - cqhci_set_tran_desc(desc, addr, len, end, dma64);
310573 + cqhci_set_tran_desc(cq_host, &desc, addr, len, end, dma64, data->blksz);
310574 desc += cq_host->trans_desc_len;
310577 @@ -942,6 +977,9 @@ static void cqhci_recovery_start(struct mmc_host *mmc)
310578 cq_host->ops->disable(mmc, true);
310580 mmc->cqe_on = false;
310587 diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
310589 --- a/drivers/mmc/host/cqhci.h
310591 @@ -88,6 +88,12 @@
310597 + * BLOCK_CNT-n
310604 @@ -145,6 +151,7 @@
310612 @@ -170,6 +177,7 @@ struct cqhci_host {
310620 @@ -234,7 +242,11 @@ irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
310624 -int cqhci_suspend(struct mmc_host *mmc);
310633 diff --git a/drivers/mmc/host/himci/Kconfig b/drivers/mmc/host/himci/Kconfig
310636 --- /dev/null
310638 @@ -0,0 +1,23 @@
310662 diff --git a/drivers/mmc/host/himci/Makefile b/drivers/mmc/host/himci/Makefile
310665 --- /dev/null
310667 @@ -0,0 +1,2 @@
310668 +obj-$(CONFIG_HIMCI) += hisi_mci.o
310669 +hisi_mci-y := himci.o himci_proc.o
310670 diff --git a/drivers/mmc/host/himci/himci.c b/drivers/mmc/host/himci/himci.c
310673 --- /dev/null
310675 @@ -0,0 +1,2582 @@
310677 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
310700 +#include <linux/dma-mapping.h>
310715 +#include <linux/dma-mapping.h>
310727 +#include <linux/clk-provider.h>
310818 + reg_value = himci_readl(host->base + MCI_BMOD);
310820 + himci_writel(reg_value, host->base + MCI_BMOD);
310823 + reg_value = himci_readl(host->base + MCI_BMOD);
310825 + himci_writel(reg_value, host->base + MCI_BMOD);
310827 + reg_value = himci_readl(host->base + MCI_CTRL);
310829 + himci_writel(reg_value, host->base + MCI_CTRL);
310841 + port = host->port;
310843 + if (host->power_status != flag || force == FORCE_ENABLE) {
310847 + reg_value = himci_readl(host->base + MCI_RESET_N);
310849 + himci_writel(reg_value, host->base + MCI_RESET_N);
310852 + reg_value = himci_readl(host->base + MCI_PWREN);
310858 + himci_writel(reg_value, host->base + MCI_PWREN);
310861 + reg_value = himci_readl(host->base + MCI_RESET_N);
310863 + himci_writel(reg_value, host->base + MCI_RESET_N);
310871 + host->power_status = flag;
310883 + card_status = readl(host->base + MCI_CDETECT);
310884 + card_status &= (HIMCI_CARD0 << host->port);
310899 + unsigned int card_value = himci_readl(host->base + MCI_WRTPRT);
310900 + return card_value & (HIMCI_CARD0 << host->port);
310921 + reg_data = himci_readl(host->base + MCI_CMD);
310926 + spin_lock_irqsave(&host->lock, flags);
310927 + reg_data = himci_readl(host->base + MCI_RINTSTS);
310930 + himci_writel(reg_data, host->base + MCI_RINTSTS);
310931 + spin_unlock_irqrestore(&host->lock, flags);
310938 + spin_unlock_irqrestore(&host->lock, flags);
310944 + if (host->is_tuning)
310947 + return -1;
310960 + reg = himci_readl(host->base + MCI_CLKENA);
310962 + reg |= (CCLK_ENABLE << host->port);
310963 + reg |= (CCLK_LOW_POWER << host->port);
310965 + reg &= ~(CCLK_ENABLE << host->port);
310966 + reg &= ~(CCLK_LOW_POWER << host->port);
310971 + if (host->devid == 2)
310972 + reg &= ~(CCLK_LOW_POWER << host->port);
310974 + himci_writel(reg, host->base + MCI_CLKENA);
310976 + cmd_reg.cmd_arg = himci_readl(host->base + MCI_CMD);
310978 + cmd_reg.bits.card_number = host->port;
310991 + himci_writel(cmd_reg.cmd_arg, host->base + MCI_CMD);
310994 + return -ETIMEDOUT;
311011 + clk_set_rate(host->clk, hclk);
311013 + hclk = clk_get_rate(host->clk);
311014 + host->mmc->actual_clock = hclk;
311026 + host->hclk = hclk;
311027 + host->cclk = reg_value ? (hclk / (reg_value * 2)) : hclk;
311028 + himci_writel((reg_value << (host->port * 8)),
311029 + host->base + MCI_CLKDIV);
311031 + clk_cmd.cmd_arg = himci_readl(host->base + MCI_CMD);
311033 + clk_cmd.bits.card_number = host->port;
311038 + himci_writel(clk_cmd.cmd_arg, host->base + MCI_CMD);
311045 + reset_control_assert(host->crg_rst);
311047 + reset_control_deassert(host->crg_rst);
311064 + tmp_reg = himci_readl(host->base + MCI_GPIO);
311066 + himci_writel(tmp_reg, host->base + MCI_GPIO);
311071 + himci_writel(0x4, host->base + MCI_CLKSRC);
311077 + himci_writel(tmp_reg, host->base + MCI_UHS_REG_EXT);
311080 + himci_writel(RW_THRESHOLD_SIZE, host->base + MCI_CARDTHRCTL);
311083 + himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
311085 + spin_lock_irqsave(&host->lock, flags);
311086 + host->pending_events = 0;
311087 + spin_unlock_irqrestore(&host->lock, flags);
311090 + tmp_reg = himci_readl(host->base + MCI_INTMASK);
311093 + himci_writel(tmp_reg, host->base + MCI_INTMASK);
311096 + tmp_reg = himci_readl(host->base + MCI_CTRL);
311099 + himci_writel(tmp_reg, host->base + MCI_CTRL);
311102 + himci_writel(DATA_TIMEOUT | RESPONSE_TIMEOUT, host->base + MCI_TIMEOUT);
311107 + himci_writel(tmp_reg, host->base + MCI_FIFOTH);
311109 + host->error_count = 0;
311110 + host->data_error_count = 0;
311139 + if (curr_status != host->card_status) {
311140 + himci_trace(2, "begin card_status = %d\n", host->card_status);
311141 + host->card_status = curr_status;
311150 + mmc_detect_change(host->mmc, 0);
311161 + himci_writel(host->dma_paddr, host->base + MCI_DBADDR);
311162 + tmp = himci_readl(host->base + MCI_BMOD);
311164 + himci_writel(tmp, host->base + MCI_BMOD);
311172 + tmp_reg = himci_readl(host->base + MCI_BMOD);
311174 + himci_writel(tmp_reg, host->base + MCI_BMOD);
311181 + regval = himci_readl(host->base + MCI_BMOD);
311183 + himci_writel(regval, host->base + MCI_BMOD);
311185 + regval = himci_readl(host->base + MCI_CTRL);
311187 + himci_writel(regval, host->base + MCI_CTRL);
311190 + himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
311206 + host->data = data;
311208 + if (data->flags & MMC_DATA_READ)
311209 + host->dma_dir = DMA_FROM_DEVICE;
311211 + host->dma_dir = DMA_TO_DEVICE;
311213 + host->dma_sg = data->sg;
311214 + host->dma_sg_num = dma_map_sg(mmc_dev(host->mmc),
311215 + data->sg, data->sg_len, host->dma_dir);
311216 + himci_assert(host->dma_sg_num);
311217 + himci_trace(2, "host->dma_sg_num is %d\n", host->dma_sg_num);
311218 + data_size = data->blksz * data->blocks;
311222 + ret = -1;
311226 + himci_trace(2, "host->dma_paddr is 0x%08lx,host->dma_vaddr is 0x%08lx\n",
311227 + (uintptr_t)host->dma_paddr,
311228 + (uintptr_t)host->dma_vaddr);
311231 + des = (struct himci_des *)host->dma_vaddr;
311234 + for (i = 0; i < host->dma_sg_num; i++) {
311235 + sg_length = sg_dma_len(&data->sg[i]);
311236 + sg_phyaddr = sg_dma_address(&data->sg[i]);
311246 + des[des_cnt].idmac_des_next_addr = host->dma_paddr
311252 + sg_length -= 0x1000;
311276 + des[des_cnt - 1].idmac_des_ctrl |= DMA_DES_LAST_DES;
311277 + des[des_cnt - 1].idmac_des_next_addr = 0;
311291 + host->cmd = cmd;
311293 + himci_writel(cmd->arg, host->base + MCI_CMDARG);
311294 + himci_trace(4, "arg_reg 0x%x, val 0x%x", MCI_CMDARG, cmd->arg);
311295 + cmd_regs.cmd_arg = himci_readl(host->base + MCI_CMD);
311298 + if (data->flags & (MMC_DATA_WRITE | MMC_DATA_READ))
311301 + if (data->flags & MMC_DATA_WRITE)
311303 + else if (data->flags & MMC_DATA_READ)
311313 + if ((host->mrq->stop) && (!(host->is_tuning)))
311317 + if (cmd == host->mrq->stop ||
311318 + cmd->opcode == MMC_STOP_TRANSMISSION) {
311321 + } else if (cmd->opcode == MMC_SEND_STATUS) {
311353 + host->cmd->error = -EINVAL;
311356 + return -EINVAL;
311359 + himci_trace(3, "cmd->opcode = %d cmd->arg = 0x%X\n",
311360 + cmd->opcode, cmd->arg);
311361 + if (cmd->opcode == MMC_SELECT_CARD) {
311362 + host->card_rca = (cmd->arg >> 16);
311364 + if (cmd->opcode == MMC_GO_IDLE_STATE)
311369 + if (cmd->opcode == SD_SWITCH_VOLTAGE)
311374 + cmd_regs.bits.card_number = host->port;
311375 + cmd_regs.bits.cmd_index = cmd->opcode;
311379 + himci_writel(DATA_INT_MASK, host->base + MCI_RINTSTS);
311380 + himci_writel(cmd_regs.cmd_arg, host->base + MCI_CMD);
311385 + return -EINVAL;
311397 + host->mrq = NULL;
311398 + host->cmd = NULL;
311399 + host->data = NULL;
311400 + mmc_request_done(host->mmc, mrq);
311414 + struct mmc_command *cmd = host->cmd;
311422 + cmd->resp[i] = himci_readl(host->base +
311423 + MCI_RESP3 - i * 0x4);
311428 + cmd->resp[i] = himci_readl(host->base +
311433 + cmd->error = -ETIMEDOUT;
311437 + cmd->error = -EILSEQ;
311442 + if (((cmd->flags & MMC_RSP_R1) == MMC_RSP_R1) &&
311443 + ((cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)) {
311444 + if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning) {
311445 + host->error_count++;
311446 + host->mrq->cmd->error = -EACCES;
311447 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
311448 + cmd->resp[0]);
311454 + if ((cmd->resp[0] & R1_READY_FOR_DATA) && (R1_CURRENT_STATE(cmd->resp[0]) ==
311456 + host->error_count++;
311457 + host->mrq->cmd->error = -EACCES;
311458 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
311459 + cmd->resp[0]);
311463 + host->cmd = NULL;
311468 + struct mmc_data *data = host->data;
311474 + dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma_dir);
311477 + data->error = -ETIMEDOUT;
311482 + data->error = -EILSEQ;
311487 + if (!data->error)
311488 + data->bytes_xfered = data->blocks * data->blksz;
311490 + data->bytes_xfered = 0;
311492 + host->data = NULL;
311500 + struct mmc_command *cmd = host->cmd;
311510 + spin_lock_irqsave(&host->lock, flags);
311511 + cmd_irq_reg = readl(host->base + MCI_RINTSTS);
311516 + host->base + MCI_RINTSTS);
311517 + spin_unlock_irqrestore(&host->lock, flags);
311522 + host->base + MCI_RINTSTS);
311523 + spin_unlock_irqrestore(&host->lock, flags);
311527 + spin_unlock_irqrestore(&host->lock, flags);
311533 + if (host->card_status == CARD_UNPLUGED) {
311534 + cmd->error = -ETIMEDOUT;
311535 + return -1;
311541 + cmd->resp[i] = himci_readl(host->base +
311545 + pr_err("%d : 0x%x\n", i, cmd->resp[i]);
311547 + cmd->error = -ETIMEDOUT;
311549 + return -1;
311573 + spin_lock_irqsave(&host->lock, flags);
311574 + cmd_irq_reg = readl(host->base + MCI_RINTSTS);
311579 + host->base + MCI_RINTSTS);
311580 + spin_unlock_irqrestore(&host->lock, flags);
311583 + spin_unlock_irqrestore(&host->lock, flags);
311588 + if (host->card_status == CARD_UNPLUGED)
311589 + return -1;
311592 + return -1;
311603 + struct mmc_data *data = host->data;
311611 + time = wait_event_timeout(host->intr_wait,
311613 + &host->pending_events), time);
311616 + spin_lock_irqsave(&host->lock, flags);
311617 + tmp_reg = himci_readl(host->base + MCI_INTMASK);
311619 + himci_writel(tmp_reg, host->base + MCI_INTMASK);
311620 + host->pending_events &= ~HIMCI_PEND_DTO_M;
311621 + spin_unlock_irqrestore(&host->lock, flags);
311624 + && (!test_bit(HIMCI_PEND_DTO_B, &host->pending_events)))
311625 + || (host->card_status == CARD_UNPLUGED)) {
311626 + data->error = -ETIMEDOUT;
311628 + host->irq_status);
311630 + himci_data_done(host, host->irq_status);
311631 + return -1;
311635 + himci_data_done(host, host->irq_status);
311652 + card_status_reg = readl(host->base + MCI_STATUS);
311662 + if (host->card_status == CARD_UNPLUGED) {
311663 + host->mrq->cmd->error = -ETIMEDOUT;
311665 + return -1;
311669 + host->mrq->cmd->error = -ETIMEDOUT;
311671 + return -1;
311692 + host->mrq = mrq;
311693 + host->irq_status = 0;
311695 + if (host->card_status == CARD_UNPLUGED) {
311696 + mrq->cmd->error = -ENODEV;
311700 + ret = himci_wait_card_complete(host, mrq->data);
311702 + mrq->cmd->error = ret;
311707 + if (mrq->data) {
311708 + ret = himci_setup_data(host, mrq->data);
311710 + mrq->data->error = ret;
311715 + byte_cnt = mrq->data->blksz * mrq->data->blocks;
311716 + himci_writel(byte_cnt, host->base + MCI_BYTCNT);
311717 + himci_writel(mrq->data->blksz, host->base + MCI_BLKSIZ);
311720 + tmp_reg = himci_readl(host->base + MCI_CTRL);
311722 + himci_writel(tmp_reg, host->base + MCI_CTRL);
311725 + tmp_reg = himci_readl(host->base + MCI_CTRL);
311736 + himci_writel(0, host->base + MCI_BYTCNT);
311737 + himci_writel(0, host->base + MCI_BLKSIZ);
311739 + if (mrq->sbc) {
311740 + ret = himci_exec_cmd(host, mrq->sbc, NULL);
311742 + mrq->sbc->error = ret;
311749 + mrq->sbc->error = ret;
311754 + ret = himci_exec_cmd(host, mrq->cmd, mrq->data);
311756 + mrq->cmd->error = ret;
311766 + if (mrq->data) {
311767 + if (!(mrq->cmd->error)) {
311769 + spin_lock_irqsave(&host->lock, flags);
311770 + tmp_reg = himci_readl(host->base + MCI_INTMASK);
311772 + himci_writel(tmp_reg, host->base + MCI_INTMASK);
311773 + spin_unlock_irqrestore(&host->lock, flags);
311777 + } else if (host->is_tuning) {
311782 + stat = himci_readl(host->base + MCI_RINTSTS);
311786 + himci_writel(stat, host->base + MCI_RINTSTS);
311802 + if (mrq->stop && (!mrq->sbc
311803 + || (mrq->sbc && (mrq->cmd->error || mrq->data->error)))) {
311807 + trans_cnt = himci_readl(host->base + MCI_TCBCNT);
311809 + if ((trans_cnt == byte_cnt) && (!(host->is_tuning))) {
311814 + mrq->stop->error = -ETIMEDOUT;
311821 + ret = himci_exec_cmd(host, host->mrq->stop,
311822 + host->data);
311824 + mrq->stop->error = ret;
311838 + spin_lock_irqsave(&host->lock, flags);
311839 + himci_writel(ALL_SD_INT_CLR, host->base + MCI_RINTSTS);
311840 + spin_unlock_irqrestore(&host->lock, flags);
311842 + if (mrq->data && mrq->data->error && !host->is_tuning)
311843 + host->data_error_count++;
311856 + ctrl = himci_readl(host->base + MCI_UHS_REG);
311857 + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
311860 + ctrl &= ~(HI_SDXC_CTRL_VDD_180 << host->port);
311861 + himci_writel(ctrl, host->base + MCI_UHS_REG);
311867 + ctrl = himci_readl(host->base + MCI_UHS_REG);
311868 + if (!(ctrl & (HI_SDXC_CTRL_VDD_180 << host->port))) {
311875 + return -EIO;
311877 + } else if (!(ctrl & (HI_SDXC_CTRL_VDD_180 << host->port)) &&
311878 + (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
311886 + ctrl |= (HI_SDXC_CTRL_VDD_180 << host->port);
311887 + himci_writel(ctrl, host->base + MCI_UHS_REG);
311892 + ctrl = himci_readl(host->base + MCI_UHS_REG);
311893 + if (ctrl & (HI_SDXC_CTRL_VDD_180 << host->port)) {
311898 + if (host->mmc->caps2 & MMC_CAP2_HS200) {
311906 + ctrl = himci_readl(host->base + MCI_RINTSTS);
311910 + host->base + MCI_RINTSTS);
311923 + ctrl &= ~(HI_SDXC_CTRL_VDD_180 << host->port);
311924 + himci_writel(ctrl, host->base + MCI_UHS_REG);
311942 + return -EAGAIN;
311974 + spin_lock_irqsave(&host->lock, flags);
311976 + reg_value = himci_readl(host->base + MCI_UHS_REG_EXT);
311979 + himci_writel(reg_value, host->base + MCI_UHS_REG_EXT);
311981 + spin_unlock_irqrestore(&host->lock, flags);
311992 + if (host->devid == 0)
311994 + else if (host->devid == 1)
311996 + else if (host->devid == 2)
311999 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
312005 + val = himci_readl(host->base + MCI_TUNING_CTRL);
312007 + himci_writel(val, host->base + MCI_TUNING_CTRL);
312015 + if (host->devid == 0)
312017 + else if (host->devid == 1)
312019 + else if (host->devid == 2)
312022 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
312029 + val = himci_readl(host->base + MCI_TUNING_CTRL);
312031 + himci_writel(val, host->base + MCI_TUNING_CTRL);
312045 + cmd.arg = (host->card_rca << 16);
312068 + himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
312072 + cmd_count--;
312075 + return -EINVAL;
312091 + if (host->devid == 0)
312093 + else if (host->devid == 1)
312095 + else if (host->devid == 2)
312098 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
312111 + if (host->devid == 0)
312113 + else if (host->devid == 1)
312115 + else if (host->devid == 2)
312118 + himci_trace(5, "Devid error, host->devid: %x", host->devid);
312130 + |<---- totalphases(ele) ---->|
312137 + |<---- totalphases(ele) ---->|
312154 + u32 startp = -1;
312155 + u32 endp = -1;
312187 + err = himci_send_tuning(host->mmc, opcode);
312215 + err = himci_send_tuning(host->mmc, opcode);
312242 + err = himci_send_tuning(host->mmc, opcode);
312272 + return -1;
312284 + (phase_num - 1), ele,
312286 + himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
312290 + return -1;
312301 + himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
312304 + host->pending_events = 0;
312337 + regval = himci_readl(host->base + MCI_TUNING_CTRL);
312364 + return -1;
312372 + printk("mix set temp-phase %d\n", index);
312403 + val = himci_readl(host->base + MCI_TUNING_CTRL);
312450 + himci_writel(ALL_INT_CLR, host->base + MCI_RINTSTS);
312488 + host->is_tuning = 1;
312493 + host->is_tuning = 0;
312515 + himci_writel(0x1, host->base + MCI_CARDTHRCTL);
312518 + host->is_tuning = 1;
312542 + fall_point = index - 1;
312556 + host->is_tuning = 0;
312560 + himci_writel(DEFAULT_PHASE, host->base + MCI_UHS_REG_EXT);
312571 + phase = phase - (HIMCI_PHASE_SCALE / 2);
312582 + himci_writel(RW_THRESHOLD_SIZE, host->base + MCI_CARDTHRCTL);
312593 + himci_trace(3, "ios->bus_width = %d ", ios->bus_width);
312594 + tmp_reg = himci_readl(host->base + MCI_CTYPE);
312595 + tmp_reg &= ~((CARD_WIDTH_0 | CARD_WIDTH_1) << host->port);
312597 + if (ios->bus_width == MMC_BUS_WIDTH_8) {
312598 + tmp_reg |= (CARD_WIDTH_0 << host->port);
312599 + himci_writel(tmp_reg, host->base + MCI_CTYPE);
312600 + } else if (ios->bus_width == MMC_BUS_WIDTH_4) {
312601 + tmp_reg |= (CARD_WIDTH_1 << host->port);
312602 + himci_writel(tmp_reg, host->base + MCI_CTYPE);
312604 + himci_writel(tmp_reg, host->base + MCI_CTYPE);
312619 + himci_trace(3, "ios->power_mode = %d ", ios->power_mode);
312620 + if (!ios->clock) {
312626 + switch (ios->power_mode) {
312637 + himci_trace(3, "ios->clock = %d ", ios->clock);
312638 + if (ios->clock) {
312642 + himci_set_cclk(host, ios->clock);
312650 + if (ios->timing == MMC_TIMING_UHS_DDR50) {
312651 + ctrl = himci_readl(host->base + MCI_UHS_REG);
312652 + if (!((HI_SDXC_CTRL_DDR_REG << host->port) & ctrl)) {
312653 + ctrl |= (HI_SDXC_CTRL_DDR_REG << host->port);
312654 + himci_writel(ctrl, host->base + MCI_UHS_REG);
312661 + if (ios->timing != MMC_TIMING_UHS_DDR50) {
312662 + ctrl = himci_readl(host->base + MCI_UHS_REG);
312663 + if ((HI_SDXC_CTRL_DDR_REG << host->port) & ctrl) {
312664 + ctrl &= ~(HI_SDXC_CTRL_DDR_REG << host->port);
312665 + himci_writel(ctrl, host->base + MCI_UHS_REG);
312681 + spin_lock_irqsave(&host->lock, flags);
312682 + reg_value = himci_readl(host->base + MCI_INTMASK);
312687 + himci_writel(reg_value, host->base + MCI_INTMASK);
312688 + spin_unlock_irqrestore(&host->lock, flags);
312722 + unsigned int port = host->port;
312724 + reg_value = himci_readl(host->base + MCI_RESET_N);
312726 + himci_writel(reg_value, host->base + MCI_RESET_N);
312730 + reg_value = himci_readl(host->base + MCI_RESET_N);
312732 + himci_writel(reg_value, host->base + MCI_RESET_N);
312745 + regval = himci_readl(host->base + MCI_STATUS);
312753 + struct mmc_card *card = mmc->card;
312755 + struct card_info *c_info = &host->c_info;
312759 + c_info->card_connect = CARD_DISCONNECT;
312763 + c_info->card_type = card->type;
312764 + c_info->card_state = card->state;
312766 + c_info->timing = mmc->ios.timing;
312767 + c_info->card_support_clock = mmc->ios.clock;
312769 + c_info->sd_bus_speed = card->sd_bus_speed;
312771 + memcpy(c_info->ssr, card->raw_ssr, ARRAY_SIZE(c_info->ssr));
312773 + c_info->card_connect = CARD_CONNECT;
312798 + spin_lock(&host->lock);
312799 + state = himci_readl(host->base + MCI_RINTSTS);
312800 + spin_unlock(&host->lock);
312804 + if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
312805 + if ((host->mmc->card != NULL)
312806 + && (host->mmc->card->type == MMC_TYPE_SDIO)) {
312807 + mstate = himci_readl(host->base + MCI_INTMASK);
312810 + spin_lock(&host->lock);
312812 + host->base + MCI_RINTSTS);
312813 + spin_unlock(&host->lock);
312815 + mmc_signal_sdio_irq(host->mmc);
312822 + host->pending_events |= HIMCI_PEND_DTO_M;
312824 + spin_lock(&host->lock);
312825 + host->irq_status = himci_readl(host->base + MCI_RINTSTS);
312826 + himci_writel(DATA_INT_MASK, host->base + MCI_RINTSTS);
312827 + spin_unlock(&host->lock);
312829 + wake_up(&host->intr_wait);
312847 + mmc->caps |= MMC_CAP_ERASE;
312849 + if (of_property_read_u32(np, "min-frequency", &mmc->f_min))
312850 + mmc->f_min = MMC_CCLK_MIN;
312852 + if (of_property_read_u32(np, "devid", &host->devid))
312853 + return -EINVAL;
312855 + if (of_find_property(np, "cap-mmc-hw-reset", &len))
312856 + mmc->caps |= MMC_CAP_HW_RESET;
312858 + if (host->devid == 0 || host->devid == 1)
312859 + mmc->caps |= MMC_CAP_CMD23;
312889 + struct device_node *np = pdev->dev.of_node;
312903 + mmc = mmc_alloc_host(sizeof(struct himci_host), &pdev->dev);
312906 + ret = -ENOMEM;
312912 + mmc->ops = &himci_ops;
312921 + ret = -ENOMEM;
312928 + ret = -ENOMEM;
312941 + ret = -ENODEV;
312947 + ret = -EINVAL;
312953 + mmc->max_blk_count = 2048;
312955 + mmc->max_blk_count = 4096;
312957 + mmc->max_segs = 1024;
312958 + mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
312959 + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
312960 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
312963 + pdev->id = host->devid;
312964 + if (host->devid >= HIMCI_SLOT_NUM) {
312966 + ret = -EINVAL;
312969 + mci_host[host->devid] = host;
312970 + host->pdev = pdev;
312971 + host->mmc = mmc;
312973 + if (host->mmc->caps & MMC_CAP_HW_RESET)
312974 + host->port = 1;
312976 + host->port = 0;
312978 + host->port = 0;
312980 + host->dma_vaddr = dma_alloc_coherent(&pdev->dev, CMD_DES_PAGE_SIZE,
312981 + &host->dma_paddr, GFP_KERNEL);
312982 + if (!host->dma_vaddr) {
312984 + ret = -ENOMEM;
312988 + host->base = devm_ioremap_resource(&pdev->dev, host_ioaddr_res);
312989 + if (IS_ERR_OR_NULL(host->base)) {
312991 + ret = -ENOMEM;
312995 + spin_lock_init(&host->lock);
312997 + host->crg_rst = devm_reset_control_get(&pdev->dev, "mmc_reset");
312998 + if (IS_ERR_OR_NULL(host->crg_rst)) {
313000 + ret = PTR_ERR(host->crg_rst);
313004 + reset_control_assert(host->crg_rst);
313006 + reset_control_deassert(host->crg_rst);
313008 + host->clk = devm_clk_get(&pdev->dev, "mmc_clk");
313009 + if (IS_ERR_OR_NULL(host->clk)) {
313011 + ret = PTR_ERR(host->clk);
313015 + clk_prepare_enable(host->clk);
313017 + host->power_status = POWER_OFF;
313021 + host->card_status = himci_sys_card_detect(host);
313023 + timer_setup(&host->timer, himci_detect_card, 0);
313024 + host->timer.expires = jiffies + detect_time;
313025 + add_timer(&host->timer);
313027 + init_waitqueue_head(&host->intr_wait);
313034 + host->irq = irq;
313045 + del_timer(&host->timer);
313047 + if (host->base)
313048 + devm_iounmap(&pdev->dev, host->base);
313050 + if (host->dma_vaddr)
313051 + dma_free_coherent(&pdev->dev, CMD_DES_PAGE_SIZE,
313052 + host->dma_vaddr, host->dma_paddr);
313078 + free_irq(host->irq, host);
313079 + del_timer_sync(&host->timer);
313082 + devm_iounmap(&pdev->dev, host->base);
313083 + dma_free_coherent(&pdev->dev, CMD_DES_PAGE_SIZE, host->dma_vaddr,
313084 + host->dma_paddr);
313100 + himci_writel(0, host->base + MCI_IDINTEN);
313101 + himci_writel(0, host->base + MCI_INTMASK);
313103 + val = himci_readl(host->base + MCI_CTRL);
313105 + himci_writel(val, host->base + MCI_CTRL);
313119 + del_timer_sync(&host->timer);
313121 + if (__clk_is_enabled(host->clk))
313122 + clk_disable_unprepare(host->clk);
313137 + if (!__clk_is_enabled(host->clk))
313138 + clk_prepare_enable(host->clk);
313143 + add_timer(&host->timer);
313159 + if (!host || !host->mmc) {
313164 + mmc = host->mmc;
313165 + del_timer_sync(&host->timer);
313171 + add_timer(&host->timer);
313187 + return host->mmc;
313193 + {.compatible = "hisilicon,hi3516a-himci"},
313194 + {.compatible = "hisilicon,hi3518ev20x-himci"},
313195 + {.compatible = "hisilicon,hi3516cv500-himci"},
313196 + {.compatible = "hisilicon,hi3516dv300-himci"},
313197 + {.compatible = "hisilicon,hi3556v200-himci"},
313198 + {.compatible = "hisilicon,hi3559v200-himci"},
313258 diff --git a/drivers/mmc/host/himci/himci.h b/drivers/mmc/host/himci/himci.h
313261 --- /dev/null
313263 @@ -0,0 +1,156 @@
313272 + 0 - all message
313273 + 1 - dump all register read/write
313274 + 2 - flow trace
313275 + 3 - timeout err and protocol err
313280 +#define NOT_FOUND -1
313420 diff --git a/drivers/mmc/host/himci/himci_hi3516a.c b/drivers/mmc/host/himci/himci_hi3516a.c
313423 --- /dev/null
313425 @@ -0,0 +1,94 @@
313510 + offset = host->devid * 6;
313520 diff --git a/drivers/mmc/host/himci/himci_hi3516cv500.c b/drivers/mmc/host/himci/himci_hi3516cv500.c
313523 --- /dev/null
313525 @@ -0,0 +1,162 @@
313582 + struct mmc_host *mmc = host->mmc;
313583 + struct mmc_ios *ios = &(mmc->ios);
313584 + unsigned int devid = host->devid;
313585 + unsigned char timing = ios->timing;
313596 + if (ios->clock == 400000) /* 400K */
313656 + struct mmc_host *mmc = host->mmc;
313657 + struct mmc_ios *ios = &(mmc->ios);
313658 + unsigned int devid = host->devid;
313659 + unsigned char timing = ios->timing;
313682 + reg_value = himci_readl((uintptr_t)(host->base) + MCI_UHS_REG_EXT);
313686 + himci_writel(reg_value, (uintptr_t)(host->base) + MCI_UHS_REG_EXT);
313688 diff --git a/drivers/mmc/host/himci/himci_hi3516dv300.c b/drivers/mmc/host/himci/himci_hi3516dv300.c
313691 --- /dev/null
313693 @@ -0,0 +1,160 @@
313750 + struct mmc_host *mmc = host->mmc;
313751 + struct mmc_ios *ios = &(mmc->ios);
313752 + unsigned int devid = host->devid;
313753 + unsigned char timing = ios->timing;
313763 + if (ios->clock == 400000) /* 400K */
313822 + struct mmc_host *mmc = host->mmc;
313823 + struct mmc_ios *ios = &(mmc->ios);
313824 + unsigned int devid = host->devid;
313825 + unsigned char timing = ios->timing;
313848 + reg_value = himci_readl(host->base + MCI_UHS_REG_EXT);
313852 + himci_writel(reg_value, host->base + MCI_UHS_REG_EXT);
313854 diff --git a/drivers/mmc/host/himci/himci_hi3518ev20x.c b/drivers/mmc/host/himci/himci_hi3518ev20x.c
313857 --- /dev/null
313859 @@ -0,0 +1,152 @@
313861 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
313994 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
314001 + offset = host->devid * 6;
314012 diff --git a/drivers/mmc/host/himci/himci_hi3556v200.c b/drivers/mmc/host/himci/himci_hi3556v200.c
314015 --- /dev/null
314017 @@ -0,0 +1,162 @@
314074 + struct mmc_host *mmc = host->mmc;
314075 + struct mmc_ios *ios = &(mmc->ios);
314076 + unsigned int devid = host->devid;
314077 + unsigned char timing = ios->timing;
314087 + if (ios->clock == 400000) /* 400K */
314147 + struct mmc_host *mmc = host->mmc;
314148 + struct mmc_ios *ios = &(mmc->ios);
314149 + unsigned int devid = host->devid;
314150 + unsigned char timing = ios->timing;
314174 + reg_value = himci_readl(host->base + MCI_UHS_REG_EXT);
314178 + himci_writel(reg_value, host->base + MCI_UHS_REG_EXT);
314180 diff --git a/drivers/mmc/host/himci/himci_hi3559v200.c b/drivers/mmc/host/himci/himci_hi3559v200.c
314183 --- /dev/null
314185 @@ -0,0 +1,164 @@
314242 + struct mmc_host *mmc = host->mmc;
314243 + struct mmc_ios *ios = &(mmc->ios);
314244 + unsigned int devid = host->devid;
314245 + unsigned char timing = ios->timing;
314256 + if (ios->clock == 400000) /* 400K */
314316 + struct mmc_host *mmc = host->mmc;
314317 + struct mmc_ios *ios = &(mmc->ios);
314318 + unsigned int devid = host->devid;
314319 + unsigned char timing = ios->timing;
314343 + reg_value = himci_readl(host->base + MCI_UHS_REG_EXT);
314347 + himci_writel(reg_value, host->base + MCI_UHS_REG_EXT);
314350 diff --git a/drivers/mmc/host/himci/himci_proc.c b/drivers/mmc/host/himci/himci_proc.c
314353 --- /dev/null
314355 @@ -0,0 +1,246 @@
314357 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
314393 + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
314394 + const int __off = 3 - ((start) / 32); \
314400 + __res |= resp[__off-1] << ((32 - __shft) % 32); \
314480 + if (!host || !host->mmc) {
314486 + c_info = &host->c_info;
314488 + present = host->mmc->ops->get_cd(host->mmc);
314495 + if (CARD_CONNECT != c_info->card_connect) {
314496 + if (host->mmc->card_status == MMC_CARD_INIT_FAIL)
314504 + mci_get_card_type(c_info->card_type)
314507 + if (c_info->card_state & MMC_STATE_BLOCKADDR) {
314508 + if (c_info->card_state & MMC_CARD_SDXC)
314515 + if (is_card_uhs(c_info->timing) &&
314516 + c_info->sd_bus_speed < ARRAY_SIZE(uhs_speeds))
314517 + uhs_bus_speed_mode = uhs_speeds[c_info->sd_bus_speed];
314520 + is_card_uhs(c_info->timing) ? "UHS " :
314521 + (is_card_hs(c_info->timing) ? "HS " : ""),
314522 + c_info->timing == MMC_TIMING_MMC_HS400 ? "HS400 " :
314523 + (c_info->timing == MMC_TIMING_MMC_HS200 ? "HS200 " : ""),
314524 + c_info->timing == MMC_TIMING_MMC_DDR52 ? "DDR " : "",
314527 + speed_class = UNSTUFF_BITS(c_info->ssr, 440 - 384, 8);
314528 + grade_speed_uhs = UNSTUFF_BITS(c_info->ssr, 396 - 384, 4);
314543 + clock = host->hclk;
314548 + clock = c_info->card_support_clock;
314553 + clock = host->cclk;
314559 + host->error_count);
314561 + host->data_error_count);
314602 diff --git a/drivers/mmc/host/himci/himci_proc.h b/drivers/mmc/host/himci/himci_proc.h
314605 --- /dev/null
314607 @@ -0,0 +1,36 @@
314609 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
314635 +#define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing copy from core/card.h */
314644 diff --git a/drivers/mmc/host/himci/himci_reg.h b/drivers/mmc/host/himci/himci_reg.h
314647 --- /dev/null
314649 @@ -0,0 +1,241 @@
314651 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
314758 +/* bit 31-8: data read timeout param */
314760 +/* bit 7-0: response timeout param */
314768 + bit 16-1: mask MMC host controller each interrupt
314794 +/* bit 15: end-bit error (read)/write no CRC interrupt status */
314809 +/* bit 10: data starvation-by-host timeout interrupt status */
314847 +/* MCI_RINTSTS(0x44) details:bit 16-1: clear
314891 diff --git a/drivers/mmc/host/mci_proc.c b/drivers/mmc/host/mci_proc.c
314894 --- /dev/null
314896 @@ -0,0 +1,301 @@
314898 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2016-2020. All rights reserved.
314951 + const u32 mask = ((size < BIT_WIDTH) ? 1 << size : 0) - 1;
314952 + const int off = 0x3 - ((start) / BIT_WIDTH);
314958 + res |= resp[off - 1] << ((BIT_WIDTH - shft) % BIT_WIDTH);
315032 + info = &host->c_info;
315034 + present = host->mmc->ops->get_cd(host->mmc);
315040 + if (info->card_connect != CARD_CONNECT) {
315041 + if (mmc->card_status == MMC_CARD_INIT_FAIL)
315049 + mci_get_card_type(info->card_type));
315051 + if (info->card_state & MMC_STATE_BLOCKADDR) {
315052 + type = (info->card_state & MMC_CARD_SDXC) ?
315057 + if (is_card_uhs(info->timing) &&
315058 + info->sd_bus_speed < ARRAY_SIZE(uhs_speeds))
315060 + uhs_speeds[info->sd_bus_speed];
315063 + is_card_uhs(info->timing) ? "UHS" :
315064 + is_card_hs(info->timing) ? "HS" :
315065 + (info->enhanced_strobe == true) ? "HS400ES" :
315066 + (info->timing == MMC_TIMING_MMC_HS400) ? "HS400" :
315067 + (info->timing == MMC_TIMING_MMC_HS200) ? "HS200" :
315068 + (info->timing == MMC_TIMING_MMC_DDR52) ? "DDR" :
315071 + speed_class = unstuff_bits(info->ssr, 56, 8); /* 56 = 440 - 384 */
315072 + grade_speed_uhs = unstuff_bits(info->ssr, 12, 4); /* 12 = 396 - 384 */
315087 + clock = info->card_support_clock;
315092 + clock = info->card_support_clock;
315097 + clock = mmc->actual_clock;
315104 + host->error_count);
315198 diff --git a/drivers/mmc/host/mci_proc.h b/drivers/mmc/host/mci_proc.h
315201 --- /dev/null
315203 @@ -0,0 +1,50 @@
315205 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2016-2020. All rights reserved.
315254 diff --git a/drivers/mmc/host/sdhci-hi3516dv200.c b/drivers/mmc/host/sdhci-hi3516dv200.c
315257 --- /dev/null
315258 +++ b/drivers/mmc/host/sdhci-hi3516dv200.c
315259 @@ -0,0 +1,674 @@
315261 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
315279 +#include "sdhci-hisi.h"
315395 + clk_prepare_enable(pltfm_host->clk);
315396 + reset_control_assert(hisi_priv->crg_rst);
315397 + reset_control_assert(hisi_priv->dll_rst);
315400 + reset_control_deassert(hisi_priv->crg_rst);
315407 + unsigned int devid = hisi_priv->devid;
315416 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
315420 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
315431 + if (ios->enhanced_strobe)
315439 + if (ios->enhanced_strobe)
315451 + struct device_node *np = pdev->dev.of_node;
315455 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
315456 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
315457 + dev_err(&pdev->dev, "get crg_rst failed.\n");
315458 + return PTR_ERR(hisi_priv->crg_rst);
315461 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
315462 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
315463 + dev_err(&pdev->dev, "get dll_rst failed.\n");
315464 + return PTR_ERR(hisi_priv->dll_rst);
315467 + hisi_priv->sampl_rst = NULL;
315469 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
315470 + if (IS_ERR(hisi_priv->crg_regmap)) {
315471 + dev_err(&pdev->dev, "get crg regmap failed.\n");
315472 + return PTR_ERR(hisi_priv->crg_regmap);
315475 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
315476 + if (IS_ERR(hisi_priv->iocfg_regmap)) {
315477 + dev_err(&pdev->dev, "get iocfg regmap failed.\n");
315478 + return PTR_ERR(hisi_priv->iocfg_regmap);
315481 + if (of_property_read_u32(np, "devid", &hisi_priv->devid))
315482 + return -EINVAL;
315484 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
315486 + dev_err(mmc_dev(host->mmc), "get clk err\n");
315487 + return -EINVAL;
315490 + pltfm_host->clk = clk;
315501 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
315502 + host->flags &= ~SDHCI_SIGNALING_330;
315503 + host->flags |= SDHCI_SIGNALING_180;
315512 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
315513 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
315514 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
315515 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
315517 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
315521 + host->mmc_host_ops.hs400_enhanced_strobe =
315524 + mci_host[slot_index++] = host->mmc;
315532 + unsigned int devid = hisi_priv->devid;
315543 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
315549 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
315554 + timeout--;
315557 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
315563 + unsigned int devid = hisi_priv->devid;
315572 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
315576 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
315583 + unsigned int devid = hisi_priv->devid;
315594 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
315600 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
315605 + timeout--;
315608 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
315614 + unsigned int devid = hisi_priv->devid;
315625 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
315631 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
315636 + timeout--;
315639 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
315650 + regmap_read(hisi_priv->crg_regmap,
315656 + timeout--;
315659 + pr_err("%s: DS 180 DLL master not ready.\n", mmc_hostname(host->mmc));
315683 + host->error_count = 0;
315717 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
315720 + switch (host->timing) {
315777 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
315780 + switch (host->timing) {
315806 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
315821 + unsigned int devid = hisi_priv->devid;
315822 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
315845 + unsigned int devid = hisi_priv->devid;
315849 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
315850 + hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
315851 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
315852 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
315853 + hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
315854 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
315855 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
315856 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
315857 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
315858 + } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
315859 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
315860 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
315861 + } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
315862 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
315863 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
315865 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
315866 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
315870 + if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
315871 + (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
315872 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
315873 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
315876 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
315877 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
315887 + host->mmc->actual_clock = 0;
315894 + reset_control_assert(hisi_priv->dll_rst);
315897 + clk_set_rate(pltfm_host->clk, clock);
315898 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
315901 + hisi_set_drv_phase(host, hisi_priv->drv_phase);
315903 + hisi_set_sample_phase(host, hisi_priv->sample_phase);
315906 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
315908 + reset_control_deassert(hisi_priv->dll_rst);
315913 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
315917 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
315926 + unsigned int devid = hisi_priv->devid;
315934 diff --git a/drivers/mmc/host/sdhci-hi3516ev200.c b/drivers/mmc/host/sdhci-hi3516ev200.c
315937 --- /dev/null
315938 +++ b/drivers/mmc/host/sdhci-hi3516ev200.c
315939 @@ -0,0 +1,669 @@
315941 + * Copyright (c) Hisilicon Technologies Co., Ltd. 20186-2020. All rights reserved.
315959 +#include "sdhci-hisi.h"
316070 + clk_prepare_enable(pltfm_host->clk);
316071 + reset_control_assert(hisi_priv->crg_rst);
316072 + reset_control_assert(hisi_priv->dll_rst);
316075 + reset_control_deassert(hisi_priv->crg_rst);
316082 + unsigned int devid = hisi_priv->devid;
316091 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316095 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
316106 + if (ios->enhanced_strobe)
316114 + if (ios->enhanced_strobe)
316126 + struct device_node *np = pdev->dev.of_node;
316130 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
316131 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
316132 + dev_err(&pdev->dev, "get crg_rst failed.\n");
316133 + return PTR_ERR(hisi_priv->crg_rst);
316136 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
316137 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
316138 + dev_err(&pdev->dev, "get dll_rst failed.\n");
316139 + return PTR_ERR(hisi_priv->dll_rst);
316142 + hisi_priv->sampl_rst = NULL;
316144 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
316145 + if (IS_ERR(hisi_priv->crg_regmap)) {
316146 + dev_err(&pdev->dev, "get crg regmap failed.\n");
316147 + return PTR_ERR(hisi_priv->crg_regmap);
316150 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
316151 + if (IS_ERR(hisi_priv->iocfg_regmap)) {
316152 + dev_err(&pdev->dev, "get iocfg regmap failed.\n");
316153 + return PTR_ERR(hisi_priv->iocfg_regmap);
316156 + if (of_property_read_u32(np, "devid", &hisi_priv->devid))
316157 + return -EINVAL;
316159 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
316161 + dev_err(mmc_dev(host->mmc), "get clk err\n");
316162 + return -EINVAL;
316165 + pltfm_host->clk = clk;
316176 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
316177 + host->flags &= ~SDHCI_SIGNALING_330;
316178 + host->flags |= SDHCI_SIGNALING_180;
316187 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
316188 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
316189 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
316190 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
316192 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
316196 + host->mmc_host_ops.hs400_enhanced_strobe =
316199 + mci_host[slot_index++] = host->mmc;
316207 + unsigned int devid = hisi_priv->devid;
316218 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316224 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
316229 + timeout--;
316232 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
316238 + unsigned int devid = hisi_priv->devid;
316247 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316251 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
316258 + unsigned int devid = hisi_priv->devid;
316269 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316275 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
316280 + timeout--;
316283 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
316289 + unsigned int devid = hisi_priv->devid;
316300 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316306 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
316311 + timeout--;
316314 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
316325 + regmap_read(hisi_priv->crg_regmap,
316331 + timeout--;
316334 + pr_err("%s: DS 180 DLL master not ready.\n", mmc_hostname(host->mmc));
316358 + host->error_count = 0;
316392 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
316395 + switch (host->timing) {
316452 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
316455 + switch (host->timing) {
316481 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
316496 + unsigned int devid = hisi_priv->devid;
316497 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
316520 + unsigned int devid = hisi_priv->devid;
316524 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
316525 + hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
316526 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
316527 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
316528 + hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
316529 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
316530 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
316531 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
316532 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
316533 + } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
316534 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
316535 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
316536 + } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
316537 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
316538 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
316540 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
316541 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
316545 + if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
316546 + (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
316547 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
316548 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
316551 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
316552 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
316562 + host->mmc->actual_clock = 0;
316569 + reset_control_assert(hisi_priv->dll_rst);
316572 + clk_set_rate(pltfm_host->clk, clock);
316573 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
316576 + hisi_set_drv_phase(host, hisi_priv->drv_phase);
316578 + hisi_set_sample_phase(host, hisi_priv->sample_phase);
316581 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
316583 + reset_control_deassert(hisi_priv->dll_rst);
316588 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
316592 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
316601 + unsigned int devid = hisi_priv->devid;
316609 diff --git a/drivers/mmc/host/sdhci-hi3516ev300.c b/drivers/mmc/host/sdhci-hi3516ev300.c
316612 --- /dev/null
316613 +++ b/drivers/mmc/host/sdhci-hi3516ev300.c
316614 @@ -0,0 +1,674 @@
316616 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
316634 +#include "sdhci-hisi.h"
316750 + clk_prepare_enable(pltfm_host->clk);
316751 + reset_control_assert(hisi_priv->crg_rst);
316752 + reset_control_assert(hisi_priv->dll_rst);
316755 + reset_control_deassert(hisi_priv->crg_rst);
316762 + unsigned int devid = hisi_priv->devid;
316771 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316775 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
316786 + if (ios->enhanced_strobe)
316794 + if (ios->enhanced_strobe)
316806 + struct device_node *np = pdev->dev.of_node;
316810 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
316811 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
316812 + dev_err(&pdev->dev, "get crg_rst failed.\n");
316813 + return PTR_ERR(hisi_priv->crg_rst);
316816 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
316817 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
316818 + dev_err(&pdev->dev, "get dll_rst failed.\n");
316819 + return PTR_ERR(hisi_priv->dll_rst);
316822 + hisi_priv->sampl_rst = NULL;
316824 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
316825 + if (IS_ERR(hisi_priv->crg_regmap)) {
316826 + dev_err(&pdev->dev, "get crg regmap failed.\n");
316827 + return PTR_ERR(hisi_priv->crg_regmap);
316830 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
316831 + if (IS_ERR(hisi_priv->iocfg_regmap)) {
316832 + dev_err(&pdev->dev, "get iocfg regmap failed.\n");
316833 + return PTR_ERR(hisi_priv->iocfg_regmap);
316836 + if (of_property_read_u32(np, "devid", &hisi_priv->devid))
316837 + return -EINVAL;
316839 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
316841 + dev_err(mmc_dev(host->mmc), "get clk err\n");
316842 + return -EINVAL;
316845 + pltfm_host->clk = clk;
316856 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
316857 + host->flags &= ~SDHCI_SIGNALING_330;
316858 + host->flags |= SDHCI_SIGNALING_180;
316867 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
316868 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
316869 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
316870 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
316872 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
316876 + host->mmc_host_ops.hs400_enhanced_strobe =
316879 + mci_host[slot_index++] = host->mmc;
316887 + unsigned int devid = hisi_priv->devid;
316898 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316904 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
316909 + timeout--;
316912 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
316918 + unsigned int devid = hisi_priv->devid;
316927 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316931 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
316938 + unsigned int devid = hisi_priv->devid;
316949 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316955 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
316960 + timeout--;
316963 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
316969 + unsigned int devid = hisi_priv->devid;
316980 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
316986 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
316991 + timeout--;
316994 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
317005 + regmap_read(hisi_priv->crg_regmap,
317011 + timeout--;
317014 + pr_err("%s: DS 180 DLL master not ready.\n", mmc_hostname(host->mmc));
317038 + host->error_count = 0;
317072 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317075 + switch (host->timing) {
317132 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317135 + switch (host->timing) {
317161 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317176 + unsigned int devid = hisi_priv->devid;
317177 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317200 + unsigned int devid = hisi_priv->devid;
317204 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
317205 + hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
317206 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
317207 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
317208 + hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
317209 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
317210 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
317211 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317212 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317213 + } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
317214 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
317215 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317216 + } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
317217 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317218 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317220 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
317221 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317225 + if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
317226 + (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
317227 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317228 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317231 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317232 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317242 + host->mmc->actual_clock = 0;
317249 + reset_control_assert(hisi_priv->dll_rst);
317252 + clk_set_rate(pltfm_host->clk, clock);
317253 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
317256 + hisi_set_drv_phase(host, hisi_priv->drv_phase);
317258 + hisi_set_sample_phase(host, hisi_priv->sample_phase);
317261 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
317263 + reset_control_deassert(hisi_priv->dll_rst);
317268 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
317272 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
317281 + unsigned int devid = hisi_priv->devid;
317289 diff --git a/drivers/mmc/host/sdhci-hi3518ev300.c b/drivers/mmc/host/sdhci-hi3518ev300.c
317292 --- /dev/null
317293 +++ b/drivers/mmc/host/sdhci-hi3518ev300.c
317294 @@ -0,0 +1,669 @@
317296 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
317314 +#include "sdhci-hisi.h"
317425 + clk_prepare_enable(pltfm_host->clk);
317426 + reset_control_assert(hisi_priv->crg_rst);
317427 + reset_control_assert(hisi_priv->dll_rst);
317430 + reset_control_deassert(hisi_priv->crg_rst);
317437 + unsigned int devid = hisi_priv->devid;
317446 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
317450 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
317461 + if (ios->enhanced_strobe)
317469 + if (ios->enhanced_strobe)
317481 + struct device_node *np = pdev->dev.of_node;
317485 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
317486 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
317487 + dev_err(&pdev->dev, "get crg_rst failed.\n");
317488 + return PTR_ERR(hisi_priv->crg_rst);
317491 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
317492 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
317493 + dev_err(&pdev->dev, "get dll_rst failed.\n");
317494 + return PTR_ERR(hisi_priv->dll_rst);
317497 + hisi_priv->sampl_rst = NULL;
317499 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
317500 + if (IS_ERR(hisi_priv->crg_regmap)) {
317501 + dev_err(&pdev->dev, "get crg regmap failed.\n");
317502 + return PTR_ERR(hisi_priv->crg_regmap);
317505 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, "iocfg_regmap");
317506 + if (IS_ERR(hisi_priv->iocfg_regmap)) {
317507 + dev_err(&pdev->dev, "get iocfg regmap failed.\n");
317508 + return PTR_ERR(hisi_priv->iocfg_regmap);
317511 + if (of_property_read_u32(np, "devid", &hisi_priv->devid))
317512 + return -EINVAL;
317514 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
317516 + dev_err(mmc_dev(host->mmc), "get clk err\n");
317517 + return -EINVAL;
317520 + pltfm_host->clk = clk;
317531 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
317532 + host->flags &= ~SDHCI_SIGNALING_330;
317533 + host->flags |= SDHCI_SIGNALING_180;
317542 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
317543 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
317544 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
317545 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
317547 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
317551 + host->mmc_host_ops.hs400_enhanced_strobe =
317554 + mci_host[slot_index++] = host->mmc;
317562 + unsigned int devid = hisi_priv->devid;
317573 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
317579 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
317584 + timeout--;
317587 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
317593 + unsigned int devid = hisi_priv->devid;
317602 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
317606 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
317613 + unsigned int devid = hisi_priv->devid;
317624 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
317630 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
317635 + timeout--;
317638 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
317644 + unsigned int devid = hisi_priv->devid;
317655 + pr_err("%s: Invalid devid %d\n", mmc_hostname(host->mmc), devid);
317661 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
317666 + timeout--;
317669 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
317680 + regmap_read(hisi_priv->crg_regmap,
317686 + timeout--;
317689 + pr_err("%s: DS 180 DLL master not ready.\n", mmc_hostname(host->mmc));
317713 + host->error_count = 0;
317747 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317750 + switch (host->timing) {
317807 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317810 + switch (host->timing) {
317836 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317851 + unsigned int devid = hisi_priv->devid;
317852 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
317875 + unsigned int devid = hisi_priv->devid;
317879 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
317880 + hisi_priv->drv_phase = 10; /* 10 for 112.5 degree */
317881 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
317882 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
317883 + hisi_priv->drv_phase = 23; /* 23 for 258.75 degree */
317884 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
317885 + } else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS) {
317886 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317887 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317888 + } else if (host->mmc->ios.timing == MMC_TIMING_SD_HS) {
317889 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
317890 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317891 + } else if (host->mmc->ios.timing == MMC_TIMING_LEGACY) {
317892 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317893 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317895 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
317896 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317900 + if ((host->mmc->ios.timing == MMC_TIMING_SD_HS) ||
317901 + (host->mmc->ios.timing == MMC_TIMING_UHS_SDR25)) {
317902 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317903 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
317906 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
317907 + hisi_priv->sample_phase = 0; /* 0 for 0 degree */
317917 + host->mmc->actual_clock = 0;
317924 + reset_control_assert(hisi_priv->dll_rst);
317927 + clk_set_rate(pltfm_host->clk, clock);
317928 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
317931 + hisi_set_drv_phase(host, hisi_priv->drv_phase);
317933 + hisi_set_sample_phase(host, hisi_priv->sample_phase);
317936 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
317938 + reset_control_deassert(hisi_priv->dll_rst);
317943 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
317947 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
317956 + unsigned int devid = hisi_priv->devid;
317964 diff --git a/drivers/mmc/host/sdhci-hi3519av100.c b/drivers/mmc/host/sdhci-hi3519av100.c
317967 --- /dev/null
317968 +++ b/drivers/mmc/host/sdhci-hi3519av100.c
317969 @@ -0,0 +1,19 @@
317971 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2020. All rights reserved.
317988 +#include "sdhci-hi3556av100.c"
317989 diff --git a/drivers/mmc/host/sdhci-hi3521dv200.c b/drivers/mmc/host/sdhci-hi3521dv200.c
317992 --- /dev/null
317993 +++ b/drivers/mmc/host/sdhci-hi3521dv200.c
317994 @@ -0,0 +1,573 @@
317996 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2020. All rights reserved.
318014 +#include "sdhci-hisi.h"
318185 + if (priv->devid == 0) {
318191 + host->error_count = 0;
318199 + regmap_write_bits(priv->iocfg_regmap, offset, IO_CFG_SDIO_MASK,
318208 + if (priv->devid == 0) { /* emmc devices */
318210 + hisi_mmc_io_cfg[host->timing][IO_CLK]);
318212 + hisi_mmc_io_cfg[host->timing][IO_CMD]);
318213 + for (i = 0; i < priv->bus_width; i++)
318215 + hisi_mmc_io_cfg[host->timing][IO_DATA]);
318217 + hisi_mmc_io_cfg[host->timing][IO_RST]);
318218 + if (host->timing == MMC_TIMING_MMC_HS400)
318220 + hisi_mmc_io_cfg[host->timing][IO_DS]);
318221 + } else if (priv->devid == 1) { /* sd devices */
318223 + hisi_sd_io_cfg[host->timing][IO_CLK]);
318225 + hisi_sd_io_cfg[host->timing][IO_CMD]);
318226 + for (i = 0; i < priv->bus_width; i++)
318228 + hisi_sd_io_cfg[host->timing][IO_DATA]);
318231 + hisi_sdio_io_cfg[host->timing][IO_CLK]);
318233 + hisi_sdio_io_cfg[host->timing][IO_CMD]);
318234 + for (i = 0; i < priv->bus_width; i++)
318236 + hisi_sdio_io_cfg[host->timing][IO_DATA]);
318246 + ret = regmap_read_poll_timeout(priv->crg_regmap, PERI_CRG_MMC_STAT,
318251 + mmc_hostname(host->mmc));
318260 + ret = regmap_read_poll_timeout(priv->crg_regmap, PERI_CRG_MMC_STAT,
318265 + mmc_hostname(host->mmc));
318274 + ret = regmap_read_poll_timeout(priv->crg_regmap, PERI_CRG_MMC_STAT,
318278 + pr_err("%s: DS DLL slave ready.\n", mmc_hostname(host->mmc));
318284 + unsigned int timing = host->mmc->ios.timing;
318290 + priv->sample_phase = priv->tuning_phase;
318292 + priv->sample_phase =
318295 + priv->drv_phase = hisi_phase_cfg[timing][DRIVE];
318302 + regmap_write_bits(priv->crg_regmap, PERI_CRG_MMC_DRV_DLL,
318332 + if (priv->devid == 0) {
318333 + priv->bus_width = hisi_get_mmc_bus_width();
318334 + if (priv->bus_width == MMC_BUS_WIDTH_8_BIT) {
318335 + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
318336 + host->mmc->caps &= ~MMC_CAP_4_BIT_DATA;
318338 + host->mmc->caps |= MMC_CAP_4_BIT_DATA;
318339 + host->mmc->caps &= ~MMC_CAP_8_BIT_DATA;
318351 + if (ios->enhanced_strobe)
318364 + reset_control_assert(priv->crg_rst);
318366 + reset_control_deassert(priv->crg_rst);
318375 + regmap_write_bits(priv->iocfg_regmap, offset,
318382 + unsigned int devid = priv->devid;
318383 + unsigned int bus_width = priv->bus_width;
318401 + /* Pull-up is required by default. */
318410 + struct device_node *np = pdev->dev.of_node;
318413 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
318414 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
318415 + rc = PTR_ERR(hisi_priv->crg_rst);
318416 + dev_err(&pdev->dev, "get crg_rst failed. %d\n", rc);
318417 + return PTR_ERR(hisi_priv->crg_rst);
318420 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
318421 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
318422 + rc = PTR_ERR(hisi_priv->dll_rst);
318423 + dev_err(&pdev->dev, "get dll_reset failed. %d\n", rc);
318424 + return PTR_ERR(hisi_priv->dll_rst);
318427 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np,
318429 + if (IS_ERR(hisi_priv->crg_regmap)) {
318430 + rc = PTR_ERR(hisi_priv->crg_regmap);
318431 + dev_err(&pdev->dev, "get crg regmap failed. %d\n", rc);
318432 + return PTR_ERR(hisi_priv->crg_regmap);
318435 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np,
318437 + if (IS_ERR(hisi_priv->iocfg_regmap)) {
318438 + rc = PTR_ERR(hisi_priv->iocfg_regmap);
318439 + dev_err(&pdev->dev, "get iocfg regmap failed. %d\n", rc);
318440 + return PTR_ERR(hisi_priv->iocfg_regmap);
318443 + if (of_property_read_u32(np, "devid", &hisi_priv->devid)) {
318444 + rc = PTR_ERR(hisi_priv->iocfg_regmap);
318445 + dev_err(mmc_dev(host->mmc), "get devid failed. %d\n", rc);
318446 + return -EINVAL;
318463 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
318465 + dev_err(mmc_dev(host->mmc), "get clk failed.\n");
318466 + return -EINVAL;
318468 + pltfm_host->clk = clk;
318480 + ret = clk_prepare_enable(pltfm_host->clk);
318490 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
318491 + host->flags &= ~SDHCI_SIGNALING_330;
318492 + host->flags |= SDHCI_SIGNALING_180;
318501 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
318502 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
318503 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
318504 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
318506 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
318509 + host->quirks2 &= ~SDHCI_QUIRK2_ACMD23_BROKEN;
318511 + host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_enhanced_strobe;
318513 + mci_host[slot_index++] = host->mmc;
318521 + unsigned int timing = host->mmc->ios.timing;
318528 + host->mmc->actual_clock = 0;
318532 + clk_set_rate(pltfm_host->clk, clk);
318533 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
318536 + hisi_set_drv_phase(host, priv->drv_phase);
318538 + hisi_set_sample_phase(host, priv->sample_phase);
318548 + reset_control_assert(priv->dll_rst);
318549 + reset_control_deassert(priv->dll_rst);
318566 + return (priv->devid == 0 || priv->devid == 1) ? 1 : 0;
318568 diff --git a/drivers/mmc/host/sdhci-hi3531dv200.c b/drivers/mmc/host/sdhci-hi3531dv200.c
318571 --- /dev/null
318572 +++ b/drivers/mmc/host/sdhci-hi3531dv200.c
318573 @@ -0,0 +1,548 @@
318575 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2020. All rights reserved.
318593 +#include "sdhci-hisi.h"
318741 + if (priv->devid == 0) {
318747 + host->error_count = 0;
318755 + regmap_write_bits(priv->iocfg_regmap, offset, IO_CFG_SDIO_MASK,
318764 + if (priv->devid == 0) { /* emmc devices */
318766 + hisi_mmc_io_cfg[host->timing][IO_CLK]);
318768 + hisi_mmc_io_cfg[host->timing][IO_CMD]);
318769 + for (i = 0; i < priv->bus_width; i++)
318771 + hisi_mmc_io_cfg[host->timing][IO_DATA]);
318773 + hisi_mmc_io_cfg[host->timing][IO_RST]);
318774 + if (host->timing == MMC_TIMING_MMC_HS400)
318776 + hisi_mmc_io_cfg[host->timing][IO_DS]);
318779 + hisi_sdio_io_cfg[host->timing][IO_CLK]);
318781 + hisi_sdio_io_cfg[host->timing][IO_CMD]);
318782 + for (i = 0; i < priv->bus_width; i++)
318784 + hisi_sdio_io_cfg[host->timing][IO_DATA]);
318795 + regmap_read(priv->crg_regmap, PERI_CRG_MMC_STAT, ®);
318800 + timeout--;
318803 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
318813 + regmap_read(priv->crg_regmap, PERI_CRG_MMC_STAT, ®);
318818 + timeout--;
318821 + pr_err("%s: P4 DLL master not locked.\n", mmc_hostname(host->mmc));
318831 + regmap_read(priv->crg_regmap, PERI_CRG_MMC_STAT, ®);
318836 + timeout--;
318839 + pr_err("%s: DS DLL slave not ready.\n", mmc_hostname(host->mmc));
318845 + unsigned int timing = host->mmc->ios.timing;
318851 + priv->sample_phase = priv->tuning_phase;
318853 + priv->sample_phase =
318856 + priv->drv_phase = hisi_phase_cfg[timing][DRIVE];
318863 + regmap_write_bits(priv->crg_regmap, PERI_CRG_MMC_DRV_DLL,
318893 + if (priv->devid == 0) {
318894 + priv->bus_width = hisi_get_mmc_bus_width();
318895 + if (priv->bus_width == MMC_BUS_WIDTH_8_BIT) {
318896 + host->mmc->caps |= MMC_CAP_8_BIT_DATA;
318897 + host->mmc->caps &= ~MMC_CAP_4_BIT_DATA;
318899 + host->mmc->caps |= MMC_CAP_4_BIT_DATA;
318900 + host->mmc->caps &= ~MMC_CAP_8_BIT_DATA;
318912 + if (ios->enhanced_strobe)
318925 + reset_control_assert(priv->crg_rst);
318927 + reset_control_deassert(priv->crg_rst);
318936 + regmap_write_bits(priv->iocfg_regmap, offset,
318943 + unsigned int devid = priv->devid;
318944 + unsigned int bus_width = priv->bus_width;
318964 + struct device_node *np = pdev->dev.of_node;
318967 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
318968 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
318969 + rc = PTR_ERR(hisi_priv->crg_rst);
318970 + dev_err(&pdev->dev, "get crg_rst failed. %d\n", rc);
318971 + return PTR_ERR(hisi_priv->crg_rst);
318974 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
318975 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
318976 + rc = PTR_ERR(hisi_priv->dll_rst);
318977 + dev_err(&pdev->dev, "get dll_reset failed. %d\n", rc);
318978 + return PTR_ERR(hisi_priv->dll_rst);
318981 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np,
318983 + if (IS_ERR(hisi_priv->crg_regmap)) {
318984 + rc = PTR_ERR(hisi_priv->crg_regmap);
318985 + dev_err(&pdev->dev, "get crg regmap failed. %d\n", rc);
318986 + return PTR_ERR(hisi_priv->crg_regmap);
318989 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np,
318991 + if (IS_ERR(hisi_priv->iocfg_regmap)) {
318992 + rc = PTR_ERR(hisi_priv->iocfg_regmap);
318993 + dev_err(&pdev->dev, "get iocfg regmap failed. %d\n", rc);
318994 + return PTR_ERR(hisi_priv->iocfg_regmap);
318997 + if (of_property_read_u32(np, "devid", &hisi_priv->devid)) {
318998 + rc = PTR_ERR(hisi_priv->iocfg_regmap);
318999 + dev_err(mmc_dev(host->mmc), "get devid failed. %d\n", rc);
319000 + return -EINVAL;
319017 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
319019 + dev_err(mmc_dev(host->mmc), "get clk failed.\n");
319020 + return -EINVAL;
319022 + pltfm_host->clk = clk;
319034 + ret = clk_prepare_enable(pltfm_host->clk);
319044 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
319045 + host->flags &= ~SDHCI_SIGNALING_330;
319046 + host->flags |= SDHCI_SIGNALING_180;
319055 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
319056 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
319057 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
319058 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
319060 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
319063 + host->quirks2 &= ~SDHCI_QUIRK2_ACMD23_BROKEN;
319065 + host->mmc_host_ops.hs400_enhanced_strobe = sdhci_hisi_enhanced_strobe;
319067 + mci_host[slot_index++] = host->mmc;
319075 + unsigned int timing = host->mmc->ios.timing;
319082 + host->mmc->actual_clock = 0;
319086 + clk_set_rate(pltfm_host->clk, clk);
319087 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
319090 + hisi_set_drv_phase(host, priv->drv_phase);
319092 + hisi_set_sample_phase(host, priv->sample_phase);
319102 + reset_control_assert(priv->dll_rst);
319103 + reset_control_deassert(priv->dll_rst);
319120 + return (priv->devid == 0) ? 1 : 0;
319122 diff --git a/drivers/mmc/host/sdhci-hi3556av100.c b/drivers/mmc/host/sdhci-hi3556av100.c
319125 --- /dev/null
319126 +++ b/drivers/mmc/host/sdhci-hi3556av100.c
319127 @@ -0,0 +1,627 @@
319129 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2020. All rights reserved.
319146 +#include "sdhci-hisi.h"
319237 + clk_prepare_enable(pltfm_host->clk);
319238 + reset_control_assert(hisi_priv->crg_rst);
319239 + reset_control_assert(hisi_priv->dll_rst);
319240 + if (hisi_priv->sampl_rst)
319241 + reset_control_assert(hisi_priv->sampl_rst);
319244 + reset_control_deassert(hisi_priv->crg_rst);
319251 + unsigned int devid = hisi_priv->devid;
319259 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
319278 + struct regmap *misc = hisi_priv->misc_regmap;
319281 + pr_debug("%s: set voltage to 330\n", mmc_hostname(host->mmc));
319283 + if (hisi_priv->devid == 1) {
319302 + mmc_hostname(host->mmc));
319304 + return -EAGAIN;
319310 + struct regmap *misc = hisi_priv->misc_regmap;
319313 + pr_debug("%s: set voltage to 180\n", mmc_hostname(host->mmc));
319315 + if (hisi_priv->devid == 0)
319318 + if (hisi_priv->devid == 1) {
319334 + if (hisi_priv->devid == 2) /* for device id 2 */
319338 + mmc_hostname(host->mmc));
319340 + return -EAGAIN;
319350 + if (ios->enhanced_strobe)
319362 + struct device_node *np = pdev->dev.of_node;
319366 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
319367 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
319368 + dev_err(&pdev->dev, "get crg_rst failed.\n");
319369 + return PTR_ERR(hisi_priv->crg_rst);
319372 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
319373 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
319374 + dev_err(&pdev->dev, "get dll_rst failed.\n");
319375 + return PTR_ERR(hisi_priv->dll_rst);
319378 + hisi_priv->sampl_rst = devm_reset_control_get(&pdev->dev, "sampl_reset");
319379 + if (IS_ERR_OR_NULL(hisi_priv->sampl_rst)) {
319380 + dev_err(&pdev->dev, "get sampl_rst failed.\n");
319381 + return PTR_ERR(hisi_priv->sampl_rst);
319384 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
319385 + if (IS_ERR(hisi_priv->crg_regmap)) {
319386 + dev_err(&pdev->dev, "get crg regmap failed.\n");
319387 + return PTR_ERR(hisi_priv->crg_regmap);
319390 + if (of_property_read_u32(np, "devid", &hisi_priv->devid))
319391 + return -EINVAL;
319393 + if (hisi_priv->devid == 0) {
319398 + return -ENOMEM;
319400 + hisi_priv->phy_addr = devm_ioremap_resource(&pdev->dev, res);
319401 + if (IS_ERR(hisi_priv->phy_addr))
319402 + return PTR_ERR(hisi_priv->phy_addr);
319404 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np,
319406 + if (IS_ERR(hisi_priv->iocfg_regmap))
319407 + return PTR_ERR(hisi_priv->iocfg_regmap);
319409 + hisi_priv->misc_regmap = syscon_regmap_lookup_by_phandle(np,
319411 + if (IS_ERR(hisi_priv->misc_regmap))
319412 + return PTR_ERR(hisi_priv->misc_regmap);
319414 + hisi_set_pd_pin_status(hisi_priv->misc_regmap);
319417 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
319419 + dev_err(mmc_dev(host->mmc), "get clk err\n");
319420 + return -EINVAL;
319423 + pltfm_host->clk = clk;
319433 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
319434 + host->flags &= ~SDHCI_SIGNALING_330;
319435 + host->flags |= SDHCI_SIGNALING_180;
319444 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
319445 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
319446 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
319447 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
319449 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
319453 + host->caps1 |= SDHCI_USE_SDR50_TUNING;
319454 + host->mmc_host_ops.hs400_enhanced_strobe =
319457 + mci_host[slot_index++] = host->mmc;
319465 + unsigned int devid = hisi_priv->devid;
319473 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
319480 + unsigned int devid = hisi_priv->devid;
319492 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
319497 + timeout--;
319500 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
319511 + regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS_DLL_STATUS, ®);
319516 + timeout--;
319519 + pr_err("%s: DS DLL master not locked.\n", mmc_hostname(host->mmc));
319535 + unsigned int devid = hisi_priv->devid;
319547 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
319552 + timeout--;
319555 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
319561 + switch (ios->signal_voltage) {
319563 + if (!(host->flags & SDHCI_SIGNALING_330))
319564 + return -EINVAL;
319567 + if (!(host->flags & SDHCI_SIGNALING_180))
319568 + return -EINVAL;
319595 + host->error_count = 0;
319601 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
319605 + if (host->timing == MMC_TIMING_UHS_SDR104)
319607 + else if (host->timing == MMC_TIMING_UHS_SDR50)
319609 + else if (host->timing == MMC_TIMING_UHS_SDR25 ||
319610 + host->timing == MMC_TIMING_SD_HS)
319625 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
319629 + if (host->timing == MMC_TIMING_UHS_SDR104)
319631 + else if (host->timing == MMC_TIMING_UHS_SDR50)
319633 + else if (host->timing == MMC_TIMING_UHS_SDR25 ||
319634 + host->timing == MMC_TIMING_SD_HS)
319649 + unsigned int devid = hisi_priv->devid;
319650 + void *phy_addr = hisi_priv->phy_addr;
319654 + if (host->timing == MMC_TIMING_MMC_HS200 ||
319655 + host->timing == MMC_TIMING_MMC_HS400 ||
319656 + host->timing == MMC_TIMING_MMC_HS) {
319676 + if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
319677 + host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
319678 + hisi_priv->drv_phase = 8; /* 8 for 90 degree */
319679 + else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
319680 + host->mmc->ios.timing == MMC_TIMING_UHS_SDR104)
319681 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
319682 + else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
319683 + hisi_priv->drv_phase = 9; /* 9 for 101.25 degree */
319685 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
319687 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
319688 + host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
319689 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
319690 + else if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
319691 + hisi_priv->sample_phase = 20; /* 20 for 225 degree */
319692 + else if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
319693 + host->mmc->ios.timing == MMC_TIMING_UHS_SDR25 ||
319694 + host->mmc->ios.timing == MMC_TIMING_SD_HS ||
319695 + host->mmc->ios.timing == MMC_TIMING_MMC_HS)
319696 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
319698 + hisi_priv->sample_phase = 0; /* 0 for 0 egree */
319706 + host->mmc->actual_clock = 0;
319713 + reset_control_assert(hisi_priv->dll_rst);
319714 + if (hisi_priv->sampl_rst)
319715 + reset_control_assert(hisi_priv->sampl_rst);
319718 + clk_set_rate(pltfm_host->clk, clock);
319719 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
319722 + hisi_set_drv_phase(host, hisi_priv->drv_phase);
319724 + hisi_set_sample_phase(host, hisi_priv->sample_phase);
319727 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
319729 + reset_control_deassert(hisi_priv->dll_rst);
319730 + if (hisi_priv->sampl_rst)
319731 + reset_control_deassert(hisi_priv->sampl_rst);
319736 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
319744 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
319755 diff --git a/drivers/mmc/host/sdhci-hi3559av100.c b/drivers/mmc/host/sdhci-hi3559av100.c
319758 --- /dev/null
319759 +++ b/drivers/mmc/host/sdhci-hi3559av100.c
319760 @@ -0,0 +1,630 @@
319762 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2020. All rights reserved.
319779 +#include "sdhci-hisi.h"
319875 + clk_prepare_enable(pltfm_host->clk);
319876 + reset_control_assert(hisi_priv->crg_rst);
319877 + reset_control_assert(hisi_priv->dll_rst);
319878 + if (hisi_priv->sampl_rst)
319879 + reset_control_assert(hisi_priv->sampl_rst);
319882 + reset_control_deassert(hisi_priv->crg_rst);
319889 + unsigned int devid = hisi_priv->devid;
319897 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
319916 + struct regmap *misc = hisi_priv->misc_regmap;
319920 + if (hisi_priv->devid == 3) /* device id 3 for sdio2 */
319923 + pr_debug("%s: set voltage to 330\n", mmc_hostname(host->mmc));
319925 + if (hisi_priv->devid == 1) {
319943 + if (hisi_priv->devid == 2) { /* device id 2 for sdio1 */
319954 + mmc_hostname(host->mmc));
319956 + return -EAGAIN;
319962 + struct regmap *misc = hisi_priv->misc_regmap;
319965 + pr_debug("%s: set voltage to 180\n", mmc_hostname(host->mmc));
319967 + if (hisi_priv->devid == 0 || hisi_priv->devid == 3) /* for device id 0 and 3 */
319970 + if (hisi_priv->devid == 1) {
319986 + mmc_hostname(host->mmc));
319988 + return -EAGAIN;
319998 + if (ios->enhanced_strobe)
320010 + struct device_node *np = pdev->dev.of_node;
320014 + hisi_priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset");
320015 + if (IS_ERR_OR_NULL(hisi_priv->crg_rst)) {
320016 + dev_err(&pdev->dev, "get crg_rst failed.\n");
320017 + return PTR_ERR(hisi_priv->crg_rst);
320020 + hisi_priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset");
320021 + if (IS_ERR_OR_NULL(hisi_priv->dll_rst)) {
320022 + dev_err(&pdev->dev, "get dll_rst failed.\n");
320023 + return PTR_ERR(hisi_priv->dll_rst);
320026 + hisi_priv->sampl_rst = devm_reset_control_get(&pdev->dev, "sampl_reset");
320027 + if (IS_ERR_OR_NULL(hisi_priv->sampl_rst)) {
320028 + dev_err(&pdev->dev, "get sampl_rst failed.\n");
320029 + return PTR_ERR(hisi_priv->sampl_rst);
320032 + hisi_priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap");
320033 + if (IS_ERR(hisi_priv->crg_regmap)) {
320034 + dev_err(&pdev->dev, "get crg regmap failed.\n");
320035 + return PTR_ERR(hisi_priv->crg_regmap);
320038 + if (of_property_read_u32(np, "devid", &hisi_priv->devid))
320039 + return -EINVAL;
320041 + if (hisi_priv->devid == 0) {
320046 + return -ENOMEM;
320048 + hisi_priv->phy_addr = devm_ioremap_resource(&pdev->dev, res);
320049 + if (IS_ERR(hisi_priv->phy_addr))
320050 + return PTR_ERR(hisi_priv->phy_addr);
320052 + hisi_priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np,
320054 + if (IS_ERR(hisi_priv->iocfg_regmap))
320055 + return PTR_ERR(hisi_priv->iocfg_regmap);
320057 + hisi_priv->misc_regmap = syscon_regmap_lookup_by_phandle(np,
320059 + if (IS_ERR(hisi_priv->misc_regmap))
320060 + return PTR_ERR(hisi_priv->misc_regmap);
320062 + hisi_set_pd_pin_status(hisi_priv->misc_regmap);
320065 + clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk");
320067 + dev_err(mmc_dev(host->mmc), "get clk err\n");
320068 + return -EINVAL;
320071 + pltfm_host->clk = clk;
320083 + if (host->mmc->caps & MMC_CAP_HW_RESET) {
320084 + host->flags &= ~SDHCI_SIGNALING_330;
320085 + host->flags |= SDHCI_SIGNALING_180;
320094 + host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
320095 + host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300);
320096 + host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
320097 + host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
320099 + host->quirks |= SDHCI_QUIRK_MISSING_CAPS |
320103 + host->caps1 |= SDHCI_USE_SDR50_TUNING;
320104 + host->mmc_host_ops.hs400_enhanced_strobe =
320107 + mci_host[slot_index++] = host->mmc;
320115 + unsigned int devid = hisi_priv->devid;
320123 + regmap_write_bits(hisi_priv->crg_regmap, offset[devid],
320130 + unsigned int devid = hisi_priv->devid;
320142 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
320147 + timeout--;
320150 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
320161 + regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS_DLL_STATUS, ®);
320166 + timeout--;
320169 + pr_err("%s: DS DLL master not locked.\n", mmc_hostname(host->mmc));
320177 + regmap_read(hisi_priv->crg_regmap, REG_EMMC_DS_DLL_STATUS, ®);
320180 + regmap_write_bits(hisi_priv->crg_regmap, REG_EMMC_DS_DLL_CTRL,
320184 + regmap_write_bits(hisi_priv->crg_regmap, REG_EMMC_DS180_DLL_CTRL,
320191 + unsigned int devid = hisi_priv->devid;
320203 + regmap_read(hisi_priv->crg_regmap, offset[devid], ®);
320208 + timeout--;
320211 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
320217 + switch (ios->signal_voltage) {
320219 + if (!(host->flags & SDHCI_SIGNALING_330))
320220 + return -EINVAL;
320223 + if (!(host->flags & SDHCI_SIGNALING_180))
320224 + return -EINVAL;
320251 + host->error_count = 0;
320257 + unsigned int devid = hisi_priv->devid;
320258 + void *iocfg_regmap = hisi_priv->iocfg_regmap;
320262 + if (host->timing == MMC_TIMING_UHS_SDR104)
320264 + else if (host->timing == MMC_TIMING_UHS_SDR50 ||
320265 + host->timing == MMC_TIMING_UHS_SDR25 ||
320266 + host->timing == MMC_TIMING_UHS_SDR12)
320294 + unsigned int devid = hisi_priv->devid;
320295 + void *phy_addr = hisi_priv->phy_addr;
320299 + if (host->timing == MMC_TIMING_MMC_HS200 ||
320300 + host->timing == MMC_TIMING_MMC_HS400 ||
320301 + host->timing == MMC_TIMING_MMC_HS) {
320319 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 ||
320320 + host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
320321 + host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
320322 + hisi_priv->drv_phase = 8; /* 8 for 90 degree */
320323 + else if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200)
320324 + hisi_priv->drv_phase = 20; /* 20 for 225 degree */
320326 + hisi_priv->drv_phase = 16; /* 16 for 180 degree */
320328 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400)
320329 + hisi_priv->sample_phase = hisi_priv->tuning_phase;
320330 + else if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
320331 + host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
320332 + hisi_priv->sample_phase = 4; /* 4 for 45 degree */
320334 + hisi_priv->sample_phase = 0; /* 0 or 0 degree */
320342 + host->mmc->actual_clock = 0;
320349 + reset_control_assert(hisi_priv->dll_rst);
320350 + if (hisi_priv->sampl_rst)
320351 + reset_control_assert(hisi_priv->sampl_rst);
320354 + clk_set_rate(pltfm_host->clk, clock);
320355 + host->mmc->actual_clock = clk_get_rate(pltfm_host->clk);
320358 + hisi_set_drv_phase(host, hisi_priv->drv_phase);
320360 + hisi_set_sample_phase(host, hisi_priv->sample_phase);
320363 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
320365 + reset_control_deassert(hisi_priv->dll_rst);
320366 + if (hisi_priv->sampl_rst)
320367 + reset_control_deassert(hisi_priv->sampl_rst);
320372 + if (host->mmc->actual_clock > MMC_HIGH_52_MAX_DTR) {
320380 + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {
320391 diff --git a/drivers/mmc/host/sdhci-hisi.c b/drivers/mmc/host/sdhci-hisi.c
320394 --- /dev/null
320395 +++ b/drivers/mmc/host/sdhci-hisi.c
320396 @@ -0,0 +1,783 @@
320398 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2020. All rights reserved.
320415 +#include "sdhci-hisi.h"
320422 + struct device_node *np = host->mmc->parent->of_node;
320426 + ret = mmc_of_parse(host->mmc);
320431 + if (of_get_property(np, "mmc-cmd-queue", NULL))
320432 + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
320434 + if (of_get_property(np, "mmc-broken-cmd23", NULL))
320435 + host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
320437 + if (of_property_read_u32(np, "bus-width", &bus_width) == 0) {
320438 + priv->bus_width = bus_width;
320440 + pr_err("%s: \"bus-width\" property is missing, assuming 1 bit.\n",
320441 + mmc_hostname(host->mmc));
320442 + priv->bus_width = 1;
320445 + if (of_get_property(np, "sdhci,1-bit-only", NULL) ||
320446 + (priv->bus_width == 1)) {
320447 + priv->bus_width = 1;
320448 + host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
320516 + timeout--;
320538 + err = mmc_send_tuning(host->mmc, opcode, NULL);
320540 + mmc_abort_tuning(host->mmc, opcode);
320551 + sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
320552 + sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
320555 + host->is_tuning = 1;
320566 + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
320567 + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
320568 + host->is_tuning = 0;
320589 + win = fall - rise + 1;
320610 + win = end_fall - rise + 1;
320646 + mmc_hostname(host->mmc), candidates);
320650 + phase = priv->sample_phase;
320654 + priv->tuning_phase = phase;
320722 + mmc_hostname(host->mmc));
320723 + return -1;
320767 + mmc_hostname(host->mmc), rise % PHASE_SCALE,
320770 + priv->tuning_phase = phase;
320791 + if (host->timing == MMC_TIMING_MMC_HS ||
320792 + host->timing == MMC_TIMING_MMC_DDR52 ||
320793 + host->timing == MMC_TIMING_MMC_HS200 ||
320794 + host->timing == MMC_TIMING_MMC_HS400) {
320805 + host->timing = timing;
320827 + return -EINVAL;
320833 + return -EINVAL;
320878 + cqhci_irq(host->mmc, intmask, cmd_error, data_error);
320893 + if (host->flags & SDHCI_USE_64_BIT_DMA)
320912 + sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary,
320931 + while (mmc->ops->card_busy(mmc)) {
320932 + timeout--;
320947 + while (mmc->ops->card_busy(mmc)) {
320948 + timeout--;
320995 + if (!(host->mmc->caps2 & MMC_CAP2_CQE))
321002 + cq_host = devm_kzalloc(host->mmc->parent, sizeof(*cq_host), GFP_KERNEL);
321005 + ret = -ENOMEM;
321009 + cq_host->mmio = host->ioaddr + 0x180;
321010 + cq_host->ops = &sdhci_hisi_cqhci_ops;
321016 + cq_host->quirks |= CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT;
321018 + dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
321020 + cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
321022 + ret = cqhci_init(cq_host, host->mmc, dma64);
321052 + if (of_get_property(pdev->dev.of_node, "mmc-cmd-queue", NULL))
321068 + pm_runtime_get_noresume(&pdev->dev);
321069 + pm_runtime_set_autosuspend_delay(&pdev->dev, HISI_MMC_AUTOSUSPEND_DELAY_MS);
321070 + pm_runtime_use_autosuspend(&pdev->dev);
321071 + pm_runtime_set_active(&pdev->dev);
321072 + pm_runtime_enable(&pdev->dev);
321080 + pm_runtime_mark_last_busy(&pdev->dev);
321081 + pm_runtime_put_autosuspend(&pdev->dev);
321088 + pm_runtime_disable(&pdev->dev);
321089 + pm_runtime_set_suspended(&pdev->dev);
321090 + pm_runtime_put_noidle(&pdev->dev);
321101 + int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
321105 + pm_runtime_get_sync(&pdev->dev);
321106 + pm_runtime_disable(&pdev->dev);
321107 + pm_runtime_put_noidle(&pdev->dev);
321180 diff --git a/drivers/mmc/host/sdhci-hisi.h b/drivers/mmc/host/sdhci-hisi.h
321183 --- /dev/null
321184 +++ b/drivers/mmc/host/sdhci-hisi.h
321185 @@ -0,0 +1,126 @@
321187 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2017-2020. All rights reserved.
321216 +#include "sdhci-pltfm.h"
321221 +#define NOT_FOUND (-1)
321312 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
321314 --- a/drivers/mmc/host/sdhci.c
321316 @@ -237,7 +237,7 @@ static void sdhci_set_default_irqs(struct sdhci_host *host)
321320 - SDHCI_INT_RESPONSE;
321323 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
321324 host->tuning_mode == SDHCI_TUNING_MODE_3)
321325 @@ -265,6 +265,9 @@ static void sdhci_init(struct sdhci_host *host, int soft)
321326 host->clock = 0;
321327 mmc->ops->set_ios(mmc, &mmc->ios);
321330 + if (host->ops->init)
321331 + host->ops->init(host);
321335 @@ -572,6 +575,60 @@ static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
321336 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
321355 + if (host->flags & SDHCI_USE_64_BIT_DMA) {
321367 + struct mmc_data *data = cmd->data;
321371 + blksz = SDHCI_MAKE_BLKSZ(0, data->blksz);
321373 + cmd_xfer = (SDHCI_MAKE_CMD(cmd->opcode, flags) << 16) | mode; // left shift 16
321375 + sdhci_write_cmd_table(host->cmd_table, data->blocks, ADMA3_CMD_VALID);
321376 + sdhci_write_cmd_table(host->cmd_table + 0x8, blksz, ADMA3_CMD_VALID); // add 0x8
321377 + sdhci_write_cmd_table(host->cmd_table + 0x10, // add 0x10
321378 + cmd->arg, ADMA3_CMD_VALID);
321379 + sdhci_write_cmd_table(host->cmd_table + 0x18, // add 0x18
321381 + sdhci_adma_write_desc(host, host->cmd_table + 0x20, // add 0x20
321382 + host->adma_addr, 0x0, ADMA2_LINK_VALID);
321383 + sdhci_write_adma3_desc(host, host->adma3_table,
321384 + host->cmd_addr, ADMA3_END);
321388 + if (host->flags & SDHCI_USE_64_BIT_DMA)
321396 @@ -639,6 +696,17 @@ static void sdhci_adma_table_pre(struct sdhci_host *host,
321401 + if (((addr & (SDHCI_DMA_BOUNDARY_SIZE - 1)) + len) >
321403 + offset = SDHCI_DMA_BOUNDARY_SIZE -
321404 + (addr & (SDHCI_DMA_BOUNDARY_SIZE - 1));
321407 + desc += host->desc_sz;
321409 + len -= offset;
321414 @@ -883,6 +951,18 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
321420 + if (host->flags & SDHCI_USE_ADMA3) {
321423 + if (host->flags & SDHCI_USE_64_BIT_DMA)
321433 @@ -959,7 +1039,6 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cm…
321435 if (host->flags & SDHCI_REQ_USE_DMA) {
321437 -
321441 @@ -992,10 +1071,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *c…
321443 if ((host->flags & SDHCI_REQ_USE_DMA) &&
321444 (host->flags & SDHCI_USE_ADMA)) {
321445 - if (host->flags & SDHCI_USE_64_BIT_DMA)
321446 - ctrl |= SDHCI_CTRL_ADMA64;
321447 - else
321448 - ctrl |= SDHCI_CTRL_ADMA32;
321453 @@ -1203,6 +1279,28 @@ static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
321454 del_timer(&host->timer);
321459 + if (!(host->flags & SDHCI_USE_ADMA3) || !cmd->data)
321460 + sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
321466 + if ((host->flags & SDHCI_USE_ADMA3) && cmd->data) {
321469 + sdhci_writel(host, (u32)host->adma3_addr,
321471 + if (host->flags & SDHCI_USE_64_BIT_DMA)
321472 + sdhci_writel(host, (u32)((u64)host->adma3_addr >> 32), // right shift 32
321475 + sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, *flags), SDHCI_COMMAND);
321482 @@ -1251,7 +1349,7 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
321486 - sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
321491 @@ -1291,7 +1389,7 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
321493 sdhci_mod_timer(host, cmd->mrq, timeout);
321495 - sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
321500 @@ -1315,6 +1413,14 @@ static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *…
321514 struct mmc_command *cmd = host->cmd;
321515 @@ -1327,6 +1433,12 @@ static void sdhci_finish_command(struct sdhci_host *host)
321517 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
321520 + if (((cmd->flags & MMC_RSP_R1) == MMC_RSP_R1) &&
321521 + ((cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR)) {
321522 + if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning)
321523 + host->error_count++;
321527 if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd)
321528 @@ -1592,6 +1704,12 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
321530 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
321541 @@ -1868,7 +1986,9 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
321544 /* Re-enable SD Clock */
321545 - host->ops->set_clock(host, host->clock);
321552 @@ -2005,6 +2125,9 @@ int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
321556 + if (host->ops->start_signal_voltage_switch)
321557 + return host->ops->start_signal_voltage_switch(host, ios);
321562 @@ -2441,6 +2564,34 @@ static void sdhci_card_event(struct mmc_host *mmc)
321563 spin_unlock_irqrestore(&host->lock, flags);
321568 + struct mmc_card *card = mmc->card;
321570 + struct card_info *c_info = &host->c_info;
321574 + c_info->card_connect = CARD_DISCONNECT;
321578 + c_info->card_type = card->type;
321579 + c_info->card_state = card->state;
321581 + c_info->timing = mmc->ios.timing;
321582 + c_info->enhanced_strobe = mmc->ios.enhanced_strobe;
321583 + c_info->card_support_clock = mmc->ios.clock;
321585 + c_info->sd_bus_speed = card->sd_bus_speed;
321587 + memcpy(c_info->ssr, card->raw_ssr, ARRAY_SIZE(c_info->ssr));
321589 + c_info->card_connect = CARD_CONNECT;
321597 @@ -2455,6 +2606,7 @@ static const struct mmc_host_ops sdhci_ops = {
321605 @@ -2565,6 +2717,9 @@ static bool sdhci_request_done(struct sdhci_host *host)
321606 host->pending_reset = false;
321609 + if (mrq->data && mrq->data->error && !host->is_tuning)
321610 + host->error_count++;
321615 @@ -2645,6 +2800,24 @@ static void sdhci_timeout_data_timer(struct timer_list *t)
321626 + host->cmd->error = -EIO;
321628 + host->cmd->error = -ETIMEDOUT;
321630 + host->cmd->error = -EILSEQ;
321633 + host->cmd->error = -EILSEQ;
321639 /* Handle auto-CMD12 error */
321640 @@ -2670,18 +2843,21 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmas…
321642 if (host->pending_reset)
321644 - pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
321647 mmc_hostname(host->mmc), (unsigned)intmask);
321648 - sdhci_dumpregs(host);
321655 - SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
321659 host->cmd->error = -ETIMEDOUT;
321661 - host->cmd->error = -EILSEQ;
321665 if (host->cmd->data &&
321666 @@ -2894,6 +3070,9 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
321670 + if ((intmask & SDHCI_INT_ERROR) && !host->is_tuning)
321671 + host->error_count++;
321673 if (host->ops->irq) {
321674 intmask = host->ops->irq(host, intmask);
321676 @@ -3225,10 +3404,12 @@ void sdhci_cqe_enable(struct mmc_host *mmc)
321682 -
321684 spin_lock_irqsave(&host->lock, flags);
321689 if (host->flags & SDHCI_USE_64_BIT_DMA)
321690 @@ -3239,7 +3420,7 @@ void sdhci_cqe_enable(struct mmc_host *mmc)
321692 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
321694 -
321699 @@ -3275,8 +3456,8 @@ void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
321703 - pr_debug("%s: sdhci: CQE off, IRQ mask %#x, IRQ status %#x\n",
321704 - mmc_hostname(mmc), host->ier,
321706 + mmc_hostname(mmc), host->ier,\
321710 @@ -3508,6 +3689,72 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
321716 + if ((host->version >= SDHCI_SPEC_400) &&
321717 + (host->caps1 & SDHCI_CAN_DO_ADMA3))
321718 + host->flags |= SDHCI_USE_ADMA3 | SDHCI_HOST_VER4_ENABLE;
321720 + if ((host->quirks2 & SDHCI_QUIRK2_BROKEN_ADMA3) &&
321721 + (host->flags & SDHCI_USE_ADMA3)) {
321723 + host->flags &= ~(SDHCI_USE_ADMA3 | SDHCI_HOST_VER4_ENABLE);
321729 + if (host->flags & SDHCI_HOST_VER4_ENABLE)
321730 + host->desc_sz = 16; //descriptor size 16
321732 + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
321738 + if (!(host->flags & SDHCI_USE_ADMA))
321739 + host->flags &= ~SDHCI_USE_ADMA3;
321741 + if (host->flags & SDHCI_USE_ADMA3) {
321744 + if (host->flags & SDHCI_USE_64_BIT_DMA)
321745 + host->adma3_desc_sz = SDHCI_ADMA3_64_DESC_SZ;
321747 + host->adma3_desc_sz = SDHCI_ADMA3_32_DESC_SZ;
321749 + host->adma3_table_sz = MAX_CMD_NUM * host->adma3_desc_sz;
321750 + host->cmd_table_sz = MAX_CMD_NUM *
321752 + buf = dma_alloc_coherent(mmc_dev(mmc), host->adma3_table_sz +
321753 + host->cmd_table_sz, dma, GFP_KERNEL);
321755 + pr_warn("%s: Unable to allocate ADMA3 buffers - falling back \
321757 + host->flags &= ~SDHCI_USE_ADMA3;
321759 + host->adma3_table = buf;
321760 + host->adma3_addr = *dma;
321762 + host->cmd_table = buf + host->adma3_desc_sz;
321763 + host->cmd_addr = *dma + host->adma3_desc_sz;
321771 + if (host->adma3_table)
321772 + dma_free_coherent(mmc_dev(mmc), host->adma3_table_sz +
321773 + host->cmd_table_sz, host->adma3_table,
321774 + host->adma3_addr);
321776 + host->adma3_table = NULL;
321777 + host->cmd_table = NULL;
321783 @@ -3544,10 +3791,9 @@ int sdhci_setup_host(struct sdhci_host *host)
321785 override_timeout_clk = host->timeout_clk;
321787 - if (host->version > SDHCI_SPEC_300) {
321788 + if (host->version > SDHCI_SPEC_420)
321790 mmc_hostname(mmc), host->version);
321791 - }
321793 if (host->quirks & SDHCI_QUIRK_BROKEN_CQE)
321794 mmc->caps2 &= ~MMC_CAP2_CQE;
321795 @@ -3575,6 +3821,8 @@ int sdhci_setup_host(struct sdhci_host *host)
321796 host->flags &= ~SDHCI_USE_ADMA;
321802 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
321803 * and *must* do 64-bit DMA. A driver has the opportunity to change
321804 @@ -3615,15 +3863,13 @@ int sdhci_setup_host(struct sdhci_host *host)
321807 if (host->flags & SDHCI_USE_64_BIT_DMA) {
321808 - host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
321809 - SDHCI_ADMA2_64_DESC_SZ;
321810 - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
321813 - host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
321814 - SDHCI_ADMA2_32_DESC_SZ;
321815 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
321818 + host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * host->desc_sz; // size 2
321820 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
321821 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
321822 host->adma_table_sz, &dma, GFP_KERNEL);
321823 @@ -3645,6 +3891,7 @@ int sdhci_setup_host(struct sdhci_host *host)
321824 host->adma_table = buf + host->align_buffer_sz;
321825 host->adma_addr = dma + host->align_buffer_sz;
321831 @@ -3891,7 +4138,6 @@ int sdhci_setup_host(struct sdhci_host *host)
321832 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
321833 int curr = regulator_get_current_limit(mmc->supply.vmmc);
321835 -
321839 @@ -4050,6 +4296,8 @@ int sdhci_setup_host(struct sdhci_host *host)
321840 host->adma_table = NULL;
321841 host->align_buffer = NULL;
321848 @@ -4067,6 +4315,8 @@ void sdhci_cleanup_host(struct sdhci_host *host)
321849 host->align_addr);
321850 host->adma_table = NULL;
321851 host->align_buffer = NULL;
321857 @@ -4111,6 +4361,7 @@ int __sdhci_add_host(struct sdhci_host *host)
321860 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
321861 + (host->flags & SDHCI_USE_ADMA3) ? "ADMA3" :
321862 (host->flags & SDHCI_USE_ADMA) ?
321863 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
321864 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
321865 @@ -4175,6 +4426,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
321869 + free_irq(host->irq, host);
321874 @@ -4184,7 +4437,6 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
321878 - free_irq(host->irq, host);
321880 del_timer_sync(&host->timer);
321881 del_timer_sync(&host->data_timer);
321882 @@ -4201,6 +4453,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead)
321884 host->adma_table = NULL;
321885 host->align_buffer = NULL;
321891 diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
321893 --- a/drivers/mmc/host/sdhci.h
321895 @@ -86,6 +86,7 @@
321903 @@ -110,6 +111,7 @@
321911 @@ -135,6 +137,7 @@
321919 @@ -168,10 +171,12 @@
321932 @@ -180,7 +185,7 @@
321936 -#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
321937 +#define SDHCI_CTRL_HS400 0x0007 /* Non-standard */
321941 @@ -189,6 +194,9 @@
321951 @@ -210,6 +218,7 @@
321959 @@ -224,6 +233,7 @@
321964 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
321967 @@ -265,6 +275,9 @@
321977 @@ -275,6 +288,9 @@
321987 @@ -288,6 +304,7 @@
321990 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
321993 /* ADMA2 32-bit DMA descriptor size */
321995 @@ -313,6 +330,12 @@ struct sdhci_adma2_32_desc {
321996 /* ADMA2 64-bit DMA descriptor size */
321999 +/* ADMA3 32-bit DMA descriptor size */
322002 +/* ADMA3 64-bit DMA descriptor size */
322006 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
322008 @@ -327,6 +350,9 @@ struct sdhci_adma2_64_desc {
322018 @@ -351,6 +377,19 @@ enum sdhci_cookie {
322038 @@ -450,6 +489,7 @@ struct sdhci_host {
322046 @@ -493,6 +533,8 @@ struct sdhci_host {
322055 @@ -522,14 +564,21 @@ struct sdhci_host {
322077 @@ -572,6 +621,10 @@ struct sdhci_host {
322088 @@ -610,6 +663,9 @@ struct sdhci_ops {
322098 diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
322100 --- a/drivers/mtd/Makefile
322102 @@ -32,7 +32,8 @@ obj-$(CONFIG_MTD_SWAP) += mtdswap.o
322103 nftl-objs := nftlcore.o nftlmount.o
322104 inftl-objs := inftlcore.o inftlmount.o
322106 -obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/
322108 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
322109 +obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/
322111 obj-$(CONFIG_MTD_UBI) += ubi/
322112 diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
322114 --- a/drivers/mtd/nand/Kconfig
322116 @@ -3,5 +3,29 @@ config MTD_NAND_CORE
322146 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
322148 --- a/drivers/mtd/nand/Makefile
322150 @@ -1,6 +1,8 @@
322151 # SPDX-License-Identifier: GPL-2.0
322153 nandcore-objs := core.o bbt.o
322154 +obj-$(CONFIG_MTD_NAND_HIFMC100) += hifmc100_nand/
322155 +obj-$(CONFIG_MTD_SPI_NAND_HIFMC100) += hifmc100/
322156 obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
322158 obj-y += onenand/
322159 diff --git a/drivers/mtd/nand/hifmc100/Kconfig b/drivers/mtd/nand/hifmc100/Kconfig
322162 --- /dev/null
322164 @@ -0,0 +1,17 @@
322182 diff --git a/drivers/mtd/nand/hifmc100/Makefile b/drivers/mtd/nand/hifmc100/Makefile
322185 --- /dev/null
322187 @@ -0,0 +1,26 @@
322191 +# Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
322212 +obj-y += hifmc_spi_nand_ids.o
322213 +obj-y += hifmc100.o hifmc100_os.o
322214 diff --git a/drivers/mtd/nand/hifmc100/hifmc100.c b/drivers/mtd/nand/hifmc100/hifmc100.c
322217 --- /dev/null
322219 @@ -0,0 +1,1218 @@
322278 + struct hifmc_spi *spi = host->spi;
322281 + clk_prepare_enable(host->clk);
322284 + clkrate = min((u_long)host->clkrate,
322285 + (u_long)CLK_FMC_TO_CRG_MHZ(spi->write->clock));
322288 + clkrate = min((u_long)host->clkrate,
322289 + (u_long)CLK_FMC_TO_CRG_MHZ(spi->read->clock));
322292 + clkrate = min((u_long)host->clkrate,
322293 + (u_long)CLK_FMC_TO_CRG_MHZ(spi->erase->clock));
322299 + ret = clk_set_rate(host->clk, clkrate);
322310 + struct hifmc_spi *spi = host->spi;
322311 + struct nand_chip *chip = host->chip;
322321 + FMC_PR(WR_DBG, "*-Start send %s page write command\n", op);
322323 + mutex_lock(host->lock);
322326 + ret = spi->driver->wait_ready(spi);
322333 + ret = spi->driver->write_enable(spi);
322342 + FMC_PR(WR_DBG, "|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
322344 + reg = OP_CFG_FM_CS(host->cmd_op.cs)
322345 + | OP_CFG_MEM_IF_TYPE(spi->write->iftype)
322348 + FMC_PR(WR_DBG, "|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
322350 + pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
322351 + block_num = host->addr_value[1] >> pages_per_block_shift;
322355 + FMC_PR(WR_DBG, "|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
322357 + page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
322361 + FMC_PR(WR_DBG, "|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
322363 + *host->epm = 0x0000;
322366 + reg = host->dma_buffer;
322368 + FMC_PR(WR_DBG, "|-Set DMA_SADDR_D[0x40]%#x\n", reg);
322371 + reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
322373 + FMC_PR(WR_DBG, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
322376 + reg = host->dma_oob;
322378 + FMC_PR(WR_DBG, "|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg);
322380 + reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
322382 + FMC_PR(WR_DBG, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
322387 + reg = OP_CTRL_WR_OPCODE(spi->write->cmd)
322396 + FMC_PR(WR_DBG, "|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
322401 + mutex_unlock(host->lock);
322402 + FMC_PR(WR_DBG, "*-End %s page program!\n", op);
322412 + if(host == NULL || host->spi == NULL) {
322413 + DB_MSG("Error: host or host->spi is NULL!\n");
322416 + spi = host->spi;
322417 + if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
322424 + FMC_PR((ER_DBG || WR_DBG), "\t*-Get status[%#x]: %#x\n", addr, status);
322431 + struct hifmc_spi *spi = host->spi;
322432 + struct nand_chip *chip = host->chip;
322443 + FMC_PR(RD_DBG, "\t*-Start %s page read\n", op);
322445 + if ((host->addr_value[0] == host->cache_addr_value[0])
322446 + && (host->addr_value[1] == host->cache_addr_value[1])) {
322447 + FMC_PR(RD_DBG, "\t*-%s read cache hit, addr[%#x %#x]\n",
322448 + op, host->addr_value[1], host->addr_value[0]);
322452 + mutex_lock(host->lock);
322455 + FMC_PR(RD_DBG, "\t|-Wait ready before %s page read\n", op);
322456 + ret = spi->driver->wait_ready(spi);
322464 + FMC_PR(RD_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
322466 + if (host->cmd_op.l_cmd == NAND_CMD_READOOB)
322467 + host->cmd_op.op_cfg = OP_CTRL_RD_OP_SEL(RD_OP_READ_OOB);
322469 + host->cmd_op.op_cfg = OP_CTRL_RD_OP_SEL(RD_OP_READ_ALL_PAGE);
322471 + reg = OP_CFG_FM_CS(host->cmd_op.cs)
322472 + | OP_CFG_MEM_IF_TYPE(spi->read->iftype)
322473 + | OP_CFG_DUMMY_NUM(spi->read->dummy)
322476 + FMC_PR(RD_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
322478 + pages_per_block_shift = chip->phys_erase_shift - chip->page_shift;
322479 + block_num = host->addr_value[1] >> pages_per_block_shift;
322484 + FMC_PR(RD_DBG, "\t|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
322486 + page_num = host->addr_value[1] - (block_num << pages_per_block_shift);
322490 + FMC_PR(RD_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
322493 + reg = host->dma_buffer;
322495 + FMC_PR(RD_DBG, "\t|-Set DMA_SADDR_D0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
322498 + reg = (host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32;
322500 + FMC_PR(RD_DBG, "\t|-Set DMA_SADDRH_D0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
322503 + reg = host->dma_oob;
322505 + FMC_PR(RD_DBG, "\t|-Set DMA_SADDR_OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB,
322509 + reg = (host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32;
322511 + FMC_PR(RD_DBG, "\t|-Set DMA_SADDRH_OOB[%#x]%#x\n", FMC_DMA_SADDRH_OOB,
322516 + reg = OP_CTRL_RD_OPCODE(spi->read->cmd) | host->cmd_op.op_cfg
322524 + FMC_PR(RD_DBG, "\t|-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
322528 + host->cache_addr_value[0] = host->addr_value[0];
322529 + host->cache_addr_value[1] = host->addr_value[1];
322532 + mutex_unlock(host->lock);
322533 + FMC_PR(RD_DBG, "\t*-End %s page read\n", op);
322539 + struct hifmc_spi *spi = host->spi;
322545 + FMC_PR(ER_DBG, "\t*-Start send cmd erase!\n");
322547 + mutex_lock(host->lock);
322550 + ret = spi->driver->wait_ready(spi);
322551 + FMC_PR(ER_DBG, "\t|-Erase wait ready, ret: %#x\n", ret);
322557 + ret = spi->driver->write_enable(spi);
322565 + FMC_PR(ER_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
322567 + reg = spi->erase->cmd;
322569 + FMC_PR(ER_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
322571 + reg = FMC_ADDRL_BLOCK_H_MASK(host->addr_value[1])
322572 + | FMC_ADDRL_BLOCK_L_MASK(host->addr_value[0]);
322574 + FMC_PR(ER_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
322576 + reg = OP_CFG_FM_CS(host->cmd_op.cs)
322577 + | OP_CFG_MEM_IF_TYPE(spi->erase->iftype)
322579 + | OP_CFG_DUMMY_NUM(spi->erase->dummy)
322582 + FMC_PR(ER_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
322588 + FMC_PR(ER_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg);
322593 + mutex_unlock(host->lock);
322594 + FMC_PR(ER_DBG, "\t*-End send cmd erase!\n");
322608 + FMC_PR(EC_DBG, "\t *-Get CFG[%#x]%#x\n", FMC_CFG, config);
322611 + cmp_cfg = host->fmc_cfg;
322613 + cmp_cfg = host->fmc_cfg_ecc0;
322625 + config = host->fmc_cfg_ecc0;
322627 + config = host->fmc_cfg;
322634 + FMC_PR(EC_DBG, "\t *-Set CFG[%#x]%#x\n", FMC_CFG, config);
322641 + FMC_PR(BT_DBG, "\t|*-Start send cmd read ID\n");
322647 + FMC_PR(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
322651 + FMC_PR(BT_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
322653 + reg = OP_CFG_FM_CS(host->cmd_op.cs)
322657 + FMC_PR(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
322661 + FMC_PR(BT_DBG, "\t||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
322668 + FMC_PR(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
322670 + host->addr_cycle = 0x0;
322676 + FMC_PR(BT_DBG, "\t|*-End read flash ID\n");
322683 + FMC_PR(BT_DBG, "\t|*-Start send cmd reset\n");
322687 + FMC_PR(BT_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
322689 + reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
322691 + FMC_PR(BT_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
322695 + FMC_PR(BT_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
322699 + FMC_PR(BT_DBG, "\t|*-End send cmd reset\n");
322706 + FMC_PR(BT_DBG, "\t||*-Start SPI Nand host init\n");
322712 + FMC_PR(BT_DBG, "\t|||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
322715 + host->fmc_cfg = reg;
322716 + host->fmc_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
322724 + host->addr_cycle = 0;
322725 + host->addr_value[0] = 0;
322726 + host->addr_value[1] = 0;
322727 + host->cache_addr_value[0] = ~0;
322728 + host->cache_addr_value[1] = ~0;
322730 + host->send_cmd_write = hifmc100_send_cmd_write;
322731 + host->send_cmd_status = hifmc100_send_cmd_status;
322732 + host->send_cmd_read = hifmc100_send_cmd_read;
322733 + host->send_cmd_erase = hifmc100_send_cmd_erase;
322734 + host->send_cmd_readid = hifmc100_send_cmd_readid;
322735 + host->send_cmd_reset = hifmc100_send_cmd_reset;
322737 + host->suspend = hifmc100_suspend;
322738 + host->resume = hifmc100_resume;
322749 + FMC_PR(BT_DBG, "\t||*-End SPI Nand host init\n");
322755 + struct hifmc_host *host = chip->priv;
322759 + if (host->cmd_op.l_cmd == NAND_CMD_READID) {
322760 + value = hifmc_readb(host->iobase + host->offset);
322761 + host->offset++;
322762 + if (host->cmd_op.data_no == host->offset) {
322763 + host->cmd_op.l_cmd = 0;
322768 + if (host->cmd_op.cmd == NAND_CMD_STATUS) {
322770 + if (host->cmd_op.l_cmd == NAND_CMD_GET_FEATURES) {
322777 + host->cmd_op.l_cmd = NAND_CMD_STATUS;
322797 + if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
322798 + value = hifmc_readb(host->buffer + host->pagesize + host->offset);
322799 + host->offset++;
322803 + host->offset++;
322805 + return hifmc_readb(host->buffer + host->column + host->offset - 1);
322811 + struct hifmc_host *host = chip->priv;
322813 + host->offset += 2;
322814 + return hifmc_readw(host->buffer + host->column + host->offset - 2);
322821 + struct hifmc_host *host = chip->priv;
322824 + if (buf == chip->oob_poi) {
322825 + memcpy((char *)host->iobase + host->pagesize, buf, len);
322827 + memcpy((char *)host->iobase, buf, len);
322830 + if (buf == chip->oob_poi) {
322831 + memcpy((char *)(host->buffer + host->pagesize), buf, len);
322833 + memcpy((char *)host->buffer, buf, len);
322842 + struct hifmc_host *host = chip->priv;
322845 + if (buf == chip->oob_poi) {
322846 + memcpy(buf, (char *)host->iobase + host->pagesize, len);
322848 + memcpy(buf, (char *)host->iobase, len);
322851 + if (buf == chip->oob_poi) {
322852 + memcpy(buf, (char *)host->buffer + host->pagesize, len);
322854 + memcpy(buf, (char *)host->buffer, len);
322859 + if (buf != chip->oob_poi) {
322861 + u_int ecc_step = host->pagesize >> 10;
322867 + err_num = GET_ECC_ERR_NUM(--ecc_step, reg);
322869 + mtd->ecc_stats.failed++;
322871 + mtd->ecc_stats.corrected += err_num;
322883 + struct hifmc_host *host = chip->priv;
322896 + if (host->mtd != mtd) {
322897 + host->mtd = mtd;
322898 + host->cmd_op.cs = chipselect;
322901 + if (!(chip->options & NAND_BROKEN_XD)) {
322902 + if ((chip->state == FL_ERASING) || (chip->state == FL_WRITING)) {
322903 + host->cmd_op.l_cmd = NAND_CMD_GET_FEATURES;
322913 + struct hifmc_host *host = chip->priv;
322921 + host->addr_cycle = 0x0;
322922 + host->addr_value[0] = 0x0;
322923 + host->addr_value[1] = 0x0;
322925 + addr_offset = host->addr_cycle << 3;
322927 + if (host->addr_cycle >= HIFMC100_ADDR_CYCLE_MASK) {
322928 + addr_offset = (host->addr_cycle -
322932 + host->addr_value[addr_value] |=
322935 + host->addr_cycle++;
322940 + host->cmd_op.cmd = cmd;
322943 + host->offset = 0;
322944 + host->send_cmd_write(host);
322949 + if (host->addr_value[0] == host->pagesize) {
322950 + host->cmd_op.l_cmd = NAND_CMD_READOOB;
322952 + host->send_cmd_read(host);
322956 + host->send_cmd_erase(host);
322960 + memset((u_char *)(host->iobase), 0,
322962 + host->cmd_op.l_cmd = cmd;
322963 + host->cmd_op.data_no = MAX_SPI_NAND_ID_LEN;
322964 + host->send_cmd_readid(host);
322968 + host->send_cmd_status(host);
322972 + host->cmd_op.l_cmd = cmd;
322976 + host->send_cmd_reset(host);
322986 + if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
322987 + if (host->cmd_op.cmd == NAND_CMD_SEQIN
322988 + || host->cmd_op.cmd == NAND_CMD_READ0
322989 + || host->cmd_op.cmd == NAND_CMD_READID) {
322990 + host->offset = 0x0;
322991 + host->column = (host->addr_value[0] & 0xffff);
322996 + host->cache_addr_value[0] = ~0;
322997 + host->cache_addr_value[1] = ~0;
323006 + struct hifmc_host *host = chip->priv;
323009 + reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
323026 + if (!(chip->options & NAND_SCAN_SILENT_NODEV)) {
323034 + * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
323041 + return -ERANGE;
323044 + oobregion->length = 32;
323045 + oobregion->offset = 32;
323054 + return -ERANGE;
323057 + oobregion->length = 30;
323058 + oobregion->offset = 2;
323073 + return -ERANGE;
323076 + oobregion->length = 14;
323077 + oobregion->offset = 14;
323086 + return -ERANGE;
323089 + oobregion->length = 14;
323090 + oobregion->offset = 2;
323104 + return -ERANGE;
323107 + oobregion->length = 6;
323108 + oobregion->offset = 6;
323117 + return -ERANGE;
323120 + oobregion->length = 6;
323121 + oobregion->offset = 2;
323149 + * Auto-sensed the page size and ecc type value. driver will try each of page
323160 + nand_dev->start_type = "Auto";
323162 + for (; info->ooblayout_ops; info++) {
323163 + if (match_page_type_to_size(info->pagetype) != mtd->writesize) {
323167 + if (mtd->oobsize < info->oobsize) {
323171 + if (!best || (best->ecctype < info->ecctype)) {
323176 + /* All SPI NAND are small-page, SLC */
323177 + chip->bits_per_cell = 1;
323184 + chip->read_byte = hifmc100_read_byte;
323185 + chip->read_word = hifmc100_read_word;
323186 + chip->write_buf = hifmc100_write_buf;
323187 + chip->read_buf = hifmc100_read_buf;
323189 + chip->select_chip = hifmc100_select_chip;
323191 + chip->cmd_ctrl = hifmc100_cmd_ctrl;
323192 + chip->dev_ready = hifmc100_dev_ready;
323194 + chip->chip_delay = FMC_CHIP_DELAY;
323196 + chip->options = NAND_SKIP_BBTSCAN | NAND_BROKEN_XD
323199 + chip->ecc.mode = NAND_ECC_NONE;
323206 + struct hifmc_host *host = chip->priv;
323213 + if (info->ecctype != NAND_ECC_0BIT) {
323214 + mtd->oobsize = info->oobsize;
323217 + host->oobsize = mtd->oobsize;
323218 + nand_dev->oobsize = host->oobsize;
323220 + host->dma_oob = host->dma_buffer + host->pagesize;
323221 + host->bbm = (u_char *)(host->buffer + host->pagesize
323223 + if(info->ooblayout_ops == NULL) {
323224 + DB_MSG("Error: info->ooblayout_ops or is NULL!\n");
323227 + info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
323229 + mtd_set_ooblayout(mtd, info->ooblayout_ops);
323232 + host->epm = (u_short *)(host->buffer + host->pagesize
323236 + if (best->ecctype == NAND_ECC_16BIT) {
323237 + if (host->pagesize == _2K) {
323239 + host->epm = (u_short *)(host->buffer + host->pagesize
323241 + } else if (host->pagesize == _4K) {
323243 + host->epm = (u_short *)(host->buffer + host->pagesize
323257 + host->ecctype = info->ecctype;
323258 + nand_dev->ecctype = host->ecctype;
323260 + return FMC_CFG_ECC_TYPE(match_ecc_type_to_reg(info->ecctype));
323270 + host->pagesize = match_page_type_to_size(info->pagetype);
323272 + return FMC_CFG_PAGE_SIZE(match_page_type_to_reg(info->pagetype));
323287 + mtd = host->mtd;
323292 + host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
323293 + page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
323309 + mtd->erasesize, mtd->writesize);
323330 + host->fmc_cfg = reg_fmc_cfg;
323331 + host->fmc_cfg_ecc0 = (host->fmc_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
323332 + FMC_PR(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
323333 + FMC_CFG, host->fmc_cfg, host->fmc_cfg_ecc0);
323339 + struct hifmc_host *host = chip->priv;
323342 + FMC_PR(BT_DBG, "\t*-Start config Block Page OOB and Ecc\n");
323351 + FMC_PR(BT_DBG, "\t|-%s Config, PageSize %s EccType %s OOBSize %d\n",
323352 + nand_dev->start_type, nand_page_name(type_info->pagetype),
323353 + nand_ecc_name(type_info->ecctype), type_info->oobsize);
323360 + FMC_PR(BT_DBG, "\t*-End config Block Page Oob and Ecc\n");
323369 + if((chip == NULL) || (chip->priv == NULL)) {
323370 + DB_MSG("Error: chip or chip->priv is NULL!\n");
323373 + host = chip->priv;
323374 + FMC_PR(BT_DBG, "\t|*-Start hifmc100 SPI Nand init\n");
323384 + host->chip = chip;
323392 + FMC_PR(BT_DBG, "\t|*-End hifmc100 SPI Nand init\n");
323399 + struct hifmc_spi *spi = host->spi;
323401 + mutex_lock(host->lock);
323404 + ret = spi->driver->wait_ready(spi);
323407 + clk_disable_unprepare(host->clk);
323408 + mutex_unlock(host->lock);
323412 + clk_disable_unprepare(host->clk);
323413 + mutex_unlock(host->lock);
323422 + struct nand_chip *chip = host->chip;
323424 + mutex_lock(host->lock);
323426 + clk_prepare_enable(host->clk);
323428 + for (cs = 0; cs < chip->numchips; cs++) {
323429 + host->send_cmd_reset(host);
323434 + mutex_unlock(host->lock);
323438 diff --git a/drivers/mtd/nand/hifmc100/hifmc100.h b/drivers/mtd/nand/hifmc100/hifmc100.h
323441 --- /dev/null
323443 @@ -0,0 +1,354 @@
323732 + /* This is maybe an un-aligment address, only for malloc or free */
323798 diff --git a/drivers/mtd/nand/hifmc100/hifmc100_os.c b/drivers/mtd/nand/hifmc100/hifmc100_os.c
323801 --- /dev/null
323803 @@ -0,0 +1,247 @@
323829 +#include <linux/dma-mapping.h>
323843 + struct hifmc_host *host = chip->priv;
323846 + host->send_cmd_reset(host);
323850 + host->offset = 0;
323851 + memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
323852 + host->send_cmd_readid(host);
323853 + nand_maf_id = hifmc_readb(chip->IO_ADDR_R);
323869 + struct hifmc_host *host = chip->priv;
323873 + FMC_PR(BT_DBG, "\t\t*-Current CS(%d) is occupied.\n",
323878 + host->cmd_op.cs = cs;
323881 + return -ENODEV;
323884 + FMC_PR(BT_DBG, "\t\t*-Scan SPI nand flash on CS: %d\n", cs);
323888 + chip_num--;
323892 + result = -ENXIO;
323907 + struct device *dev = &pltdev->dev;
323909 + struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
323911 + FMC_PR(BT_DBG, "\t*-Start SPI Nand flash driver probe\n");
323915 + return -ENXIO;
323922 + return -ENOMEM;
323927 + host->dev = &pltdev->dev;
323929 + host->chip = chip = (struct nand_chip *)&host[1];
323930 + host->mtd = mtd = nand_to_mtd(chip);
323932 + host->regbase = fmc->regbase;
323933 + host->iobase = fmc->iobase;
323934 + host->clk = fmc->clk;
323935 + host->lock = &fmc->lock;
323936 + host->buffer = fmc->buffer;
323937 + host->dma_buffer = fmc->dma_buffer;
323939 + memset((char *)host->iobase, 0xff, fmc->dma_len);
323940 + chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
323942 + chip->priv = host;
323945 + result = clk_prepare_enable(host->clk);
323953 + np = of_get_next_available_child(dev->of_node, NULL);
323958 + mtd->name = np->name;
323959 + mtd->type = MTD_NANDFLASH;
323960 + mtd->priv = chip;
323961 + mtd->owner = THIS_MODULE;
323963 + result = of_property_read_u32(np, "spi-max-frequency", &host->clkrate);
323971 + FMC_PR(BT_DBG, "\t|-Scan SPI Nand failed.\n");
323977 + FMC_PR(BT_DBG, "\t*-End driver probe !!\n");
323981 + result = -ENODEV;
323984 + clk_disable_unprepare(host->clk);
323994 + if (host->clk)
323995 + clk_disable_unprepare(host->clk);
323996 + if (host->mtd)
323997 + nand_release(host->mtd);
324009 + if (host && host->suspend) {
324010 + return (host->suspend)(pltdev, state);
324020 + if (host && host->resume) {
324021 + return (host->resume)(pltdev);
324029 + { .compatible = "hisilicon,hisi-spi-nand" },
324051 diff --git a/drivers/mtd/nand/hifmc100/hifmc100_spi_general.c b/drivers/mtd/nand/hifmc100/hifmc100_…
324054 --- /dev/null
324056 @@ -0,0 +1,313 @@
324089 + return -1;
324091 + host = (struct hifmc_host *)spi->host;
324094 + return -1;
324100 + return -1;
324105 + FMC_PR(SR_DBG, "\t\t|*-Start Get Status\n");
324107 + reg = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
324109 + FMC_PR(SR_DBG, "\t\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
324113 + FMC_PR(SR_DBG, "\t\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
324118 + FMC_PR(SR_DBG, "\t\t|*-End Get Status, result: %#x\n", *val);
324123 + FMC_PR(FT_DBG, "\t|||*-Start %s feature, addr[%#x]\n", str[op], addr);
324129 + FMC_PR(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
324132 + FMC_PR(FT_DBG, "\t||||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, addr);
324134 + reg = OP_CFG_FM_CS(host->cmd_op.cs)
324138 + FMC_PR(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
324142 + FMC_PR(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
324149 + if (!val || !host->iobase) {
324150 + DB_MSG("Error: host->iobase is NULL !\n");
324151 + return -1;
324154 + hifmc_writeb(*val, host->iobase);
324155 + FMC_PR(FT_DBG, "\t||||-Write IO[%#lx]%#x\n", (long)host->iobase,
324156 + *(u_char *)host->iobase);
324162 + FMC_PR(FT_DBG, "\t||||-Set OP[%#x]%#x\n", FMC_OP, reg);
324167 + if (!val || !host->iobase) {
324168 + DB_MSG("Error: val or host->iobase is NULL !\n");
324169 + return -1;
324171 + *val = hifmc_readb(host->iobase);
324172 + FMC_PR(FT_DBG, "\t||||-Read IO[%#lx]%#x\n", (long)host->iobase,
324173 + *(u_char *)host->iobase);
324178 + FMC_PR(FT_DBG, "\t|||*-End %s Feature[%#x]:%#x\n", str[op], addr, *val);
324193 + if(spi == NULL || spi->host == NULL) {
324194 + DB_MSG("Error: host or host->spi is NULL!\n");
324195 + return -1;
324197 + host = (struct hifmc_host *)spi->host;
324202 + return -1;
324204 + if ((host->cmd_op.l_cmd == NAND_CMD_ERASE2)
324208 + if ((host->cmd_op.l_cmd == NAND_CMD_PAGEPROG)
324232 + if(spi == NULL || spi->host == NULL) {
324233 + DB_MSG("Error: host or host->spi is NULL!\n");
324234 + return -1;
324236 + host = spi->host;
324240 + FMC_PR(WE_DBG, "\t|*-Start Write Enable\n");
324244 + return -1;
324246 + FMC_PR(WE_DBG, "\t||-Write Enable was opened! reg: %#x\n",
324252 + FMC_PR(WE_DBG, "\t||-Get GLOBAL_CFG[%#x]%#x\n", FMC_GLOBAL_CFG, regl);
324256 + FMC_PR(WE_DBG, "\t||-Set GLOBAL_CFG[%#x]%#x\n",
324262 + FMC_PR(WE_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, regl);
324264 + regl = OP_CFG_FM_CS(host->cmd_op.cs) | OP_CFG_OEN_EN;
324266 + FMC_PR(WE_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regl);
324270 + FMC_PR(WE_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, regl);
324275 + if(!spi->driver) {
324276 + DB_MSG("Error: spi->driver is NULL!\n");
324277 + return -1;
324279 + spi->driver->wait_ready(spi);
324283 + return -1;
324285 + FMC_PR(WE_DBG, "\t||-Write Enable success. reg: %#x\n", reg);
324292 + FMC_PR(WE_DBG, "\t|*-End Write Enable\n");
324302 + FMC_PR(QE_DBG, "\t\t|||*-SPI read iftype: %s write iftype: %s\n",
324303 + if_str[spi->read->iftype], if_str[spi->write->iftype]);
324305 + if ((spi->read->iftype == IF_TYPE_QUAD)
324306 + || (spi->read->iftype == IF_TYPE_QIO)
324307 + || (spi->write->iftype == IF_TYPE_QUAD)
324308 + || (spi->write->iftype == IF_TYPE_QIO)) {
324325 + if(!spi || !spi->host || !spi->driver) {
324326 + DB_MSG("Error: host or spi->host or spi->driver is NULL!\n");
324327 + return -1;
324329 + FMC_PR(QE_DBG, "\t||*-Start SPI Nand flash QE\n");
324333 + FMC_PR(QE_DBG, "\t|||*-End Quad check, SPI Nand %s Quad.\n", str[op]);
324337 + return -1;
324338 + FMC_PR(QE_DBG, "\t|||-Get [%#x]feature: %#x\n", FEATURE_ADDR, reg);
324340 + FMC_PR(QE_DBG, "\t||*-SPI Nand quad was %sd!\n", str[op]);
324352 + return -1;
324353 + FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad\n", str[op]);
324355 + spi->driver->wait_ready(spi);
324359 + return -1;
324361 + FMC_PR(QE_DBG, "\t|||-SPI Nand %s Quad succeed!\n", str[op]);
324366 + FMC_PR(QE_DBG, "\t||*-End SPI Nand %s Quad.\n", str[op]);
324370 diff --git a/drivers/mtd/nand/hifmc100/hifmc_spi_nand_ids.c b/drivers/mtd/nand/hifmc100/hifmc_spi_n…
324373 --- /dev/null
324375 @@ -0,0 +1,2457 @@
324513 + * MXIC MX35LF2GE4AB 256MB (SOP-16Pin)
324515 + * 1.6 All-flash AFS1GQ4UAC 128MB Add 1 chip
324518 + * 1.8 ALL-flash AFS2GQ4UAD 256MB Add 2 chip
324537 + * 2.7 Dosilicon DS35Q1GA-IB 128MB Add 2 chip
324538 + * Dosilicon DS35Q2GA-IB 256MB
324542 + * Etron 1.8V EM78D044VCF-H 256MB
324543 + * Etron 3.3V EM73C044VCC-H 128MB
324546 + * FM FM25S01-DND-A-G 128MB 3.3V
324792 + /* ESMT F50L1G41LB-104YG2ME 1Gbit */
324794 + .name = "F50L1G41LB-104YG2ME",
325521 + /* MXIC MX35LF2GE4AB 2Gbit SOP-16Pin */
325667 + /* All-flash AFS1GQ4UAC 1Gbit */
325698 + /* All-flash AFS2GQ4UAD 2Gbit */
326191 + /* Dosilicon 3.3V DS35Q1GA-IB 1Gbit */
326193 + .name = "DS35Q1GA-IB",
326251 + /* Etron 1.8V EM78F044VCA-H 8Gbit */
326253 + .name = "EM78F044VCA-H",
326282 + /* Etron 1.8V EM78E044VCA-H 4Gbit */
326284 + .name = "EM78E044VCA-H",
326313 + /* Etron 1.8V EM78D044VCF-H 2Gbit */
326315 + .name = "EM78D044VCF-H",
326344 + /* Etron 3.3V EM73C044VCC-H 1Gbit */
326346 + .name = "EM73C044VCC-H",
326404 + /* Dosilicon 3.3V DS35Q2GA-IB 1Gb */
326406 + .name = "DS35Q2GA-IB",
326433 + /* FM 3.3v FM25S01-DND-A-G 1Gbit */
326435 + .name = "FM25S01-DND-A-G",
326505 + for (fitspiop = spiop = (rw_type ? spiinfo->write : spiinfo->read);
326507 + if (((*spiop)->iftype & iftype)
326508 + && ((*spiop)->dummy <= max_dummy)
326509 + && (*fitspiop)->iftype < (*spiop)->iftype) {
326522 + spiop_erase->size = 0;
326524 + if (spiinfo->erase[ix] == NULL) {
326527 + if (spiinfo->erasesize == spiinfo->erase[ix]->size) {
326528 + memcpy(&spiop_erase[ix], spiinfo->erase[ix],
326555 + FMC_PR(BT_DBG, "\t||*-Start Get SPI operation iftype\n");
326558 + if (spi->write->iftype == iftype_write[ix]) {
326559 + spi->write->iftype = iftype_write[ix + 1];
326563 + FMC_PR(BT_DBG, "\t|||-Get best write iftype: %s \n",
326564 + if_str[spi->write->iftype]);
326567 + if (spi->read->iftype == iftype_read[ix]) {
326568 + spi->read->iftype = iftype_read[ix + 1];
326572 + FMC_PR(BT_DBG, "\t|||-Get best read iftype: %s \n",
326573 + if_str[spi->read->iftype]);
326575 + spi->erase->iftype = IF_TYPE_STD;
326576 + FMC_PR(BT_DBG, "\t|||-Get best erase iftype: %s \n",
326577 + if_str[spi->erase->iftype]);
326579 + FMC_PR(BT_DBG, "\t||*-End Get SPI operation iftype \n");
326597 + if (chip == NULL || chip->priv == NULL) {
326601 + host = chip->priv;
326602 + if (host->spi == NULL) {
326603 + DB_MSG("Error: host->spi is NULL!\n");
326606 + spi = host->spi;
326607 + FMC_PR(BT_DBG, "\t|*-Start match SPI operation & chip init\n");
326609 + spi->host = host;
326610 + spi->name = spi_dev->name;
326611 + spi->driver = spi_dev->driver;
326612 + if(!spi->driver) {
326613 + DB_MSG("Error: host->driver is NULL!\n");
326617 + hifmc100_spi_nand_search_rw(spi_dev, spi->read,
326620 + FMC_PR(BT_DBG, "\t||-Save spi->read op cmd:%#x\n", spi->read->cmd);
326622 + hifmc100_spi_nand_search_rw(spi_dev, spi->write,
326625 + FMC_PR(BT_DBG, "\t||-Save spi->write op cmd:%#x\n", spi->write->cmd);
326627 + hifmc100_spi_nand_get_erase(spi_dev, spi->erase);
326628 + FMC_PR(BT_DBG, "\t||-Save spi->erase op cmd:%#x\n", spi->erase->cmd);
326632 + if (spi->driver->qe_enable) {
326633 + spi->driver->qe_enable(spi);
326640 + FMC_PR(BT_DBG, "\t||-Get protect status[%#x]: %#x\n", PROTECT_ADDR,
326647 + FMC_PR(BT_DBG, "\t||-Set [%#x]FT %#x\n", PROTECT_ADDR, reg);
326649 + spi->driver->wait_ready(spi);
326654 + FMC_PR(BT_DBG, "\t||-Check BP disable result: %#x\n", reg);
326664 + FMC_PR(BT_DBG, "\t||-Get feature status[%#x]: %#x\n", FEATURE_ADDR,
326671 + FMC_PR(BT_DBG, "\t||-Set [%#x]FT: %#x\n", FEATURE_ADDR, reg);
326673 + spi->driver->wait_ready(spi);
326678 + FMC_PR(BT_DBG, "\t||-Check internal ECC disable result: %#x\n",
326685 + hifmc_cs_user[host->cmd_op.cs]++;
326687 + FMC_PR(BT_DBG, "\t|*-End match SPI operation & chip init\n");
326699 + struct hifmc_host *host = chip->priv;
326703 + FMC_PR(BT_DBG, "\t*-Start find SPI Nand flash\n");
326706 + host->cmd_op.cs, id[0], id[1]);
326708 + for (; spi_dev->id_len; spi_dev++) {
326709 + if (!access_ok(VERIFY_READ, id, spi_dev->id_len)) {
326713 + if (memcmp(id, spi_dev->id, spi_dev->id_len)) {
326717 + for (ix = 2; ix < spi_dev->id_len; ix++) {
326718 + if((spi_dev->id_len <= MAX_SPI_NAND_ID_LEN)) {
326724 + FMC_PR(BT_DBG, "\t||-CS(%d) found SPI Nand: %s\n",
326725 + host->cmd_op.cs, spi_dev->name);
326727 + type->name = spi_dev->name;
326728 + memcpy(type->id, spi_dev->id, spi_dev->id_len);
326729 + type->pagesize = spi_dev->pagesize;
326730 + type->chipsize = (unsigned int)(spi_dev->chipsize >> 20);
326731 + type->erasesize = spi_dev->erasesize;
326732 + type->id_len = spi_dev->id_len;
326733 + type->oobsize = spi_dev->oobsize;
326734 + FMC_PR(BT_DBG, "\t|-Save struct nand_flash_dev info\n");
326736 + mtd->oobsize = spi_dev->oobsize;
326737 + mtd->erasesize = spi_dev->erasesize;
326738 + mtd->writesize = spi_dev->pagesize;
326739 + chip->chipsize = spi_dev->chipsize;
326743 + FMC_PR(BT_DBG, "\t*-Found SPI nand: %s\n", spi_dev->name);
326748 + FMC_PR(BT_DBG, "\t*-Not found SPI nand flash, %s\n", buffer);
326769 + if((host == NULL) || (host->spi == NULL)) {
326770 + DB_MSG("Error: host or host->spi is NULL!\n");
326773 + spi = host->spi;
326775 + FMC_PR(PM_DBG, "\t|-SPI read iftype: %s write iftype: %s\n",
326776 + str[spi->read->iftype], str[spi->write->iftype]);
326778 + if (spi->driver->qe_enable) {
326779 + spi->driver->qe_enable(spi);
326786 + FMC_PR(PM_DBG, "\t|-Get protect status[%#x]: %#x\n", PROTECT_ADDR,
326793 + FMC_PR(PM_DBG, "\t|-Set [%#x]FT %#x\n", PROTECT_ADDR, reg);
326795 + spi->driver->wait_ready(spi);
326800 + FMC_PR(PM_DBG, "\t|-Check BP disable result: %#x\n", reg);
326810 + FMC_PR(PM_DBG, "\t|-Get feature status[%#x]: %#x\n", FEATURE_ADDR,
326817 + FMC_PR(PM_DBG, "\t|-Set [%#x]FT: %#x\n", FEATURE_ADDR, reg);
326819 + spi->driver->wait_ready(spi);
326824 + FMC_PR(PM_DBG, "\t|-Check internal ECC disable result: %#x\n",
326833 diff --git a/drivers/mtd/nand/hifmc100_nand/Kconfig b/drivers/mtd/nand/hifmc100_nand/Kconfig
326836 --- /dev/null
326838 @@ -0,0 +1,50 @@
326889 diff --git a/drivers/mtd/nand/hifmc100_nand/Makefile b/drivers/mtd/nand/hifmc100_nand/Makefile
326892 --- /dev/null
326894 @@ -0,0 +1,26 @@
326919 +obj-y += hifmc_nand_spl_ids.o
326920 +obj-y += hifmc100_nand.o hifmc100_nand_os.o
326921 diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.c b/drivers/mtd/nand/hifmc100_nand/hifmc1…
326924 --- /dev/null
326926 @@ -0,0 +1,1170 @@
326962 + unsigned int reg = (unsigned int)host->dma_buffer;
326965 + FMC_PR(DMA_DB, "\t\t *-Start %s page dma transfer\n", op);
326968 + FMC_PR(DMA_DB, "\t\t |-Set ADDR0[%#x]%#x\n", FMC_DMA_SADDR_D0, reg);
326971 + reg = (unsigned int)((host->dma_buffer & FMC_DMA_SADDRH_MASK) >> 32);
326973 + FMC_PR(DMA_DB, "\t\t |-Set ADDRH0[%#x]%#x\n", FMC_DMA_SADDRH_D0, reg);
326978 + FMC_PR(DMA_DB, "\t\t |-Set ADDR1[%#x]%#x\n", FMC_DMA_SADDR_D1, reg);
326982 + FMC_PR(DMA_DB, "\t\t |-Set ADDR2[%#x]%#x\n", FMC_DMA_SADDR_D2, reg);
326986 + FMC_PR(DMA_DB, "\t\t |-Set ADDR3[%#x]%#x\n", FMC_DMA_SADDR_D3, reg);
326988 + reg = host->dma_oob;
326990 + FMC_PR(DMA_DB, "\t\t |-Set OOB[%#x]%#x\n", FMC_DMA_SADDR_OOB, reg);
326993 + reg = (unsigned int)((host->dma_oob & FMC_DMA_SADDRH_MASK) >> 32);
326995 + FMC_PR(DMA_DB, "\t\t |-Set ADDRH0[%#x]%#x\n", FMC_DMA_SADDRH_OOB, reg);
326998 + if (host->ecctype == NAND_ECC_0BIT) {
326999 + hifmc_writel(host, FMC_DMA_LEN, FMC_DMA_LEN_SET(host->oobsize));
327000 + FMC_PR(DMA_DB, "\t\t |-Set LEN[%#x]%#x\n", FMC_DMA_LEN, reg);
327004 + FMC_PR(DMA_DB, "\t\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
327011 + FMC_PR(DMA_DB, "\t\t |-Set AHBCTRL[%#x]%#x\n", FMC_DMA_AHB_CTRL, reg);
327013 + reg = OP_CFG_FM_CS(host->cmd_op.cs) |
327014 + OP_CFG_ADDR_NUM(host->addr_cycle);
327016 + FMC_PR(DMA_DB, "\t\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
327023 + FMC_PR(DMA_DB, "\t\t |-Set OP_CTRL[%#x]%#x\n", FMC_OP_CTRL, reg);
327027 + FMC_PR(DMA_DB, "\t\t *-End %s page dma transfer\n", op);
327037 + FMC_PR(WR_DBG, "\t|*-Start send page programme cmd\n");
327039 + if (*host->bbm != 0xFF && *host->bbm != 0x00) {
327042 + GET_PAGE_INDEX(host), *host->bbm);
327045 + host->enable_ecc_randomizer(host, ENABLE, ENABLE);
327047 + reg = host->addr_value[1];
327049 + FMC_PR(WR_DBG, "\t||-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
327051 + reg = host->addr_value[0] & 0xffff0000;
327053 + FMC_PR(WR_DBG, "\t||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
327057 + FMC_PR(WR_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
327059 + *host->epm = 0x0000;
327063 + FMC_PR(WR_DBG, "\t|*-End send page read cmd\n");
327071 + FMC_PR(RD_DBG, "\t*-Start send page read cmd\n");
327073 + if ((host->addr_value[0] == host->cache_addr_value[0]) &&
327074 + (host->addr_value[1] == host->cache_addr_value[1])) {
327075 + FMC_PR(RD_DBG, "\t*-Cache hit! addr1[%#x], addr0[%#x]\n",
327076 + host->addr_value[1], host->addr_value[0]);
327080 + host->page_status = 0;
327082 + host->enable_ecc_randomizer(host, ENABLE, ENABLE);
327086 + FMC_PR(RD_DBG, "\t|-Set INT_CLR[%#x]%#x\n", FMC_INT_CLR, reg);
327088 + reg = host->nand_cfg;
327090 + FMC_PR(RD_DBG, "\t|-Set CFG[%#x]%#x\n", FMC_CFG, reg);
327092 + reg = host->addr_value[1];
327094 + FMC_PR(RD_DBG, "\t|-Set ADDRH[%#x]%#x\n", FMC_ADDRH, reg);
327096 + reg = host->addr_value[0] & 0xffff0000;
327098 + FMC_PR(RD_DBG, "\t|-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
327102 + FMC_PR(RD_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
327107 + host->page_status |= HIFMC100_PS_UC_ECC;
327110 + host->cache_addr_value[0] = host->addr_value[0];
327111 + host->cache_addr_value[1] = host->addr_value[1];
327113 + FMC_PR(RD_DBG, "\t*-End send page read cmd\n");
327121 + FMC_PR(ER_DBG, "\t *-Start send cmd erase\n");
327124 + host->enable_ecc_randomizer(host, DISABLE, DISABLE);
327126 + reg = host->addr_value[0];
327128 + FMC_PR(ER_DBG, "\t |-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
327132 + FMC_PR(ER_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
327134 + reg = OP_CFG_FM_CS(host->cmd_op.cs) |
327135 + OP_CFG_ADDR_NUM(host->addr_cycle);
327137 + FMC_PR(ER_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
327146 + FMC_PR(ER_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
327150 + FMC_PR(ER_DBG, "\t |*-End send cmd erase\n");
327171 + FMC_PR(EC_DBG, "\t |*-Start %s randomizer\n", rand_op);
327172 + FMC_PR(EC_DBG, "\t ||-Get global CFG[%#x]%#x\n",
327175 + FMC_PR(EC_DBG, "\t ||-Set global CFG[%#x]%#x\n",
327182 + reg = (ecc_en ? host->nand_cfg : host->nand_cfg_ecc0);
327185 + FMC_PR(EC_DBG, "\t |%s-Start %s ECC0 mode\n", change ? "|" : "*",
327187 + FMC_PR(EC_DBG, "\t ||-Get CFG[%#x]%#x\n", FMC_CFG, old_reg);
327189 + FMC_PR(EC_DBG, "\t ||-Set CFG[%#x]%#x\n", FMC_CFG, reg);
327194 + FMC_PR(EC_DBG, "\t |*-End randomizer and ECC0 mode config\n");
327203 + host->enable_ecc_randomizer(host, DISABLE, DISABLE);
327205 + regval = OP_CFG_FM_CS(host->cmd_op.cs);
327219 + FMC_PR(BT_DBG, "\t *-Start read nand flash ID\n");
327221 + host->enable_ecc_randomizer(host, DISABLE, DISABLE);
327223 + reg = FMC_DATA_NUM_CNT(host->cmd_op.data_no);
327225 + FMC_PR(BT_DBG, "\t |-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
327229 + FMC_PR(BT_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
327233 + FMC_PR(BT_DBG, "\t |-Set ADDRL[%#x]%#x\n", FMC_ADDRL, reg);
327235 + reg = OP_CFG_FM_CS(host->cmd_op.cs) |
327238 + FMC_PR(BT_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
327245 + FMC_PR(BT_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
327247 + host->addr_cycle = 0x0;
327251 + FMC_PR(BT_DBG, "\t *-End read nand flash ID\n");
327259 + FMC_PR(BT_DBG, "\t *-Start reset nand flash\n");
327263 + FMC_PR(BT_DBG, "\t |-Set CMD[%#x]%#x\n", FMC_CMD, reg);
327265 + reg = OP_CFG_FM_CS(host->cmd_op.cs);
327267 + FMC_PR(BT_DBG, "\t |-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
327273 + FMC_PR(BT_DBG, "\t |-Set OP[%#x]%#x\n", FMC_OP, reg);
327277 + FMC_PR(BT_DBG, "\t *-End reset nand flash\n");
327285 + struct hifmc_host *host = chip->priv;
327287 + if (host->cmd_op.l_cmd == NAND_CMD_READID) {
327288 + value = hifmc_readb((void __iomem *)(chip->IO_ADDR_R + host->offset));
327289 + host->offset++;
327290 + if (host->cmd_op.data_no == host->offset) {
327291 + host->cmd_op.l_cmd = 0;
327296 + if (host->cmd_op.cmd == NAND_CMD_STATUS) {
327298 + if (host->cmd_op.l_cmd == NAND_CMD_ERASE1) {
327299 + FMC_PR(ER_DBG, "\t*-Erase WP status: %#x\n", value);
327301 + if (host->cmd_op.l_cmd == NAND_CMD_PAGEPROG) {
327302 + FMC_PR(WR_DBG, "\t*-Write WP status: %#x\n", value);
327307 + if (host->cmd_op.l_cmd == NAND_CMD_READOOB) {
327308 + value = hifmc_readb((void __iomem *)(host->buffer +
327309 + host->pagesize + host->offset));
327310 + host->offset++;
327314 + host->offset++;
327316 + return hifmc_readb((void __iomem *)(host->buffer + host->column +
327317 + host->offset - 1));
327324 + struct hifmc_host *host = chip->priv;
327326 + host->offset += 2;
327327 + return hifmc_readw(host->buffer + host->column + host->offset - 2);
327335 + struct hifmc_host *host = chip->priv;
327338 + if (buf == chip->oob_poi) {
327339 + memcpy((char *)host->iobase + host->pagesize, buf, len);
327341 + memcpy((char *)host->iobase, buf, len);
327344 + if (buf == chip->oob_poi) {
327345 + memcpy((char *)host->buffer + host->pagesize, buf, len);
327347 + memcpy((char *)host->buffer, buf, len);
327365 + err_num = GET_ECC_ERR_NUM(--ecc_st, reg);
327367 + mtd->ecc_stats.failed++;
327369 + mtd->ecc_stats.corrected += err_num;
327379 + struct hifmc_host *host = chip->priv;
327382 + if (buf == chip->oob_poi) {
327383 + memcpy(buf, (char *)host->iobase + host->pagesize, len);
327385 + memcpy(buf, (char *)host->iobase, len);
327388 + if (buf == chip->oob_poi) {
327389 + memcpy(buf, (char *)host->buffer + host->pagesize, len);
327391 + memcpy(buf, (char *)host->buffer, len);
327396 + if (buf != chip->oob_poi) {
327398 + u_int ecc_step = host->pagesize >> 10;
327400 + /* 2K or 4K or 8K(1) or 16K(1-1) pagesize */
327405 + /* 8K(2) or 16K(1-2) pagesize */
327409 + /* 16K(2-1) pagesize */
327413 + /* 16K(2-2) pagesize */
327429 + struct hifmc_host *host = chip->priv;
327442 + host->cmd_op.cs = chipselect;
327443 + if (host->mtd != mtd) {
327444 + host->mtd = mtd;
327447 + switch (chip->state) {
327449 + host->cmd_op.l_cmd = NAND_CMD_ERASE1;
327453 + FMC_PR(ER_DBG, "\t*-Erase chip: %d\n", chipselect);
327456 + host->cmd_op.l_cmd = NAND_CMD_PAGEPROG;
327460 + FMC_PR(WR_DBG, "\t*-Write chip: %d\n", chipselect);
327463 + host->cmd_op.l_cmd = NAND_CMD_READ0;
327467 + FMC_PR(RD_DBG, "\t*-Read chip: %d\n", chipselect);
327480 + struct hifmc_host *host = chip->priv;
327487 + host->addr_cycle = 0x0;
327488 + host->addr_value[0] = 0x0;
327489 + host->addr_value[1] = 0x0;
327491 + addr_offset = host->addr_cycle << 3;
327493 + if (host->addr_cycle >= HIFMC100_ADDR_CYCLE_MASK) {
327494 + addr_offset = (host->addr_cycle -
327499 + host->addr_value[addr_value] |=
327502 + host->addr_cycle++;
327507 + host->cmd_op.cmd = cmd;
327510 + host->offset = 0;
327511 + host->send_cmd_pageprog(host);
327516 + if (host->addr_value[0] == host->pagesize) {
327517 + host->cmd_op.l_cmd = NAND_CMD_READOOB;
327519 + host->send_cmd_readstart(host);
327523 + host->cmd_op.l_cmd = cmd;
327524 + host->send_cmd_erase(host);
327528 + memset((u_char *)(chip->IO_ADDR_R), 0, MAX_NAND_ID_LEN);
327529 + host->cmd_op.l_cmd = cmd;
327530 + host->cmd_op.data_no = MAX_NAND_ID_LEN;
327531 + host->send_cmd_readid(host);
327535 + host->send_cmd_status(host);
327539 + host->cmd_op.l_cmd = cmd;
327543 + host->send_cmd_reset(host);
327554 + host->enable_ecc_randomizer(host, ENABLE, ENABLE);
327556 + if ((dat == NAND_CMD_NONE) && host->addr_cycle) {
327557 + if (host->cmd_op.cmd == NAND_CMD_SEQIN ||
327558 + host->cmd_op.cmd == NAND_CMD_READ0 ||
327559 + host->cmd_op.cmd == NAND_CMD_READID) {
327560 + host->offset = 0x0;
327561 + host->column = (host->addr_value[0] & 0xffff);
327566 + host->cache_addr_value[0] = ~0;
327567 + host->cache_addr_value[1] = ~0;
327579 + * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
327585 + return -ERANGE;
327588 + oobregion->length = 32;
327589 + oobregion->offset = 32;
327598 + return -ERANGE;
327601 + oobregion->length = 30;
327602 + oobregion->offset = 2;
327617 + return -ERANGE;
327620 + oobregion->length = 14;
327621 + oobregion->offset = 14;
327630 + return -ERANGE;
327633 + oobregion->length = 14;
327634 + oobregion->offset = 2;
327647 + return -ERANGE;
327650 + oobregion->length = 6;
327651 + oobregion->offset = 6;
327660 + return -ERANGE;
327663 + oobregion->length = 6;
327664 + oobregion->offset = 2;
327705 + * 0 - This NAND NOT support randomizer
327706 + * 1 - This NAND support randomizer.
327729 + struct hifmc_host *host = chip->priv;
327732 + nand_dev->start_type = "Auto";
327733 + nand_dev->flags |= (IS_NANDC_HW_AUTO(host) | IS_NANDC_CONFIG_DONE(host));
327735 + for (; info->ooblayout_ops; info++) {
327736 + if (match_page_type_to_size(info->pagetype) != mtd->writesize) {
327740 + if (mtd->oobsize < info->oobsize) {
327744 + if (!best || (best->ecctype < info->ecctype)) {
327756 + host->ecctype = info->ecctype;
327757 + FMC_PR(BT_DBG, "\t |-Save best EccType %d(%s)\n", host->ecctype,
327758 + match_ecc_type_to_str(info->ecctype));
327760 + nand_dev->ecctype = host->ecctype;
327762 + return FMC_CFG_ECC_TYPE(match_ecc_type_to_reg(info->ecctype));
327769 + host->pagesize = match_page_type_to_size(info->pagetype);
327770 + FMC_PR(BT_DBG, "\t |-Save best PageSize %d(%s)\n", host->pagesize,
327771 + match_page_type_to_str(info->pagetype));
327773 + return FMC_CFG_PAGE_SIZE(match_page_type_to_reg(info->pagetype));
327782 + struct mtd_info *mtd = host->mtd;
327784 + host->block_page_mask = ((mtd->erasesize / mtd->writesize) - 1);
327785 + page_per_block = mtd->erasesize / match_page_type_to_size(info->pagetype);
327801 + mtd->erasesize, mtd->writesize);
327817 + if (hifmc100_nand_support_randomizer(host->pagesize, host->ecctype)) {
327818 + host->flags |= IS_NAND_RANDOM(nand_dev);
327826 + !hifmc100_nand_support_randomizer(host->pagesize,
327827 + host->ecctype)) {
327836 + host->nand_cfg = reg_fmc_cfg;
327837 + host->nand_cfg_ecc0 = (host->nand_cfg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
327838 + FMC_PR(BT_DBG, "\t|-Save FMC_CFG[%#x]: %#x and FMC_CFG_ECC0: %#x\n",
327839 + FMC_CFG, host->nand_cfg, host->nand_cfg_ecc0);
327842 + host->enable_ecc_randomizer(host, ENABLE, ENABLE);
327848 + host->read_retry = NULL;
327850 + if (host->read_retry && !IS_NAND_RANDOM(host)) {
327863 + struct hifmc_host *host = chip->priv;
327866 + if (info->ecctype != NAND_ECC_0BIT) {
327867 + mtd->oobsize = info->oobsize;
327869 + mtd->oobavail = HIFMC100_NAND_OOBSIZE_FOR_YAFFS;
327871 + host->oobsize = mtd->oobsize;
327873 + buffer_len = host->pagesize + host->oobsize;
327875 + memset(host->buffer, 0xff, buffer_len);
327876 + host->dma_oob = host->dma_buffer + host->pagesize;
327878 + host->bbm = (unsigned char *)(host->buffer + host->pagesize +
327881 + info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
327883 + mtd_set_ooblayout(mtd, info->ooblayout_ops);
327886 + host->epm = (u_short *)(host->buffer + host->pagesize +
327890 + if (best->ecctype == NAND_ECC_16BIT) {
327891 + if (host->pagesize == _2K) {
327893 + host->epm = (u_short *)(host->buffer + host->pagesize +
327895 + } else if (host->pagesize == _4K) {
327897 + host->epm = (u_short *)(host->buffer + host->pagesize +
327907 + struct hifmc_host *host = chip->priv;
327911 + FMC_PR(BT_DBG, "\t*-Start config Block Page OOB and Ecc\n");
327916 + FMC_PR(BT_DBG, "\t|-%s Config, PageSize %s EccType %s OobSize %d\n",
327917 + nand_dev->start_type, nand_page_name(type_info->pagetype),
327918 + nand_ecc_name(type_info->ecctype), type_info->oobsize);
327925 + if (mtd->writesize > NAND_MAX_PAGESIZE ||
327926 + mtd->oobsize > NAND_MAX_OOBSIZE) {
327933 + if (mtd->writesize != host->pagesize) {
327935 + unsigned int writesize = mtd->writesize;
327937 + while (writesize > host->pagesize) {
327941 + chip->chipsize = chip->chipsize >> shift;
327942 + mtd->erasesize = mtd->erasesize >> shift;
327943 + mtd->writesize = host->pagesize;
327947 + FMC_PR(BT_DBG, "\t*-End config Block Page Oob and Ecc\n");
327955 + struct hifmc_host *host = chip->priv;
327957 + memset((char *)chip->IO_ADDR_R, 0xff, host->dma_len);
327959 + chip->read_byte = hifmc100_read_byte;
327960 + chip->read_word = hifmc100_read_word;
327961 + chip->write_buf = hifmc100_write_buf;
327962 + chip->read_buf = hifmc100_read_buf;
327964 + chip->select_chip = hifmc100_select_chip;
327966 + chip->cmd_ctrl = hifmc100_cmd_ctrl;
327967 + chip->dev_ready = hifmc100_dev_ready;
327969 + chip->chip_delay = FMC_CHIP_DELAY;
327971 + chip->options = NAND_NEED_READRDY | NAND_BROKEN_XD |
327974 + chip->ecc.mode = NAND_ECC_NONE;
327982 + FMC_PR(BT_DBG, "\t *-Start nand host init\n");
327985 + FMC_PR(BT_DBG, "\t |-Read FMC CFG[%#x]%#x\n", FMC_CFG, reg);
327990 + FMC_PR(BT_DBG, "\t |-Change flash type to Nand flash\n");
327995 + FMC_PR(BT_DBG, "\t |-Controller enter normal mode\n");
327998 + FMC_PR(BT_DBG, "\t |-Set CFG[%#x]%#x\n", FMC_CFG, reg);
328000 + host->nand_cfg = reg;
328001 + host->nand_cfg_ecc0 = (reg & ~ECC_TYPE_MASK) | ECC_TYPE_0BIT;
328004 + FMC_PR(BT_DBG, "\t |-Read global CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
328006 + host->flags &= ~NAND_RANDOMIZER;
328007 + FMC_PR(BT_DBG, "\t |-Default disable randomizer\n");
328010 + FMC_PR(BT_DBG, "\t |-Set global CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
328019 + host->addr_cycle = 0;
328020 + host->addr_value[0] = 0;
328021 + host->addr_value[1] = 0;
328022 + host->cache_addr_value[0] = ~0;
328023 + host->cache_addr_value[1] = ~0;
328025 + host->send_cmd_pageprog = hifmc100_send_cmd_write;
328026 + host->send_cmd_status = hifmc100_send_cmd_status;
328027 + host->send_cmd_readstart = hifmc100_send_cmd_read;
328028 + host->send_cmd_erase = hifmc100_send_cmd_erase;
328029 + host->send_cmd_readid = hifmc100_send_cmd_readid;
328030 + host->send_cmd_reset = hifmc100_send_cmd_reset;
328037 + host->flags |= NANDC_HW_AUTO;
328040 + host->flags |= NANDC_CONFIG_DONE;
328041 + FMC_PR(BT_DBG, "\t |-Auto config pagesize and ecctype\n");
328044 + host->enable_ecc_randomizer = hifmc100_ecc_randomizer;
328046 + FMC_PR(BT_DBG, "\t *-End nand host init\n");
328054 + struct hifmc_host *host = chip->priv;
328057 + clk_prepare_enable(host->clk);
328060 + host->version = hifmc_readl(host, FMC_VERSION);
328061 + if (host->version != HIFMC_VER_100) {
328062 + return -EFAULT;
328069 + return -EFAULT;
328071 + host->chip = chip;
328093 + clk_prepare_enable(host->clk);
328094 + FMC_PR(PM_DBG, "\t |-enable system clock\n");
328097 diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand.h b/drivers/mtd/nand/hifmc100_nand/hifmc1…
328100 --- /dev/null
328102 @@ -0,0 +1,151 @@
328182 + /* This is maybe an un-aligment address, only for malloc or free */
328254 diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand_os.c b/drivers/mtd/nand/hifmc100_nand/hif…
328257 --- /dev/null
328259 @@ -0,0 +1,180 @@
328300 + struct device *dev = &pltdev->dev;
328302 + struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
328306 + return -ENXIO;
328313 + return -ENOMEM;
328318 + host->dev = &pltdev->dev;
328319 + host->chip = chip = (struct nand_chip *)&host[1];
328320 + host->mtd = mtd = nand_to_mtd(chip);
328321 + host->regbase = fmc->regbase;
328322 + host->iobase = fmc->iobase;
328323 + host->clk = fmc->clk;
328324 + chip->IO_ADDR_R = chip->IO_ADDR_W = host->iobase;
328325 + host->buffer = fmc->buffer;
328326 + host->dma_buffer = fmc->dma_buffer;
328327 + host->dma_len = fmc->dma_len;
328330 + chip->priv = host;
328337 + np = of_get_next_available_child(dev->of_node, NULL);
328338 + mtd->name = np->name;
328339 + mtd->type = MTD_NANDFLASH;
328340 + mtd->priv = chip;
328341 + mtd->flags = MTD_CAP_NANDFLASH;
328342 + mtd->owner = THIS_MODULE;
328345 + result = -ENXIO;
328349 + result = mtd_device_register(host->mtd, parts, nr_parts);
328355 + return (result == 1) ? -ENODEV : 0;
328358 + clk_disable_unprepare(host->clk);
328367 + clk_disable_unprepare(host->clk);
328368 + nand_release(host->mtd);
328378 + struct device *dev = &pltdev->dev;
328379 + if (!host || !host->clk) {
328380 + dev_err(dev,"host or host->clk is null err\n");
328392 + clk_disable_unprepare(host->clk);
328393 + FMC_PR(PM_DBG, "\t|-disable system clock\n");
328406 + chip = host->chip;
328408 + for (cs = 0; cs < chip->numchips; cs++) {
328409 + host->send_cmd_reset(host);
328440 diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc100_nand_os.h b/drivers/mtd/nand/hifmc100_nand/hif…
328443 --- /dev/null
328445 @@ -0,0 +1,72 @@
328476 +#include <linux/dma-mapping.h>
328518 diff --git a/drivers/mtd/nand/hifmc100_nand/hifmc_nand_spl_ids.c b/drivers/mtd/nand/hifmc100_nand/h…
328521 --- /dev/null
328523 @@ -0,0 +1,982 @@
328590 + type->options = 0;
328591 + type->pagesize = pagesizes[(id[3] & 0x03)];
328592 + type->erasesize = blocksizes[blocktype];
328593 + type->oobsize = oobsizes[oobtype];
328610 + type->options = 0;
328611 + type->pagesize = pagesizes[(id[3] & 0x03)];
328612 + type->erasesize = blocksizes[blocktype];
328613 + type->oobsize = oobsizes[oobtype];
328671 + * MISC | MLC | P1UAGA30AT-GCA | 8bit/512 |
328672 + * MISC | MLC | PSU8GA30AT-GIA/ASU8GA30IT-G30CA | 4bit/512 |
329385 + .name = "P1UAGA30AT-GCA",
329400 + * PowerFlash ASU8GA30IT-G30CA ID and MIRA PSU8GA30AT-GIA ID are
329403 + .name = "PSU8GA30AT-GIA/ASU8GA30IT-G30CA",
329443 + FMC_PR(BT_DBG, "\t *-Start find special nand flash\n");
329448 + for (; spl_dev->length; spl_dev++) {
329449 + if (!access_ok(VERIFY_READ, id, spl_dev->length)) {
329453 + if (memcmp(id, spl_dev->id, spl_dev->length)) {
329457 + FMC_PR(BT_DBG, "\t |-Found special Nand flash: %s\n",
329458 + spl_dev->name);
329460 + if (spl_dev->probe) {
329461 + type = spl_dev->probe(id);
329463 + type->options = spl_dev->options;
329464 + type->pagesize = spl_dev->pagesize;
329465 + type->erasesize = spl_dev->erasesize;
329466 + type->oobsize = spl_dev->oobsize;
329469 + type->name = spl_dev->name;
329470 + type->id_len = spl_dev->length;
329471 + memcpy(type->id, id, type->id_len);
329472 + type->chipsize = (unsigned int)(spl_dev->chipsize >> 20);
329473 + FMC_PR(BT_DBG, "\t |-Save struct nand_flash_dev info\n");
329475 + memcpy(nand_dev->ids, id, MAX_NAND_ID_LEN);
329476 + nand_dev->oobsize = type->oobsize;
329477 + nand_dev->flags = spl_dev->flags;
329478 + nand_dev->read_retry_type = spl_dev->read_retry_type;
329479 + FMC_PR(BT_DBG, "\t |-Save struct nand_dev_t information\n");
329481 + mtd->oobsize = spl_dev->oobsize;
329482 + mtd->erasesize = spl_dev->erasesize;
329483 + mtd->writesize = spl_dev->pagesize;
329484 + chip->chipsize = spl_dev->chipsize;
329485 + mtd->size = spl_dev->chipsize;
329489 + nand_dev->read_retry_type = NAND_RR_NONE;
329491 + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
329492 + chip->read_byte(mtd);
329493 + chip->read_byte(mtd);
329495 + FMC_PR(BT_DBG, "\t *-Not found special nand flash\n");
329506 diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
329508 --- a/drivers/mtd/nand/raw/Makefile
329510 @@ -58,7 +58,7 @@ obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
329511 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
329512 obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
329514 -nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
329515 +nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o hinfc_gen.o hinfc_spl_ids.o match_ta…
329516 nand-objs += nand_amd.o
329517 nand-objs += nand_hynix.o
329518 nand-objs += nand_macronix.o
329519 diff --git a/drivers/mtd/nand/raw/hinfc_gen.c b/drivers/mtd/nand/raw/hinfc_gen.c
329522 --- /dev/null
329524 @@ -0,0 +1,237 @@
329661 + while (loop-- > 0 && n) {
329763 diff --git a/drivers/mtd/nand/raw/hinfc_gen.h b/drivers/mtd/nand/raw/hinfc_gen.h
329766 --- /dev/null
329768 @@ -0,0 +1,281 @@
329961 +#define IS_NANDC_HW_AUTO(_host) ((_host)->flags & NANDC_HW_AUTO)
329962 +#define IS_NANDC_CONFIG_DONE(_host) ((_host)->flags & NANDC_CONFIG_DONE)
329963 +#define IS_NANDC_SYNC_BOOT(_host) ((_host)->flags & NANDC_IS_SYNC_BOOT)
329965 +#define IS_NAND_RANDOM(_dev) ((_dev)->flags & NAND_RANDOMIZER)
329966 +#define IS_NAND_ONLY_SYNC(_dev) ((_dev)->flags & NAND_MODE_ONLY_SYNC)
329967 +#define IS_NAND_SYNC_ASYNC(_dev) ((_dev)->flags & NAND_MODE_SYNC_ASYNC)
329968 +#define IS_NAND_ONFI(_dev) ((_dev)->flags & NAND_IS_ONFI)
330051 diff --git a/drivers/mtd/nand/raw/hinfc_spl_ids.c b/drivers/mtd/nand/raw/hinfc_spl_ids.c
330054 --- /dev/null
330056 @@ -0,0 +1,970 @@
330105 + unsigned char *id = nand_dev->ids;
330106 + struct nand_flash_dev *type = &nand_dev->flash_dev;
330117 + type->options = 0;
330118 + type->pagesize = pagesizes[(id[3] & 0x03)];
330119 + type->erasesize = blocksizes[blocktype];
330120 + nand_dev->oobsize = oobsizes[oobtype];
330129 + unsigned char *id = nand_dev->ids;
330130 + struct nand_flash_dev *type = &nand_dev->flash_dev;
330139 + type->options = 0;
330140 + type->pagesize = pagesizes[(id[3] & 0x03)];
330141 + type->erasesize = blocksizes[blocktype];
330142 + nand_dev->oobsize = oobsizes[oobtype];
330202 + * MISC | MLC | P1UAGA30AT-GCA | 8bit/512 |
330203 + * MISC | MLC | PSU8GA30AT-GIA/ASU8GA30IT-G30CA | 4bit/512 |
330865 + .name = "P1UAGA30AT-GCA",
330880 + * PowerFlash ASU8GA30IT-G30CA ID and MIRA PSU8GA30AT-GIA ID are
330883 + .name = "PSU8GA30AT-GIA/ASU8GA30IT-G30CA",
330927 + unsigned char *byte = nand_dev->ids;
330928 + struct nand_flash_dev *type = &nand_dev->flash_dev;
330935 + for (spl_dev = nand_flash_special_dev; spl_dev->length; spl_dev++) {
330936 + if (memcmp(byte, spl_dev->id, spl_dev->length))
330941 + if (spl_dev->probe) {
330942 + type = spl_dev->probe(nand_dev);
330944 + type->options = spl_dev->options;
330945 + type->pagesize = spl_dev->pagesize;
330946 + type->erasesize = spl_dev->erasesize;
330947 + nand_dev->oobsize = spl_dev->oobsize;
330950 + nand_dev->read_retry_type = spl_dev->read_retry_type;
330951 + nand_dev->flags = spl_dev->flags;
330953 + type->id[1] = byte[1];
330954 + type->chipsize = (unsigned long)(spl_dev->chipsize >> 20);
330955 + type->name = spl_dev->name;
330958 + nand_dev->read_retry_type = NAND_RR_NONE;
330972 + memcpy(nand_dev->ids, id_data, 8);
330977 + type = &nand_dev->flash_dev;
330979 + if (!mtd->name)
330980 + mtd->name = type->name;
330982 + chip->chipsize = (uint64_t)type->chipsize << 20;
330983 + mtd->erasesize = type->erasesize;
330984 + mtd->writesize = type->pagesize;
330985 + mtd->oobsize = nand_dev->oobsize;
330986 + *busw = (type->options & NAND_BUSWIDTH_16);
330996 + if (!nand_dev->oobsize)
330997 + nand_dev->oobsize = mtd->oobsize;
331011 + if (nand_dev->read_retry_type != NAND_RR_NONE)
331012 + hinfc_pr_msg("Read-Retry \n");
331014 + if (nand_dev->start_type)
331015 + hinfc_pr_msg("Nand(%s): ", nand_dev->start_type);
331019 + hinfc_pr_msg("OOB:%dB ", nand_dev->oobsize);
331020 + hinfc_pr_msg("ECC:%s ", nand_ecc_name(nand_dev->ecctype));
331027 diff --git a/drivers/mtd/nand/raw/match_table.c b/drivers/mtd/nand/raw/match_table.c
331030 --- /dev/null
331032 @@ -0,0 +1,102 @@
331037 + * Create by Hisilicon 2013-08-15
331046 + while (length-- > 0) {
331047 + if (table->reg == reg) {
331048 + return table->type;
331057 + while (length-- > 0) {
331058 + if (table->type == type) {
331059 + return table->reg;
331069 + while (length-- > 0) {
331070 + if (!strncmp(table->str, str, size)) {
331071 + return table->type;
331081 + while (length-- > 0) {
331082 + if (table->type == type) {
331083 + return table->str;
331092 + while (nr_table-- > 0) {
331093 + if (table->reg == reg) {
331094 + return table->type;
331103 + while (nr_table-- > 0) {
331104 + if (table->type == type) {
331105 + return table->reg;
331115 + while (nr_table-- > 0) {
331116 + if (!memcmp(table->data, data, size)) {
331117 + return table->type;
331127 + while (nr_table-- > 0) {
331128 + if (table->type == type) {
331129 + return table->data;
331135 diff --git a/drivers/mtd/nand/raw/match_table.h b/drivers/mtd/nand/raw/match_table.h
331138 --- /dev/null
331140 @@ -0,0 +1,51 @@
331145 + * Create by Hisilicon 2013-08-15
331192 diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
331194 --- a/drivers/mtd/nand/raw/nand_base.c
331196 @@ -47,6 +47,7 @@
331204 @@ -4409,6 +4410,10 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
331212 ops->retlen = 0;
331215 @@ -5632,7 +5637,8 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
331219 - int busw, ret;
331222 u8 *id_data = chip->id.data;
331225 @@ -5680,6 +5686,30 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
331227 chip->manufacturer.desc = manufacturer;
331235 + chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
331247 + return -ENODEV;
331256 @@ -5741,12 +5771,16 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
331257 chip->options |= type->options;
331263 if (!mtd->name)
331264 mtd->name = chip->parameters.model;
331266 if (chip->options & NAND_BUSWIDTH_AUTO) {
331270 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
331273 @@ -5796,6 +5830,10 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
331275 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
331276 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
331279 + hinfc_show_info(mtd, nand_manufacturer_name(manufacturer), type->name);
331284 diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
331286 --- a/drivers/mtd/nand/raw/nand_ids.c
331288 @@ -181,10 +181,18 @@ static const struct nand_manufacturer nand_manufacturers[] = {
331295 + {NAND_MFR_ALL_FLASH, "All-flash"},
331300 - {NAND_MFR_WINBOND, "Winbond"},
331308 diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
331310 --- a/drivers/mtd/spi-nor/Kconfig
331311 +++ b/drivers/mtd/spi-nor/Kconfig
331312 @@ -69,11 +69,12 @@ config SPI_FSL_QUADSPI
331316 - tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
331317 - depends on ARCH_HISI || COMPILE_TEST
331318 - depends on HAS_IOMEM
331319 + tristate "Hisilicon FMCV100 SPI-NOR Flash Controller(SFC)"
331323 - This enables support for hisilicon SPI-NOR flash controller.
331325 + (FMCV100)- SPI-NOR flash controller.
331329 @@ -129,4 +130,32 @@ config SPI_STM32_QUADSPI
331330 This enables support for the STM32 Quad SPI controller.
331362 diff --git a/drivers/mtd/spi-nor/hisi-sfc.c b/drivers/mtd/spi-nor/hisi-sfc.c
331364 --- a/drivers/mtd/spi-nor/hisi-sfc.c
331365 +++ b/drivers/mtd/spi-nor/hisi-sfc.c
331366 @@ -27,6 +27,13 @@
331380 @@ -90,6 +97,7 @@ enum hifmc_iftype {
331388 @@ -97,10 +105,16 @@ struct hifmc_priv {
331405 @@ -110,17 +124,25 @@ struct hifmc_host {
331415 -static inline int hisi_spi_nor_wait_op_finish(struct hifmc_host *host)
331422 + return -1;
331424 return readl_poll_timeout(host->regbase + FMC_INT, reg,
331428 -static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
331433 @@ -143,28 +165,70 @@ static int hisi_spi_nor_get_if_type(enum spi_nor_protocol proto)
331437 - return if_type;
331447 + reg = readl(host->regbase + FMC_CFG);
331450 + writel(reg, host->regbase + FMC_CFG);
331464 + reg = readl(host->regbase + FMC_CFG);
331467 + writel(reg, host->regbase + FMC_CFG);
331471 + reg = readl(host->regbase + FMC_GLOBAL_CFG);
331473 + writel(reg, host->regbase + FMC_GLOBAL_CFG);
331480 writel(reg, host->regbase + FMC_SPI_TIMING_CFG);
331486 struct hifmc_priv *priv = nor->priv;
331487 struct hifmc_host *host = priv->host;
331493 + mutex_lock(host->lock);
331495 + clkrate = min_t(u32, priv->clkrate, nor->clkrate);
331496 + ret = clk_set_rate(host->clk, clkrate);
331498 mutex_lock(&host->lock);
331500 ret = clk_set_rate(host->clk, priv->clkrate);
331505 @@ -172,22 +236,37 @@ static int hisi_spi_nor_prep(struct spi_nor *nor, enum spi_nor_ops ops)
331517 + mutex_unlock(host->lock);
331519 mutex_unlock(&host->lock);
331527 struct hifmc_priv *priv = nor->priv;
331528 struct hifmc_host *host = priv->host;
331530 clk_disable_unprepare(host->clk);
331532 + mutex_unlock(host->lock);
331535 mutex_unlock(&host->lock);
331543 @@ -198,10 +277,14 @@ static int hisi_spi_nor_op_reg(struct spi_nor *nor,
331545 writel(reg, host->regbase + FMC_CMD);
331547 - reg = FMC_DATA_NUM_CNT(len);
331549 writel(reg, host->regbase + FMC_DATA_NUM);
331552 + reg = OP_CFG_FM_CS(priv->chipselect) | OP_CFG_OEN_EN;
331554 reg = OP_CFG_FM_CS(priv->chipselect);
331556 writel(reg, host->regbase + FMC_OP_CFG);
331558 writel(0xff, host->regbase + FMC_INT_CLR);
331559 @@ -211,6 +294,7 @@ static int hisi_spi_nor_op_reg(struct spi_nor *nor,
331567 @@ -226,6 +310,7 @@ static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
331575 @@ -238,6 +323,7 @@ static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
331583 @@ -254,7 +340,19 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
331584 writel(reg, host->regbase + FMC_CFG);
331586 writel(start_off, host->regbase + FMC_ADDRL);
331590 + writel(reg, host->regbase + FMC_DMA_SADDR_D0);
331594 + writel(reg, host->regbase + FMC_DMA_SADDRH_D0);
331597 writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
331600 writel(FMC_DMA_LEN_SET(len), host->regbase + FMC_DMA_LEN);
331602 reg = OP_CFG_FM_CS(priv->chipselect);
331603 @@ -265,6 +363,11 @@ static int hisi_spi_nor_dma_transfer(struct spi_nor *nor, loff_t start_off,
331606 reg |= OP_CFG_DUMMY_NUM(nor->read_dummy >> 3);
331612 writel(reg, host->regbase + FMC_OP_CFG);
331614 writel(0xff, host->regbase + FMC_INT_CLR);
331615 @@ -285,8 +388,13 @@ static ssize_t hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
331620 + for (offset = 0; offset < len; offset += host->dma_len) {
331621 + size_t trans = min_t(size_t, host->dma_len, len - offset);
331624 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
331628 from + offset, host->dma_buffer, trans, FMC_OP_READ);
331629 @@ -308,8 +416,13 @@ static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
331634 + for (offset = 0; offset < len; offset += host->dma_len) {
331635 + size_t trans = min_t(size_t, host->dma_len, len - offset);
331638 size_t trans = min_t(size_t, HIFMC_DMA_MAX_LEN, len - offset);
331641 memcpy(host->buffer, write_buf + offset, trans);
331643 @@ -323,25 +436,52 @@ static ssize_t hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
331671 - const struct spi_nor_hwcaps hwcaps = {
331684 - struct device *dev = host->dev;
331685 - struct spi_nor *nor;
331686 - struct hifmc_priv *priv;
331687 - struct mtd_info *mtd;
331694 + if (!host || !host->dev)
331695 + return -ENXIO;
331697 + dev = host->dev;
331700 return -ENOMEM;
331701 @@ -360,6 +500,15 @@ static int hisi_spi_nor_register(struct device_node *np,
331706 + if (priv->chipselect != host->num_chip) {
331709 + priv->chipselect, host->num_chip);
331710 + priv->chipselect = host->num_chip;
331714 ret = of_property_read_u32(np, "spi-max-frequency",
331715 &priv->clkrate);
331717 @@ -377,18 +526,34 @@ static int hisi_spi_nor_register(struct device_node *np,
331718 nor->read = hisi_spi_nor_read;
331719 nor->write = hisi_spi_nor_write;
331720 nor->erase = NULL;
331733 mtd = &nor->mtd;
331734 mtd->name = np->name;
331740 + hifmc_cs_user[host->num_chip]++;
331745 + host->num_chip++;
331748 host->nor[host->num_chip] = nor;
331749 - host->num_chip++;
331753 @@ -407,14 +572,25 @@ static int hisi_spi_nor_register_all(struct hifmc_host *host)
331756 for_each_available_child_of_node(dev->of_node, np) {
331757 - ret = hisi_spi_nor_register(np, host);
331758 - if (ret)
331759 - goto fail;
331760 -
331762 if (host->num_chip == HIFMC_MAX_CHIP_NUM) {
331766 + if (hifmc_cs_user[host->num_chip]) {
331768 + host->num_chip);
331777 + host->num_chip++;
331783 @@ -424,12 +600,23 @@ static int hisi_spi_nor_register_all(struct hifmc_host *host)
331790 struct device *dev = &pdev->dev;
331797 + struct hisi_fmc *fmc = dev_get_drvdata(dev->parent);
331800 + dev_err(&pdev->dev, "get mfd fmc devices failed\n");
331801 + return -ENXIO;
331807 @@ -438,6 +625,15 @@ static int hisi_spi_nor_probe(struct platform_device *pdev)
331809 host->dev = dev;
331812 + host->regbase = fmc->regbase;
331813 + host->iobase = fmc->iobase;
331814 + host->clk = fmc->clk;
331815 + host->lock = &fmc->lock;
331816 + host->buffer = fmc->buffer;
331817 + host->dma_buffer = fmc->dma_buffer;
331818 + host->dma_len = fmc->dma_len;
331821 host->regbase = devm_ioremap_resource(dev, res);
331822 if (IS_ERR(host->regbase))
331823 @@ -462,44 +658,138 @@ static int hisi_spi_nor_probe(struct platform_device *pdev)
331824 &host->dma_buffer, GFP_KERNEL);
331825 if (!host->buffer)
331826 return -ENOMEM;
331829 ret = clk_prepare_enable(host->clk);
331834 mutex_init(&host->lock);
331842 mutex_destroy(&host->lock);
331845 clk_disable_unprepare(host->clk);
331855 - hisi_spi_nor_unregister_all(host);
331856 - mutex_destroy(&host->lock);
331857 + if (host && host->clk) {
331860 + mutex_destroy(&host->lock);
331862 + clk_disable_unprepare(host->clk);
331875 + if (!host || !host->clk)
331878 + mutex_lock(host->lock);
331879 + clk_prepare_enable(host->clk);
331882 + for (i = 0; i < host->num_chip; i++)
331883 + spi_nor_driver_shutdown(host->nor[i]);
331885 + clk_disable_unprepare(host->clk);
331886 + mutex_unlock(host->lock);
331887 + dev_dbg(host->dev, "End of driver shutdown\n");
331898 + if (!host || !host->clk)
331901 + mutex_lock(host->lock);
331902 + clk_prepare_enable(host->clk);
331905 + for (i = 0; i < host->num_chip; i++)
331906 + spi_nor_suspend(host->nor[i], state);
331908 clk_disable_unprepare(host->clk);
331909 + mutex_unlock(host->lock);
331910 + dev_dbg(host->dev, "End of suspend\n");
331921 + if (!host || !host->clk)
331924 + mutex_lock(host->lock);
331925 + clk_prepare_enable(host->clk);
331928 + for (i = 0; i < host->num_chip; i++)
331929 + hisi_spi_nor_resume(host->nor[i]);
331931 + mutex_unlock(host->lock);
331932 + dev_dbg(host->dev, "End of resume\n");
331941 { .compatible = "hisilicon,fmc-spi-nor"},
331949 .name = "hisi-sfc",
331952 - .probe = hisi_spi_nor_probe,
331953 - .remove = hisi_spi_nor_remove,
331966 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
331968 --- a/drivers/mtd/spi-nor/spi-nor.c
331969 +++ b/drivers/mtd/spi-nor/spi-nor.c
331970 @@ -41,6 +41,73 @@
332044 @@ -91,6 +158,11 @@ struct flash_info {
332055 #define JEDEC_MFR(info) ((info)->id[0])
332056 @@ -522,6 +594,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
332061 + if ((nor->level) && (addr < nor->end_addr)) {
332062 + dev_err(nor->dev, "Error: The erase area was locked\n");
332064 + return -EINVAL;
332067 /* whole-chip erase? */
332068 if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
332070 @@ -910,6 +989,243 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
332305 +/* Different from spi-max-frequency in DTS, the clk here stands for the clock
332314 @@ -971,6 +1287,57 @@ static int macronix_quad_enable(struct spi_nor *nor);
332328 + * Macronix/MXIC MX25U25635F/45G 32M 64K 1V8 25645G-DTR
332329 + * Macronix/MXIC MX25L(256/257) 32M 64K 3V3 25645G-DTR
332330 + * Macronix/MXIC MX25U51245G 64M 64K 1V8 51245G-DTR
332364 + * FM FM25Q64-SOB-T-G 8M 64K 3V3
332365 + * FM FM25Q128-SOB-T-G 16M 64K 3V3
332370 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
332372 @@ -991,9 +1358,18 @@ static const struct flash_info spi_nor_ids[] = {
332373 /* EON -- en25xxx */
332385 - { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
332392 @@ -1013,7 +1389,24 @@ static const struct flash_info spi_nor_ids[] = {
332396 - /* GigaDevice */
332418 @@ -1025,22 +1418,23 @@ static const struct flash_info spi_nor_ids[] = {
332422 - "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
332428 - "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
332434 - "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
332441 - "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
332446 @@ -1073,45 +1467,107 @@ static const struct flash_info spi_nor_ids[] = {
332450 - /* Macronix */
332456 - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
332459 - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
332463 - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
332464 - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
332466 - { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
332469 - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_N…
332470 - { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_RE…
332472 - { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
332477 + /* MXIC 3.3V MX25L6436FM2I-08G/MX25L6433FM2I-08G */
332478 + { "mx25l64XXfm2i-08g", INFO(0xc22017, 0, 64 * 1024, 128,
332514 - /* Micron */
332536 - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
332565 @@ -1122,8 +1578,14 @@ static const struct flash_info spi_nor_ids[] = {
332580 @@ -1200,7 +1662,7 @@ static const struct flash_info spi_nor_ids[] = {
332584 - /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
332585 + /* Winbond 3.3V-- w25x "blocks" are 64K, "sectors" are 4KiB */
332589 @@ -1216,18 +1678,43 @@ static const struct flash_info spi_nor_ids[] = {
332615 + { "w25q256jw-im", INFO(0xef8019, 0, 64 * 1024, 512,
332619 + { "w25q256jw-iq", INFO(0xef6019, 0, 64 * 1024, 512,
332630 - {
332631 - "w25q32jv", INFO(0xef7016, 0, 64 * 1024, 64,
332632 - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
332633 - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
332634 - },
332635 - { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
332639 @@ -1239,12 +1726,19 @@ static const struct flash_info spi_nor_ids[] = {
332643 - { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
332644 - { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
332659 /* Catalyst / On Semiconductor -- non-JEDEC */
332661 @@ -1263,6 +1757,41 @@ static const struct flash_info spi_nor_ids[] = {
332678 + { "xt25f32bssigu-s", INFO(0x0b4016, 0, 64 * 1024, 64,
332688 + { "FM25Q64-SOB-T-G",INFO(0xa14017, 0, 64 * 1024, 128,
332690 + { "FM25Q128-SOB-T-G",INFO(0xa14018, 0, 64 * 1024, 256,
332703 @@ -1278,6 +1807,13 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
332709 + dev_err(nor->dev, "unrecognized Manufacturer ID\n");
332710 + return ERR_PTR(-ENODEV);
332714 for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
332716 if (info->id_len) {
332717 @@ -1426,6 +1962,13 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
332722 + if (nor->level && (to < nor->end_addr)) {
332723 + dev_err(nor->dev, "Error: The DMA write area was locked\n");
332725 + return -EINVAL;
332731 @@ -1571,6 +2114,19 @@ static int spansion_quad_enable(struct spi_nor *nor)
332743 + dev_dbg(nor->dev, "setting Quad Enable (non-volatile) bit\n");
332751 @@ -1578,7 +2134,7 @@ static int spansion_quad_enable(struct spi_nor *nor)
332755 - if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
332757 dev_err(nor->dev, "Spansion Quad bit not set\n");
332758 return -EINVAL;
332760 @@ -1586,6 +2142,394 @@ static int spansion_quad_enable(struct spi_nor *nor)
332778 + dev_dbg(nor->dev, "setting xtx Quad Enable (non-volatile) bit\n");
332786 + nor->cmd_buf[0] = val_l;
332787 + nor->cmd_buf[1] = val_h;
332788 + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
332795 + dev_err(nor->dev, "xtx Quad bit not set\n");
332796 + return -EINVAL;
332807 + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
332809 + dev_err(nor->dev, "error %d reading EVCR\n", ret);
332816 + nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
332817 + ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
332819 + dev_err(nor->dev, "error while writing EVCR register\n");
332828 + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
332830 + dev_err(nor->dev, "error %d reading EVCR\n", ret);
332834 + dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
332835 + return -EINVAL;
332848 + /* First, Quad Enable for 16-Pin GD flash, use WRSR[01h] cmd */
332861 + dev_err(nor->dev,
332863 + return -EINVAL;
332874 + /* Second, Quad Enable for 8-Pin GD flash, use WRCR[31h] cmd */
332880 + nor->cmd_buf[0] = (regval & 0xff) | CR_QUAD_EN_SPAN;
332882 + ret = nor->write_reg(nor, SPINOR_OP_WRCR, nor->cmd_buf, 1);
332884 + dev_err(nor->dev, "error while writing config register\n");
332894 + dev_err(nor->dev, "GigaDevice Quad bit not set\n");
332895 + return -EINVAL;
332913 + nor->cmd_buf[0] = val;
332914 + ret = nor->write_reg(nor, SPINOR_OP_WRCR, nor->cmd_buf, 1);
332916 + dev_err(nor->dev,
332917 + "error while writing status register-2\n");
332918 + return -EINVAL;
332937 + if (!nor->level) {
332938 + nor->end_addr = 0;
332939 + dev_warn(nor->dev, "all blocks is unlocked.\n");
332943 + sectorsize = info->sector_size;
332944 + chipsize = sectorsize * info->n_sectors;
332945 + lock_level_max = nor->lock_level_max;
332950 + if ((nor->level != lock_level_max)
332951 + && (nor->level != 1))
332952 + nor->end_addr = chipsize - (sectorsize <<
332953 + (lock_level_max - nor->level - 1));
332955 + nor->end_addr = chipsize;
332963 + if (nor->level != lock_level_max)
332964 + nor->end_addr = chipsize - (sectorsize
332965 + << (lock_level_max - nor->level));
332967 + nor->end_addr = chipsize;
332970 + if (nor->level != lock_level_max)
332971 + nor->end_addr = chipsize - (sectorsize
332972 + << (nor->level - 1));
332974 + nor->end_addr = chipsize;
332981 + nor->end_addr = chipsize >> (lock_level_max - nor->level);
332995 + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
332997 + dev_err(nor->dev, "error %d reading SR\n", ret);
333006 + dev_dbg(nor->dev, "the current level[%d]\n", level);
333009 + nor->lock_level_max = LOCK_LEVEL_MAX(bp_num) - 5;
333010 + chipsize = info->sector_size * info->n_sectors;
333013 + nor->lock_level_max--;
333015 + nor->lock_level_max = LOCK_LEVEL_MAX(bp_num);
333016 + dev_dbg(nor->dev, "Get the max bp level: [%d]\n",
333017 + nor->lock_level_max);
333025 + struct device *dev = nor->dev;
333027 + chipsize = info->sector_size * info->n_sectors;
333036 + nor->level = hisi_bp_to_level(nor, info, BP_NUM_3);
333041 + nor->level = hisi_bp_to_level(nor, info, BP_NUM_3);
333043 + nor->level = hisi_bp_to_level(nor, info, BP_NUM_4);
333048 + nor->level = hisi_bp_to_level(nor, info, BP_NUM_3);
333050 + nor->level = hisi_bp_to_level(nor, info, BP_NUM_4);
333057 + if (nor->end_addr)
333059 + nor->end_addr);
333073 + ret = nor->read_reg(nor, SPINOR_OP_RDSR3, &val, 1);
333075 + dev_err(nor->dev, "error %d reading Status Reg 3.\n", ret);
333080 + dev_dbg(nor->dev, "Device has worked on RESET#.\n");
333084 + dev_dbg(nor->dev, "Start to enable RESET# function.\n");
333087 + nor->write_reg(nor, SPINOR_OP_WRSR3, &val, 1);
333089 + dev_err(nor->dev, "error while writing Status Reg 3.\n");
333093 + dev_dbg(nor->dev, "Enable RESET# function success.\n");
333122 + ret = nor->read_reg(nor, SPINOR_OP_RDSR3, &cval, 1);
333124 + dev_err(nor->dev, "error %d reading config Reg.\n", ret);
333132 + nor->cmd_buf[0]=val;
333133 + nor->cmd_buf[1]=(cval & (~CR_DUMMY_CYCLE));
333134 + ret = nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
333144 + memcpy(params, info->params, sizeof(*params));
333145 + params->size = info->sector_size * info->n_sectors;
333146 + params->page_size = info->page_size;
333153 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register.
333155 @@ -1772,6 +2716,7 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor)
333163 @@ -1836,6 +2781,7 @@ struct spi_nor_flash_parameter {
333171 @@ -1935,7 +2881,7 @@ static int spi_nor_read_sfdp_dma_unsafe(struct spi_nor *nor, u32 addr,
333174 return -ENOMEM;
333175 -
333180 @@ -2401,7 +3347,7 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
333183 return -ENOMEM;
333184 -
333189 @@ -2498,11 +3444,28 @@ static int spi_nor_init_params(struct spi_nor *nor,
333190 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
333197 params->quad_enable = macronix_quad_enable;
333202 + params->quad_enable = micron_quad_enable;
333206 + params->quad_enable = gd_quad_enable;
333210 + params->quad_enable = xtx_quad_enable;
333213 + params->quad_enable = puya_quad_enable;
333218 @@ -2601,7 +3564,7 @@ static int spi_nor_select_read(struct spi_nor *nor,
333220 return -EINVAL;
333222 - cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));
333225 return -EINVAL;
333227 @@ -2727,6 +3690,22 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
333229 nor->quad_enable = NULL;
333234 + dev_err(nor->dev, "Clear Dtr Mode Fail.\n");
333238 + if (!(hwcaps->mask & (SNOR_HWCAPS_READ_1_1_4 | SNOR_HWCAPS_READ_1_4_4))) {
333241 + dev_err(nor->dev, "Enable RESET# Fail.\n");
333250 @@ -2797,10 +3776,83 @@ void spi_nor_restore(struct spi_nor *nor)
333258 + /* disable 4-byte addressing if the device exceeds 16MiB */
333259 + if (nor->addr_width == 4) {
333304 + if (info->params)
333317 + /* enable 4-byte addressing if the device exceeds 16MiB */
333318 + if (nor->addr_width == 4 && JEDEC_MFR(info) != SNOR_MFR_SPANSION)
333332 struct device *dev = nor->dev;
333333 struct mtd_info *mtd = &nor->mtd;
333334 @@ -2812,7 +3864,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
333338 - /* Reset SPI protocol for all commands. */
333340 nor->reg_proto = SNOR_PROTO_1_1_1;
333341 nor->read_proto = SNOR_PROTO_1_1_1;
333342 nor->write_proto = SNOR_PROTO_1_1_1;
333343 @@ -2820,8 +3872,11 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
333346 /* Try to auto-detect if chip name wasn't specified or not found */
333347 - if (!info)
333354 return -ENOENT;
333356 @@ -2859,10 +3914,22 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
333357 if (info->flags & SPI_S3AN)
333358 nor->flags |= SNOR_F_READY_XSR_RDY;
333360 - /* Parse the Serial Flash Discoverable Parameters table. */
333361 - ret = spi_nor_init_params(nor, info, ¶ms);
333362 - if (ret)
333363 - return ret;
333369 + if (info->params)
333381 if (!mtd->name)
333382 mtd->name = dev_name(dev);
333383 @@ -2877,7 +3944,10 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
333387 - info->flags & SPI_NOR_HAS_LOCK) {
333391 + info->flags & SPI_NOR_HAS_LOCK) {
333392 nor->flash_lock = stm_lock;
333393 nor->flash_unlock = stm_unlock;
333394 nor->flash_is_locked = stm_is_locked;
333395 @@ -2924,7 +3994,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
333397 if (of_property_read_bool(np, "broken-flash-reset"))
333398 nor->flags |= SNOR_F_BROKEN_RESET;
333399 -
333400 /* Some devices cannot do fast-read, no matter what DT tells us */
333401 if (info->flags & SPI_NOR_NO_FR)
333403 @@ -2954,6 +4023,16 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
333404 nor->addr_width = 3;
333409 + if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) /* device supports dual or quad */
333410 + && (hwcaps->mask & (~SNOR_HWCAPS_READ)) /* controller supports fast mode */
333411 + && info->clkrate)
333412 + nor->clkrate = info->clkrate;
333414 + nor->clkrate = 24000000;
333417 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
333419 nor->addr_width);
333420 diff --git a/drivers/net/ethernet/hisilicon/Kconfig b/drivers/net/ethernet/hisilicon/Kconfig
333422 --- a/drivers/net/ethernet/hisilicon/Kconfig
333424 @@ -125,4 +125,6 @@ config HNS3_ENET
333431 diff --git a/drivers/net/ethernet/hisilicon/Makefile b/drivers/net/ethernet/hisilicon/Makefile
333433 --- a/drivers/net/ethernet/hisilicon/Makefile
333435 @@ -8,4 +8,5 @@ obj-$(CONFIG_HIP04_ETH) += hip04_eth.o
333436 obj-$(CONFIG_HNS_MDIO) += hns_mdio.o
333437 obj-$(CONFIG_HNS) += hns/
333438 obj-$(CONFIG_HNS3) += hns3/
333439 -obj-$(CONFIG_HISI_FEMAC) += hisi_femac.o
333440 +obj-$(CONFIG_HISI_FEMAC) += hisi-femac/
333441 +obj-$(CONFIG_HIETH_GMAC) += higmac/
333442 diff --git a/drivers/net/ethernet/hisilicon/higmac/Kconfig b/drivers/net/ethernet/hisilicon/higmac/…
333445 --- /dev/null
333447 @@ -0,0 +1,106 @@
333459 + ports at 10/100/1000 Mbit/s in full-duplex or half-duplex mode.
333509 + When buffer is available, we will send zero-quanta pause frame.
333554 diff --git a/drivers/net/ethernet/hisilicon/higmac/Makefile b/drivers/net/ethernet/hisilicon/higmac…
333557 --- /dev/null
333559 @@ -0,0 +1,2 @@
333560 +obj-$(CONFIG_HIETH_GMAC) += hieth-gmac.o
333561 +hieth-gmac-objs := board.o higmac.o pm.o util.o autoeee/autoeee.o autoeee/phy_id_table.o
333562 diff --git a/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.c b/drivers/net/ethernet/hisilic…
333565 --- /dev/null
333567 @@ -0,0 +1,162 @@
333569 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
333572 + * Create: 2018-10-08
333584 + switch (ld->phy->speed) {
333605 + v = readl(ld->gmac_iobase + EEE_CLK);
333608 + writel(v, ld->gmac_iobase + EEE_CLK);
333610 + v = readl(ld->gmac_iobase + EEE_CLK);
333613 + writel(v, ld->gmac_iobase + EEE_CLK);
333622 + writel(0x7c, ld->gmac_iobase +
333624 + writel(0x1e0400, ld->gmac_iobase + EEE_TIMER);
333626 + v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
333629 + writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
333631 + v = readl(ld->gmac_iobase + EEE_ENABLE);
333633 + writel(v, ld->gmac_iobase + EEE_ENABLE);
333640 + pr_info("enter phy-EEE mode\n");
333642 + v = readl(ld->gmac_iobase + EEE_ENABLE);
333643 + v &= ~BIT_EEE_ENABLE; /* disable auto-EEE */
333644 + writel(v, ld->gmac_iobase + EEE_ENABLE);
333653 + if (ld == NULL || ld->eee_init == NULL || ld->phy == NULL)
333655 + phy_id = ld->phy->phy_id;
333656 + if (ld->eee_init != NULL)
333663 + eee_available = phy_info->eee_available;
333664 + if (netif_msg_wol(ld) && phy_info->name != NULL)
333666 + phy_info->phy_id, phy_info->name, eee_available);
333676 + ld->eee_init = phy_info->eee_init;
333680 + lp_eee_capable = ld->eee_init(ld->phy);
333684 + if (ld->phy->link) {
333690 + pr_info("enter auto-EEE mode\n");
333696 + v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
333698 + writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
333704 + ld->eee_init = NULL;
333706 + pr_info("non-EEE mode\n");
333714 + v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
333717 + writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
333725 + v = readl(ld->gmac_iobase + EEE_LINK_STATUS);
333728 + writel(v, ld->gmac_iobase + EEE_LINK_STATUS);
333730 diff --git a/drivers/net/ethernet/hisilicon/higmac/autoeee/autoeee.h b/drivers/net/ethernet/hisilic…
333733 --- /dev/null
333735 @@ -0,0 +1,52 @@
333737 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
333740 + * Create: 2018-10-08
333772 +/* ----------------------------phy register-------------------------------*/
333788 diff --git a/drivers/net/ethernet/hisilicon/higmac/autoeee/phy_id_table.c b/drivers/net/ethernet/hi…
333791 --- /dev/null
333793 @@ -0,0 +1,184 @@
333795 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
333798 + * Create: 2018-10-08
333940 + /* EEE_CAPABILITY register: support 100M-BaseT */
333945 + /* EEE_ADVERTISEMENT register: advertising 100M-BaseT */
333954 + phy_write(phy_dev, MII_BMCR, v); /* auto-neg restart */
333978 diff --git a/drivers/net/ethernet/hisilicon/higmac/board.c b/drivers/net/ethernet/hisilicon/higmac/…
333981 --- /dev/null
333983 @@ -0,0 +1,118 @@
333985 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
333988 + * Create: 2018-10-08
333999 + if (priv == NULL || priv->port_rst == NULL)
334001 + reset_control_deassert(priv->port_rst);
334005 + reset_control_assert(priv->port_rst);
334008 + reset_control_deassert(priv->port_rst);
334019 + if (priv->internal_phy)
334029 + if (priv->phy_rst != NULL) {
334031 + reset_control_deassert(priv->phy_rst);
334036 + reset_control_assert(priv->phy_rst);
334045 + reset_control_deassert(priv->phy_rst);
334068 + if (priv == NULL || priv->clk == NULL || priv->netdev == NULL || priv->macif_clk == NULL)
334071 + if (priv->netdev->flags & IFF_UP)
334072 + clk_disable_unprepare(priv->macif_clk);
334080 + if (priv->netdev->flags & IFF_UP)
334081 + clk_disable_unprepare(priv->clk);
334083 + if (priv->internal_phy)
334089 + if (priv == NULL || priv->netdev == NULL || priv->clk == NULL)
334092 + if (priv->internal_phy)
334095 + if (priv->netdev->flags & IFF_UP)
334096 + clk_prepare_enable(priv->macif_clk);
334099 + if (priv->netdev->flags & IFF_UP)
334100 + clk_prepare_enable(priv->clk);
334102 diff --git a/drivers/net/ethernet/hisilicon/higmac/higmac.c b/drivers/net/ethernet/hisilicon/higmac…
334105 --- /dev/null
334107 @@ -0,0 +1,2645 @@
334109 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
334112 + * Create: 2018-10-08
334134 +#include <linux/dma-mapping.h>
334156 +static int debug = -1;
334166 + writel(BITS_RX_FQ_DEPTH_EN, priv->gmac_iobase + RX_FQ_REG_EN);
334167 + val = readl(priv->gmac_iobase + RX_FQ_DEPTH);
334170 + writel(val, priv->gmac_iobase + RX_FQ_DEPTH);
334171 + writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
334173 + writel(BITS_RX_BQ_DEPTH_EN, priv->gmac_iobase + RX_BQ_REG_EN);
334174 + val = readl(priv->gmac_iobase + RX_BQ_DEPTH);
334177 + writel(val, priv->gmac_iobase + RX_BQ_DEPTH);
334178 + for (i = 1; i < priv->num_rxqs; i++) {
334180 + val = readl(priv->gmac_iobase + reg);
334183 + writel(val, priv->gmac_iobase + reg);
334185 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
334187 + writel(BITS_TX_BQ_DEPTH_EN, priv->gmac_iobase + TX_BQ_REG_EN);
334188 + val = readl(priv->gmac_iobase + TX_BQ_DEPTH);
334191 + writel(val, priv->gmac_iobase + TX_BQ_DEPTH);
334192 + writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
334194 + writel(BITS_TX_RQ_DEPTH_EN, priv->gmac_iobase + TX_RQ_REG_EN);
334195 + val = readl(priv->gmac_iobase + TX_RQ_DEPTH);
334198 + writel(val, priv->gmac_iobase + TX_RQ_DEPTH);
334199 + writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
334208 + writel(BITS_RX_FQ_START_ADDR_EN, priv->gmac_iobase + RX_FQ_REG_EN);
334210 + val = readl(priv->gmac_iobase + RX_FQ_DEPTH);
334213 + writel(val, priv->gmac_iobase + RX_FQ_DEPTH);
334215 + writel((u32)phy_addr, priv->gmac_iobase + RX_FQ_START_ADDR);
334216 + writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
334225 + writel(BITS_RX_BQ_START_ADDR_EN, priv->gmac_iobase + RX_BQ_REG_EN);
334227 + val = readl(priv->gmac_iobase + RX_BQ_DEPTH);
334230 + writel(val, priv->gmac_iobase + RX_BQ_DEPTH);
334232 + writel((u32)phy_addr, priv->gmac_iobase + RX_BQ_START_ADDR);
334233 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
334242 + writel(BITS_TX_BQ_START_ADDR_EN, priv->gmac_iobase + TX_BQ_REG_EN);
334244 + val = readl(priv->gmac_iobase + TX_BQ_DEPTH);
334247 + writel(val, priv->gmac_iobase + TX_BQ_DEPTH);
334249 + writel((u32)phy_addr, priv->gmac_iobase + TX_BQ_START_ADDR);
334250 + writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
334259 + writel(BITS_TX_RQ_START_ADDR_EN, priv->gmac_iobase + TX_RQ_REG_EN);
334261 + val = readl(priv->gmac_iobase + TX_RQ_DEPTH);
334264 + writel(val, priv->gmac_iobase + TX_RQ_DEPTH);
334266 + writel((u32)phy_addr, priv->gmac_iobase + TX_RQ_START_ADDR);
334267 + writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
334278 + higmac_set_rx_fq(priv, priv->RX_FQ.phys_addr);
334279 + higmac_set_rx_bq(priv, priv->RX_BQ.phys_addr);
334280 + higmac_set_tx_rq(priv, priv->TX_RQ.phys_addr);
334281 + higmac_set_tx_bq(priv, priv->TX_BQ.phys_addr);
334283 + for (i = 1; i < priv->num_rxqs; i++) {
334286 + priv->gmac_iobase + RX_BQ_REG_EN);
334288 + val = readl(priv->gmac_iobase + reg);
334290 + val |= ((priv->pool[BASE_QUEUE_NUMS + i].phys_addr) >> REG_BIT_WIDTH) <<
334292 + writel(val, priv->gmac_iobase + reg);
334295 + writel((u32)(priv->pool[BASE_QUEUE_NUMS + i].phys_addr),
334296 + priv->gmac_iobase + reg);
334297 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
334305 + if (priv->has_rxhash_cap)
334307 + if (priv->has_rss_cap)
334309 + writel(val, priv->gmac_iobase + HW_CAP_EN);
334315 + if (!priv->axi_bus_cfg_base)
334321 + if (!(readl(priv->axi_bus_cfg_base) >> BURST_OUTSTANDING_OFFSET))
334322 + writel(BURST4_OUTSTANDING1, priv->axi_bus_cfg_base);
334324 + writel(BURST4_OUTSTANDING1, priv->axi_bus_cfg_base);
334337 + writel(0, priv->gmac_iobase + ENA_PMU_INT);
334338 + writel(~0, priv->gmac_iobase + RAW_PMU_INT);
334340 + for (i = 1; i < priv->num_rxqs; i++) {
334342 + writel(0, priv->gmac_iobase + reg);
334344 + writel(~0, priv->gmac_iobase + RSS_RAW_PMU_INT);
334347 + val = readl(priv->gmac_iobase + REC_FILT_CONTROL);
334349 + writel(val, priv->gmac_iobase + REC_FILT_CONTROL);
334352 + val = readl(priv->gmac_iobase + CRF_MIN_PACKET);
334355 + writel(val, priv->gmac_iobase + CRF_MIN_PACKET);
334358 + writel(CONTROL_WORD_CONFIG, priv->gmac_iobase + CONTROL_WORD);
334360 + writel(0, priv->gmac_iobase + COL_SLOT_TIME);
334362 + writel(DUPLEX_HALF, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL);
334367 + writel(val, priv->gmac_iobase + IN_QUEUE_TH);
334370 + writel(0x10000, priv->gmac_iobase + RX_BQ_IN_TIMEOUT_TH);
334372 + writel(0x18000, priv->gmac_iobase + TX_RQ_IN_TIMEOUT_TH);
334383 + ld->gmac_iobase + ENA_PMU_INT);
334393 + writel(~0, ld->gmac_iobase + reg);
334404 + for (i = 0; i < ld->num_rxqs; i++)
334412 + writel(0, ld->gmac_iobase + ENA_PMU_INT);
334422 + writel(0, ld->gmac_iobase + reg);
334433 + for (i = 0; i < ld->num_rxqs; i++)
334446 + val = readl(ld->gmac_iobase + reg);
334455 + writel(0xF, ld->gmac_iobase + DESC_WR_RD_ENA);
334462 + writel(0, ld->gmac_iobase + DESC_WR_RD_ENA);
334469 + writel(BITS_TX_EN | BITS_RX_EN, ld->gmac_iobase + PORT_EN);
334475 + writel(0, ld->gmac_iobase + PORT_EN);
334485 + rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL);
334490 + if ((dev->flags & IFF_PROMISC)) {
334498 + if (dev->flags & IFF_BROADCAST) /* no broadcast */
334503 + if (netdev_mc_empty(dev) || !(dev->flags & IFF_MULTICAST)) {
334505 + writel(0, ld->gmac_iobase + PORT_MC_ADDR_LOW);
334506 + writel(0, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
334509 + (dev->flags & IFF_MULTICAST)) {
334514 + d = (ha->addr[0] << 8) | (ha->addr[1]); /* shift left 8bits */
334515 + writel(d, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
334517 + d = (ha->addr[2] << 24) | (ha->addr[3] << 16) |
334518 + (ha->addr[4] << 8) | (ha->addr[5]); /* a4 << 8 | a5 */
334519 + writel(d, ld->gmac_iobase + PORT_MC_ADDR_LOW);
334526 + writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL);
334542 + writel(STOP_RX_TX, ld->gmac_iobase + STOP_CMD);
334544 + spin_lock_irqsave(&ld->rxlock, rxflags);
334546 + wr_offset = readl(ld->gmac_iobase + RX_BQ_WR_ADDR);
334548 + rd_offset = readl(ld->gmac_iobase + RX_BQ_RD_ADDR);
334550 + writel(wr_offset, ld->gmac_iobase + RX_BQ_RD_ADDR);
334552 + for (i = 1; i < ld->num_rxqs; i++) {
334558 + wr_offset = readl(ld->gmac_iobase + rx_bq_wr_reg);
334559 + writel(wr_offset, ld->gmac_iobase + rx_bq_rd_reg);
334563 + wr_offset = readl(ld->gmac_iobase + RX_FQ_WR_ADDR);
334565 + rd_offset = readl(ld->gmac_iobase + RX_FQ_RD_ADDR);
334567 + rd_offset = (RX_DESC_NUM - 1) << DESC_BYTE_SHIFT;
334569 + rd_offset -= DESC_SIZE;
334571 + writel(rd_offset, ld->gmac_iobase + RX_FQ_WR_ADDR);
334573 + for (i = 0; i < ld->RX_FQ.count; i++) {
334574 + if (!ld->RX_FQ.skb[i])
334575 + ld->RX_FQ.skb[i] = SKB_MAGIC;
334577 + spin_unlock_irqrestore(&ld->rxlock, rxflags);
334583 + spin_lock_irqsave(&ld->txlock, txflags);
334585 + wr_offset = readl(ld->gmac_iobase + TX_RQ_WR_ADDR);
334587 + rd_offset = readl(ld->gmac_iobase + TX_RQ_RD_ADDR);
334589 + writel(wr_offset, ld->gmac_iobase + TX_RQ_RD_ADDR);
334592 + rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
334594 + rd_offset = (TX_DESC_NUM - 1) << DESC_BYTE_SHIFT;
334596 + rd_offset -= DESC_SIZE;
334598 + writel(rd_offset, ld->gmac_iobase + TX_BQ_WR_ADDR);
334600 + for (i = 0; i < ld->TX_BQ.count; i++) {
334601 + if (!ld->TX_BQ.skb[i])
334602 + ld->TX_BQ.skb[i] = SKB_MAGIC;
334604 + spin_unlock_irqrestore(&ld->txlock, txflags);
334613 + unsigned char *mac = dev->dev_addr;
334617 + writel(val, priv->gmac_iobase + STATION_ADDR_HIGH);
334620 + writel(val, priv->gmac_iobase + STATION_ADDR_LOW);
334630 + for (i = 0; i < ld->RX_FQ.count; i++) {
334631 + skb = ld->RX_FQ.skb[i];
334633 + ld->rx_skb[i] = NULL;
334634 + ld->RX_FQ.skb[i] = NULL;
334643 + * dma_unmap_single(dev, dma_addr, skb->len,
334655 + for (i = 0; i < ld->TX_BQ.count; i++) {
334656 + skb = ld->TX_BQ.skb[i];
334658 + ld->tx_skb[i] = NULL;
334659 + ld->TX_BQ.skb[i] = NULL;
334668 +/* reset and re-config gmac */
334672 + if (ld == NULL || ld->netdev == NULL)
334677 + spin_lock_irqsave(&ld->rxlock, rxflags);
334678 + spin_lock_irqsave(&ld->txlock, txflags);
334685 + higmac_hw_set_mac_addr(ld->netdev);
334689 + if (ld->netdev->flags & IFF_UP) {
334695 + higmac_set_multicast_list(ld->netdev);
334701 + spin_unlock_irqrestore(&ld->txlock, txflags);
334702 + spin_unlock_irqrestore(&ld->rxlock, rxflags);
334732 + tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR);
334733 + tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
334736 + if (unlikely((long long)time_now -
334750 + val = readl(priv->gmac_iobase + MAC_CLEAR);
334752 + writel(val, priv->gmac_iobase + MAC_CLEAR);
334756 + val = readl(priv->gmac_iobase + MAC_CLEAR);
334758 + writel(val, priv->gmac_iobase + MAC_CLEAR);
334770 + if (priv == NULL || priv->phy == NULL)
334772 + phy = priv->phy;
334773 + if (phy->link) {
334774 + if ((priv->old_speed != phy->speed) ||
334775 + (priv->old_duplex != phy->duplex)) {
334779 + spin_lock_irqsave(&priv->txlock, txflags);
334783 + higmac_config_port(dev, phy->speed, phy->duplex);
334788 + spin_unlock_irqrestore(&priv->txlock, txflags);
334790 + higmac_set_flow_ctrl_state(priv, phy->pause);
334792 + if (priv->autoeee)
334796 + priv->old_link = 1;
334797 + priv->old_speed = phy->speed;
334798 + priv->old_duplex = phy->duplex;
334800 + } else if (priv->old_link) {
334802 + priv->old_link = 0;
334803 + priv->old_speed = SPEED_UNKNOWN;
334804 + priv->old_duplex = DUPLEX_UNKNOWN;
334815 + return -ENOMEM;
334816 + tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR);
334817 + tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR);
334819 + return (tx_bq_rd_offset >> DESC_BYTE_SHIFT) + TX_DESC_NUM -
334820 + (tx_bq_wr_offset >> DESC_BYTE_SHIFT) - 1;
334825 + ld->sg_count = ld->TX_BQ.count + HIGMAC_SG_DESC_ADD;
334826 + if (has_cap_cci(ld->hw_cap)) {
334827 + ld->dma_sg_desc = kmalloc_array(ld->sg_count,
334830 + if (ld->dma_sg_desc)
334831 + ld->dma_sg_phy = virt_to_phys(ld->dma_sg_desc);
334833 + ld->dma_sg_desc = (struct sg_desc *)dma_alloc_coherent(ld->dev,
334834 + ld->sg_count * sizeof(struct sg_desc),
334835 + &ld->dma_sg_phy, GFP_KERNEL);
334838 + if (!ld->dma_sg_desc) {
334840 + return -ENOMEM;
334843 + pr_info("Higmac dma_sg_phy: 0x%pK\n", (void *)(uintptr_t)ld->dma_sg_phy);
334846 + ld->sg_head = 0;
334847 + ld->sg_tail = 0;
334854 + if (ld->dma_sg_desc) {
334855 + if (has_cap_cci(ld->hw_cap))
334856 + kfree(ld->dma_sg_desc);
334858 + dma_free_coherent(ld->dev,
334859 + ld->sg_count * sizeof(struct sg_desc),
334860 + ld->dma_sg_desc, ld->dma_sg_phy);
334861 + ld->dma_sg_desc = NULL;
334869 + start = readl(priv->gmac_iobase + RX_FQ_WR_ADDR);
334870 + end = readl(priv->gmac_iobase + RX_FQ_RD_ADDR);
334885 + start = readl(priv->gmac_iobase + rx_bq_rd_reg);
334886 + end = readl(priv->gmac_iobase + rx_bq_wr_reg);
334904 + if (ld->netdev == NULL) {
334905 + higmac_trace(HIGMAC_NORMAL_LEVEL, "ld->netdev is null");
334908 + dev_hold(ld->netdev);
334909 + dev = ld->netdev;
334917 + spin_lock(&ld->rxlock);
334922 + for (rxq_id = 0; rxq_id < ld->num_rxqs; rxq_id++) {
334924 + napi_schedule(&ld->q_napi[rxq_id].napi);
334927 + spin_unlock(&ld->rxlock);
334929 + ld->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
334930 + mod_timer(&ld->monitor, ld->monitor.expires);
334943 + dma_info.start = dma_cnt(readl(priv->gmac_iobase + RX_FQ_WR_ADDR));
334945 + dma_info.end = dma_cnt(readl(priv->gmac_iobase + RX_FQ_RD_ADDR));
334949 + if (priv->RX_FQ.skb[dma_info.pos] || priv->rx_skb[dma_info.pos])
334952 + skb = netdev_alloc_skb_ip_align(priv->netdev, len);
334956 + if (!has_cap_cci(priv->hw_cap)) {
334957 + addr = dma_map_single(priv->dev, skb->data, len,
334959 + if (dma_mapping_error(priv->dev, addr)) {
334964 + addr = virt_to_phys(skb->data);
334967 + desc = priv->RX_FQ.desc + dma_info.pos;
334968 + desc->data_buff_addr = (u32)addr;
334970 + desc->reserve31 = addr >> REG_BIT_WIDTH;
334972 + priv->RX_FQ.skb[dma_info.pos] = skb;
334973 + priv->rx_skb[dma_info.pos] = skb;
334975 + desc->buffer_len = len - 1;
334976 + desc->data_len = 0;
334977 + desc->fl = 0;
334978 + desc->descvid = DESC_VLD_FREE;
334979 + desc->skb_id = dma_info.pos;
334994 + writel(dma_byte(dma_info.pos), priv->gmac_iobase + RX_FQ_WR_ADDR);
335007 + len = desc->data_len;
335009 + if (!has_cap_cci(ld->hw_cap)) {
335010 + addr = desc->data_buff_addr;
335012 + addr |= (dma_addr_t)(desc->reserve31) << REG_BIT_WIDTH;
335014 + dma_unmap_single(ld->dev, addr, HIETH_MAX_FRAME_SIZE,
335019 + if (skb->len > HIETH_MAX_FRAME_SIZE) {
335020 + netdev_err(dev, "rcv len err, len = %d\n", skb->len);
335021 + dev->stats.rx_errors++;
335022 + dev->stats.rx_length_errors++;
335027 + skb->protocol = eth_type_trans(skb, dev);
335028 + skb->ip_summed = CHECKSUM_NONE;
335036 + if ((dev->features & NETIF_F_RXHASH) && desc->has_hash)
335037 + skb_set_hash(skb, desc->rxhash, desc->l3_hash ?
335042 + napi_gro_receive(&ld->q_napi[rxq_id].napi, skb);
335043 + dev->stats.rx_packets++;
335044 + dev->stats.rx_bytes += len;
335053 + spin_lock(&ld->rxlock);
335054 + skb = ld->rx_skb[skb_id];
335056 + spin_unlock(&ld->rxlock);
335058 + return -1;
335062 + if (unlikely(skb != ld->RX_FQ.skb[skb_id])) {
335063 + netdev_err(dev, "desc->skb(0x%p),RX_FQ.skb[%d](0x%p)\n",
335064 + skb, skb_id, ld->RX_FQ.skb[skb_id]);
335065 + if (ld->RX_FQ.skb[skb_id] == SKB_MAGIC) {
335066 + spin_unlock(&ld->rxlock);
335071 + ld->RX_FQ.skb[skb_id] = NULL;
335073 + spin_unlock(&ld->rxlock);
335092 + dma_info.start = dma_cnt(readl(ld->gmac_iobase + rx_bq_rd_reg));
335094 + dma_info.end = dma_cnt(readl(ld->gmac_iobase + rx_bq_wr_reg));
335103 + desc = ld->pool[BASE_QUEUE_NUMS + rxq_id].desc + dma_info.pos;
335105 + desc = ld->RX_BQ.desc + dma_info.pos;
335106 + skb_id = desc->skb_id;
335111 + spin_lock(&ld->rxlock);
335112 + ld->rx_skb[skb_id] = NULL;
335113 + spin_unlock(&ld->rxlock);
335118 + writel(dma_byte(dma_info.pos), ld->gmac_iobase + rx_bq_rd_reg);
335120 + spin_lock(&ld->rxlock);
335122 + spin_unlock(&ld->rxlock);
335136 + unsigned int tx_err = tx_bq_desc->tx_err;
335145 + tx_bq_desc->data_buff_addr,
335146 + tx_bq_desc->desc1.val, tx_bq_desc->tx_err);
335148 + desc_cur = ld->dma_sg_desc + ld->TX_BQ.sg_desc_offset[desc_pos];
335154 + return -1;
335164 + int nfrags = tx_rq_desc->desc1.tx.nfrags_num;
335170 + desc_offset = ld->TX_BQ.sg_desc_offset[desc_pos];
335171 + WARN_ON(desc_offset != ld->sg_tail);
335172 + desc_cur = ld->dma_sg_desc + desc_offset;
335174 + addr = desc_cur->linear_addr;
335176 + addr |= (dma_addr_t)(desc_cur->reserv3 >>
335180 + len = desc_cur->linear_len;
335181 + dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE);
335183 + addr = desc_cur->frags[i].addr;
335186 + (desc_cur->frags[i].reserved >>
335190 + len = desc_cur->frags[i].size;
335191 + dma_unmap_page(ld->dev, addr, len,
335200 + int nfrags = tx_rq_desc->desc1.tx.nfrags_num;
335209 + netif_carrier_off(ld->netdev);
335210 + netif_stop_queue(ld->netdev);
335212 + phy_stop(ld->phy);
335213 + del_timer_sync(&ld->monitor);
335214 + return -1;
335217 + if (tx_rq_desc->desc1.tx.tso_flag || nfrags)
335223 + if (!has_cap_cci(ld->hw_cap)) {
335224 + addr = tx_rq_desc->data_buff_addr;
335226 + addr |= (dma_addr_t)(tx_rq_desc->reserve_desc2 &
335230 + len = tx_rq_desc->desc1.tx.data_len;
335231 + dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE);
335234 + if (!has_cap_cci(ld->hw_cap))
335237 + ld->sg_tail = (ld->sg_tail + 1) % ld->sg_count;
335257 + if (priv->tso_supported) {
335260 + } else if (!has_cap_cci(priv->hw_cap)) {
335261 + addr = desc->data_buff_addr;
335263 + addr |= (dma_addr_t)(desc->rxhash & TX_DESC_HI8_MASK) <<
335266 + dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE);
335281 + spin_lock(&priv->txlock);
335284 + dma_info.start = dma_cnt(readl(priv->gmac_iobase + TX_RQ_RD_ADDR));
335286 + dma_info.end = dma_cnt(readl(priv->gmac_iobase + TX_RQ_WR_ADDR));
335290 + skb = priv->tx_skb[dma_info.pos];
335296 + if (skb != priv->TX_BQ.skb[dma_info.pos]) {
335298 + dma_info.pos, priv->TX_BQ.skb[dma_info.pos], skb);
335299 + if (priv->TX_BQ.skb[dma_info.pos] == SKB_MAGIC)
335304 + bytes_compl += skb->len;
335305 + desc = priv->TX_RQ.desc + dma_info.pos;
335309 + priv->TX_BQ.skb[dma_info.pos] = NULL;
335311 + priv->tx_skb[dma_info.pos] = NULL;
335317 + writel(dma_byte(dma_info.pos), priv->gmac_iobase + TX_RQ_RD_ADDR);
335322 + if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl)
335323 + netif_wake_queue(priv->netdev);
335325 + spin_unlock(&priv->txlock);
335332 + struct higmac_netdev_local *priv = q_napi->ndev_priv;
335338 + dev_hold(priv->netdev);
335339 + if (q_napi->rxq_id) {
335341 + raw_int_mask = def_int_mask_queue((u32)q_napi->rxq_id);
335348 + if (!q_napi->rxq_id)
335349 + higmac_xmit_reclaim(priv->netdev);
335350 + num = higmac_rx(priv->netdev, budget - work_done, q_napi->rxq_id);
335355 + ints = readl(priv->gmac_iobase + raw_int_reg);
335357 + writel(ints, priv->gmac_iobase + raw_int_reg);
335358 + } while (ints || higmac_rxq_has_packets(priv, q_napi->rxq_id));
335362 + higmac_irq_enable_queue(priv, q_napi->rxq_id);
335365 + dev_put(priv->netdev);
335372 + struct higmac_netdev_local *ld = q_napi->ndev_priv;
335376 + if (higmac_queue_irq_disabled(ld, q_napi->rxq_id))
335379 + if (q_napi->rxq_id) {
335381 + raw_int_mask = def_int_mask_queue((u32)q_napi->rxq_id);
335387 + ints = readl(ld->gmac_iobase + raw_int_reg);
335389 + writel(ints, ld->gmac_iobase + raw_int_reg);
335391 + if (likely(ints || higmac_rxq_has_packets(ld, q_napi->rxq_id))) {
335392 + higmac_irq_disable_queue(ld, q_napi->rxq_id);
335393 + napi_schedule(&q_napi->napi);
335403 + int nfrags = skb_shinfo(skb)->nr_frags;
335410 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
335411 + int len = frag->size;
335413 + if (!has_cap_cci(ld->hw_cap)) {
335414 + dma_addr = skb_frag_dma_map(ld->dev, frag, 0,
335416 + ret = dma_mapping_error(ld->dev, dma_addr);
335419 + return -EFAULT;
335421 + desc_cur->frags[i].addr = (u32)dma_addr;
335423 + desc_cur->frags[i].reserved =
335429 + page_to_phys(skb_frag_page(frag)) + frag->page_offset;
335430 + desc_cur->frags[i].addr = (u32)phys_addr;
335432 + desc_cur->frags[i].reserved =
335437 + desc_cur->frags[i].size = len;
335440 + addr = ld->dma_sg_phy + ld->sg_head * sizeof(struct sg_desc);
335441 + tx_bq_desc->data_buff_addr = (u32)addr;
335443 + tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
335446 + ld->TX_BQ.sg_desc_offset[desc_pos] = ld->sg_head;
335448 + ld->sg_head = (ld->sg_head + 1) % ld->sg_count;
335462 + if (unlikely(((ld->sg_head + 1) % ld->sg_count) == ld->sg_tail)) {
335465 + return -EBUSY;
335468 + desc_cur = ld->dma_sg_desc + ld->sg_head;
335471 + if (tx_bq_desc->desc1.tx.tso_flag &&
335472 + tx_bq_desc->desc1.tx.ip_ver == PKT_IPV6 &&
335473 + tx_bq_desc->desc1.tx.prot_type == PKT_UDP)
335474 + desc_cur->ipv6_id = ntohl(skb_shinfo(skb)->ip6_frag_id);
335476 + desc_cur->total_len = skb->len;
335477 + desc_cur->linear_len = skb_headlen(skb);
335478 + if (!has_cap_cci(ld->hw_cap)) {
335479 + dma_addr = dma_map_single(ld->dev, skb->data,
335480 + desc_cur->linear_len,
335482 + ret = dma_mapping_error(ld->dev, dma_addr);
335485 + return -EFAULT;
335487 + desc_cur->linear_addr = (u32)dma_addr;
335489 + desc_cur->reserv3 = (dma_addr >> REG_BIT_WIDTH) <<
335493 + phys_addr = virt_to_phys(skb->data);
335494 + desc_cur->linear_addr = (u32)phys_addr;
335496 + desc_cur->reserv3 = (phys_addr >> REG_BIT_WIDTH) <<
335512 + int nfrags = skb_shinfo(skb)->nr_frags;
335528 + if (!has_cap_cci(ld->hw_cap)) {
335529 + addr = dma_map_single(ld->dev, skb->data, skb->len, DMA_TO_DEVICE);
335530 + ret = dma_mapping_error(ld->dev, addr);
335533 + return -EFAULT;
335535 + tx_bq_desc->data_buff_addr = (u32)addr;
335537 + tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
335541 + addr = virt_to_phys(skb->data);
335542 + tx_bq_desc->data_buff_addr = (u32)addr;
335544 + tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) &
335572 + int gso_segs = skb_shinfo(skb)->gso_segs;
335573 + if (gso_segs == 0 && skb_shinfo(skb)->gso_size != 0)
335574 + gso_segs = DIV_ROUND_UP(skb->len, skb_shinfo(skb)->gso_size);
335578 + netif_stop_queue(ld->netdev);
335580 + ld->netdev->stats.tx_dropped++;
335581 + ld->netdev->stats.tx_fifo_errors++;
335584 + netif_wake_queue(ld->netdev);
335587 + segs = skb_gso_segment(skb, ld->netdev->features & ~(NETIF_F_CSUM_MASK |
335594 + segs = segs->next;
335595 + curr_skb->next = NULL;
335596 + ret = higmac_net_xmit(curr_skb, ld->netdev);
335606 + ld->netdev->stats.tx_dropped++;
335616 + if (!has_cap_cci(ld->hw_cap)) {
335617 + addr = dma_map_single(ld->dev, skb->data, skb->len, DMA_TO_DEVICE);
335618 + if (unlikely(dma_mapping_error(ld->dev, addr))) {
335620 + dev->stats.tx_dropped++;
335621 + ld->tx_skb[pos] = NULL;
335622 + ld->TX_BQ.skb[pos] = NULL;
335623 + return -1;
335625 + desc->data_buff_addr = (u32)addr;
335627 + desc->rxhash = (addr >> REG_BIT_WIDTH) & TX_DESC_HI8_MASK;
335630 + addr = virt_to_phys(skb->data);
335631 + desc->data_buff_addr = (u32)addr;
335633 + desc->rxhash = (addr >> REG_BIT_WIDTH) & TX_DESC_HI8_MASK;
335636 + desc->buffer_len = HIETH_MAX_FRAME_SIZE - 1;
335637 + desc->data_len = skb->len;
335638 + desc->fl = DESC_FL_FULL;
335639 + desc->descvid = DESC_VLD_BUSY;
335646 + if (skb->len < ETH_HLEN) {
335648 + dev->stats.tx_errors++;
335649 + dev->stats.tx_dropped++;
335650 + return -1;
335672 + pos = dma_cnt(readl(ld->gmac_iobase + TX_BQ_WR_ADDR));
335674 + spin_lock_irqsave(&ld->txlock, txflags);
335676 + if (unlikely(ld->tx_skb[pos] || ld->TX_BQ.skb[pos])) {
335677 + dev->stats.tx_dropped++;
335678 + dev->stats.tx_fifo_errors++;
335680 + spin_unlock_irqrestore(&ld->txlock, txflags);
335685 + ld->TX_BQ.skb[pos] = skb;
335686 + ld->tx_skb[pos] = skb;
335688 + desc = ld->TX_BQ.desc + pos;
335690 + if (ld->tso_supported) {
335693 + ld->tx_skb[pos] = NULL;
335694 + ld->TX_BQ.skb[pos] = NULL;
335695 + spin_unlock_irqrestore(&ld->txlock, txflags);
335697 + if (ret == -ENOTSUPP)
335701 + dev->stats.tx_dropped++;
335707 + spin_unlock_irqrestore(&ld->txlock, txflags);
335720 + writel(dma_byte(pos), ld->gmac_iobase + TX_BQ_WR_ADDR);
335723 + dev->stats.tx_packets++;
335724 + dev->stats.tx_bytes += skb->len;
335725 + netdev_sent_queue(dev, skb->len);
335727 + spin_unlock_irqrestore(&ld->txlock, txflags);
335738 + for (i = 0; i < priv->num_rxqs; i++) {
335739 + q_napi = &priv->q_napi[i];
335740 + napi_enable(&q_napi->napi);
335750 + for (i = 0; i < priv->num_rxqs; i++) {
335751 + q_napi = &priv->q_napi[i];
335752 + napi_disable(&q_napi->napi);
335761 + clk_prepare_enable(ld->macif_clk);
335762 + clk_prepare_enable(ld->clk);
335783 + phy_start(ld->phy);
335789 + spin_lock_irqsave(&ld->rxlock, flags);
335791 + spin_unlock_irqrestore(&ld->rxlock, flags);
335793 + ld->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
335794 + mod_timer(&ld->monitor, ld->monitor.expires);
335813 + phy_stop(ld->phy);
335814 + del_timer_sync(&ld->monitor);
335816 + clk_disable_unprepare(ld->clk);
335817 + clk_disable_unprepare(ld->macif_clk);
335824 + dev->stats.tx_errors++;
335839 + v = readl(ld->gmac_iobase + TSO_COE_CTRL);
335844 + writel(v, ld->gmac_iobase + TSO_COE_CTRL);
335851 + netdev_features_t changed = dev->features ^ features;
335865 + return &dev->stats;
335902 + ld->autoeee = of_property_read_bool(node, "autoeee");
335904 + ld->internal_phy =
335905 + of_property_read_bool(node, "internal-phy");
335914 + for (i = 0; i < QUEUE_NUMS + RSS_NUM_RXQS - 1; i++) {
335915 + if (priv->pool[i].desc) {
335916 + if (has_cap_cci(priv->hw_cap))
335917 + kfree(priv->pool[i].desc);
335919 + dma_free_coherent(priv->dev, priv->pool[i].size,
335920 + priv->pool[i].desc,
335921 + priv->pool[i].phys_addr);
335922 + priv->pool[i].desc = NULL;
335926 + kfree(priv->RX_FQ.skb);
335927 + kfree(priv->TX_BQ.skb);
335928 + priv->RX_FQ.skb = NULL;
335929 + priv->TX_BQ.skb = NULL;
335931 + if (priv->tso_supported) {
335932 + kfree(priv->TX_BQ.sg_desc_offset);
335933 + priv->TX_BQ.sg_desc_offset = NULL;
335936 + kfree(priv->tx_skb);
335937 + priv->tx_skb = NULL;
335939 + kfree(priv->rx_skb);
335940 + priv->rx_skb = NULL;
335945 + priv->RX_FQ.skb = kzalloc(priv->RX_FQ.count
335947 + if (!priv->RX_FQ.skb)
335948 + return -ENOMEM;
335950 + priv->rx_skb = kzalloc(priv->RX_FQ.count
335952 + if (priv->rx_skb == NULL)
335953 + return -ENOMEM;
335955 + priv->TX_BQ.skb = kzalloc(priv->TX_BQ.count
335957 + if (!priv->TX_BQ.skb)
335958 + return -ENOMEM;
335960 + priv->tx_skb = kzalloc(priv->TX_BQ.count
335962 + if (priv->tx_skb == NULL)
335963 + return -ENOMEM;
335965 + if (priv->tso_supported) {
335966 + priv->TX_BQ.sg_desc_offset = kzalloc(priv->TX_BQ.count
335968 + if (!priv->TX_BQ.sg_desc_offset)
335969 + return -ENOMEM;
335981 + if (priv == NULL || priv->dev == NULL)
335982 + return -EINVAL;
335983 + dev = priv->dev;
335985 + return -EINVAL;
335986 + priv->RX_FQ.count = RX_DESC_NUM;
335987 + priv->RX_BQ.count = RX_DESC_NUM;
335988 + priv->TX_BQ.count = TX_DESC_NUM;
335989 + priv->TX_RQ.count = TX_DESC_NUM;
335992 + priv->pool[BASE_QUEUE_NUMS + i].count = RX_DESC_NUM;
335994 + for (i = 0; i < (QUEUE_NUMS + RSS_NUM_RXQS - 1); i++) {
335995 + size = priv->pool[i].count * sizeof(struct higmac_desc);
335996 + if (has_cap_cci(priv->hw_cap)) {
336010 + priv->pool[i].size = size;
336011 + priv->pool[i].desc = virt_addr;
336012 + priv->pool[i].phys_addr = phys_addr;
336015 + if (higmac_init_desc_queue_mem(priv) == -ENOMEM)
336019 + if (has_cap_cci(priv->hw_cap))
336027 + return -ENOMEM;
336034 + if (priv == NULL || priv->netdev == NULL)
336036 + for (i = 0; i < priv->num_rxqs; i++) {
336037 + q_napi = &priv->q_napi[i];
336038 + q_napi->rxq_id = i;
336039 + q_napi->ndev_priv = priv;
336040 + netif_napi_add(priv->netdev, &q_napi->napi, higmac_poll,
336051 + for (i = 0; i < priv->num_rxqs; i++) {
336052 + q_napi = &priv->q_napi[i];
336053 + netif_napi_del(&q_napi->napi);
336063 + if (pdev == NULL || priv == NULL || priv->dev == NULL || pdev->name == NULL)
336064 + return -ENOMEM;
336066 + dev = priv->dev;
336067 + for (i = 0; i < priv->num_rxqs; i++) {
336073 + priv->irq[i] = ret;
336075 + ret = devm_request_irq(dev, priv->irq[i], higmac_interrupt,
336076 + IRQF_SHARED, pdev->name,
336077 + &priv->q_napi[i]);
336090 + struct device *dev = &pdev->dev;
336091 + struct net_device *ndev = priv->netdev;
336096 + priv->gmac_iobase = devm_ioremap_resource(dev, res);
336097 + if (IS_ERR(priv->gmac_iobase)) {
336098 + ret = PTR_ERR(priv->gmac_iobase);
336103 + priv->macif_base = devm_ioremap_resource(dev, res);
336104 + if (IS_ERR(priv->macif_base)) {
336105 + ret = PTR_ERR(priv->macif_base);
336111 + priv->axi_bus_cfg_base = devm_ioremap_resource(dev, res);
336112 + if (IS_ERR(priv->axi_bus_cfg_base))
336113 + priv->axi_bus_cfg_base = NULL;
336115 + priv->port_rst = devm_reset_control_get(dev, HIGMAC_PORT_RST_NAME);
336116 + if (IS_ERR(priv->port_rst)) {
336117 + ret = PTR_ERR(priv->port_rst);
336121 + priv->macif_rst = devm_reset_control_get(dev, HIGMAC_MACIF_RST_NAME);
336122 + if (IS_ERR(priv->macif_rst)) {
336123 + ret = PTR_ERR(priv->macif_rst);
336127 + priv->phy_rst = devm_reset_control_get(dev, HIGMAC_PHY_RST_NAME);
336128 + if (IS_ERR(priv->phy_rst))
336129 + priv->phy_rst = NULL;
336131 + priv->clk = devm_clk_get(&pdev->dev, HIGMAC_MAC_CLK_NAME);
336132 + if (IS_ERR(priv->clk)) {
336134 + ret = -ENODEV;
336138 + ret = clk_prepare_enable(priv->clk);
336151 + priv->macif_clk = devm_clk_get(&pdev->dev, HIGMAC_MACIF_CLK_NAME);
336152 + if (IS_ERR(priv->macif_clk))
336153 + priv->macif_clk = NULL;
336155 + if (priv->macif_clk != NULL) {
336156 + ret = clk_prepare_enable(priv->macif_clk);
336171 + spin_lock_init(&priv->rxlock);
336172 + spin_lock_init(&priv->txlock);
336173 + spin_lock_init(&priv->pmtlock);
336176 + ndev->irq = priv->irq[0];
336177 + ndev->watchdog_timeo = 3 * HZ; /* 3HZ */
336178 + ndev->netdev_ops = &hieth_netdev_ops;
336179 + ndev->ethtool_ops = &hieth_ethtools_ops;
336181 + if (priv->has_rxhash_cap)
336182 + ndev->hw_features |= NETIF_F_RXHASH;
336183 + if (priv->has_rss_cap)
336184 + ndev->hw_features |= NETIF_F_NTUPLE;
336185 + if (priv->tso_supported)
336186 + ndev->hw_features |= NETIF_F_SG |
336191 + ndev->hw_features |= NETIF_F_RXCSUM;
336195 + ndev->features |= ndev->hw_features;
336196 + ndev->features |= NETIF_F_HIGHDMA | NETIF_F_GSO;
336197 + ndev->vlan_features |= ndev->features;
336199 + timer_setup(&priv->monitor, higmac_monitor_func, 0);
336201 + device_set_wakeup_capable(priv->dev, 1);
336207 + device_set_wakeup_enable(priv->dev, 1);
336209 + priv->wol_enable = false;
336211 + priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
336214 + if (!has_cap_cci(priv->hw_cap)) {
336215 + struct device *dev = &pdev->dev;
336241 + priv->phy = of_phy_connect(ndev, priv->phy_node,
336242 + &higmac_adjust_link, 0, priv->phy_mode);
336243 + if (priv->phy == NULL || priv->phy->drv == NULL) {
336244 + ret = -ENODEV;
336249 + if ((priv->phy->phy_id == 0) && !fixed_link) {
336250 + pr_info("phy %d not found\n", priv->phy->mdio.addr);
336251 + ret = -ENODEV;
336256 + priv->phy->mdio.addr, priv->phy->drv->name, priv->phy->phy_id);
336259 + if ((priv->phy_mode == PHY_INTERFACE_MODE_MII) ||
336260 + (priv->phy_mode == PHY_INTERFACE_MODE_RMII)) {
336261 + priv->phy->advertising &= ~(SUPPORTED_1000baseT_Half |
336268 + if (priv->phy->phy_id == HISILICON_PHY_ID_FESTAV200)
336269 + priv->phy->supported &= ~(ADVERTISED_1000baseT_Full |
336275 + priv->phy->supported |= SUPPORTED_Pause;
336276 + if (priv->flow_ctrl)
336277 + priv->phy->advertising |= SUPPORTED_Pause;
336279 + if (priv->autoeee)
336294 + hw_cap = readl(priv->gmac_iobase + CRF_MIN_PACKET);
336295 + priv->tso_supported = has_tso_cap(hw_cap);
336296 + priv->has_rxhash_cap = has_rxhash_cap(hw_cap);
336297 + priv->has_rss_cap = has_rss_cap(hw_cap);
336301 + if (priv->has_rss_cap) {
336302 + priv->rss_info.ind_tbl_size = RSS_INDIRECTION_TABLE_SIZE;
336306 + if (priv->has_rxhash_cap) {
336307 + priv->rss_info.hash_cfg = DEF_HASH_CFG;
336319 + ether_addr_copy(ndev->dev_addr, mac_addr);
336320 + if (!is_valid_ether_addr(ndev->dev_addr)) {
336323 + ndev->dev_addr);
336344 + netdev_err(ndev, "not find phy-mode\n");
336347 + priv->phy_mode = ret;
336349 + priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
336350 + if (priv->phy_node == NULL) {
336351 + /* check if a fixed-link is defined in device-tree */
336363 + priv->phy_node = of_node_get(node);
336366 + netdev_err(ndev, "not find phy-handle\n");
336367 + ret = -EINVAL;
336377 + struct device *dev = &pdev->dev;
336378 + struct device_node *node = dev->of_node;
336385 + if (of_device_is_compatible(node, "hisilicon,higmac-v5"))
336393 + return -ENOMEM;
336399 + priv->dev = dev;
336401 + priv->netdev = ndev;
336402 + priv->num_rxqs = num_rxqs;
336404 + if (of_device_is_compatible(node, "hisilicon,higmac-v3"))
336405 + priv->hw_cap |= HW_CAP_CCI;
336421 + if (priv->tso_supported) {
336428 + ret = register_netdev(priv->netdev);
336444 + clk_disable_unprepare(priv->clk);
336445 + if (priv->macif_clk != NULL)
336446 + clk_disable_unprepare(priv->macif_clk);
336449 + phy_modes(priv->phy_mode), priv->phy->mdio.addr);
336455 + if (priv->tso_supported)
336466 + struct device *dev = &pdev->dev;
336467 + struct device_node *node = dev->of_node;
336499 + if (priv->phy == NULL)
336512 + phy_disconnect(priv->phy);
336514 + of_node_put(priv->phy_node);
336516 + if (priv->macif_clk != NULL)
336517 + clk_disable_unprepare(priv->macif_clk);
336519 + clk_disable_unprepare(priv->clk);
336533 + del_timer_sync(&priv->monitor);
336542 + if (priv->tso_supported)
336546 + phy_disconnect(priv->phy);
336547 + of_node_put(priv->phy_node);
336561 + for (i = 0; i < priv->num_rxqs; i++)
336562 + disable_irq(priv->irq[i]);
336569 + for (i = 0; i < priv->num_rxqs; i++)
336570 + enable_irq(priv->irq[i]);
336583 + if (!priv->wol_enable)
336584 + phy_disconnect(priv->phy);
336585 + del_timer_sync(&priv->monitor);
336601 + if (!(ndev->flags & IFF_UP))
336602 + clk_prepare_enable(priv->clk);
336606 + if (!(ndev->flags & IFF_UP))
336607 + clk_disable_unprepare(priv->clk);
336611 + if (!priv->wol_enable) {
336617 + genphy_suspend(priv->phy); /* power down phy */
336635 + * by re-write the mac CRG register.
336638 + if (priv->wol_enable)
336647 + * So if we want to restart MAC and re-initialize it,
336650 + if (!(ndev->flags & IFF_UP))
336651 + clk_prepare_enable(priv->clk);
336662 + if (priv->wol_enable)
336663 + phy_disconnect(priv->phy);
336665 + ret = phy_connect_direct(ndev, priv->phy, higmac_adjust_link,
336666 + priv->phy_mode);
336674 + if (ndev->flags & IFF_UP) {
336675 + priv->monitor.expires = jiffies + HIGMAC_MONITOR_TIMER;
336676 + mod_timer(&priv->monitor, priv->monitor.expires);
336677 + priv->old_link = 0;
336678 + priv->old_speed = SPEED_UNKNOWN;
336679 + priv->old_duplex = DUPLEX_UNKNOWN;
336684 + if (ndev->flags & IFF_UP)
336685 + phy_start(priv->phy);
336690 + if (!(ndev->flags & IFF_UP))
336691 + clk_disable_unprepare(priv->clk);
336703 + { .compatible = "hisilicon,higmac-v1", },
336704 + { .compatible = "hisilicon,higmac-v2", },
336705 + { .compatible = "hisilicon,higmac-v3", },
336706 + { .compatible = "hisilicon,higmac-v4", },
336707 + { .compatible = "hisilicon,higmac-v5", },
336753 diff --git a/drivers/net/ethernet/hisilicon/higmac/higmac.h b/drivers/net/ethernet/hisilicon/higmac…
336756 --- /dev/null
336758 @@ -0,0 +1,603 @@
336760 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
336763 + * Create: 2018-10-08
336841 +#define Q_ADDR_HI8_MASK (BIT(Q_ADDR_HI8_OFFSET) - 1)
336931 + ((i) - 1) * 0x10)
336936 +#define rss_ena_int_queue(i) (RSS_QUEUE1_ENA_INT + ((i) - 1) * 0x4)
336937 +#define rx_bq_depth_queue(i) (RSS_QUEUE1_DEPTH + ((i) - 1) * 0x10)
336939 + ((i) - 1) * 0x10) : RX_BQ_WR_ADDR)
336941 + ((i) - 1) * 0x10) : RX_BQ_RD_ADDR)
336943 +#define def_int_mask_queue(i) (0x3 << (2 * ((i) - 1)))
337097 +#define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
337250 + int index; /* 0 -- mac0, 1 -- mac1 */
337273 + } pool[QUEUE_NUMS + RSS_NUM_RXQS - 1];
337362 diff --git a/drivers/net/ethernet/hisilicon/higmac/pm.c b/drivers/net/ethernet/hisilicon/higmac/pm.c
337365 --- /dev/null
337367 @@ -0,0 +1,341 @@
337369 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
337372 + * Create: 2018-10-08
337405 + pm_reg_config_backup.pmt_ctrl = readl(ld->gmac_iobase + PMT_CTRL);
337406 + pm_reg_config_backup.pmt_mask0 = readl(ld->gmac_iobase + PMT_MASK0);
337407 + pm_reg_config_backup.pmt_mask1 = readl(ld->gmac_iobase + PMT_MASK1);
337408 + pm_reg_config_backup.pmt_mask2 = readl(ld->gmac_iobase + PMT_MASK2);
337409 + pm_reg_config_backup.pmt_mask3 = readl(ld->gmac_iobase + PMT_MASK3);
337410 + pm_reg_config_backup.pmt_cmd = readl(ld->gmac_iobase + PMT_CMD);
337411 + pm_reg_config_backup.pmt_offset = readl(ld->gmac_iobase + PMT_OFFSET);
337412 + pm_reg_config_backup.pmt_crc1_0 = readl(ld->gmac_iobase + PMT_CRC1_0);
337413 + pm_reg_config_backup.pmt_crc3_2 = readl(ld->gmac_iobase + PMT_CRC3_2);
337432 + * 1 0 * all pkts can wake-up(non-exist)
337433 + * 1 1 0 all pkts can wake-up
337438 + if (config->filter[i].valid) {
337439 + if (config->filter[i].offset < PM_FILTER_OFFSET_MIN)
337442 + offset |= config->filter[i].offset << (i * 8);
337451 + v = config->filter[i].mask_bytes;
337453 + writel(v, ld->gmac_iobase + reg_mask);
337456 + crc[i] = calculate_crc16(config->filter[i].value, v);
337458 + v = readl(ld->gmac_iobase + PMT_CRC1_0);
337461 + writel(v, ld->gmac_iobase + PMT_CRC1_0);
337463 + v = readl(ld->gmac_iobase + PMT_CRC3_2);
337464 + v &= ~(0xFFFF << (16 * (i - 2))); /* filer 2 3, 16 bits mask */
337465 + v |= crc[i] << (16 * (i - 2)); /* filer 2 3, 16 bits mask */
337466 + writel(v, ld->gmac_iobase + PMT_CRC3_2);
337472 + writel(offset, ld->gmac_iobase + PMT_OFFSET);
337473 + writel(cmd, ld->gmac_iobase + PMT_CMD);
337483 + return -EINVAL;
337485 + spin_lock_irqsave(&ld->pmtlock, flags);
337486 + if (config->wakeup_pkts_enable) {
337488 + v = readl(ld->gmac_iobase + PMT_CTRL);
337490 + writel(v, ld->gmac_iobase + PMT_CTRL); /* any side effect? */
337499 + if (config->uc_pkts_enable)
337501 + if (config->wakeup_pkts_enable)
337503 + if (config->magic_pkts_enable)
337507 + writel(v, ld->gmac_iobase + PMT_CTRL);
337511 + spin_unlock_irqrestore(&ld->pmtlock, flags);
337516 +/* pmt_config will overwrite pre-config */
337530 + priv->pm_state = PM_SET;
337531 + priv->wol_enable = true;
337532 + device_set_wakeup_enable(priv->dev, 1);
337542 + return -EINVAL;
337543 + spin_lock_irqsave(&ld->pmtlock, flags);
337544 + if (ld->pm_state == PM_SET) {
337547 + v = readl(ld->gmac_iobase + PMT_CTRL);
337551 + writel(v, ld->gmac_iobase + PMT_CTRL);
337553 + ld->pm_state = PM_CLEAR;
337556 + spin_unlock_irqrestore(&ld->pmtlock, flags);
337567 + spin_lock_irqsave(&ld->pmtlock, flags);
337569 + v = readl(ld->gmac_iobase + PMT_CTRL);
337574 + writel(v, ld->gmac_iobase + PMT_CTRL);
337576 + spin_unlock_irqrestore(&ld->pmtlock, flags);
337578 + ld->wol_enable = false;
337587 + spin_lock_irqsave(&ld->pmtlock, flags);
337589 + writel(v, ld->gmac_iobase + PMT_MASK0);
337592 + writel(v, ld->gmac_iobase + PMT_MASK1);
337595 + writel(v, ld->gmac_iobase + PMT_MASK2);
337598 + writel(v, ld->gmac_iobase + PMT_MASK3);
337601 + writel(v, ld->gmac_iobase + PMT_CMD);
337604 + writel(v, ld->gmac_iobase + PMT_OFFSET);
337607 + writel(v, ld->gmac_iobase + PMT_CRC1_0);
337610 + writel(v, ld->gmac_iobase + PMT_CRC3_2);
337613 + writel(v, ld->gmac_iobase + PMT_CTRL);
337614 + spin_unlock_irqrestore(&ld->pmtlock, flags);
337621 +#define CRC_NAME "CRC-16"
337630 +#define TOPBIT BIT(WIDTH - 1)
337660 + reversed |= BIT((nbits - 1) - bit);
337676 + /* Start with the dividend followed by zeros, WIDTH - 8. */
337677 + remainder = (unsigned short)(dividend << (WIDTH - 8));
337679 + /* Perform modulo-2 division, a bit at a time for 8 times. */
337680 + for (bit = 8; bit > 0; --bit) {
337702 + data = reverse_data(message[byte]) ^ (remainder >> (WIDTH - 8));
337709 diff --git a/drivers/net/ethernet/hisilicon/higmac/pm.h b/drivers/net/ethernet/hisilicon/higmac/pm.h
337712 --- /dev/null
337714 @@ -0,0 +1,59 @@
337716 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
337719 + * Create: 2020-05-19
337731 + unsigned char index; /* bit0--eth0 bit1--eth1 */
337775 diff --git a/drivers/net/ethernet/hisilicon/higmac/proc_dev.c b/drivers/net/ethernet/hisilicon/higm…
337778 --- /dev/null
337780 @@ -0,0 +1,119 @@
337782 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
337785 + * Create: 2018-10-08
337833 + * |---hw_stats
337834 + * |---skb_pools
337870 + return -EINVAL;
337874 + if (rq->ifr_data == NULL ||
337875 + copy_from_user(&config, rq->ifr_data, sizeof(config)))
337876 + return -EFAULT;
337880 + if (rq->ifr_data == NULL || copy_from_user(&val, rq->ifr_data, sizeof(val)))
337881 + return -EFAULT;
337885 + if (rq->ifr_data == NULL || copy_from_user(&val, rq->ifr_data, sizeof(val)))
337886 + return -EFAULT;
337891 + return -EINVAL;
337893 + if (priv->phy == NULL)
337894 + return -EINVAL;
337896 + return phy_mii_ioctl(priv->phy, rq, cmd);
337900 diff --git a/drivers/net/ethernet/hisilicon/higmac/sockioctl.h b/drivers/net/ethernet/hisilicon/hig…
337903 --- /dev/null
337905 @@ -0,0 +1,19 @@
337907 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
337910 + * Create: 2018-10-08
337919 +#define SIOCSETSUSPEND (SIOCDEVPRIVATE + 5) /* call dev->suspend, debug */
337920 +#define SIOCSETRESUME (SIOCDEVPRIVATE + 6) /* call dev->resume, debug */
337925 diff --git a/drivers/net/ethernet/hisilicon/higmac/tso.h b/drivers/net/ethernet/hisilicon/higmac/ts…
337928 --- /dev/null
337930 @@ -0,0 +1,59 @@
337932 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
337935 + * Create: 2018-10-08
337990 diff --git a/drivers/net/ethernet/hisilicon/higmac/util.c b/drivers/net/ethernet/hisilicon/higmac/u…
337993 --- /dev/null
337995 @@ -0,0 +1,975 @@
337997 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
338000 + * Create: 2020-05-19
338034 + switch (priv->phy_mode) {
338064 + reset_control_assert(priv->macif_rst);
338065 + writel_relaxed(val, priv->macif_base);
338066 + reset_control_deassert(priv->macif_rst);
338068 + writel_relaxed(BIT_MODE_CHANGE_EN, priv->gmac_iobase + MODE_CHANGE_EN);
338075 + writel_relaxed(val, priv->gmac_iobase + PORT_MODE);
338076 + writel_relaxed(0, priv->gmac_iobase + MODE_CHANGE_EN);
338077 + writel_relaxed(duplex, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL);
338086 + return -EINVAL;
338087 + if (dev->features & NETIF_F_RXCSUM) {
338088 + hdr_csum_done = desc->header_csum_done;
338089 + payload_csum_done = desc->payload_csum_done;
338090 + hdr_csum_err = desc->header_csum_err;
338091 + payload_csum_err = desc->payload_csum_err;
338095 + dev->stats.rx_errors++;
338096 + dev->stats.rx_crc_errors++;
338098 + return -1;
338100 + skb->ip_summed = CHECKSUM_UNNECESSARY;
338149 + ld->flow_ctrl = flow_ctrl_en;
338150 + ld->pause = tx_flow_ctrl_pause_time;
338151 + ld->pause_interval = tx_flow_ctrl_pause_interval;
338152 + ld->flow_ctrl_active_threshold = tx_flow_ctrl_active_threshold;
338153 + ld->flow_ctrl_deactive_threshold = tx_flow_ctrl_deactive_threshold;
338165 + writel(ld->pause, ld->gmac_iobase + FC_TX_TIMER);
338166 + writel(ld->pause_interval, ld->gmac_iobase + PAUSE_THR);
338168 + rx_fq_empty_th = readl(ld->gmac_iobase + RX_FQ_ALEMPTY_TH);
338170 + rx_fq_empty_th |= (ld->flow_ctrl_active_threshold <<
338172 + writel(rx_fq_empty_th, ld->gmac_iobase + RX_FQ_ALEMPTY_TH);
338174 + rx_fq_full_th = readl(ld->gmac_iobase + RX_FQ_ALFULL_TH);
338176 + rx_fq_full_th |= (ld->flow_ctrl_deactive_threshold <<
338178 + writel(rx_fq_full_th, ld->gmac_iobase + RX_FQ_ALFULL_TH);
338180 + rx_bq_empty_th = readl(ld->gmac_iobase + RX_BQ_ALEMPTY_TH);
338182 + rx_bq_empty_th |= (ld->flow_ctrl_active_threshold <<
338184 + writel(rx_bq_empty_th, ld->gmac_iobase + RX_BQ_ALEMPTY_TH);
338186 + rx_bq_full_th = readl(ld->gmac_iobase + RX_BQ_ALFULL_TH);
338188 + rx_bq_full_th |= (ld->flow_ctrl_deactive_threshold <<
338190 + writel(rx_bq_full_th, ld->gmac_iobase + RX_BQ_ALFULL_TH);
338192 + writel(0, ld->gmac_iobase + CRF_TX_PAUSE);
338194 + rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL);
338196 + writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL);
338205 + flow_rx_q_en = readl(ld->gmac_iobase + RX_PAUSE_EN);
338207 + if (pause && (ld->flow_ctrl & FLOW_TX))
338209 + writel(flow_rx_q_en, ld->gmac_iobase + RX_PAUSE_EN);
338211 + flow = readl(ld->gmac_iobase + PAUSE_EN);
338214 + if (ld->flow_ctrl & FLOW_RX)
338216 + if (ld->flow_ctrl & FLOW_TX)
338219 + writel(flow, ld->gmac_iobase + PAUSE_EN);
338226 + l3_proto = skb->protocol;
338227 + if (skb->protocol == htons(ETH_P_8021Q))
338240 + l4_proto = ip_hdr(skb)->protocol;
338242 + l4_proto = ipv6_hdr(skb)->nexthdr;
338262 + eth = (struct ethhdr *)(skb->data);
338263 + if (skb_is_gso(skb) && is_broadcast_ether_addr(eth->h_dest))
338264 + return -ENOTSUPP;
338273 + l4_proto = ipv6_hdr(skb)->nexthdr;
338282 + return -ENOTSUPP;
338284 + if (skb->ip_summed == CHECKSUM_PARTIAL &&
338286 + return -EFAULT;
338295 + (ip_hdr(skb)->ihl > IPV4_HEAD_LENGTH));
338303 + * if tcp_mtu_probe() use (2 * tp->mss_cache) as probe_size,
338308 + return -EINVAL;
338310 + return -ENOTSUPP;
338324 + if (((skb->ip_summed == CHECKSUM_PARTIAL) || skb_is_gso(skb)) &&
338326 + return -ENOTSUPP;
338339 + csum = skb_checksum(skb, offset, skb->len - offset, 0);
338341 + offset += skb->csum_offset;
338347 + *(__sum16 *)(skb->data + offset) = udp_csum;
338349 + skb->ip_summed = CHECKSUM_NONE;
338357 + int max_data_len = skb->len - ETH_HLEN;
338359 + l3_proto = skb->protocol;
338360 + if (skb->protocol == htons(ETH_P_8021Q)) {
338362 + tx_bq_desc->desc1.tx.vlan_flag = 1;
338363 + max_data_len -= VLAN_HLEN;
338370 + tx_bq_desc->desc1.tx.ip_ver = PKT_IPV4;
338371 + tx_bq_desc->desc1.tx.ip_hdr_len = iph->ihl;
338374 + (ntohs(iph->tot_len) <= (iph->ihl << 2))) /* shift left 2 */
338375 + iph->tot_len = htons(GSO_MAX_SIZE - 1);
338377 + *max_mss -= iph->ihl * WORD_TO_BYTE;
338378 + *l4_proto = iph->protocol;
338380 + tx_bq_desc->desc1.tx.ip_ver = PKT_IPV6;
338381 + tx_bq_desc->desc1.tx.ip_hdr_len = PKT_IPV6_HDR_LEN;
338382 + *max_mss -= PKT_IPV6_HDR_LEN * WORD_TO_BYTE;
338383 + *l4_proto = ipv6_hdr(skb)->nexthdr;
338389 + tx_bq_desc->desc1.tx.prot_type = PKT_TCP;
338390 + if (tcp_hdr(skb)->doff < sizeof(struct tcphdr) / WORD_TO_BYTE)
338391 + return -EFAULT;
338392 + tx_bq_desc->desc1.tx.prot_hdr_len = tcp_hdr(skb)->doff;
338393 + *max_mss -= tcp_hdr(skb)->doff * WORD_TO_BYTE;
338395 + tx_bq_desc->desc1.tx.prot_type = PKT_UDP;
338396 + tx_bq_desc->desc1.tx.prot_hdr_len = PKT_UDP_HDR_LEN;
338398 + *max_mss -= sizeof(struct frag_hdr);
338415 + return -EINVAL;
338417 + nfrags = skb_shinfo(skb)->nr_frags;
338418 + if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
338421 + tx_bq_desc->desc1.val = 0;
338424 + tx_bq_desc->desc1.tx.tso_flag = 1;
338425 + tx_bq_desc->desc1.tx.sg_flag = 1;
338427 + tx_bq_desc->desc1.tx.sg_flag = 1;
338436 + tx_bq_desc->desc1.tx.data_len =
338437 + (skb_shinfo(skb)->gso_size > max_mss) ? max_mss :
338438 + skb_shinfo(skb)->gso_size;
338440 + tx_bq_desc->desc1.tx.data_len = skb->len;
338446 + tx_bq_desc->desc1.tx.coe_flag = 1;
338448 + tx_bq_desc->desc1.tx.nfrags_num = nfrags;
338450 + tx_bq_desc->desc1.tx.hw_own = DESC_VLD_BUSY;
338459 + strncpy(info->driver, "higmac driver", sizeof(info->driver));
338460 + strncpy(info->version, "higmac v200", sizeof(info->version));
338461 + strncpy(info->bus_info, "platform", sizeof(info->bus_info));
338468 + return ld->phy->link ? HIGMAC_LINKED : 0;
338476 + if (ld->phy != NULL)
338477 + return phy_ethtool_gset(ld->phy, cmd);
338479 + return -EINVAL;
338488 + return -EPERM;
338490 + if (ld->phy != NULL)
338491 + return phy_ethtool_sset(ld->phy, cmd);
338493 + return -EINVAL;
338504 + pause->rx_pause = 0;
338505 + pause->tx_pause = 0;
338506 + pause->autoneg = ld->phy->autoneg;
338508 + if (ld->flow_ctrl & FLOW_RX)
338509 + pause->rx_pause = 1;
338510 + if (ld->flow_ctrl & FLOW_TX)
338511 + pause->tx_pause = 1;
338518 + struct phy_device *phy = ld->phy;
338522 + return -ENOMEM;
338524 + if (pause->rx_pause)
338526 + if (pause->tx_pause)
338529 + if (new_pause != ld->flow_ctrl)
338530 + ld->flow_ctrl = new_pause;
338532 + higmac_set_flow_ctrl_state(ld, phy->pause);
338533 + phy->advertising &= ~SUPPORTED_Pause;
338534 + if (ld->flow_ctrl)
338535 + phy->advertising |= SUPPORTED_Pause;
338537 + if (phy->autoneg) {
338549 + return priv->msg_enable;
338556 + priv->msg_enable = level;
338568 + return priv->rss_info.ind_tbl_size;
338575 + struct higmac_rss_info *rss = &priv->rss_info;
338581 + memcpy(hkey, rss->key, RSS_HASH_KEY_SIZE);
338586 + for (i = 0; i < rss->ind_tbl_size; i++)
338587 + indir[i] = rss->ind_tbl[i];
338599 + rss = &priv->rss_info;
338600 + hkey = readl(priv->gmac_iobase + RSS_HASH_KEY);
338601 + *((u32 *)rss->key) = hkey;
338606 + struct higmac_rss_info *rss = &priv->rss_info;
338608 + writel(*((u32 *)rss->key), priv->gmac_iobase + RSS_HASH_KEY);
338613 + void __iomem *base = priv->gmac_iobase;
338619 + netdev_err(priv->netdev, "wait rss ready timeout!\n");
338620 + return -ETIMEDOUT;
338635 + rss = &priv->rss_info;
338636 + for (i = 0; i < rss->ind_tbl_size; i++) {
338639 + rss_val = BIT_IND_TLB_WR | (rss->ind_tbl[i] << 8) | i; /* shift 8 */
338640 + writel(rss_val, priv->gmac_iobase + RSS_IND_TBL);
338651 + rss = &priv->rss_info;
338652 + for (i = 0; i < rss->ind_tbl_size; i++) {
338655 + writel(i, priv->gmac_iobase + RSS_IND_TBL);
338658 + rss_val = readl(priv->gmac_iobase + RSS_IND_TBL);
338659 + rss->ind_tbl[i] = (rss_val >> 10) & 0x3; /* right shift 10 */
338667 + struct higmac_rss_info *rss = &priv->rss_info;
338670 + return -EOPNOTSUPP;
338675 + for (i = 0; i < rss->ind_tbl_size; i++)
338676 + rss->ind_tbl[i] = indir[i];
338680 + memcpy(rss->key, hkey, RSS_HASH_KEY_SIZE);
338693 + info->data |= RXH_IP_SRC | RXH_IP_DST;
338695 + info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
338697 + info->data |= RXH_VLAN;
338703 + u32 hash_cfg = priv->rss_info.hash_cfg;
338705 + info->data = 0;
338707 + switch (info->flow_type) {
338733 + return -EINVAL;
338743 + int ret = -EOPNOTSUPP;
338745 + return -EINVAL;
338746 + switch (info->cmd) {
338748 + info->data = priv->num_rxqs;
338763 + writel(priv->rss_info.hash_cfg, priv->gmac_iobase + RSS_HASH_CONFIG);
338769 + switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
338777 + return -EINVAL;
338779 + if (info->data & RXH_VLAN)
338789 + if (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3))
338790 + return -EINVAL;
338791 + if (info->data & RXH_VLAN)
338802 + if (priv == NULL || priv->netdev == NULL)
338803 + return -EINVAL;
338804 + hash_cfg = priv->rss_info.hash_cfg;
338805 + netdev_info(priv->netdev, "Set RSS flow type = %d, data = %lld\n",
338806 + info->flow_type, info->data);
338808 + if (!(info->data & RXH_IP_SRC) || !(info->data & RXH_IP_DST))
338809 + return -EINVAL;
338811 + switch (info->flow_type) {
338814 + TCPV4_L4_HASH_EN, TCPV4_VLAN_HASH_EN) == -EINVAL)
338815 + return -EINVAL;
338819 + TCPV6_L4_HASH_EN, TCPV6_VLAN_HASH_EN) == -EINVAL)
338820 + return -EINVAL;
338824 + UDPV4_L4_HASH_EN, UDPV4_L4_HASH_EN) == -EINVAL)
338825 + return -EINVAL;
338829 + UDPV6_L4_HASH_EN, UDPV6_L4_HASH_EN) == -EINVAL)
338830 + return -EINVAL;
338834 + IPV4_VLAN_HASH_EN) == -EINVAL)
338835 + return -EINVAL;
338840 + IPV6_VLAN_HASH_EN) == -EINVAL)
338841 + return -EINVAL;
338844 + return -EINVAL;
338847 + priv->rss_info.hash_cfg = hash_cfg;
338857 + return -EINVAL;
338858 + switch (info->cmd) {
338864 + return -EOPNOTSUPP;
338872 + if (phy_dev->interface != PHY_INTERFACE_MODE_RMII)
338897 + if (phy_dev->interface != PHY_INTERFACE_MODE_RMII)
338915 + if (phy_dev->interface != PHY_INTERFACE_MODE_RMII)
338971 diff --git a/drivers/net/ethernet/hisilicon/higmac/util.h b/drivers/net/ethernet/hisilicon/higmac/u…
338974 --- /dev/null
338976 @@ -0,0 +1,102 @@
338978 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
338981 + * Create: 2018-10-08
339079 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/Makefile b/drivers/net/ethernet/hisilicon/hi…
339082 --- /dev/null
339083 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/Makefile
339084 @@ -0,0 +1,6 @@
339089 +obj-$(CONFIG_HISI_FEMAC) += hisi-femac.o
339090 +hisi-femac-objs := hisi_femac.o phy_fix.o util.o
339091 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/festa_s28v115_2c02.h b/drivers/net/ethernet/…
339094 --- /dev/null
339095 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/festa_s28v115_2c02.h
339096 @@ -0,0 +1,191 @@
339098 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
339101 + * Create: 2018-10-08
339289 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/festa_s28v202_2e01.h b/drivers/net/ethernet/…
339292 --- /dev/null
339293 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/festa_s28v202_2e01.h
339294 @@ -0,0 +1,84 @@
339296 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
339299 + * Create: 2020-05-11
339379 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/festa_v272_2723.h b/drivers/net/ethernet/his…
339382 --- /dev/null
339383 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/festa_v272_2723.h
339384 @@ -0,0 +1,44 @@
339386 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
339389 + * Create: 2018-10-08
339430 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.c b/drivers/net/ethernet/hisilico…
339433 --- /dev/null
339434 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.c
339435 @@ -0,0 +1,1581 @@
339437 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
339440 + * Create: 2018-10-08
339464 + val = readl(priv->glb_base + GLB_IRQ_ENA);
339465 + writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
339472 + val = readl(priv->glb_base + GLB_IRQ_ENA);
339473 + writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
339506 + phy_dev = dev->phydev;
339518 + val = (val & 0xe0) | ((val & 0x1f) - 1);
339534 + val = (val & 0xe0) | ((val & 0x1f) - 1);
339558 + dev = priv->ndev;
339588 + schedule_delayed_work(&priv->watchdog_queue, FEPHY_OPT_TIMER);
339600 + desc_cur = priv->tx_ring.desc + pos;
339602 + addr = desc_cur->linear_addr;
339603 + len = desc_cur->linear_len;
339604 + dma_unmap_single(priv->dev, addr, len, DMA_TO_DEVICE);
339606 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
339607 + addr = desc_cur->frags[i].addr;
339608 + len = desc_cur->frags[i].size;
339609 + dma_unmap_page(priv->dev, addr, len, DMA_TO_DEVICE);
339616 + if (!(skb_is_gso(skb) || skb_shinfo(skb)->nr_frags)) {
339619 + dma_addr = priv->txq.dma_phys[pos];
339620 + dma_unmap_single(priv->dev, dma_addr, skb->len, DMA_TO_DEVICE);
339630 + struct hisi_femac_queue *txq = &priv->txq;
339637 + val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK;
339638 + while (val < priv->tx_fifo_used_cnt) {
339639 + skb = txq->skb[txq->tail];
339642 + val, priv->tx_fifo_used_cnt);
339645 + hisi_femac_tx_dma_unmap(priv, skb, txq->tail);
339647 + bytes_compl += skb->len;
339650 + priv->tx_fifo_used_cnt--;
339652 + val = readl(priv->port_base + ADDRQ_STAT) & TX_CNT_INUSE_MASK;
339653 + txq->skb[txq->tail] = NULL;
339654 + txq->tail = (txq->tail + 1) % txq->num;
339673 + reg_addr = readl(priv->port_base + TSO_DBG_ADDR);
339674 + reg_tx_info = readl(priv->port_base + TSO_DBG_TX_INFO);
339675 + reg_tx_err = readl(priv->port_base + TSO_DBG_TX_ERR);
339680 + sg_index = (reg_addr - priv->tx_ring.dma_phys) / sizeof(struct tx_desc);
339681 + sg_desc = priv->tx_ring.desc + sg_index;
339703 + netdev_features_t features = dev->features;
339714 + segs = segs->next;
339715 + curr_skb->next = NULL;
339720 + segs = segs->next;
339721 + curr_skb->next = NULL;
339733 + dev->stats.tx_dropped++;
339745 + desc_cur = priv->tx_ring.desc + pos;
339747 + desc_cur->ipv6_id = ntohl(skb_shinfo(skb)->ip6_frag_id);
339749 + desc_cur->total_len = skb->len;
339750 + addr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
339752 + if (unlikely(dma_mapping_error(priv->dev, addr))) {
339753 + return -EINVAL;
339755 + desc_cur->linear_addr = addr;
339756 + desc_cur->linear_len = skb_headlen(skb);
339758 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
339759 + skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
339760 + int len = frag->size;
339762 + addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
339763 + ret = dma_mapping_error(priv->dev, addr);
339765 + return -EINVAL;
339767 + desc_cur->frags[i].addr = addr;
339768 + desc_cur->frags[i].size = len;
339777 + struct phy_device *phy = dev->phydev;
339780 + if (phy->link)
339782 + if (phy->duplex == DUPLEX_FULL)
339784 + if (phy->speed == SPEED_100)
339787 + if ((status != priv->link_status) &&
339788 + ((status | priv->link_status) & MAC_PORTSET_LINKED)) {
339789 + writel(status, priv->port_base + MAC_PORTSET);
339790 + priv->link_status = status;
339793 + priv->tx_pause_en = phy->pause;
339800 + struct hisi_femac_queue *rxq = &priv->rxq;
339808 + pos = rxq->head;
339809 + while (readl(priv->port_base + ADDRQ_STAT) & BIT_RX_READY) {
339810 + if (!CIRC_SPACE(pos, rxq->tail, rxq->num)) {
339813 + if (unlikely(rxq->skb[pos])) {
339814 + netdev_err(priv->ndev, "err skb[%d]=%p\n",
339815 + pos, rxq->skb[pos]);
339819 + skb = netdev_alloc_skb_ip_align(priv->ndev, len);
339824 + alloc_rxbuf_align = ((uintptr_t)skb->data - NET_IP_ALIGN) &
339825 + (RXBUF_ADDR_ALIGN_SIZE - 1);
339827 + reserve_room = RXBUF_ADDR_ALIGN_SIZE -
339829 + len -= reserve_room;
339833 + addr = dma_map_single(priv->dev, skb->data, len,
339835 + if (dma_mapping_error(priv->dev, addr)) {
339839 + rxq->dma_phys[pos] = addr;
339840 + rxq->skb[pos] = skb;
339841 + writel(addr, priv->port_base + IQ_ADDR);
339842 + pos = (pos + 1) % rxq->num;
339844 + rxq->head = pos;
339855 + skb->ip_summed = CHECKSUM_NONE;
339856 + if (dev->features & NETIF_F_RXCSUM) {
339872 + dev->stats.rx_errors++;
339873 + dev->stats.rx_crc_errors++;
339877 + skb->ip_summed = CHECKSUM_UNNECESSARY;
339881 + skb_queue_tail(&priv->rx_head, skb);
339887 + struct hisi_femac_queue *rxq = &priv->rxq;
339892 + spin_lock_irqsave(&priv->rxlock, rxflags);
339893 + pos = rxq->tail;
339894 + while (readl(priv->glb_base + GLB_IRQ_RAW) & IRQ_INT_RX_RDY) {
339895 + rx_pkt_info = readl(priv->port_base + IQFRM_DES);
339897 + len -= ETH_FCS_LEN;
339900 + writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
339902 + skb = rxq->skb[pos];
339907 + rxq->skb[pos] = NULL;
339909 + dma_unmap_single(priv->dev, rxq->dma_phys[pos], MAX_FRAME_SIZE,
339912 + if (unlikely(skb->len > MAX_FRAME_SIZE)) {
339913 + netdev_err(dev, "rcv len err, len = %d\n", skb->len);
339914 + dev->stats.rx_errors++;
339915 + dev->stats.rx_length_errors++;
339922 + pos = (pos + 1) % rxq->num;
339924 + rxq->tail = pos;
339927 + spin_unlock_irqrestore(&priv->rxlock, rxflags);
339933 + struct sk_buff *skb = skb_dequeue(&priv->rx_head);
339937 + skb->protocol = eth_type_trans(skb, dev);
339938 + napi_gro_receive(&priv->napi, skb);
339939 + dev->stats.rx_packets++;
339940 + dev->stats.rx_bytes += skb->len;
339946 + skb = skb_dequeue(&priv->rx_head);
339959 + skb->ip_summed = CHECKSUM_NONE;
339960 + if (dev->features & NETIF_F_RXCSUM) {
339976 + dev->stats.rx_errors++;
339977 + dev->stats.rx_crc_errors++;
339979 + return -1;
339981 + skb->ip_summed = CHECKSUM_UNNECESSARY;
339991 + struct hisi_femac_queue *rxq = &priv->rxq;
339996 + pos = rxq->tail;
339997 + while (readl(priv->glb_base + GLB_IRQ_RAW) & IRQ_INT_RX_RDY) {
339998 + rx_pkt_info = readl(priv->port_base + IQFRM_DES);
340000 + len -= ETH_FCS_LEN;
340003 + writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
340007 + skb = rxq->skb[pos];
340012 + rxq->skb[pos] = NULL;
340014 + dma_unmap_single(priv->dev, rxq->dma_phys[pos], MAX_FRAME_SIZE,
340017 + if (unlikely(skb->len > MAX_FRAME_SIZE)) {
340018 + netdev_err(dev, "rcv len err, len = %d\n", skb->len);
340019 + dev->stats.rx_errors++;
340020 + dev->stats.rx_length_errors++;
340028 + skb->protocol = eth_type_trans(skb, dev);
340029 + napi_gro_receive(&priv->napi, skb);
340030 + dev->stats.rx_packets++;
340031 + dev->stats.rx_bytes += len;
340033 + pos = (pos + 1) % rxq->num;
340038 + rxq->tail = pos;
340050 + struct net_device *dev = priv->ndev;
340062 + task -= num;
340067 + ints = readl(priv->glb_base + GLB_IRQ_RAW);
340069 + priv->glb_base + GLB_IRQ_RAW);
340087 + ints = readl(priv->glb_base + GLB_IRQ_RAW);
340093 + priv->glb_base + GLB_IRQ_RAW);
340095 + napi_schedule(&priv->napi);
340098 + if (has_tso_cap(priv->hw_cap) && unlikely(ints & INT_TX_ERR))
340106 + priv->tx_ring.desc = (struct tx_desc *)dma_zalloc_coherent(priv->dev,
340107 + TXQ_NUM * sizeof(struct tx_desc), &priv->tx_ring.dma_phys, GFP_KERNEL);
340108 + if (!priv->tx_ring.desc) {
340109 + return -ENOMEM;
340117 + if (priv->tx_ring.desc)
340118 + dma_free_coherent(priv->dev, TXQ_NUM * sizeof(struct tx_desc),
340119 + priv->tx_ring.desc, priv->tx_ring.dma_phys);
340120 + priv->tx_ring.desc = NULL;
340126 + queue->skb = devm_kcalloc(dev, num, sizeof(struct sk_buff *), GFP_KERNEL);
340127 + if (queue->skb == NULL) {
340128 + return -ENOMEM;
340131 + queue->dma_phys = devm_kcalloc(dev, num, sizeof(dma_addr_t), GFP_KERNEL);
340132 + if (queue->dma_phys == NULL) {
340133 + return -ENOMEM;
340136 + queue->num = num;
340137 + queue->head = 0;
340138 + queue->tail = 0;
340147 + ret = hisi_femac_init_queue(priv->dev, &priv->txq, TXQ_NUM);
340152 + ret = hisi_femac_init_queue(priv->dev, &priv->rxq, RXQ_NUM);
340157 + priv->tx_fifo_used_cnt = 0;
340164 + struct hisi_femac_queue *txq = &priv->txq;
340165 + struct hisi_femac_queue *rxq = &priv->rxq;
340170 + pos = rxq->tail;
340171 + while (pos != rxq->head) {
340172 + skb = rxq->skb[pos];
340174 + netdev_err(priv->ndev, "NULL rx skb. pos=%d, head=%d\n",
340175 + pos, rxq->head);
340176 + pos = (pos + 1) % rxq->num;
340180 + dma_addr = rxq->dma_phys[pos];
340181 + dma_unmap_single(priv->dev, dma_addr, MAX_FRAME_SIZE, DMA_FROM_DEVICE);
340184 + rxq->skb[pos] = NULL;
340185 + pos = (pos + 1) % rxq->num;
340187 + rxq->tail = pos;
340189 + pos = txq->tail;
340190 + while (pos != txq->head) {
340191 + skb = txq->skb[pos];
340193 + netdev_err(priv->ndev, "NULL tx skb. pos=%d, head=%d\n",
340194 + pos, txq->head);
340195 + pos = (pos + 1) % txq->num;
340200 + txq->skb[pos] = NULL;
340201 + pos = (pos + 1) % txq->num;
340203 + txq->tail = pos;
340204 + priv->tx_fifo_used_cnt = 0;
340213 + writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
340216 + writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
340225 + val = readl(priv->glb_base + GLB_SOFT_RESET);
340227 + writel(val, priv->glb_base + GLB_SOFT_RESET);
340229 + usleep_range(500, 800); /* wait 500-800us */
340232 + writel(val, priv->glb_base + GLB_SOFT_RESET);
340241 + hisi_femac_set_hw_mac_addr(priv, dev->dev_addr);
340246 + writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
340252 + napi_enable(&priv->napi);
340254 + priv->link_status = 0;
340255 + if (dev->phydev)
340256 + phy_start(dev->phydev);
340259 + if (has_tso_cap(priv->hw_cap))
340273 + if (dev->phydev)
340274 + phy_stop(dev->phydev);
340277 + napi_disable(&priv->napi);
340281 + * to prevent potential risk of use-after-free.
340286 + priv->tx_pause_en = false;
340290 + skb_queue_purge(&priv->rx_head);
340299 + struct hisi_femac_queue *txq = &priv->txq;
340302 + val = readl(priv->port_base + ADDRQ_STAT);
340306 + dev->stats.tx_dropped++;
340307 + dev->stats.tx_fifo_errors++;
340312 + if (unlikely(!CIRC_SPACE(txq->head, txq->tail,
340313 + txq->num))) {
340315 + dev->stats.tx_dropped++;
340316 + dev->stats.tx_fifo_errors++;
340328 + struct hisi_femac_queue *txq = &priv->txq;
340338 + if (ret == -ENOTSUPP)
340342 + dev->stats.tx_dropped++;
340348 + if (!(skb_is_gso(skb) || skb_shinfo(skb)->nr_frags)) {
340349 + addr = dma_map_single(priv->dev, skb->data,
340350 + skb->len, DMA_TO_DEVICE);
340351 + if (unlikely(dma_mapping_error(priv->dev, addr))) {
340353 + dev->stats.tx_dropped++;
340357 + ret = hisi_femac_fill_sg_desc(priv, skb, txq->head);
340360 + dev->stats.tx_dropped++;
340364 + addr = priv->tx_ring.dma_phys +
340365 + txq->head * sizeof(struct tx_desc);
340370 + txq->dma_phys[txq->head] = addr;
340374 + txq->skb[txq->head] = skb;
340375 + txq->head = (txq->head + 1) % txq->num;
340377 + writel(addr, priv->port_base + EQ_ADDR);
340378 + writel(pkt_info, priv->port_base + EQFRM_LEN);
340380 + priv->tx_fifo_used_cnt++;
340382 + dev->stats.tx_packets++;
340383 + dev->stats.tx_bytes += skb->len;
340384 + netdev_sent_queue(dev, skb->len);
340394 + if (!is_valid_ether_addr(skaddr->sa_data)) {
340395 + return -EADDRNOTAVAIL;
340398 + memcpy(dev->dev_addr, skaddr->sa_data, dev->addr_len);
340399 + dev->addr_assign_type &= ~NET_ADDR_RANDOM;
340401 + hisi_femac_set_hw_mac_addr(priv, dev->dev_addr);
340411 + val = readl(priv->glb_base + glb_mac_h16(reg_n));
340417 + writel(val, priv->glb_base + glb_mac_h16(reg_n));
340430 + writel(val, priv->glb_base + low);
340432 + val = readl(priv->glb_base + high);
340436 + writel(val, priv->glb_base + high);
340444 + val = readl(priv->glb_base + GLB_FWCTRL);
340450 + writel(val, priv->glb_base + GLB_FWCTRL);
340456 + struct net_device *dev = priv->ndev;
340459 + val = readl(priv->glb_base + GLB_MACTCTRL);
340461 + (dev->flags & IFF_ALLMULTI)) {
340472 + hisi_femac_set_hw_addr_filter(priv, ha->addr, reg);
340477 + writel(val, priv->glb_base + GLB_MACTCTRL);
340483 + struct net_device *dev = priv->ndev;
340486 + val = readl(priv->glb_base + GLB_MACTCTRL);
340498 + hisi_femac_set_hw_addr_filter(priv, ha->addr, reg);
340503 + writel(val, priv->glb_base + GLB_MACTCTRL);
340510 + if (dev->flags & IFF_PROMISC) {
340523 + return -EINVAL;
340526 + if (!dev->phydev) {
340527 + return -EINVAL;
340530 + return phy_mii_ioctl(dev->phydev, ifreq, cmd);
340555 + if (priv->tx_pause_active_thresh < FC_ACTIVE_MIN ||
340556 + priv->tx_pause_active_thresh > FC_ACTIVE_MAX)
340557 + priv->tx_pause_active_thresh = FC_ACTIVE_DEFAULT;
340559 + if (priv->tx_pause_deactive_thresh < FC_DEACTIVE_MIN ||
340560 + priv->tx_pause_deactive_thresh > FC_DEACTIVE_MAX)
340561 + priv->tx_pause_deactive_thresh = FC_DEACTIVE_DEFAULT;
340563 + if (priv->tx_pause_active_thresh >= priv->tx_pause_deactive_thresh) {
340564 + priv->tx_pause_active_thresh = FC_ACTIVE_DEFAULT;
340565 + priv->tx_pause_deactive_thresh = FC_DEACTIVE_DEFAULT;
340571 + reset_control_assert(priv->mac_rst);
340572 + reset_control_deassert(priv->mac_rst);
340582 + reset_control_deassert(priv->phy_rst);
340583 + hisi_femac_sleep_us(priv->phy_reset_delays[PRE_DELAY]);
340585 + reset_control_assert(priv->phy_rst);
340590 + hisi_femac_sleep_us(priv->phy_reset_delays[PULSE]);
340591 + reset_control_deassert(priv->phy_rst);
340593 + hisi_femac_sleep_us(priv->phy_reset_delays[POST_DELAY]);
340602 + if (priv->ndev->phydev->interface == PHY_INTERFACE_MODE_RMII)
340604 + writel(val, priv->port_base + MAC_PORTSEL);
340607 + writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
340610 + if (has_tso_cap(priv->hw_cap)) {
340612 + val = readl(priv->port_base + TSO_DBG_EN);
340614 + writel(val, priv->port_base + TSO_DBG_EN);
340617 + val = readl(priv->glb_base + GLB_FWCTRL);
340620 + writel(val, priv->glb_base + GLB_FWCTRL);
340622 + val = readl(priv->glb_base + GLB_MACTCTRL);
340624 + writel(val, priv->glb_base + GLB_MACTCTRL);
340626 + val = readl(priv->port_base + MAC_SET);
340629 + writel(val, priv->port_base + MAC_SET);
340633 + writel(val, priv->port_base + RX_COALESCE_SET);
340636 + writel(val, priv->port_base + QLEN_SET);
340645 + struct device *dev = &pdev->dev;
340646 + struct device_node *node = dev->of_node;
340649 + if (of_device_is_compatible(node, "hisilicon,hisi-femac-v2"))
340650 + priv->hw_cap |= HW_CAP_TSO | HW_CAP_RXCSUM;
340653 + priv->port_base = devm_ioremap_resource(dev, res);
340654 + if (IS_ERR(priv->port_base)) {
340655 + ret = PTR_ERR(priv->port_base);
340660 + priv->glb_base = devm_ioremap_resource(dev, res);
340661 + if (IS_ERR(priv->glb_base)) {
340662 + ret = PTR_ERR(priv->glb_base);
340666 + priv->clk = devm_clk_get(&pdev->dev, NULL);
340667 + if (IS_ERR(priv->clk)) {
340669 + ret = -ENODEV;
340673 + ret = clk_prepare_enable(priv->clk);
340684 + struct device *dev = &pdev->dev;
340685 + struct device_node *node = dev->of_node;
340687 + struct net_device *ndev = priv->ndev;
340689 + priv->mac_rst = devm_reset_control_get(dev, "mac");
340690 + if (IS_ERR(priv->mac_rst))
340691 + return PTR_ERR(priv->mac_rst);
340697 + ether_addr_copy(ndev->dev_addr, mac_addr);
340698 + if (!is_valid_ether_addr(ndev->dev_addr)) {
340701 + ndev->dev_addr);
340709 + struct device *dev = &pdev->dev;
340710 + struct device_node *node = dev->of_node;
340713 + priv->phy_rst = devm_reset_control_get(dev, "phy");
340714 + if (IS_ERR(priv->phy_rst)) {
340715 + priv->phy_rst = NULL;
340718 + priv->phy_reset_delays, DELAYS_NUM);
340726 + phy = of_phy_get_and_connect(priv->ndev, node, hisi_femac_adjust_link);
340728 + /* check if a fixed-link is defined in device-tree */
340739 + phy = of_phy_connect(priv->ndev, of_node_get(node), &hisi_femac_adjust_link, 0,
340747 + *ret = -ENODEV;
340752 + phy->advertising |= ADVERTISED_Pause;
340753 + phy->supported |= ADVERTISED_Pause;
340754 + phy->advertising &= ~(ADVERTISED_1000baseT_Full |
340758 + (unsigned long)phy->phy_id, phy_modes(phy->interface));
340766 + struct net_device *ndev = priv->ndev;
340768 + ndev->watchdog_timeo = 6 * HZ; /* 6HZ */
340769 + ndev->priv_flags |= IFF_UNICAST_FLT;
340770 + ndev->netdev_ops = &hisi_femac_netdev_ops;
340771 + ndev->ethtool_ops = &hisi_femac_ethtools_ops;
340772 + netif_napi_add(ndev, &priv->napi, hisi_femac_poll, FEMAC_POLL_WEIGHT);
340775 + INIT_DELAYED_WORK(&priv->watchdog_queue, hisi_femac_watchdog);
340776 + schedule_delayed_work(&priv->watchdog_queue, FEPHY_OPT_TIMER);
340779 + if (has_tso_cap(priv->hw_cap))
340780 + ndev->hw_features |= NETIF_F_SG |
340784 + if (has_rxcsum_cap(priv->hw_cap))
340785 + ndev->hw_features |= NETIF_F_RXCSUM;
340786 + ndev->features |= ndev->hw_features;
340787 + ndev->vlan_features |= ndev->features;
340789 + device_set_wakeup_capable(priv->dev, true);
340790 + device_set_wakeup_enable(priv->dev, true);
340792 + priv->tx_pause_en = true;
340793 + priv->tx_pause_active_thresh = TX_FLOW_CTRL_ACTIVE_THRESHOLD;
340794 + priv->tx_pause_deactive_thresh = TX_FLOW_CTRL_DEACTIVE_THRESHOLD;
340800 + if (has_rxcsum_cap(priv->hw_cap))
340810 + skb_queue_head_init(&priv->rx_head);
340811 + spin_lock_init(&priv->rxlock);
340817 + if (has_tso_cap(priv->hw_cap)) {
340828 + struct device *dev = &pdev->dev;
340829 + struct net_device *ndev = priv->ndev;
340832 + ndev->irq = platform_get_irq(pdev, 0);
340833 + if (ndev->irq <= 0) {
340835 + ret = -ENODEV;
340839 + ret = devm_request_irq(dev, ndev->irq, hisi_femac_interrupt,
340840 + IRQF_SHARED, pdev->name, ndev);
340842 + dev_err(dev, "devm_request_irq %d failed!\n", ndev->irq);
340856 + struct device *dev = &pdev->dev;
340864 + return -ENOMEM;
340867 + SET_NETDEV_DEV(ndev, &pdev->dev);
340870 + priv->dev = dev;
340871 + priv->ndev = ndev;
340898 + if (has_tso_cap(priv->hw_cap))
340901 + netif_napi_del(&priv->napi);
340904 + clk_disable_unprepare(priv->clk);
340916 + netif_napi_del(&priv->napi);
340918 + if (has_tso_cap(priv->hw_cap))
340921 + phy_disconnect(ndev->phydev);
340923 + cancel_delayed_work_sync(&priv->watchdog_queue);
340925 + clk_disable_unprepare(priv->clk);
340940 + disable_irq(ndev->irq);
340946 + clk_disable_unprepare(priv->clk);
340956 + clk_prepare_enable(priv->clk);
340957 + if (priv->phy_rst != NULL)
340965 + enable_irq(ndev->irq);
340973 + .compatible = "hisilicon,hisi-femac-v1",
340976 + .compatible = "hisilicon,hisi-femac-v2",
340979 + .compatible = "hisilicon,hi3516cv500-femac",
340982 + .compatible = "hisilicon,hi3516cv300-femac",
340985 + .compatible = "hisilicon,hi3536dv100-femac",
340988 + .compatible = "hisilicon,hi3556v200-femac",
340991 + .compatible = "hisilicon,hi3559v200-femac",
341000 + .name = "hisi-femac",
341016 +MODULE_ALIAS("platform:hisi-femac");
341017 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.h b/drivers/net/ethernet/hisilico…
341020 --- /dev/null
341021 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/hisi_femac.h
341022 @@ -0,0 +1,269 @@
341024 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
341027 + * Create: 2020-05-19
341053 +#define HW_RX_FIFO_DEPTH (MAX_HW_FIFO_DEPTH - HW_TX_FIFO_DEPTH)
341126 +#define MAX_MULTICAST_ADDRESSES (MAX_MAC_FILTER_NUM - MAX_UNICAST_ADDRESSES)
341152 +#define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
341210 +#define regval_to_temp(val) ((val - 117) * 165 / 798 - 40)
341292 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/phy_fix.c b/drivers/net/ethernet/hisilicon/h…
341295 --- /dev/null
341296 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/phy_fix.c
341297 @@ -0,0 +1,109 @@
341299 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
341302 + * Create: 2018-10-08
341407 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/phy_fix.h b/drivers/net/ethernet/hisilicon/h…
341410 --- /dev/null
341411 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/phy_fix.h
341412 @@ -0,0 +1,22 @@
341414 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2018-2020. All rights reserved.
341417 + * Create: 2018-10-08
341435 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/util.c b/drivers/net/ethernet/hisilicon/hisi…
341438 --- /dev/null
341439 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/util.c
341440 @@ -0,0 +1,318 @@
341442 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
341445 + * Create: 2020-05-19
341463 + csum = skb_checksum(skb, offset, skb->len - offset, 0);
341465 + offset += skb->csum_offset;
341472 + *(__sum16 *)(skb->data + offset) = udp_csum;
341474 + skb->ip_summed = CHECKSUM_NONE;
341481 + l3_proto = skb->protocol;
341482 + if (skb->protocol == htons(ETH_P_8021Q))
341497 + l4_proto = ipv6_hdr(skb)->nexthdr;
341506 + return -ENOTSUPP;
341509 + if (skb->ip_summed == CHECKSUM_PARTIAL &&
341511 + return -EINVAL;
341521 + * if tcp_mtu_probe() use (2 * tp->mss_cache) as probe_size,
341526 + return -ENOTSUPP;
341558 + } else if (skb_shinfo(skb)->nr_frags) {
341562 + pkt_info |= (skb_shinfo(skb)->nr_frags << BIT_OFFSET_NFRAGS_NUM);
341563 + pkt_info |= (skb_is_gso(skb) ? ((skb_shinfo(skb)->gso_size > max_mss) ?
341564 + max_mss : skb_shinfo(skb)->gso_size) :
341565 + (skb->len + ETH_FCS_LEN));
341581 + max_data_len = skb->len - ETH_HLEN;
341583 + if (skb->ip_summed == CHECKSUM_PARTIAL)
341586 + l3_proto = skb->protocol;
341587 + if (skb->protocol == htons(ETH_P_8021Q)) {
341589 + max_data_len -= VLAN_HLEN;
341597 + (ntohs(iph->tot_len) <= (iph->ihl << 2))) /* trans 2 bytes */
341598 + iph->tot_len = htons(GSO_MAX_SIZE - 1);
341600 + max_mss -= iph->ihl * WORD_TO_BYTE;
341601 + pkt_info |= (iph->ihl << BIT_OFFSET_IP_HEADER_LEN);
341602 + l4_proto = iph->protocol;
341604 + max_mss -= IPV6_HDR_LEN * WORD_TO_BYTE;
341607 + l4_proto = ipv6_hdr(skb)->nexthdr;
341613 + max_mss -= tcp_hdr(skb)->doff * WORD_TO_BYTE;
341614 + pkt_info |= (tcp_hdr(skb)->doff << BIT_OFFSET_PROT_HEADER_LEN);
341617 + max_mss -= sizeof(struct frag_hdr);
341653 + tx_flow_ctrl = readl(priv->port_base + FC_LEVEL);
341655 + tx_flow_ctrl |= priv->tx_pause_deactive_thresh;
341657 + tx_flow_ctrl |= priv->tx_pause_active_thresh << BITS_FC_ACTIVE_THR_OFFSET;
341659 + pause_en = readl(priv->port_base + MAC_SET);
341661 + if (priv->tx_pause_en) {
341669 + writel(tx_flow_ctrl, priv->port_base + FC_LEVEL);
341671 + writel(pause_en, priv->port_base + MAC_SET);
341679 + if (dev == NULL || dev->phydev == NULL || pause == NULL)
341682 + pause->autoneg = dev->phydev->autoneg;
341683 + pause->rx_pause = 1;
341684 + if (priv->tx_pause_en)
341685 + pause->tx_pause = 1;
341695 + if (dev == NULL || pause == NULL || pause->rx_pause == 0) {
341696 + return -EINVAL;
341699 + phy = dev->phydev;
341701 + if (pause->tx_pause != priv->tx_pause_en) {
341702 + priv->tx_pause_en = pause->tx_pause;
341706 + if (phy != NULL && phy->autoneg) {
341709 + /* auto-negotiation automatically restarted */
341711 + cmd.supported = phy->supported;
341712 + cmd.advertising = phy->advertising;
341713 + cmd.autoneg = phy->autoneg;
341714 + cmd.speed = phy->speed;
341715 + cmd.duplex = phy->duplex;
341716 + cmd.phy_address = phy->mdio.addr;
341731 + val = readl(priv->port_base + RX_COE_CTRL);
341735 + writel(val, priv->port_base + RX_COE_CTRL);
341744 + return -1;
341747 + changed = dev->features ^ features;
341759 diff --git a/drivers/net/ethernet/hisilicon/hisi-femac/util.h b/drivers/net/ethernet/hisilicon/hisi…
341762 --- /dev/null
341763 +++ b/drivers/net/ethernet/hisilicon/hisi-femac/util.h
341764 @@ -0,0 +1,25 @@
341766 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2020-2020. All rights reserved.
341769 + * Create: 2020-05-19
341791 diff --git a/drivers/net/ethernet/hisilicon/hisi_femac.c b/drivers/net/ethernet/hisilicon/hisi_fema…
341793 --- a/drivers/net/ethernet/hisilicon/hisi_femac.c
341795 @@ -98,7 +98,7 @@
341799 -#define FEMAC_POLL_WEIGHT 16
341802 #define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
341804 @@ -1001,6 +1001,6 @@ static struct platform_driver hisi_femac_driver = {
341808 -MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
341811 MODULE_ALIAS("platform:hisi-femac");
341812 diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c b/drivers/net/ethernet/hisilicon/hn…
341814 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c
341816 @@ -706,7 +706,7 @@ static void hns_gmac_get_strings(u32 stringset, u8 *data)
341820 - if (stringset == ETH_SS_STATS)
341825 diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c b/drivers/net/ethernet/hisilicon/hns…
341827 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c
341829 @@ -446,7 +446,7 @@ void hns_ppe_update_stats(struct hns_ppe_cb *ppe_cb)
341833 - if (stringset == ETH_SS_STATS)
341838 diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c b/drivers/net/ethernet/hisilicon/hns…
341840 --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c
341842 @@ -899,7 +899,7 @@ void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data)
341846 - if (stringset == ETH_SS_STATS)
341851 diff --git a/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx4/e…
341853 --- a/drivers/net/ethernet/mellanox/mlx4/en_ethtool.c
341855 @@ -2078,14 +2078,17 @@ static int mlx4_en_get_module_eeprom(struct net_device *dev,
341856 ret = mlx4_get_module_info(mdev->dev, priv->port,
341857 offset, ee->len - i, data + i);
341859 - if (!ret) /* Done reading */
341862 + memset(data + i, 0, ee->len - i);
341868 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
341869 i, offset, ee->len - i, ret);
341870 - return 0;
341875 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
341877 --- a/drivers/net/phy/Kconfig
341879 @@ -107,6 +107,13 @@ config MDIO_HISI_FEMAC
341893 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
341895 --- a/drivers/net/phy/Makefile
341897 @@ -31,7 +31,10 @@ obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o
341898 obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
341899 obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
341900 obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
341901 -obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
341902 +obj-$(CONFIG_ARCH_HI3531DV200) += mdio_hi3531dv200_gemac.o
341903 +obj-$(CONFIG_ARCH_HI3535AV100) += mdio_hi3535av100_gemac.o
341904 +obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio_hisi_femac.o
341905 +obj-$(CONFIG_MDIO_HISI_GEMAC) += mdio_hisi_gemac.o
341906 obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
341907 obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
341908 obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
341909 diff --git a/drivers/net/phy/mdio-hisi-femac.c b/drivers/net/phy/mdio-hisi-femac.c
341912 --- a/drivers/net/phy/mdio-hisi-femac.c
341914 @@ -1,166 +0,0 @@
341915 -/*
341916 - * Hisilicon Fast Ethernet MDIO Bus Driver
341917 - *
341918 - * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
341919 - *
341920 - * This program is free software; you can redistribute it and/or modify
341921 - * it under the terms of the GNU General Public License as published by
341922 - * the Free Software Foundation; either version 2 of the License, or
341923 - * (at your option) any later version.
341924 - *
341925 - * This program is distributed in the hope that it will be useful,
341926 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
341927 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
341928 - * GNU General Public License for more details.
341929 - *
341930 - * You should have received a copy of the GNU General Public License
341931 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
341932 - */
341933 -
341934 -#include <linux/clk.h>
341935 -#include <linux/iopoll.h>
341936 -#include <linux/kernel.h>
341937 -#include <linux/module.h>
341938 -#include <linux/of_address.h>
341939 -#include <linux/of_mdio.h>
341940 -#include <linux/platform_device.h>
341941 -
341942 -#define MDIO_RWCTRL 0x00
341943 -#define MDIO_RO_DATA 0x04
341944 -#define MDIO_WRITE BIT(13)
341945 -#define MDIO_RW_FINISH BIT(15)
341946 -#define BIT_PHY_ADDR_OFFSET 8
341947 -#define BIT_WR_DATA_OFFSET 16
341948 -
341949 -struct hisi_femac_mdio_data {
341950 - struct clk *clk;
341951 - void __iomem *membase;
341952 -};
341953 -
341954 -static int hisi_femac_mdio_wait_ready(struct hisi_femac_mdio_data *data)
341955 -{
341956 - u32 val;
341957 -
341958 - return readl_poll_timeout(data->membase + MDIO_RWCTRL,
341959 - val, val & MDIO_RW_FINISH, 20, 10000);
341960 -}
341961 -
341962 -static int hisi_femac_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
341963 -{
341964 - struct hisi_femac_mdio_data *data = bus->priv;
341965 - int ret;
341966 -
341967 - ret = hisi_femac_mdio_wait_ready(data);
341968 - if (ret)
341969 - return ret;
341970 -
341971 - writel((mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
341972 - data->membase + MDIO_RWCTRL);
341973 -
341974 - ret = hisi_femac_mdio_wait_ready(data);
341975 - if (ret)
341976 - return ret;
341977 -
341978 - return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
341979 -}
341980 -
341981 -static int hisi_femac_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
341982 - u16 value)
341983 -{
341984 - struct hisi_femac_mdio_data *data = bus->priv;
341985 - int ret;
341986 -
341987 - ret = hisi_femac_mdio_wait_ready(data);
341988 - if (ret)
341989 - return ret;
341990 -
341991 - writel(MDIO_WRITE | (value << BIT_WR_DATA_OFFSET) |
341992 - (mii_id << BIT_PHY_ADDR_OFFSET) | regnum,
341993 - data->membase + MDIO_RWCTRL);
341994 -
341995 - return hisi_femac_mdio_wait_ready(data);
341996 -}
341997 -
341998 -static int hisi_femac_mdio_probe(struct platform_device *pdev)
341999 -{
342000 - struct device_node *np = pdev->dev.of_node;
342001 - struct mii_bus *bus;
342002 - struct hisi_femac_mdio_data *data;
342003 - struct resource *res;
342004 - int ret;
342005 -
342006 - bus = mdiobus_alloc_size(sizeof(*data));
342007 - if (!bus)
342008 - return -ENOMEM;
342009 -
342010 - bus->name = "hisi_femac_mii_bus";
342011 - bus->read = &hisi_femac_mdio_read;
342012 - bus->write = &hisi_femac_mdio_write;
342013 - snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
342014 - bus->parent = &pdev->dev;
342015 -
342016 - data = bus->priv;
342017 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342018 - data->membase = devm_ioremap_resource(&pdev->dev, res);
342019 - if (IS_ERR(data->membase)) {
342020 - ret = PTR_ERR(data->membase);
342021 - goto err_out_free_mdiobus;
342022 - }
342023 -
342024 - data->clk = devm_clk_get(&pdev->dev, NULL);
342025 - if (IS_ERR(data->clk)) {
342026 - ret = PTR_ERR(data->clk);
342027 - goto err_out_free_mdiobus;
342028 - }
342029 -
342030 - ret = clk_prepare_enable(data->clk);
342031 - if (ret)
342032 - goto err_out_free_mdiobus;
342033 -
342034 - ret = of_mdiobus_register(bus, np);
342035 - if (ret)
342036 - goto err_out_disable_clk;
342037 -
342038 - platform_set_drvdata(pdev, bus);
342039 -
342040 - return 0;
342041 -
342042 -err_out_disable_clk:
342043 - clk_disable_unprepare(data->clk);
342044 -err_out_free_mdiobus:
342045 - mdiobus_free(bus);
342046 - return ret;
342047 -}
342048 -
342049 -static int hisi_femac_mdio_remove(struct platform_device *pdev)
342050 -{
342051 - struct mii_bus *bus = platform_get_drvdata(pdev);
342052 - struct hisi_femac_mdio_data *data = bus->priv;
342053 -
342054 - mdiobus_unregister(bus);
342055 - clk_disable_unprepare(data->clk);
342056 - mdiobus_free(bus);
342057 -
342058 - return 0;
342059 -}
342060 -
342061 -static const struct of_device_id hisi_femac_mdio_dt_ids[] = {
342062 - { .compatible = "hisilicon,hisi-femac-mdio" },
342063 - { }
342064 -};
342065 -MODULE_DEVICE_TABLE(of, hisi_femac_mdio_dt_ids);
342066 -
342067 -static struct platform_driver hisi_femac_mdio_driver = {
342068 - .probe = hisi_femac_mdio_probe,
342069 - .remove = hisi_femac_mdio_remove,
342070 - .driver = {
342071 - .name = "hisi-femac-mdio",
342072 - .of_match_table = hisi_femac_mdio_dt_ids,
342073 - },
342074 -};
342075 -
342076 -module_platform_driver(hisi_femac_mdio_driver);
342077 -
342078 -MODULE_DESCRIPTION("Hisilicon Fast Ethernet MAC MDIO interface driver");
342079 -MODULE_AUTHOR("Dongpo Li <lidongpo@hisilicon.com>");
342080 -MODULE_LICENSE("GPL v2");
342081 diff --git a/drivers/net/phy/mdio_hi3531dv200_gemac.c b/drivers/net/phy/mdio_hi3531dv200_gemac.c
342084 --- /dev/null
342086 @@ -0,0 +1,280 @@
342241 + pinout = devm_ioremap(&pdev->dev, phyaddr, REG_SIZE_BYTES);
342247 + devm_iounmap(&pdev->dev, pinout);
342342 + struct device_node *np = pdev->dev.of_node;
342363 + return -EINVAL;
342367 diff --git a/drivers/net/phy/mdio_hi3535av100_gemac.c b/drivers/net/phy/mdio_hi3535av100_gemac.c
342370 --- /dev/null
342372 @@ -0,0 +1,280 @@
342527 + pinout = devm_ioremap(&pdev->dev, phyaddr, REG_SIZE_BYTES);
342533 + devm_iounmap(&pdev->dev, pinout);
342628 + struct device_node *np = pdev->dev.of_node;
342649 + return -EINVAL;
342653 diff --git a/drivers/net/phy/mdio_hisi_femac.c b/drivers/net/phy/mdio_hisi_femac.c
342656 --- /dev/null
342658 @@ -0,0 +1,489 @@
342728 +#define PHY_RESET_DELAYS_PROPERTY "hisilicon,phy-reset-delays-us"
342754 + return readl_poll_timeout_atomic(data->membase + MDIO_RWCTRL,
342760 + struct hisi_femac_mdio_data *data = bus->priv;
342768 + data->membase + MDIO_RWCTRL);
342774 + return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
342780 + struct hisi_femac_mdio_data *data = bus->priv;
342789 + data->membase + MDIO_RWCTRL);
342814 + reset_control_deassert(data->phy_rst);
342815 + hisi_femac_sleep_us(data->phy_reset_delays[PRE_DELAY]);
342817 + reset_control_assert(data->phy_rst);
342821 + hisi_femac_sleep_us(data->phy_reset_delays[PULSE]);
342822 + reset_control_deassert(data->phy_rst);
342824 + hisi_femac_sleep_us(data->phy_reset_delays[POST_DELAY]);
342839 + addr = of_mdio_parse_addr(&data->bus->dev, child);
342845 + data->phy_addr = addr;
342851 + return (data->fephy_iobase ?
342852 + !(readl(data->fephy_iobase) & BIT_FEPHY_SEL) : false);
342860 + clk_disable_unprepare(data->clk);
342862 + val = readl(data->fephy_iobase);
342864 + val |= data->phy_addr;
342865 + writel(val, data->fephy_iobase);
342867 + clk_prepare_enable(data->fephy_clk);
342870 + reset_control_assert(data->fephy_rst);
342872 + reset_control_deassert(data->fephy_rst);
342876 + clk_prepare_enable(data->clk);
342912 + val = fephy_expanded_read(data->bus, data->phy_addr,
342915 + } while (!val && --timeout);
342925 + struct mii_bus *bus = data->bus;
342926 + u32 phy_addr = data->phy_addr;
342937 + val = readl(data->fephy_trim_iobase);
342939 + val = readl(data->fephy_iobase);
342981 + } while (!val && --timeout);
343004 + if (!data->fephy_iobase)
343007 + val = readl(data->fephy_iobase);
343009 + val |= (data->phy_addr + 1);
343010 + writel(val, data->fephy_iobase);
343015 + struct device_node *np = pdev->dev.of_node;
343023 + return -ENOMEM;
343025 + bus->name = "hisi_femac_mii_bus";
343026 + bus->read = &hisi_femac_mdio_read;
343027 + bus->write = &hisi_femac_mdio_write;
343028 + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
343029 + bus->parent = &pdev->dev;
343031 + data = bus->priv;
343032 + data->bus = bus;
343034 + data->membase = devm_ioremap_resource(&pdev->dev, res);
343035 + if (IS_ERR(data->membase)) {
343036 + ret = PTR_ERR(data->membase);
343042 + data->fephy_iobase = devm_ioremap_resource(&pdev->dev, res);
343043 + if (IS_ERR(data->fephy_iobase)) {
343044 + ret = PTR_ERR(data->fephy_iobase);
343048 + data->fephy_iobase = NULL;
343053 + data->fephy_trim_iobase = devm_ioremap_resource(&pdev->dev,
343055 + if (IS_ERR(data->fephy_trim_iobase)) {
343056 + ret = PTR_ERR(data->fephy_trim_iobase);
343060 + data->fephy_trim_iobase = NULL;
343063 + data->clk = devm_clk_get(&pdev->dev, "mdio");
343064 + if (IS_ERR(data->clk)) {
343065 + ret = PTR_ERR(data->clk);
343069 + data->fephy_clk = devm_clk_get(&pdev->dev, "phy");
343070 + if (IS_ERR(data->fephy_clk))
343071 + data->fephy_clk = NULL;
343073 + ret = clk_prepare_enable(data->clk);
343077 + data->phy_rst = devm_reset_control_get(&pdev->dev, "external-phy");
343078 + if (IS_ERR(data->phy_rst)) {
343079 + data->phy_rst = NULL;
343083 + data->phy_reset_delays,
343090 + data->fephy_rst = devm_reset_control_get(&pdev->dev, "internal-phy");
343091 + if (IS_ERR(data->fephy_rst))
343092 + data->fephy_rst = NULL;
343109 + clk_disable_unprepare(data->fephy_clk);
343110 + clk_disable_unprepare(data->clk);
343119 + struct hisi_femac_mdio_data *data = bus->priv;
343122 + clk_disable_unprepare(data->clk);
343129 + { .compatible = "hisilicon,hisi-femac-mdio" },
343138 + .name = "hisi-femac-mdio",
343148 diff --git a/drivers/net/phy/mdio_hisi_gemac.c b/drivers/net/phy/mdio_hisi_gemac.c
343151 --- /dev/null
343153 @@ -0,0 +1,256 @@
343213 + return readl_poll_timeout(data->membase + MDIO_SINGLE_CMD,
343219 + struct hisi_gemac_mdio_data *data = bus->priv;
343228 + data->membase + MDIO_SINGLE_CMD);
343234 + /* if read data is invalid, we just return 0 instead of -EAGAIN.
343237 + if (readl(data->membase + MDIO_RDATA_STATUS))
343240 + return readl(data->membase + MDIO_SINGLE_DATA) >> 16;
343246 + struct hisi_gemac_mdio_data *data = bus->priv;
343253 + writel(value, data->membase + MDIO_SINGLE_DATA);
343256 + data->membase + MDIO_SINGLE_CMD);
343263 + if (data->phy_rst) {
343265 + reset_control_deassert(data->phy_rst);
343270 + reset_control_assert(data->phy_rst);
343278 + reset_control_deassert(data->phy_rst);
343313 + struct device_node *np = pdev->dev.of_node;
343327 + return -ENOMEM;
343329 + bus->name = "hisi_gemac_mii_bus";
343330 + bus->read = &hisi_gemac_mdio_read;
343331 + bus->write = &hisi_gemac_mdio_write;
343332 + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
343333 + bus->parent = &pdev->dev;
343335 + data = bus->priv;
343338 + ret = -ENXIO;
343341 + data->membase = devm_ioremap(&pdev->dev, res->start,
343343 + if (!data->membase) {
343344 + ret = -ENOMEM;
343348 + data->clk = devm_clk_get(&pdev->dev, NULL);
343349 + if (IS_ERR(data->clk)) {
343350 + ret = PTR_ERR(data->clk);
343354 + ret = clk_prepare_enable(data->clk);
343358 + data->phy_rst = devm_reset_control_get(&pdev->dev, "phy_reset");
343359 + if (IS_ERR(data->phy_rst))
343360 + data->phy_rst = NULL;
343372 + clk_disable_unprepare(data->clk);
343381 + struct hisi_gemac_mdio_data *data = bus->priv;
343384 + clk_disable_unprepare(data->clk);
343391 + { .compatible = "hisilicon,hisi-gemac-mdio" },
343400 + .name = "hisi-gemac-mdio",
343410 diff --git a/drivers/net/phy/mdio_hisi_gemac.h b/drivers/net/phy/mdio_hisi_gemac.h
343413 --- /dev/null
343415 @@ -0,0 +1,32 @@
343448 diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
343450 --- a/drivers/net/phy/phy.c
343452 @@ -355,6 +355,28 @@ int phy_ethtool_ksettings_set(struct phy_device *phydev,
343458 + cmd->supported = phydev->supported;
343460 + cmd->advertising = phydev->advertising;
343461 + cmd->lp_advertising = phydev->lp_advertising;
343463 + ethtool_cmd_speed_set(cmd, phydev->speed);
343464 + cmd->duplex = phydev->duplex;
343465 + if (phydev->interface == PHY_INTERFACE_MODE_MOCA)
343466 + cmd->port = PORT_BNC;
343468 + cmd->port = PORT_MII;
343469 + cmd->phy_address = phydev->mdio.addr;
343470 + cmd->transceiver = phy_is_internal(phydev) ?
343472 + cmd->autoneg = phydev->autoneg;
343473 + cmd->eth_tp_mdix_ctrl = phydev->mdix;
343481 diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
343483 --- a/drivers/net/phy/realtek.c
343485 @@ -32,6 +32,12 @@
343492 + when pin No.25 via 4.7k-ohm to DVDD-RG.
343498 @@ -171,6 +177,10 @@ static int rtl8211f_config_init(struct phy_device *phydev)
343503 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
343506 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
343507 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
343508 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
343509 diff --git a/drivers/net/usb/cdc_mbim.c b/drivers/net/usb/cdc_mbim.c
343511 --- a/drivers/net/usb/cdc_mbim.c
343513 @@ -23,6 +23,7 @@
343521 diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/r…
343523 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
343525 @@ -5453,6 +5453,7 @@ static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
343533 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
343535 --- a/drivers/pci/Kconfig
343537 @@ -148,3 +148,4 @@ source "drivers/pci/hotplug/Kconfig"
343542 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
343544 --- a/drivers/pci/Makefile
343546 @@ -33,5 +33,6 @@ obj-$(CONFIG_PCI_ENDPOINT) += endpoint/
343548 obj-y += controller/
343549 obj-y += switch/
343550 +obj-$(CONFIG_HIPCIE) += hipcie/
343552 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
343553 diff --git a/drivers/pci/hipcie/Kconfig b/drivers/pci/hipcie/Kconfig
343556 --- /dev/null
343558 @@ -0,0 +1,27 @@
343578 + the card of pcie-to-sata to connect to the sata disk, with the default max read
343586 diff --git a/drivers/pci/hipcie/Makefile b/drivers/pci/hipcie/Makefile
343589 --- /dev/null
343591 @@ -0,0 +1,8 @@
343593 +obj-$(CONFIG_HIPCIE) += hipcie.o
343595 +hipcie-objs := pcie.o
343598 + EXTRA_CFLAGS += -DPCIE_DEBUG
343600 diff --git a/drivers/pci/hipcie/pci.h b/drivers/pci/hipcie/pci.h
343603 --- /dev/null
343605 @@ -0,0 +1,96 @@
343665 + * Per-controller structure
343673 + u64 mem_offset; /* bus->cpu memory mapping offset */
343674 + unsigned long io_offset; /* bus->cpu IO mapping offset */
343696 + dev_dbg(&dev->dev, "assigning IRQ %02d\n", irq);
343702 diff --git a/drivers/pci/hipcie/pcie.c b/drivers/pci/hipcie/pcie.c
343705 --- /dev/null
343707 @@ -0,0 +1,985 @@
343709 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
343758 + pr_debug("%s->%d," str "\n", \
343769 + pr_err("%s->%d,assert fail!\n", \
343775 + pr_err("%s->%d" str "\n", __func__, __LINE__, ##arg)
343804 + pcie_controller_none = -1,
343842 + { .root_bus_nr = -1, },
343843 + { .root_bus_nr = -1, }
343884 + for (; i >= 0; i--) {
343887 + && pcie_info[i].root_bus_nr != -1)
343901 + struct pcie_info *info = bus_to_info(bus->number);
343910 + address = info->base_addr + (PCIE_CFG_BUS(bus->number)
343932 + struct pcie_info *info = bus_to_info(bus->number);
343944 + info->controller);
343945 + return -1;
343983 + * For host-side config space read, ignore device func nr.
343986 + return -EIO;
343988 + val = (u32)readl((void *)(uintptr_t)(info->conf_base_addr +
344008 + struct pcie_info *info = bus_to_info(bus->number);
344017 + if (bus->number == info->root_bus_nr)
344024 + bus->number & 0xff, devfn, where, size, *value);
344032 + struct pcie_info *info = bus_to_info(bus->number);
344045 + info->controller);
344046 + return -1;
344087 + return -EIO;
344101 + writel(org, ((void __iomem *)(uintptr_t)info->conf_base_addr +
344112 + struct pcie_info *info = bus_to_info(bus->number);
344116 + bus->number & 0xff, devfn, where, size, value);
344124 + if (bus->number == info->root_bus_nr)
344143 + list_for_each_entry(dev, &bus->devices, bus_list) {
344158 + list_for_each_entry(dev, &bus->devices, bus_list) {
344159 + BUG_ON(!dev->is_probed);
344160 + child = dev->subordinate;
344184 + struct device_node *dn = pdev->dev.of_node;
344189 + int pcie_contrl = -1;
344197 + return -EINVAL;
344205 + ret = devm_of_pci_get_host_bridge_resources(&pdev->dev, bus_start, 0xff, &res,
344209 + bus = pci_create_root_bus(&pdev->dev, bus_start, &pcie_ops, hipcie, &res);
344211 + return -ENOMEM;
344215 + bus->msi = &hipcie->msi.chip;
344223 + pcie_info[pcie_contrl].root_bus_nr = bus->number;
344224 + info = bus_to_info(bus->number);
344240 + struct device_node *dn = pdev->dev.of_node;
344253 + return -EINVAL;
344261 + ret = devm_of_pci_get_host_bridge_resources(&pdev->dev, bus_start, 0xff, &res, &io_addr);
344265 + bus = pci_create_root_bus(&pdev->dev, bus_start, &pcie_ops, hipcie, &res);
344267 + return -ENOMEM;
344271 + bus->msi = &hipcie->msi.chip;
344279 + pcie_info[pcie_contrl].root_bus_nr = bus->number;
344280 + info = bus_to_info(bus->number);
344305 + mutex_lock(&chip->lock);
344307 + msi = find_first_zero_bit(chip->used, HISI_PCI_MSI_NR);
344309 + set_bit(msi, chip->used);
344311 + msi = -ENOSPC;
344313 + mutex_unlock(&chip->lock);
344320 + struct device *dev = chip->chip.dev;
344322 + mutex_lock(&chip->lock);
344324 + if (!test_bit(irq, chip->used))
344327 + clear_bit(irq, chip->used);
344329 + mutex_unlock(&chip->lock);
344335 + struct device *dev = hi_pcie->dev;
344336 + struct hisi_msi *msi = &hi_pcie->msi;
344340 + pcie_info[hi_pcie->nr_controllers].conf_base_addr;
344353 + irq = irq_find_mapping(msi->domain, index);
344355 + if (test_bit(index, msi->used)) {
344383 + if (pdev->bus->number == pcie_info[0].root_bus_nr ||
344384 + pdev->bus->number == pcie_info[1].root_bus_nr)
344391 + irq = irq_create_mapping(msi->domain, hwirq);
344394 + return -EINVAL;
344399 + desc->msi_attrib.multiple = 0x5;
344401 + msg.address_lo = virt_to_phys((void *)(uintptr_t)msi->pages);
344402 + msg.address_hi = (virt_to_phys((void *)(uintptr_t)msi->pages) >> 32);
344436 + irq_set_chip_data(irq, domain->host_data);
344447 + struct device *dev = pcie->dev;
344449 + struct hisi_msi *msi = &pcie->msi;
344454 + pcie_info[pcie->nr_controllers].conf_base_addr;
344458 + return -EINVAL;
344461 + mutex_init(&msi->lock);
344463 + msi->chip.dev = dev;
344464 + msi->chip.setup_irq = hisi_msi_setup_irq;
344465 + msi->chip.teardown_irq = hisi_msi_teardown_irq;
344467 + msi->domain = irq_domain_add_linear(dev->of_node, HISI_PCI_MSI_NR,
344468 + &msi_domain_ops, &msi->chip);
344469 + if (!msi->domain) {
344471 + return -ENOMEM;
344480 + msi->irq = err;
344482 + err = request_irq(msi->irq, hisi_pcie_msi_irq, IRQF_NO_THREAD,
344490 + msi->pages = __get_free_pages(GFP_KERNEL, 0);
344491 + base = virt_to_phys((void *)(uintptr_t)msi->pages);
344509 + irq_domain_remove(msi->domain);
344515 + struct hisi_msi *msi = &pcie->msi;
344518 + pcie_info[pcie->nr_controllers].conf_base_addr;
344530 + free_pages(msi->pages, 0);
344532 + if (msi->irq > 0)
344533 + free_irq(msi->irq, pcie);
344536 + irq = irq_find_mapping(msi->domain, i);
344541 + irq_domain_remove(msi->domain);
344554 + return -ENOMEM;
344560 + return -ENOMEM;
344563 + hipcie->dev = &pdev->dev;
344565 + g_of_node = pdev->dev.of_node;
344569 + return -EIO;
344576 + return -EINVAL;
344581 + return -EIO;
344588 + return -EINVAL;
344594 + hipcie->nr_controllers = pcie_controllers_nr;
344596 + hipcie->nr_controllers);
344629 + return -EIO;
344677 + { .compatible = "hisilicon,hisi-pcie", },
344683 + .name = "hisi-pcie",
344691 +MODULE_DESCRIPTION("Hisilicon PCI-Express Root Complex driver");
344693 diff --git a/drivers/pci/hipcie/pcie_hi3519av100.c b/drivers/pci/hipcie/pcie_hi3519av100.c
344696 --- /dev/null
344698 @@ -0,0 +1,281 @@
344700 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
344731 + .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1,
344741 + .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1),
344751 + void __iomem *config_base = (void __iomem *)info->conf_base_addr;
344756 + writel((ptable + i)->viewport, config_base + 0x900);
344757 + writel((ptable + i)->lbar, config_base + 0x90c);
344758 + writel((ptable + i)->ubar, config_base + 0x910);
344759 + writel((ptable + i)->lar, config_base + 0x914);
344760 + writel((ptable + i)->ltar, config_base + 0x918);
344761 + writel((ptable + i)->utar, config_base + 0x91c);
344762 + writel((ptable + i)->region_ctrl_1, config_base + 0x904);
344763 + writel((ptable + i)->region_ctrl_2, config_base + 0x908);
344792 + return -EINVAL;
344799 + return -EINVAL;
344806 + return -EINVAL;
344813 + return -EINVAL;
344820 + return -EINVAL;
344826 + return -EINVAL;
344829 + info->controller = pcie_contrl;
344832 + info->conf_base_addr = (unsigned int)ioremap_nocache(pcie_dbi_base,
344834 + if (!info->conf_base_addr) {
344836 + return -EIO;
344840 + info->base_addr = (unsigned int)ioremap_nocache(pcie_ep_conf_base,
344842 + if (!info->base_addr) {
344843 + iounmap((void *)info->conf_base_addr);
344845 + return -EIO;
344853 + if (info->base_addr) {
344854 + iounmap((void *)info->base_addr);
344857 + if (info->conf_base_addr) {
344858 + iounmap((void *)info->conf_base_addr);
344867 + dbi_base = (void *)info->conf_base_addr;
344913 + * Set PCIE controller class code to be PCI-PCI bridge device
344980 diff --git a/drivers/pci/hipcie/pcie_hi3519av100.h b/drivers/pci/hipcie/pcie_hi3519av100.h
344983 --- /dev/null
344985 @@ -0,0 +1,64 @@
344987 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
345050 diff --git a/drivers/pci/hipcie/pcie_hi3531dv200.c b/drivers/pci/hipcie/pcie_hi3531dv200.c
345053 --- /dev/null
345055 @@ -0,0 +1,611 @@
345057 + * Copyright (c) 2017-2019 HiSilicon Technologies Co., Ltd.
345087 + .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1, /* Limit Address Register */
345097 + .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1), /* Limit Address Register */
345110 + .lar = PCIE_EP1_CONF_BASE + (2 << 20) - 1, /* Limit Address Register */
345120 + .lar = PCIE_EP1_CONF_BASE + (__128MB__ - 1), /* Limit Address Register */
345131 + void __iomem *config_base = (void __iomem *)(uintptr_t)info->conf_base_addr;
345136 + if (info->controller == 1) {
345140 + ctl1_lbar_offset = (unsigned int)(info->root_bus_nr) << 20;
345141 + ptable->lbar += ctl1_lbar_offset;
345142 + ptable->lar += ctl1_lbar_offset;
345144 + (ptable + 1)->lbar += ctl1_lbar_offset;
345149 + writel((ptable + i)->viewport, config_base + ATU_VIEWPORT_REG);
345150 + writel((ptable + i)->lbar, config_base + ATU_BASE_LOW_REG);
345151 + writel((ptable + i)->ubar, config_base + ATU_BASE_HIGH_REG);
345152 + writel((ptable + i)->lar, config_base + ATU_LIMIT_REG);
345153 + writel((ptable + i)->ltar, config_base + ATU_TARGET_LOW_REG);
345154 + writel((ptable + i)->utar, config_base + ATU_ATRGET_HIGH_REG);
345155 + writel((ptable + i)->region_ctrl_1, config_base + ATU_REGION_CTRL1_REG);
345156 + writel((ptable + i)->region_ctrl_2, config_base + ATU_REGION_CTRL2_REG);
345164 + val = readl((void *)(uintptr_t)(info->conf_base_addr + PCIE_SYS_STATE0));
345237 + return -EINVAL;
345244 + return -EINVAL;
345251 + return -EINVAL;
345256 + return -EINVAL;
345263 + return -EINVAL;
345270 + return -EINVAL;
345277 + return -EINVAL;
345283 + return -EINVAL;
345287 + info_tmp->controller = pcie_contrl;
345290 + info_tmp->conf_base_addr = (uintptr_t)ioremap_nocache(pcie_dbi_base,
345292 + if (!info_tmp->conf_base_addr) {
345294 + return -EIO;
345298 + info_tmp->base_addr = (unsigned long)(uintptr_t)ioremap_nocache(
345300 + if (!info_tmp->base_addr) {
345301 + iounmap((void *)(uintptr_t)info_tmp->conf_base_addr);
345303 + return -EIO;
345311 + if (info->base_addr)
345312 + iounmap((void *)(uintptr_t)info->base_addr);
345314 + if (info->conf_base_addr)
345315 + iounmap((void *)(uintptr_t)info->conf_base_addr);
345510 + return -EINVAL;
345516 + return -EINVAL;
345519 + dbi_base = (void *)(uintptr_t)info->conf_base_addr;
345578 + * Set PCIE controller class code to be PCI-PCI bridge device
345667 diff --git a/drivers/pci/hipcie/pcie_hi3531dv200.h b/drivers/pci/hipcie/pcie_hi3531dv200.h
345670 --- /dev/null
345672 @@ -0,0 +1,69 @@
345674 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
345742 diff --git a/drivers/pci/hipcie/pcie_hi3535av100.c b/drivers/pci/hipcie/pcie_hi3535av100.c
345745 --- /dev/null
345747 @@ -0,0 +1,479 @@
345749 + * Copyright (c) 2017-2019 HiSilicon Technologies Co., Ltd.
345779 + .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1, /* Limit Address Register */
345789 + .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1), /* Limit Address Register */
345799 + void __iomem *config_base = (void __iomem *)(uintptr_t)info->conf_base_addr;
345805 + writel((ptable + i)->viewport, config_base + ATU_VIEWPORT_REG);
345806 + writel((ptable + i)->lbar, config_base + ATU_BASE_LOW_REG);
345807 + writel((ptable + i)->ubar, config_base + ATU_BASE_HIGH_REG);
345808 + writel((ptable + i)->lar, config_base + ATU_LIMIT_REG);
345809 + writel((ptable + i)->ltar, config_base + ATU_TARGET_LOW_REG);
345810 + writel((ptable + i)->utar, config_base + ATU_ATRGET_HIGH_REG);
345811 + writel((ptable + i)->region_ctrl_1, config_base + ATU_REGION_CTRL1_REG);
345812 + writel((ptable + i)->region_ctrl_2, config_base + ATU_REGION_CTRL2_REG);
345820 + val = readl((void *)(uintptr_t)(info->conf_base_addr + PCIE_SYS_STATE0));
345887 + return -EINVAL;
345894 + return -EINVAL;
345901 + return -EINVAL;
345908 + return -EINVAL;
345915 + return -EINVAL;
345922 + return -EINVAL;
345928 + return -EINVAL;
345932 + info_tmp->controller = pcie_contrl;
345935 + info_tmp->conf_base_addr = (unsigned long)(uintptr_t)ioremap_nocache(
345937 + if (!info_tmp->conf_base_addr) {
345939 + return -EIO;
345943 + info_tmp->base_addr = (unsigned long)(uintptr_t)ioremap_nocache(
345945 + if (!info_tmp->base_addr) {
345946 + iounmap((void *)(uintptr_t)info_tmp->conf_base_addr);
345948 + return -EIO;
345956 + if (info->base_addr)
345957 + iounmap((void *)(uintptr_t)info->base_addr);
345959 + if (info->conf_base_addr)
345960 + iounmap((void *)(uintptr_t)info->conf_base_addr);
346070 + return -EINVAL;
346076 + return -EINVAL;
346079 + dbi_base = (void *)(uintptr_t)info->conf_base_addr;
346138 + * Set PCIE controller class code to be PCI-PCI bridge device
346227 diff --git a/drivers/pci/hipcie/pcie_hi3559av100.c b/drivers/pci/hipcie/pcie_hi3559av100.c
346230 --- /dev/null
346232 @@ -0,0 +1,389 @@
346234 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
346268 + .lar = PCIE_EP_CONF_BASE + (2 << 20) - 1,
346278 + .lar = PCIE_EP_CONF_BASE + (__128MB__ - 1),
346288 + void __iomem *config_base = (void __iomem *)info->conf_base_addr;
346293 + writel((ptable + i)->viewport, config_base + 0x900);
346294 + writel((ptable + i)->lbar, config_base + 0x90c);
346295 + writel((ptable + i)->ubar, config_base + 0x910);
346296 + writel((ptable + i)->lar, config_base + 0x914);
346297 + writel((ptable + i)->ltar, config_base + 0x918);
346298 + writel((ptable + i)->utar, config_base + 0x91c);
346299 + writel((ptable + i)->region_ctrl_1, config_base + 0x904);
346300 + writel((ptable + i)->region_ctrl_2, config_base + 0x908);
346369 + return -EINVAL;
346376 + return -EINVAL;
346379 + info->controller = 0;
346382 + info->conf_base_addr = (unsigned long)ioremap_nocache(PCIE_DBI_BASE,
346384 + if (!info->conf_base_addr) {
346386 + return -EIO;
346390 + info->base_addr = (unsigned long)ioremap_nocache(PCIE_EP_CONF_BASE,
346392 + if (!info->base_addr) {
346393 + iounmap((void *)info->conf_base_addr);
346395 + return -EIO;
346403 + if (info->base_addr) {
346404 + iounmap((void *)info->base_addr);
346407 + if (info->conf_base_addr) {
346408 + iounmap((void *)info->conf_base_addr);
346419 + dbi_base = (void *)info->conf_base_addr;
346554 + * Set PCIE controller class code to be PCI-PCI bridge device
346622 diff --git a/drivers/pci/hipcie/pcie_hi3559av100.h b/drivers/pci/hipcie/pcie_hi3559av100.h
346625 --- /dev/null
346627 @@ -0,0 +1,79 @@
346629 + * Copyright (c) 2017-2018 HiSilicon Technologies Co., Ltd.
346707 diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
346709 --- a/drivers/pci/pci-driver.c
346710 +++ b/drivers/pci/pci-driver.c
346711 @@ -18,6 +18,7 @@
346719 @@ -389,6 +390,9 @@ static int __pci_device_probe(struct pci_driver *drv, struct pci_dev *pci_dev)
346724 + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
346729 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
346731 --- a/drivers/phy/Kconfig
346733 @@ -56,5 +56,6 @@ source "drivers/phy/samsung/Kconfig"
346740 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
346742 --- a/drivers/phy/Makefile
346744 @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
346745 obj-$(CONFIG_ARCH_RENESAS) += renesas/
346746 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
346747 obj-$(CONFIG_ARCH_TEGRA) += tegra/
346748 +obj-$(CONFIG_ARCH_HISI_BVT) += hibvt/
346749 obj-y += broadcom/ \
346752 diff --git a/drivers/phy/hibvt/Kconfig b/drivers/phy/hibvt/Kconfig
346755 --- /dev/null
346757 @@ -0,0 +1,23 @@
346781 diff --git a/drivers/phy/hibvt/Makefile b/drivers/phy/hibvt/Makefile
346784 --- /dev/null
346786 @@ -0,0 +1,5 @@
346790 +obj-$(CONFIG_PHY_HISI_SATA) += phy-hisi-sata.o
346791 +obj-y += usb/
346792 diff --git a/drivers/phy/hibvt/phy-hi3521dv200-sata.c b/drivers/phy/hibvt/phy-hi3521dv200-sata.c
346795 --- /dev/null
346796 +++ b/drivers/phy/hibvt/phy-hi3521dv200-sata.c
346797 @@ -0,0 +1,681 @@
346799 + * Copyright (c) 2016-2019 HiSilicon Technologies Co., Ltd.
346818 +#include "phy-hisi-sata.h"
347246 + printk("----------hisi_sata_clk_diable--------\n");
347442 + /* set phy PX TX pre-emphasis */
347479 diff --git a/drivers/phy/hibvt/phy-hi3531dv200-sata.c b/drivers/phy/hibvt/phy-hi3531dv200-sata.c
347482 --- /dev/null
347483 +++ b/drivers/phy/hibvt/phy-hi3531dv200-sata.c
347484 @@ -0,0 +1,1081 @@
347486 + * Copyright (c) 2016-2019 HiSilicon Technologies Co., Ltd.
347505 +#include "phy-hisi-sata.h"
348472 + /* set phy PX TX pre-emphasis */
348566 diff --git a/drivers/phy/hibvt/phy-hi3535av100-sata.c b/drivers/phy/hibvt/phy-hi3535av100-sata.c
348569 --- /dev/null
348570 +++ b/drivers/phy/hibvt/phy-hi3535av100-sata.c
348571 @@ -0,0 +1,730 @@
348573 + * Copyright (c) 2016-2019 HiSilicon Technologies Co., Ltd.
348592 +#include "phy-hisi-sata.h"
349235 + /* set phy PX TX pre-emphasis */
349302 diff --git a/drivers/phy/hibvt/phy-hisi-sata.c b/drivers/phy/hibvt/phy-hisi-sata.c
349305 --- /dev/null
349306 +++ b/drivers/phy/hibvt/phy-hisi-sata.c
349307 @@ -0,0 +1,175 @@
349309 + * Copyright (c) 2016-2019 HiSilicon Technologies Co., Ltd.
349343 +#include "phy-hi3531dv200-sata.c"
349347 +#include "phy-hi3535av100-sata.c"
349351 +#include "phy-hi3521dv200-sata.c"
349355 +#include "phy-hi3521dv200-sata.c"
349366 + return -EINVAL;
349409 + struct device *dev = &pdev->dev;
349417 + return -ENOENT;
349420 + mmio = devm_ioremap(dev, res->start, resource_size(res));
349422 + return -ENOMEM;
349430 + of_property_read_u32(dev->of_node, "ports_num_max", &ports_num);
349444 + struct device *dev = &pdev->dev;
349454 + struct device *dev = &pdev->dev;
349463 + { .compatible = "hisilicon,hisi-sata-phy", },
349473 + .name = "hisi-sata-phy",
349481 +MODULE_ALIAS("platform:hisi-sata-phy");
349483 diff --git a/drivers/phy/hibvt/phy-hisi-sata.h b/drivers/phy/hibvt/phy-hisi-sata.h
349486 --- /dev/null
349487 +++ b/drivers/phy/hibvt/phy-hisi-sata.h
349488 @@ -0,0 +1,39 @@
349490 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
349528 diff --git a/drivers/phy/hibvt/usb/Kconfig b/drivers/phy/hibvt/usb/Kconfig
349531 --- /dev/null
349533 @@ -0,0 +1,85 @@
349619 diff --git a/drivers/phy/hibvt/usb/Makefile b/drivers/phy/hibvt/usb/Makefile
349622 --- /dev/null
349624 @@ -0,0 +1,17 @@
349625 +obj-$(CONFIG_HIBVT_USB_PHY) += phy-hisi-usb.o
349626 +obj-$(CONFIG_ARCH_HI3531DV200) += phy-hi3531dv200-usb.o
349627 +obj-$(CONFIG_ARCH_HI3535AV100) += phy-hi3531dv200-usb.o
349628 +obj-$(CONFIG_ARCH_HI3521DV200) += phy-hi3521dv200-usb.o
349629 +obj-$(CONFIG_ARCH_HI3520DV500) += phy-hi3521dv200-usb.o
349630 +obj-$(CONFIG_ARCH_HI3559AV100) += phy-hi3559av100-usb.o
349631 +obj-$(CONFIG_ARCH_HI3569V100) += phy-hi3559av100-usb.o
349632 +obj-$(CONFIG_ARCH_HI3556AV100) += phy-hi3556av100-usb.o
349633 +obj-$(CONFIG_ARCH_HI3519AV100) += phy-hi3519av100-usb.o
349634 +obj-$(CONFIG_ARCH_HI3568V100) += phy-hi3519av100-usb.o
349635 +obj-$(CONFIG_ARCH_HI3516CV500) += phy-hi3516cv500-usb.o
349636 +obj-$(CONFIG_ARCH_HI3516DV300) += phy-hi3516dv300-usb.o
349637 +obj-$(CONFIG_ARCH_HI3559V200) += phy-hi3559v200-usb.o
349638 +obj-$(CONFIG_ARCH_HI3562V100) += phy-hi3559v200-usb.o
349639 +obj-$(CONFIG_ARCH_HI3566V100) += phy-hi3559v200-usb.o
349640 +obj-$(CONFIG_ARCH_HI3556V200) += phy-hi3556v200-usb.o
349641 +obj-$(CONFIG_PHY_HISI_XVP_USB2) += phy-hixvp-hisi-usb.o
349642 diff --git a/drivers/phy/hibvt/usb/phy-hi3516cv500-usb.c b/drivers/phy/hibvt/usb/phy-hi3516cv500-us…
349645 --- /dev/null
349646 +++ b/drivers/phy/hibvt/usb/phy-hi3516cv500-usb.c
349647 @@ -0,0 +1,310 @@
349649 + * phy-hi3516cv500-usb.c
349653 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
349674 +#include "phy-hisi-usb.h"
349804 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349806 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349810 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349812 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349816 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349818 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349824 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349828 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349832 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349835 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349839 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349841 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349845 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349849 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349858 + priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
349859 + if (priv->ctrl_base == NULL)
349862 + reg = readl(priv->ctrl_base + REG_GUCTL1);
349866 + writel(reg, priv->ctrl_base + REG_GUCTL1);
349869 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
349871 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
349874 + reg = readl(priv->ctrl_base + REG_GCTL);
349877 + writel(reg, priv->ctrl_base + REG_GCTL);
349880 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
349883 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
349886 + writel(USB2_G_TXTHRCFG, priv->ctrl_base + GTXTHRCFG);
349887 + writel(USB2_G_RXTHRCFG, priv->ctrl_base + GRXTHRCFG);
349890 + iounmap(priv->ctrl_base);
349908 + /* Pre-emphasis tuning */
349914 + /* Pre-emphasis strength */
349952 + reg = readl(priv->peri_crg + CRG_BASE_REG);
349954 + writel(reg, priv->peri_crg + CRG_BASE_REG);
349958 diff --git a/drivers/phy/hibvt/usb/phy-hi3516dv300-usb.c b/drivers/phy/hibvt/usb/phy-hi3516dv300-us…
349961 --- /dev/null
349962 +++ b/drivers/phy/hibvt/usb/phy-hi3516dv300-usb.c
349963 @@ -0,0 +1,310 @@
349965 + * phy-hi3516dv300-usb.c
349969 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
349990 +#include "phy-hisi-usb.h"
350120 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350122 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350126 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350128 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350132 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350134 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350140 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350144 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350148 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350151 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350155 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350157 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350161 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350165 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350174 + priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
350175 + if (priv->ctrl_base == NULL)
350178 + reg = readl(priv->ctrl_base + REG_GUCTL1);
350182 + writel(reg, priv->ctrl_base + REG_GUCTL1);
350185 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
350187 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
350190 + reg = readl(priv->ctrl_base + REG_GCTL);
350193 + writel(reg, priv->ctrl_base + REG_GCTL);
350196 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
350199 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
350202 + writel(USB2_G_TXTHRCFG, priv->ctrl_base + GTXTHRCFG);
350203 + writel(USB2_G_RXTHRCFG, priv->ctrl_base + GRXTHRCFG);
350206 + iounmap(priv->ctrl_base);
350224 + /* Pre-emphasis tuning */
350230 + /* Pre-emphasis strength */
350268 + reg = readl(priv->peri_crg + CRG_BASE_REG);
350270 + writel(reg, priv->peri_crg + CRG_BASE_REG);
350274 diff --git a/drivers/phy/hibvt/usb/phy-hi3519av100-usb.c b/drivers/phy/hibvt/usb/phy-hi3519av100-us…
350277 --- /dev/null
350278 +++ b/drivers/phy/hibvt/usb/phy-hi3519av100-usb.c
350279 @@ -0,0 +1,431 @@
350281 + * phy-hi3519av100-usb.c
350285 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
350306 +#include "phy-hisi-usb.h"
350395 + reg = readl(priv->peri_crg + USB3_CTRL);
350398 + writel(reg, priv->peri_crg + USB3_CTRL);
350402 + reg = readl(priv->peri_crg + USB3_CTRL);
350404 + writel(reg, priv->peri_crg + USB3_CTRL);
350408 + reg = readl(priv->peri_crg + USB2_PHY);
350410 + writel(reg, priv->peri_crg + USB2_PHY);
350414 + reg = readl(priv->peri_crg + USB3_CTRL);
350416 + writel(reg, priv->peri_crg + USB3_CTRL);
350420 + reg = readl(priv->peri_crg + USB2_PHY);
350422 + writel(reg, priv->peri_crg + USB2_PHY);
350426 + reg = readl(priv->peri_crg + USB2_PHY);
350428 + writel(reg, priv->peri_crg + USB2_PHY);
350432 + reg = readl(priv->peri_crg + USB3_CTRL);
350434 + writel(reg, priv->peri_crg + USB3_CTRL);
350443 + priv->ctrl_base = ioremap_nocache(USB2_CTRL_REGBASE, __64K__);
350444 + if (priv->ctrl_base == NULL)
350447 + reg = readl(priv->ctrl_base + REG_GUCTL1);
350451 + writel(reg, priv->ctrl_base + REG_GUCTL1);
350455 + reg = readl(priv->ctrl_base + REG_GCTL);
350458 + writel(reg, priv->ctrl_base + REG_GCTL);
350460 + iounmap(priv->ctrl_base);
350468 + /* port0 phy high-spped DC adjust: 0% --> 4% */
350469 + /* port0 pre elec adjust: 0 --> 1x */
350470 + reg = readl(priv->misc_ctrl + USB2_PHY0);
350475 + writel(reg, priv->misc_ctrl + USB2_PHY0);
350478 + /* port1 phy high-spped DC adjust: 0% --> 4% */
350479 + /* port1 pre elec adjust: 0 --> 1x */
350480 + reg = readl(priv->misc_ctrl + USB2_PHY1);
350485 + writel(reg, priv->misc_ctrl + USB2_PHY1);
350499 + reg = readl(priv->sys_ctrl + SYSSTAT);
350502 + reg = readl(priv->peri_crg + USB3_COMBPHY);
350504 + writel(reg, priv->peri_crg + USB3_COMBPHY);
350508 + reg = readl(priv->peri_crg + USB3_CTRL);
350510 + writel(reg, priv->peri_crg + USB3_CTRL);
350515 + reg = readl(priv->sys_ctrl + SYSSTAT);
350518 + reg = readl(priv->peri_crg + USB3_COMBPHY);
350520 + writel(reg, priv->peri_crg + USB3_COMBPHY);
350523 + reg = readl(priv->peri_crg + USB3_COMBPHY);
350525 + writel(reg, priv->peri_crg + USB3_COMBPHY);
350537 + reg = readl(priv->peri_crg + USB3_CTRL);
350540 + writel(reg, priv->peri_crg + USB3_CTRL);
350544 + reg = readl(priv->misc_ctrl + PORT0_CTRL);
350546 + writel(reg, priv->misc_ctrl + PORT0_CTRL);
350552 + reg = readl(priv->peri_crg + USB2_PHY);
350554 + writel(reg, priv->peri_crg + USB2_PHY);
350558 + reg = readl(priv->peri_crg + USB3_CTRL);
350560 + writel(reg, priv->peri_crg + USB3_CTRL);
350564 + reg = readl(priv->peri_crg + USB2_PHY);
350566 + writel(reg, priv->peri_crg + USB2_PHY);
350570 + reg = readl(priv->peri_crg + USB2_PHY);
350572 + writel(reg, priv->peri_crg + USB2_PHY);
350578 + reg = readl(priv->peri_crg + USB3_CTRL);
350580 + writel(reg, priv->peri_crg + USB3_CTRL);
350589 + priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
350590 + if (priv->ctrl_base == NULL)
350593 + reg = readl(priv->ctrl_base + REG_GUCTL1);
350597 + writel(reg, priv->ctrl_base + REG_GUCTL1);
350600 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
350602 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
350606 + reg = readl(priv->ctrl_base + REG_GCTL);
350609 + writel(reg, priv->ctrl_base + REG_GCTL);
350612 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
350615 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
350618 + writel(PERI_USB3_GTXTHRCFG, priv->ctrl_base + GTXTHRCFG);
350621 + iounmap(priv->ctrl_base);
350629 + priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
350630 + if (priv->ctrl_base == NULL)
350635 + * adjust 0x1000 --> 0x1001.
350637 + reg = readl(priv->sys_ctrl + HPM_INFO_OFFSET);
350639 + writel(TX_SWING_COMP_CFG, priv->misc_ctrl + USB3_PCIE_COMBO_PHY);
350640 + writel(TX_SWING_COMP_RCFG, priv->misc_ctrl + USB3_PCIE_COMBO_PHY);
350641 + writel(TX_SWING_COMP_CFG_VAL, priv->misc_ctrl + USB3_PCIE_COMBO_PHY);
350646 + /* usb3 Tx margin adjust: 0 --> 900mv */
350647 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
350650 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
350653 + iounmap(priv->ctrl_base);
350683 + reg = readl(priv->peri_crg + USB3_CTRL);
350685 + writel(reg, priv->peri_crg + USB3_CTRL);
350696 + reg = readl(priv->peri_crg + USB3_CTRL);
350698 + writel(reg, priv->peri_crg + USB3_CTRL);
350701 + reg = readl(priv->sys_ctrl + SYSSTAT);
350704 + reg = readl(priv->peri_crg + USB3_COMBPHY);
350706 + writel(reg, priv->peri_crg + USB3_COMBPHY);
350711 diff --git a/drivers/phy/hibvt/usb/phy-hi3521dv200-usb.c b/drivers/phy/hibvt/usb/phy-hi3521dv200-us…
350714 --- /dev/null
350715 +++ b/drivers/phy/hibvt/usb/phy-hi3521dv200-usb.c
350716 @@ -0,0 +1,446 @@
350718 + * phy-hi3521dv200-usb.c
350742 +#include "phy-hisi-usb.h"
350830 + writel(DEF_VAL_3632, priv->peri_crg + PERI_CRG3632);
350831 + writel(DEF_VAL_3636, priv->peri_crg + PERI_CRG3636);
350832 + writel(DEF_VAL_3640, priv->peri_crg + PERI_CRG3640);
350833 + writel(DEF_VAL_3644, priv->peri_crg + PERI_CRG3644);
350834 + writel(DEF_VAL_3672, priv->peri_crg + PERI_CRG3672);
350850 + trim_val = readl(priv->sys_ctrl);
350921 + trim_val = readl(priv->sys_ctrl);
350992 + trim_val = readl(priv->sys_ctrl);
351068 + reg = readl(priv->peri_crg + PERI_CRG3636);
351070 + writel(reg, priv->peri_crg + PERI_CRG3636);
351074 + reg = readl(priv->peri_crg + PERI_CRG3672);
351076 + writel(reg, priv->peri_crg + PERI_CRG3672);
351080 + reg = readl(priv->peri_crg + PERI_CRG3636);
351082 + writel(reg, priv->peri_crg + PERI_CRG3636);
351086 + reg = readl(priv->peri_crg + PERI_CRG3672);
351088 + writel(reg, priv->peri_crg + PERI_CRG3672);
351096 + reg = readl(priv->peri_crg + PERI_CRG3632);
351102 + writel(reg, priv->peri_crg + PERI_CRG3632);
351106 + reg = readl(priv->peri_crg + PERI_CRG3632);
351108 + writel(reg, priv->peri_crg + PERI_CRG3632);
351120 + reg = readl(priv->peri_crg + PERI_CRG3644);
351122 + writel(reg, priv->peri_crg + PERI_CRG3644);
351126 + reg = readl(priv->peri_crg + PERI_CRG3644);
351128 + writel(reg, priv->peri_crg + PERI_CRG3644);
351134 + reg = readl(priv->peri_crg + PERI_CRG3640);
351138 + writel(reg, priv->peri_crg + PERI_CRG3640);
351142 + reg = readl(priv->peri_crg + PERI_CRG3640);
351144 + writel(reg, priv->peri_crg + PERI_CRG3640);
351163 diff --git a/drivers/phy/hibvt/usb/phy-hi3531dv200-usb.c b/drivers/phy/hibvt/usb/phy-hi3531dv200-us…
351166 --- /dev/null
351167 +++ b/drivers/phy/hibvt/usb/phy-hi3531dv200-usb.c
351168 @@ -0,0 +1,526 @@
351170 + * phy-hi3531dv200-usb.c
351194 +#include "phy-hisi-usb.h"
351324 + trim_val = readl(priv->sys_ctrl);
351358 + reg = readl(priv->peri_crg + PERI_CRG3640);
351360 + writel(reg, priv->peri_crg + PERI_CRG3640);
351364 + reg = readl(priv->peri_crg + PERI_CRG3644);
351366 + writel(reg, priv->peri_crg + PERI_CRG3644);
351370 + reg = readl(priv->peri_crg + PERI_CRG3644);
351372 + writel(reg, priv->peri_crg + PERI_CRG3644);
351376 + reg = readl(priv->peri_crg + PERI_CRG3644);
351378 + writel(reg, priv->peri_crg + PERI_CRG3644);
351382 + reg = readl(priv->peri_crg + PERI_CRG3640);
351386 + writel(reg, priv->peri_crg + PERI_CRG3640);
351390 + reg = readl(priv->peri_crg + PERI_CRG3640);
351392 + writel(reg, priv->peri_crg + PERI_CRG3640);
351410 + reg = readl(priv->peri_crg + PERI_CRG3640);
351412 + writel(reg, priv->peri_crg + PERI_CRG3640);
351416 + reg = readl(priv->peri_crg + PERI_CRG3644);
351418 + writel(reg, priv->peri_crg + PERI_CRG3644);
351456 + trim_val = readl(priv->sys_ctrl);
351516 + trim_val = readl(priv->sys_ctrl);
351553 + writel(PI_CURRENT_TRIM_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0);
351554 + writel(PI_CURRENT_TRIM_VAL, priv->misc_ctrl + COMBPHY_CTRL0);
351555 + writel(PI_CURRENT_TRIM_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0);
351559 + writel(TX_SWING_COMP_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0);
351560 + writel(TX_SWING_COMP_VAL, priv->misc_ctrl + COMBPHY_CTRL0);
351561 + writel(TX_SWING_COMP_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0);
351571 + reg = readl(priv->misc_ctrl + USB_CTRL6);
351573 + writel(reg, priv->misc_ctrl + USB_CTRL6);
351577 + reg = readl(priv->peri_crg + PERI_CRG3664);
351579 + writel(reg, priv->peri_crg + PERI_CRG3664);
351583 + reg = readl(priv->peri_crg + PERI_CRG3676);
351585 + writel(reg, priv->peri_crg + PERI_CRG3676);
351589 + reg = readl(priv->peri_crg + PERI_CRG3636);
351591 + writel(reg, priv->peri_crg + PERI_CRG3636);
351595 + reg = readl(priv->peri_crg + PERI_CRG3672);
351597 + writel(reg, priv->peri_crg + PERI_CRG3672);
351601 + reg = readl(priv->peri_crg + PERI_CRG3636);
351603 + writel(reg, priv->peri_crg + PERI_CRG3636);
351607 + reg = readl(priv->peri_crg + PERI_CRG3672);
351609 + writel(reg, priv->peri_crg + PERI_CRG3672);
351613 + reg = readl(priv->peri_crg + PERI_CRG3636);
351615 + writel(reg, priv->peri_crg + PERI_CRG3636);
351619 + reg = readl(priv->peri_crg + PERI_CRG3672);
351621 + writel(reg, priv->peri_crg + PERI_CRG3672);
351625 + reg = readl(priv->peri_crg + PERI_CRG3676);
351627 + writel(reg, priv->peri_crg + PERI_CRG3676);
351631 + reg = readl(priv->peri_crg + PERI_CRG3676);
351633 + writel(reg, priv->peri_crg + PERI_CRG3676);
351637 + reg = readl(priv->peri_crg + PERI_CRG3664);
351643 + writel(reg, priv->peri_crg + PERI_CRG3664);
351647 + reg = readl(priv->peri_crg + PERI_CRG3632);
351649 + writel(reg, priv->peri_crg + PERI_CRG3632);
351653 + reg = readl(priv->peri_crg + PERI_CRG3664);
351655 + writel(reg, priv->peri_crg + PERI_CRG3664);
351677 + reg = readl(priv->peri_crg + PERI_CRG3664);
351679 + writel(reg, priv->peri_crg + PERI_CRG3664);
351683 + reg = readl(priv->peri_crg + PERI_CRG3636);
351685 + writel(reg, priv->peri_crg + PERI_CRG3636);
351689 + reg = readl(priv->peri_crg + PERI_CRG3672);
351691 + writel(reg, priv->peri_crg + PERI_CRG3672);
351695 diff --git a/drivers/phy/hibvt/usb/phy-hi3556av100-usb.c b/drivers/phy/hibvt/usb/phy-hi3556av100-us…
351698 --- /dev/null
351699 +++ b/drivers/phy/hibvt/usb/phy-hi3556av100-usb.c
351700 @@ -0,0 +1,429 @@
351702 + * phy-hi3556av100-usb.c
351706 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
351727 +#include "phy-hisi-usb.h"
351816 + reg = readl(priv->peri_crg + USB3_CTRL);
351819 + writel(reg, priv->peri_crg + USB3_CTRL);
351823 + reg = readl(priv->peri_crg + USB3_CTRL);
351825 + writel(reg, priv->peri_crg + USB3_CTRL);
351829 + reg = readl(priv->peri_crg + USB2_PHY);
351831 + writel(reg, priv->peri_crg + USB2_PHY);
351835 + reg = readl(priv->peri_crg + USB3_CTRL);
351837 + writel(reg, priv->peri_crg + USB3_CTRL);
351841 + reg = readl(priv->peri_crg + USB2_PHY);
351843 + writel(reg, priv->peri_crg + USB2_PHY);
351847 + reg = readl(priv->peri_crg + USB2_PHY);
351849 + writel(reg, priv->peri_crg + USB2_PHY);
351853 + reg = readl(priv->peri_crg + USB3_CTRL);
351855 + writel(reg, priv->peri_crg + USB3_CTRL);
351864 + priv->ctrl_base = ioremap_nocache(USB2_CTRL_REGBASE, __64K__);
351865 + if (priv->ctrl_base == NULL)
351868 + reg = readl(priv->ctrl_base + REG_GUCTL1);
351872 + writel(reg, priv->ctrl_base + REG_GUCTL1);
351876 + reg = readl(priv->ctrl_base + REG_GCTL);
351879 + writel(reg, priv->ctrl_base + REG_GCTL);
351881 + iounmap(priv->ctrl_base);
351889 + /* port0 phy high-spped DC adjust: 0% --> 4% */
351890 + /* port0 pre elec adjust: 0 --> 1x */
351891 + reg = readl(priv->misc_ctrl + USB2_PHY0);
351896 + writel(reg, priv->misc_ctrl + USB2_PHY0);
351899 + /* port1 phy high-spped DC adjust: 0% --> 4% */
351900 + /* port1 pre elec adjust: 0 --> 1x */
351901 + reg = readl(priv->misc_ctrl + USB2_PHY1);
351906 + writel(reg, priv->misc_ctrl + USB2_PHY1);
351920 + reg = readl(priv->sys_ctrl + SYSSTAT);
351923 + reg = readl(priv->peri_crg + USB3_COMBPHY);
351925 + writel(reg, priv->peri_crg + USB3_COMBPHY);
351929 + reg = readl(priv->peri_crg + USB3_CTRL);
351931 + writel(reg, priv->peri_crg + USB3_CTRL);
351936 + reg = readl(priv->sys_ctrl + SYSSTAT);
351939 + reg = readl(priv->peri_crg + USB3_COMBPHY);
351941 + writel(reg, priv->peri_crg + USB3_COMBPHY);
351944 + reg = readl(priv->peri_crg + USB3_COMBPHY);
351946 + writel(reg, priv->peri_crg + USB3_COMBPHY);
351958 + reg = readl(priv->peri_crg + USB3_CTRL);
351961 + writel(reg, priv->peri_crg + USB3_CTRL);
351965 + reg = readl(priv->misc_ctrl + PORT0_CTRL);
351967 + writel(reg, priv->misc_ctrl + PORT0_CTRL);
351973 + reg = readl(priv->peri_crg + USB2_PHY);
351975 + writel(reg, priv->peri_crg + USB2_PHY);
351979 + reg = readl(priv->peri_crg + USB3_CTRL);
351981 + writel(reg, priv->peri_crg + USB3_CTRL);
351985 + reg = readl(priv->peri_crg + USB2_PHY);
351987 + writel(reg, priv->peri_crg + USB2_PHY);
351991 + reg = readl(priv->peri_crg + USB2_PHY);
351993 + writel(reg, priv->peri_crg + USB2_PHY);
351999 + reg = readl(priv->peri_crg + USB3_CTRL);
352001 + writel(reg, priv->peri_crg + USB3_CTRL);
352010 + priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
352011 + if (priv->ctrl_base == NULL)
352014 + reg = readl(priv->ctrl_base + REG_GUCTL1);
352018 + writel(reg, priv->ctrl_base + REG_GUCTL1);
352021 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352023 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352027 + reg = readl(priv->ctrl_base + REG_GCTL);
352030 + writel(reg, priv->ctrl_base + REG_GCTL);
352033 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352036 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352039 + writel(PERI_USB3_GTXTHRCFG, priv->ctrl_base + GTXTHRCFG);
352042 + iounmap(priv->ctrl_base);
352050 + priv->ctrl_base = ioremap_nocache(USB3_CTRL_REGBASE, __64K__);
352051 + if (priv->ctrl_base == NULL)
352056 + * adjust 0x1000 --> 0x1001.
352058 + reg = readl(priv->sys_ctrl + HPM_INFO_OFFSET);
352060 + writel(TX_SWING_COMP_CFG, priv->misc_ctrl + USB3_PCIE_COMBO_PHY);
352061 + writel(TX_SWING_COMP_RCFG, priv->misc_ctrl + USB3_PCIE_COMBO_PHY);
352062 + writel(TX_SWING_COMP_CFG_VAL, priv->misc_ctrl + USB3_PCIE_COMBO_PHY);
352066 + /* usb3 Tx margin adjust: 0 --> 900mv */
352067 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352070 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352072 + iounmap(priv->ctrl_base);
352102 + reg = readl(priv->peri_crg + USB3_CTRL);
352104 + writel(reg, priv->peri_crg + USB3_CTRL);
352115 + reg = readl(priv->peri_crg + USB3_CTRL);
352117 + writel(reg, priv->peri_crg + USB3_CTRL);
352120 + reg = readl(priv->sys_ctrl + SYSSTAT);
352123 + reg = readl(priv->peri_crg + USB3_COMBPHY);
352125 + writel(reg, priv->peri_crg + USB3_COMBPHY);
352130 diff --git a/drivers/phy/hibvt/usb/phy-hi3556v200-usb.c b/drivers/phy/hibvt/usb/phy-hi3556v200-usb.c
352133 --- /dev/null
352134 +++ b/drivers/phy/hibvt/usb/phy-hi3556v200-usb.c
352135 @@ -0,0 +1,310 @@
352137 + * phy-hi3556v200-usb.c
352141 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
352162 +#include "phy-hisi-usb.h"
352292 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352294 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352298 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352300 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352304 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352306 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352312 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352316 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352320 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352323 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352327 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352329 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352333 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352337 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352346 + priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
352347 + if (priv->ctrl_base == NULL)
352350 + reg = readl(priv->ctrl_base + REG_GUCTL1);
352354 + writel(reg, priv->ctrl_base + REG_GUCTL1);
352357 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352359 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352362 + reg = readl(priv->ctrl_base + REG_GCTL);
352365 + writel(reg, priv->ctrl_base + REG_GCTL);
352368 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352371 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352374 + writel(USB2_G_TXTHRCFG, priv->ctrl_base + GTXTHRCFG);
352375 + writel(USB2_G_RXTHRCFG, priv->ctrl_base + GRXTHRCFG);
352378 + iounmap(priv->ctrl_base);
352396 + /* Pre-emphasis tuning */
352402 + /* Pre-emphasis strength */
352440 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352442 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352446 diff --git a/drivers/phy/hibvt/usb/phy-hi3559av100-usb.c b/drivers/phy/hibvt/usb/phy-hi3559av100-us…
352449 --- /dev/null
352450 +++ b/drivers/phy/hibvt/usb/phy-hi3559av100-usb.c
352451 @@ -0,0 +1,372 @@
352453 + * phy-hi3559av100-usb.c
352457 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
352478 +#include "phy-hisi-usb.h"
352564 + reg = readl(priv->sys_ctrl + SYSSTAT);
352592 + reg = readl(priv->peri_crg + USB3_COMBPHY);
352595 + reg = readl(priv->peri_crg + USB3_CTRL);
352597 + writel(reg, priv->peri_crg + USB3_CTRL);
352602 + writel(reg, priv->peri_crg + USB3_COMBPHY);
352605 + reg = readl(priv->peri_crg + USB3_CTRL);
352607 + writel(reg, priv->peri_crg + USB3_CTRL);
352611 + writel(reg, priv->peri_crg + USB3_COMBPHY);
352618 + reg = readl(priv->peri_crg + USB3_COMBPHY);
352628 + writel(reg, priv->peri_crg + USB3_COMBPHY);
352638 + reg = readl(priv->peri_crg + USB3_CTRL);
352640 + writel(reg, priv->peri_crg + USB3_CTRL);
352646 + reg = readl(priv->misc_ctrl + USB_PORT0);
352648 + writel(reg, priv->misc_ctrl + USB_PORT0);
352651 + reg = readl(priv->misc_ctrl + USB_PORT1);
352653 + writel(reg, priv->misc_ctrl + USB_PORT1);
352656 + reg = readl(priv->peri_crg + USB2_PHY);
352658 + writel(reg, priv->peri_crg + USB2_PHY);
352662 + reg = readl(priv->peri_crg + USB3_CTRL);
352664 + writel(reg, priv->peri_crg + USB3_CTRL);
352668 + reg = readl(priv->peri_crg + USB2_PHY);
352670 + writel(reg, priv->peri_crg + USB2_PHY);
352674 + reg = readl(priv->peri_crg + USB2_PHY);
352676 + writel(reg, priv->peri_crg + USB2_PHY);
352682 + reg = readl(priv->peri_crg + USB3_CTRL);
352684 + writel(reg, priv->peri_crg + USB3_CTRL);
352693 + reg = readl(priv->ctrl_base + REG_GUCTL1);
352697 + writel(reg, priv->ctrl_base + REG_GUCTL1);
352700 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352702 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352705 + reg = readl(priv->ctrl_base + REG_GCTL);
352708 + writel(reg, priv->ctrl_base + REG_GCTL);
352711 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
352714 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
352721 + writel(reg, priv->ctrl_base + GTXTHRCFG);
352723 + writel(reg, priv->ctrl_base + GRXTHRCFG);
352738 + reg = readl(priv->misc_ctrl + USB2_PHY0_CTRL);
352740 + reg |= USB2_PHY_VREF; /* [7:4] -> (eye vref = 4%) */
352741 + reg |= USB2_PHY_PRE; /* [13:12] -> (pre electric = 3x) */
352742 + writel(reg, priv->misc_ctrl + USB2_PHY0_CTRL);
352746 + reg = readl(priv->misc_ctrl + USB2_PHY1_CTRL);
352748 + reg |= USB2_PHY_VREF; /* [7:4] -> (eye vref = 4%) */
352749 + reg |= USB2_PHY_PRE; /* [13:12] -> (pre electric = 3x) */
352750 + writel(reg, priv->misc_ctrl + USB2_PHY1_CTRL);
352755 + * adjust 0x1000 --> 0x1001.
352759 + writel(P0_TX_SWING_COMP_CFG, priv->misc_ctrl + USB3_COMB_PHY);
352760 + writel(P0_TX_SWING_COMP_RCFG, priv->misc_ctrl + USB3_COMB_PHY);
352761 + writel(P0_TX_SWING_COMP_VAL, priv->misc_ctrl + USB3_COMB_PHY);
352764 + writel(P1_TX_SWING_COMP_CFG, priv->misc_ctrl + USB3_COMB_PHY);
352765 + writel(P1_TX_SWING_COMP_RCFG, priv->misc_ctrl + USB3_COMB_PHY);
352766 + writel(P1_TX_SWING_COMP_VAL, priv->misc_ctrl + USB3_COMB_PHY);
352772 + writel(USB3_TX_MARGIN_VAL, priv->ctrl_base + REG_GUSB3PIPECTL0);
352784 + if (priv->phyid == IS_CTRL1) {
352805 + if (priv->phyid == IS_CTRL1)
352808 + reg = readl(priv->peri_crg + USB3_CTRL);
352810 + writel(reg, priv->peri_crg + USB3_CTRL);
352813 + reg = readl(priv->peri_crg + USB3_COMBPHY);
352820 + writel(reg, priv->peri_crg + USB3_COMBPHY);
352824 diff --git a/drivers/phy/hibvt/usb/phy-hi3559v200-usb.c b/drivers/phy/hibvt/usb/phy-hi3559v200-usb.c
352827 --- /dev/null
352828 +++ b/drivers/phy/hibvt/usb/phy-hi3559v200-usb.c
352829 @@ -0,0 +1,310 @@
352831 + * phy-hi3559v200-usb.c
352835 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
352856 +#include "phy-hisi-usb.h"
352986 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352988 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352992 + reg = readl(priv->peri_crg + CRG_BASE_REG);
352994 + writel(reg, priv->peri_crg + CRG_BASE_REG);
352998 + reg = readl(priv->peri_crg + CRG_BASE_REG);
353000 + writel(reg, priv->peri_crg + CRG_BASE_REG);
353006 + reg = readl(priv->peri_crg + CRG_BASE_REG);
353010 + writel(reg, priv->peri_crg + CRG_BASE_REG);
353014 + reg = readl(priv->peri_crg + CRG_BASE_REG);
353017 + writel(reg, priv->peri_crg + CRG_BASE_REG);
353021 + reg = readl(priv->peri_crg + CRG_BASE_REG);
353023 + writel(reg, priv->peri_crg + CRG_BASE_REG);
353027 + reg = readl(priv->peri_crg + CRG_BASE_REG);
353031 + writel(reg, priv->peri_crg + CRG_BASE_REG);
353040 + priv->ctrl_base = ioremap_nocache(CTRL_BASE_REG, __64K__);
353041 + if (priv->ctrl_base == NULL)
353044 + reg = readl(priv->ctrl_base + REG_GUCTL1);
353048 + writel(reg, priv->ctrl_base + REG_GUCTL1);
353051 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
353053 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
353056 + reg = readl(priv->ctrl_base + REG_GCTL);
353059 + writel(reg, priv->ctrl_base + REG_GCTL);
353062 + reg = readl(priv->ctrl_base + REG_GUSB3PIPECTL0);
353065 + writel(reg, priv->ctrl_base + REG_GUSB3PIPECTL0);
353068 + writel(USB2_G_TXTHRCFG, priv->ctrl_base + GTXTHRCFG);
353069 + writel(USB2_G_RXTHRCFG, priv->ctrl_base + GRXTHRCFG);
353072 + iounmap(priv->ctrl_base);
353090 + /* Pre-emphasis tuning */
353096 + /* Pre-emphasis strength */
353134 + reg = readl(priv->peri_crg + CRG_BASE_REG);
353136 + writel(reg, priv->peri_crg + CRG_BASE_REG);
353140 diff --git a/drivers/phy/hibvt/usb/phy-hisi-usb.c b/drivers/phy/hibvt/usb/phy-hisi-usb.c
353143 --- /dev/null
353144 +++ b/drivers/phy/hibvt/usb/phy-hisi-usb.c
353145 @@ -0,0 +1,149 @@
353147 + * phy-hisi-usb.c
353172 +#include "phy-hisi-usb.h"
353176 + struct device *dev = &pdev->dev;
353179 + struct device_node *np = pdev->dev.of_node;
353183 + return -ENOMEM;
353188 + return -ENOMEM;
353191 + priv->peri_crg = of_iomap(np, CRG_NODE_IDX);
353192 + if (IS_ERR(priv->peri_crg))
353193 + priv->peri_crg = NULL;
353195 + priv->misc_ctrl = of_iomap(np, MISC_NODE_IDX);
353196 + if (IS_ERR(priv->misc_ctrl))
353197 + priv->misc_ctrl = NULL;
353199 + priv->sys_ctrl = of_iomap(np, SYS_NODE_IDX);
353200 + if (IS_ERR(priv->sys_ctrl))
353201 + priv->sys_ctrl = NULL;
353203 + priv->ctrl_base = of_iomap(np, CTRL_NODE_IDX);
353204 + if (IS_ERR(priv->ctrl_base))
353205 + priv->ctrl_base = NULL;
353207 + if (of_property_read_u32(np, "phyid", &priv->phyid))
353208 + return -EINVAL;
353219 + iounmap(priv->peri_crg);
353220 + iounmap(priv->misc_ctrl);
353221 + iounmap(priv->sys_ctrl);
353223 + iounmap(priv->ctrl_base);
353231 + struct device *dev = &pdev->dev;
353232 + struct phy *phy = dev_get_drvdata(&pdev->dev);
353248 + { .compatible = "hisilicon,hisi-usb-phy", },
353249 + { .compatible = "hisilicon,hisi-usb3-phy_0", },
353250 + { .compatible = "hisilicon,hisi-usb3-phy_1", },
353288 + .name = "hisi-usb-phy",
353295 diff --git a/drivers/phy/hibvt/usb/phy-hisi-usb.h b/drivers/phy/hibvt/usb/phy-hisi-usb.h
353298 --- /dev/null
353299 +++ b/drivers/phy/hibvt/usb/phy-hisi-usb.h
353300 @@ -0,0 +1,72 @@
353302 + * phy-hisi-usb.h
353373 diff --git a/drivers/phy/hibvt/usb/phy-hixvp-hisi-usb.c b/drivers/phy/hibvt/usb/phy-hixvp-hisi-usb.c
353376 --- /dev/null
353377 +++ b/drivers/phy/hibvt/usb/phy-hixvp-hisi-usb.c
353378 @@ -0,0 +1,803 @@
353380 + * phy-hixvp-hisi-usb.c
353400 +#include <linux/clk-provider.h>
353410 +#include "phy-hisi-usb.h"
353483 + priv->vbus_flag = 1;
353485 + priv->pwren_flag = 1;
353487 + priv->ana_cfg_0_flag = 1;
353489 + priv->ana_cfg_2_flag = 1;
353491 + priv->ana_cfg_4_flag = 1;
353493 + priv->trim_flag = 1;
353495 + priv->svb_predev5_flag = 1;
353497 + priv->svb_predev4_flag = 1;
353499 + priv->svb_predev3_flag = 1;
353501 + priv->svb_predev2_flag = 1;
353503 + priv->svb_flag = 1;
353514 + if (dev->of_node == NULL)
353521 + ret = of_property_read_u32(dev->of_node, "ana_cfg_0_eye_val",
353522 + &(priv->ana_cfg_0_eye_val));
353524 + priv->ana_cfg_0_flag = 0;
353526 + ret = of_property_read_u32(dev->of_node, "ana_cfg_0_offset",
353527 + &(priv->ana_cfg_0_offset));
353529 + priv->ana_cfg_0_flag = 0;
353531 + ret = of_property_read_u32(dev->of_node, "ana_cfg_2_eye_val",
353532 + &(priv->ana_cfg_2_eye_val));
353534 + priv->ana_cfg_2_flag = 0;
353536 + ret = of_property_read_u32(dev->of_node, "ana_cfg_2_offset",
353537 + &(priv->ana_cfg_2_offset));
353539 + priv->ana_cfg_2_flag = 0;
353541 + ret = of_property_read_u32(dev->of_node, "ana_cfg_4_eye_val",
353542 + &(priv->ana_cfg_4_eye_val));
353544 + priv->ana_cfg_4_flag = 0;
353546 + ret = of_property_read_u32(dev->of_node, "ana_cfg_4_offset",
353547 + &(priv->ana_cfg_4_offset));
353549 + priv->ana_cfg_4_flag = 0;
353557 + if (priv->ana_cfg_0_flag)
353558 + writel(priv->ana_cfg_0_eye_val, priv->phy_base + priv->ana_cfg_0_offset);
353560 + if (priv->ana_cfg_2_flag)
353561 + writel(priv->ana_cfg_2_eye_val, priv->phy_base + priv->ana_cfg_2_offset);
353563 + if (priv->ana_cfg_4_flag)
353564 + writel(priv->ana_cfg_4_eye_val, priv->phy_base + priv->ana_cfg_4_offset);
353575 + if (dev->of_node == NULL)
353579 + ret = of_property_read_u32(dev->of_node, "trim_otp_addr",
353580 + &(priv->trim_otp_addr));
353582 + priv->trim_flag = 0;
353584 + ret = of_property_read_u32(dev->of_node, "trim_otp_mask",
353585 + &(priv->trim_otp_mask));
353587 + priv->trim_flag = 0;
353589 + ret = of_property_read_u32(dev->of_node, "trim_otp_bit_offset",
353590 + &(priv->trim_otp_bit_offset));
353592 + priv->trim_flag = 0;
353594 + ret = of_property_read_u32(dev->of_node, "trim_otp_min", &(priv->trim_otp_min));
353596 + priv->trim_flag = 0;
353598 + ret = of_property_read_u32(dev->of_node, "trim_otp_max", &(priv->trim_otp_max));
353600 + priv->trim_flag = 0;
353612 + if (priv->trim_flag) {
353613 + phy_trim = ioremap_nocache(priv->trim_otp_addr, __1K__);
353618 + trim_otp_val = (reg & priv->trim_otp_mask);
353619 + if ((trim_otp_val >= priv->trim_otp_min) &&
353620 + (trim_otp_val <= priv->trim_otp_max)) {
353622 + reg = readl(priv->phy_base + HIXVP_PHY_TRIM_OFFSET);
353624 + reg |= HIXVP_PHY_TRIM_VAL(trim_otp_val >> priv->trim_otp_bit_offset);
353625 + writel(reg, priv->phy_base + HIXVP_PHY_TRIM_OFFSET);
353639 + if (dev->of_node == NULL)
353643 + ret = of_property_read_u32(dev->of_node, "svb_otp_addr", &
353644 + (priv->svb_otp_addr));
353646 + priv->svb_flag = 0;
353648 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev5_min",
353649 + &(priv->svb_otp_predev5_min));
353651 + priv->svb_predev5_flag = 0;
353653 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev5_max",
353654 + &(priv->svb_otp_predev5_max));
353656 + priv->svb_predev5_flag = 0;
353658 + ret = of_property_read_u32(dev->of_node, "svb_phy_predev5_val",
353659 + &(priv->svb_phy_predev5_val));
353661 + priv->svb_predev5_flag = 0;
353663 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev4_min",
353664 + &(priv->svb_otp_predev4_min));
353666 + priv->svb_predev4_flag = 0;
353668 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev4_max",
353669 + &(priv->svb_otp_predev4_max));
353671 + priv->svb_predev4_flag = 0;
353673 + ret = of_property_read_u32(dev->of_node, "svb_phy_predev4_val",
353674 + &(priv->svb_phy_predev4_val));
353676 + priv->svb_predev4_flag = 0;
353687 + if (dev->of_node == NULL)
353690 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev3_min",
353691 + &(priv->svb_otp_predev3_min));
353693 + priv->svb_predev3_flag = 0;
353695 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev3_max",
353696 + &(priv->svb_otp_predev3_max));
353698 + priv->svb_predev3_flag = 0;
353700 + ret = of_property_read_u32(dev->of_node, "svb_phy_predev3_val",
353701 + &(priv->svb_phy_predev3_val));
353703 + priv->svb_predev3_flag = 0;
353705 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev2_min",
353706 + &(priv->svb_otp_predev2_min));
353708 + priv->svb_predev2_flag = 0;
353710 + ret = of_property_read_u32(dev->of_node, "svb_otp_predev2_max",
353711 + &(priv->svb_otp_predev2_max));
353713 + priv->svb_predev2_flag = 0;
353715 + ret = of_property_read_u32(dev->of_node, "svb_phy_predev2_val",
353716 + &(priv->svb_phy_predev2_val));
353718 + priv->svb_predev2_flag = 0;
353730 + if (priv->svb_flag) {
353731 + phy_svb = ioremap_nocache(priv->svb_otp_addr, __1K__);
353736 + reg = readl(priv->phy_base + HIXVP_PHY_SVB_OFFSET);
353738 + if ((ret >= priv->svb_otp_predev5_min) &&
353739 + (ret < priv->svb_otp_predev5_max) && (priv->svb_predev5_flag))
353740 + reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev5_val);
353741 + else if ((ret >= priv->svb_otp_predev4_min) &&
353742 + (ret < priv->svb_otp_predev4_max) && (priv->svb_predev4_flag))
353743 + reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev4_val);
353744 + else if ((ret >= priv->svb_otp_predev3_min) &&
353745 + (ret <= priv->svb_otp_predev3_max) && (priv->svb_predev3_flag))
353746 + reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev3_val);
353747 + else if ((ret > priv->svb_otp_predev2_min) &&
353748 + (ret <= priv->svb_otp_predev2_max) && (priv->svb_predev2_flag))
353749 + reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev2_val);
353751 + reg |= HIXVP_PHY_SVB_VAL(priv->svb_phy_predev4_val);
353753 + writel(reg, priv->phy_base + HIXVP_PHY_SVB_OFFSET);
353766 + if (dev->of_node == NULL)
353770 + ret = of_property_read_u32(dev->of_node, "vbus_offset", &(priv->vbus_offset));
353772 + priv->vbus_flag = 0;
353774 + ret = of_property_read_u32(dev->of_node, "vbus_val", &(priv->vbus_val));
353776 + priv->vbus_flag = 0;
353779 + ret = of_property_read_u32(dev->of_node, "pwren_offset", &(priv->pwren_offset));
353781 + priv->pwren_flag = 0;
353783 + ret = of_property_read_u32(dev->of_node, "pwren_val", &(priv->pwren_val));
353785 + priv->pwren_flag = 0;
353787 + if (priv->vbus_flag)
353788 + writel(priv->vbus_val, priv->pin_base + priv->vbus_offset);
353792 + if (priv->pwren_flag)
353793 + writel(priv->pwren_val, priv->pin_base + priv->pwren_offset);
353804 + return -EINVAL;
353806 + if (dev->of_node == NULL)
353807 + return -EINVAL;
353810 + ret = of_property_read_u32(dev->of_node, "phy_pll_offset",
353811 + &(priv->phy_pll_offset));
353817 + ret = of_property_read_u32(dev->of_node, "phy_pll_mask", &(priv->phy_pll_mask));
353823 + ret = of_property_read_u32(dev->of_node, "phy_pll_val", &(priv->phy_pll_val));
353839 + return -EINVAL;
353841 + if (dev->of_node == NULL)
353842 + return -EINVAL;
353845 + ret = of_property_read_u32(dev->of_node, "crg_offset", &(priv->crg_offset));
353851 + ret = of_property_read_u32(dev->of_node, "crg_defal_mask",
353852 + &(priv->crg_defal_mask));
353858 + ret = of_property_read_u32(dev->of_node, "crg_defal_val",
353859 + &(priv->crg_defal_val));
353866 + reg = readl(priv->crg_base + priv->crg_offset);
353867 + reg &= ~priv->crg_defal_mask;
353868 + reg |= priv->crg_defal_val;
353869 + writel(reg, priv->crg_base + priv->crg_offset);
353880 + return -EINVAL;
353900 + struct device *dev = priv->dev;
353901 + struct device_node *np = dev->of_node;
353904 + priv->num_clocks = count;
353909 + priv->clks =
353910 + devm_kcalloc(dev, priv->num_clocks, sizeof(struct clk *), GFP_KERNEL);
353911 + if (priv->clks == NULL)
353912 + return -ENOMEM;
353914 + for (i = 0; i < priv->num_clocks; i++) {
353919 + while (--i >= 0)
353920 + clk_put(priv->clks[i]);
353922 + devm_kfree(dev, priv->clks);
353923 + priv->clks = NULL;
353927 + priv->clks[i] = clk;
353935 + struct device *dev = &pdev->dev;
353936 + struct device_node *np = pdev->dev.of_node;
353945 + priv->usb_phy_tpor_rst = devm_reset_control_get(dev, "phy_tpor_reset");
353946 + if (IS_ERR_OR_NULL(priv->usb_phy_tpor_rst)) {
353948 + return PTR_ERR(priv->usb_phy_tpor_rst);
353951 + priv->usb_phy_por_rst = devm_reset_control_get(dev, "phy_por_reset");
353952 + if (IS_ERR_OR_NULL(priv->usb_phy_por_rst)) {
353954 + return PTR_ERR(priv->usb_phy_por_rst);
353964 + return -EINVAL;
353966 + priv->phy_base = of_iomap(np, 0);
353967 + if (IS_ERR(priv->phy_base))
353968 + return -ENOMEM;
353970 + priv->crg_base = of_iomap(np, 1);
353971 + if (IS_ERR(priv->crg_base)) {
353972 + iounmap(priv->phy_base);
353973 + return -ENOMEM;
353976 + priv->pin_base = of_iomap(np, 2);
353977 + if (IS_ERR(priv->pin_base)) {
353978 + iounmap(priv->phy_base);
353979 + iounmap(priv->crg_base);
353980 + return -ENOMEM;
353992 + for (i = 0; i < priv->num_clocks; i++) {
353993 + ret = clk_prepare_enable(priv->clks[i]);
353995 + while (--i >= 0) {
353996 + clk_disable_unprepare(priv->clks[i]);
353997 + clk_put(priv->clks[i]);
354005 + ret = reset_control_deassert(priv->usb_phy_por_rst);
354010 + reg = readl(priv->phy_base + priv->phy_pll_offset);
354011 + reg &= ~priv->phy_pll_mask;
354012 + reg |= priv->phy_pll_val;
354013 + writel(reg, priv->phy_base + priv->phy_pll_offset);
354018 + ret = reset_control_deassert(priv->usb_phy_tpor_rst);
354037 + for (i = 0; i < priv->num_clocks; i++)
354038 + clk_disable_unprepare(priv->clks[i]);
354040 + ret = reset_control_assert(priv->usb_phy_por_rst);
354044 + ret = reset_control_assert(priv->usb_phy_tpor_rst);
354059 + struct device *dev = &pdev->dev;
354062 + struct device_node *np = pdev->dev.of_node;
354066 + phy = devm_phy_create(dev, dev->of_node, &hisi_usb_hixvp_phy_ops);
354072 + return -ENOMEM;
354079 + return -ENOMEM;
354083 + priv->dev = dev;
354110 + iounmap(priv->phy_base);
354111 + iounmap(priv->crg_base);
354112 + iounmap(priv->pin_base);
354122 + struct device *dev = &pdev->dev;
354126 + for (i = 0; i < priv->num_clocks; i++)
354127 + clk_put(priv->clks[i]);
354129 + iounmap(priv->phy_base);
354130 + iounmap(priv->crg_base);
354131 + iounmap(priv->pin_base);
354145 + return -1;
354155 + return -1;
354165 + { .compatible = "hisilicon,hixvp-usb2-phy" },
354173 + .name = "hisi-usb-hixvp-phy",
354180 +MODULE_ALIAS("platform:hisi-usb-hixvp-phy");
354182 diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
354184 --- a/drivers/power/reset/Kconfig
354186 @@ -94,7 +94,7 @@ config POWER_RESET_GPIO_RESTART
354189 bool "Hisilicon power-off driver"
354190 - depends on ARCH_HISI
354195 diff --git a/drivers/ras/Kconfig b/drivers/ras/Kconfig
354197 --- a/drivers/ras/Kconfig
354199 @@ -28,8 +28,8 @@ menuconfig RAS
354203 -if RAS
354206 -source arch/x86/ras/Kconfig
354209 -endif
354211 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
354213 --- a/drivers/rtc/Kconfig
354215 @@ -868,6 +868,14 @@ comment "Platform RTC drivers"
354225 + will be called rtc-hibvt.
354228 tristate "PC-style 'CMOS'"
354230 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
354232 --- a/drivers/rtc/Makefile
354234 @@ -23,6 +23,7 @@ rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o
354238 +obj-$(CONFIG_RTC_DRV_HIBVT) += rtc-hibvt.o
354239 obj-$(CONFIG_RTC_DRV_88PM80X) += rtc-88pm80x.o
354240 obj-$(CONFIG_RTC_DRV_88PM860X) += rtc-88pm860x.o
354241 obj-$(CONFIG_RTC_DRV_AB3100) += rtc-ab3100.o
354242 diff --git a/drivers/rtc/rtc-hibvt.c b/drivers/rtc/rtc-hibvt.c
354245 --- /dev/null
354246 +++ b/drivers/rtc/rtc-hibvt.c
354247 @@ -0,0 +1,663 @@
354249 + * rtc-hibvt.c
354461 + while (r_data.bits.spi_busy && (--cnt));
354464 + return -EIO;
354485 + while (r_data.bits.spi_busy && (--cnt));
354488 + return -EIO;
354540 + hibvt_rtc_read(rtc->regs, RTC_INT_RAW, &raw_value);
354544 + hibvt_rtc_write(rtc->regs, RTC_INT_CLR, 1);
354546 + hibvt_rtc_read(rtc->regs, RTC_LORD, &raw_value);
354548 + hibvt_rtc_write(rtc->regs, RTC_LORD,
354551 + hibvt_rtc_read(rtc->regs, RTC_LORD, &raw_value);
354553 + hibvt_rtc_write(rtc->regs, RTC_LORD, (REG_LOCK_STAT) | raw_value);
354556 + hibvt_rtc_read(rtc->regs, RTC_LORD, &raw_value);
354558 + } while ((raw_value & REG_LOCK_STAT) && (--cnt));
354561 + return -EBUSY;
354563 + hibvt_rtc_read(rtc->regs, RTC_S_COUNT, &time_str.second);
354564 + hibvt_rtc_read(rtc->regs, RTC_M_COUNT, &time_str.minute);
354565 + hibvt_rtc_read(rtc->regs, RTC_H_COUNT, &time_str.hour);
354566 + hibvt_rtc_read(rtc->regs, RTC_D_COUNT_L, &time_str.dayl);
354567 + hibvt_rtc_read(rtc->regs, RTC_D_COUNT_H, &time_str.dayh);
354589 + hibvt_rtc_write(rtc->regs, RTC_LR_10MS, 0);
354590 + hibvt_rtc_write(rtc->regs, RTC_LR_S, time->tm_sec);
354591 + hibvt_rtc_write(rtc->regs, RTC_LR_M, time->tm_min);
354592 + hibvt_rtc_write(rtc->regs, RTC_LR_H, time->tm_hour);
354593 + hibvt_rtc_write(rtc->regs, RTC_LR_D_L, (days & 0xFF));
354594 + hibvt_rtc_write(rtc->regs, RTC_LR_D_H, (days >> 8)); /* Move to a Low 8 bit. */
354596 + hibvt_rtc_write(rtc->regs, RTC_LORD,
354600 + hibvt_rtc_read(rtc->regs, RTC_LORD, &raw_value);
354602 + } while ((raw_value & REG_LOAD_STAT) && (--cnt));
354605 + return -EBUSY;
354621 + hibvt_rtc_read(rtc->regs, RTC_MR_S, &time_str.second);
354622 + hibvt_rtc_read(rtc->regs, RTC_MR_M, &time_str.minute);
354623 + hibvt_rtc_read(rtc->regs, RTC_MR_H, &time_str.hour);
354624 + hibvt_rtc_read(rtc->regs, RTC_MR_D_L, &time_str.dayl);
354625 + hibvt_rtc_read(rtc->regs, RTC_MR_D_H, &time_str.dayh);
354630 + rtc_time_to_tm(seconds, &alrm->time);
354632 + hibvt_rtc_read(rtc->regs, RTC_IMSC, &int_state);
354634 + alrm->enabled = !!(int_state & AIE_INT_MASK);
354635 + alrm->pending = alrm->enabled;
354647 + rtc_tm_to_time(&alrm->time, &seconds);
354651 + hibvt_rtc_write(rtc->regs, RTC_MR_10MS, 0);
354652 + hibvt_rtc_write(rtc->regs, RTC_MR_S, alrm->time.tm_sec);
354653 + hibvt_rtc_write(rtc->regs, RTC_MR_M, alrm->time.tm_min);
354654 + hibvt_rtc_write(rtc->regs, RTC_MR_H, alrm->time.tm_hour);
354655 + hibvt_rtc_write(rtc->regs, RTC_MR_D_L, (days & 0xFF));
354656 + hibvt_rtc_write(rtc->regs, RTC_MR_D_H, (days >> 8)); /* Move to a Low 8 bit. */
354658 + hibvt_rtc_read(rtc->regs, RTC_IMSC, &val);
354659 + if (alrm->enabled)
354660 + hibvt_rtc_write(rtc->regs, RTC_IMSC, val | AIE_INT_MASK);
354662 + hibvt_rtc_write(rtc->regs, RTC_IMSC, val & ~AIE_INT_MASK);
354673 + hibvt_rtc_read(rtc->regs, RTC_IMSC, &val);
354675 + hibvt_rtc_write(rtc->regs, RTC_IMSC, val | AIE_INT_MASK);
354677 + hibvt_rtc_write(rtc->regs, RTC_IMSC, val & ~AIE_INT_MASK);
354691 + hibvt_rtc_read(rtc->regs, RTC_INT, &val);
354692 + hibvt_rtc_write(rtc->regs, RTC_INT_CLR, AIE_INT_MASK);
354695 + rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
354715 + return -EFAULT;
354720 + return -EINVAL;
354722 + /* freq convert: (freq-3270000) * 3052 / 10000 */
354723 + pll_info.pll_value = (pll_info.pll_value - 3270000) *
354731 + hibvt_rtc_write(rtc->regs, RTC_FREQ_H, freq_h);
354732 + hibvt_rtc_write(rtc->regs, RTC_FREQ_L, freq_l);
354741 + hibvt_rtc_read(rtc->regs, RTC_FREQ_H, &freq_h);
354742 + hibvt_rtc_read(rtc->regs, RTC_FREQ_L, &freq_l);
354746 + return -1;
354759 + return -EFAULT;
354764 + return -ENOIOCTLCMD;
354779 + void *spi_reg = rtc->regs;
354786 + * clk div value = (apb_clk/spi_clk)/2-1,
354798 + return -1;
354836 + hibvt_rtc_write(rtc->regs, RTC_INT_CLR, 1);
354847 + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
354849 + return -ENOMEM;
354852 + rtc->regs = devm_ioremap_resource(&pdev->dev, mem);
354853 + if (IS_ERR((const void *)rtc->regs)) {
354854 + dev_err(&pdev->dev, "could not map I/O memory\n");
354855 + return PTR_ERR((const void *)rtc->regs);
354858 + rtc->rtc_irq = platform_get_irq(pdev, 0);
354859 + ret = devm_request_irq(&pdev->dev, rtc->rtc_irq,
354860 + hibvt_rtc_alm_interrupt, 0, pdev->name, rtc);
354862 + dev_err(&pdev->dev, "could not request irq %d\n", rtc->rtc_irq);
354867 + rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
354869 + if (IS_ERR(rtc->rtc_dev)) {
354870 + dev_err(&pdev->dev, "could not register rtc device\n");
354871 + return PTR_ERR(rtc->rtc_dev);
354875 + dev_err(&pdev->dev, "hibvt_rtc_init failed.\n");
354876 + return -EIO;
354879 + dev_info(&pdev->dev, "RTC driver for hibvt enabled\n");
354890 + { .compatible = "hisilicon,hi35xx-rtc" },
354911 diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
354913 --- a/drivers/scsi/ufs/Kconfig
354915 @@ -109,3 +109,12 @@ config SCSI_UFS_HISI
354923 + ---help---
354928 diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
354930 --- a/drivers/scsi/ufs/Makefile
354932 @@ -8,3 +8,4 @@ ufshcd-core-objs := ufshcd.o ufs-sysfs.o
354933 obj-$(CONFIG_SCSI_UFSHCD_PCI) += ufshcd-pci.o
354934 obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += ufshcd-pltfrm.o
354935 obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
354936 +obj-$(CONFIG_SCSI_UFS_HI3559AV100) += hi3559av100.o
354937 diff --git a/drivers/scsi/ufs/hi3559av100.c b/drivers/scsi/ufs/hi3559av100.c
354940 --- /dev/null
354942 @@ -0,0 +1,659 @@
354944 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2020. All rights reserved.
354969 +#include "ufshcd-pltfrm.h"
355026 + struct ufs_pa_layer_attr *pmp = &hba->pwr_info;
355029 + if (pmp->pwr_rx == FAST_MODE || pmp->pwr_rx == FASTAUTO_MODE) {
355030 + mode = 8 - pmp->gear_rx * 2 - pmp->hs_rate; /* mode[8 - gear * 2 - rate] */
355058 + } while (retry--);
355228 + /* set the HS-prepare length and sync length to MAX value,
355293 + /* disable auto H8 Power-Gating */
355309 + dev_err(hba->dev, "Link is not up\n");
355310 + return -1;
355313 + dev_err(hba->dev, "Connection setup failed\n");
355314 + return -1;
355323 + struct ufs_pa_layer_attr *pwr_mode = &hba->pwr_info;
355328 + ufshcd_dme_set_attr(hba, 0x15680000, 0x0, pwr_mode->gear_tx, DME_LOCAL);
355330 + ufshcd_dme_set_attr(hba, 0x15830000, 0x0, pwr_mode->gear_rx, DME_LOCAL);
355332 + if (pwr_mode->pwr_rx == FAST_MODE || pwr_mode->pwr_rx == FASTAUTO_MODE) {
355334 + ufshcd_dme_set_attr(hba, 0x156a0000, 0x0, pwr_mode->hs_rate, DME_LOCAL);
355348 + ufshcd_dme_set_attr(hba, 0x15600000, 0x0, pwr_mode->lane_tx, DME_LOCAL);
355350 + ufshcd_dme_set_attr(hba, 0x15800000, 0x0, pwr_mode->lane_rx, DME_LOCAL);
355384 + (pwr_mode->pwr_rx << 4) | pwr_mode->pwr_tx, DME_LOCAL); /* rx shift 4 */
355402 + struct ufs_pa_layer_attr *pmp = &hba->pwr_info;
355404 + if (pmp->pwr_rx == FAST_MODE || pmp->pwr_rx == FASTAUTO_MODE) {
355405 + mode = 8 - pmp->gear_rx * 2 - pmp->hs_rate; /* mode[8 - gear * 2 - rate] */
355408 + if (pmp->gear_rx == UFS_PWM_G1) {
355411 + } else if (pmp->gear_rx == UFS_PWM_G2) {
355414 + } else if (pmp->gear_rx == UFS_PWM_G3) {
355417 + } else if (pmp->gear_rx == UFS_PWM_G4) {
355454 + while (--retry) {
355472 + return -1;
355489 + struct ufs_pa_layer_attr *dev_req_params = &hba->pwr_info;
355491 + dev_req_params->pwr_rx = hba->hc_pwm;
355492 + dev_req_params->pwr_tx = hba->hc_pwm;
355494 + dev_req_params->gear_rx = hba->hc_gear;
355495 + dev_req_params->gear_tx = hba->hc_gear;
355497 + dev_req_params->hs_rate = hba->hc_rate;
355499 + dev_req_params->lane_rx = hba->lanes_per_direction;
355500 + dev_req_params->lane_tx = hba->lanes_per_direction;
355510 + *dev_max_params = hba->pwr_info;
355511 + *dev_req_params = hba->pwr_info;
355515 + return -1;
355544 + struct device *dev = &pdev->dev;
355546 + of_id = of_match_node(hiufs_pltfm_pm_match, dev->of_node);
355547 + vops = (struct ufs_hba_variant_ops *)of_id->data;
355550 + crg_base = devm_ioremap(dev, mem_res->start, resource_size(mem_res));
355555 + misc_base = devm_ioremap(dev, mem_res->start, resource_size(mem_res));
355574 + pm_runtime_get_sync(&(pdev)->dev);
355602 diff --git a/drivers/scsi/ufs/hi3559av100.h b/drivers/scsi/ufs/hi3559av100.h
355605 --- /dev/null
355607 @@ -0,0 +1,111 @@
355609 + * Copyright (c) Hisilicon Technologies Co., Ltd. 2019-2020. All rights reserved.
355719 diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
355721 --- a/drivers/scsi/ufs/ufshcd-pltfrm.c
355722 +++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
355723 @@ -41,6 +41,9 @@
355724 #include "ufshcd-pltfrm.h"
355733 @@ -204,6 +207,9 @@ static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
355734 struct device *dev = hba->dev;
355735 struct ufs_vreg_info *info = &hba->vreg_info;
355737 + if (hba->info_skip)
355740 err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);
355743 @@ -221,6 +227,18 @@ static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
355750 + struct device *dev = hba->dev;
355751 + struct device_node *np = dev->of_node;
355752 + if (of_get_property(np, "cd-gpio", NULL))
355753 + hba->cd_gpio = of_get_named_gpio(np, "cd-gpio", 0);
355755 + hba->cd_gpio = -1;
355761 * ufshcd_pltfrm_suspend - suspend power management function
355762 @@ -274,6 +292,34 @@ void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
355768 + struct device *dev = hba->dev;
355771 + ret = of_property_read_u32(dev->of_node, "skip-info", &hba->info_skip);
355773 + hba->info_skip = 0;
355778 + struct device *dev = hba->dev;
355781 + ret = of_property_read_u32(dev->of_node, "power-mode", &hba->hc_pwm);
355783 + hba->hc_pwm = UFSHCD_DEFAULT_PWM;
355785 + ret = of_property_read_u32(dev->of_node, "gear", &hba->hc_gear);
355787 + hba->hc_gear = UFSHCD_DEFAULT_GEAR;
355789 + ret = of_property_read_u32(dev->of_node, "rate", &hba->hc_rate);
355791 + hba->hc_rate = UFSHCD_DEFAULT_RATE;
355796 struct device *dev = hba->dev;
355797 @@ -326,6 +372,7 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,
355800 hba->vops = vops;
355805 @@ -340,6 +387,8 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,
355814 diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
355816 --- a/drivers/scsi/ufs/ufshcd.c
355818 @@ -5636,6 +5636,40 @@ static irqreturn_t ufshcd_intr(int irq, void *__hba)
355827 + if (gpio_is_valid(hba->cd_gpio))
355828 + ret = gpio_get_value(hba->cd_gpio) ? D_NO_DETECT : D_DETECT;
355838 + spin_lock_irqsave(hba->host->host_lock, flags);
355839 + hba->card_status_changed = true;
355840 + hba->ufshcd_state = UFSHCD_STATE_OFFLINE;
355841 + spin_unlock_irqrestore(hba->host->host_lock, flags);
355846 + * into suspend mode and interface re-establishment be permitted
355849 + if (!(work_pending(&hba->cd_work))) {
355850 + queue_work(hba->cd_wq, &hba->cd_work);
355859 @@ -6007,6 +6041,10 @@ static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
355870 @@ -6021,6 +6059,8 @@ static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
355879 @@ -6329,6 +6369,7 @@ static int ufs_get_device_desc(struct ufs_hba *hba,
355880 dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
355883 + hba->manufacturer_id = dev_desc->wmanufacturerid;
355886 /* Zero-pad entire buffer for string termination. */
355887 @@ -6787,6 +6828,138 @@ static const struct attribute_group *ufshcd_driver_groups[] = {
355904 + * 1-1) B = I : (I) -> R
355908 + * 1-2) B = R : (R) -> I
355912 + * 2-1) B = I : (I) -> R
355915 + * 2-2) B = R : (R)
355922 + if (hba->latest_card_status == H_INSERT) {
355944 + current_status = hba->latest_card_status;
355946 + pm_runtime_get_sync(hba->dev);
355953 + spin_lock_irqsave(hba->host->host_lock, flags);
355954 + if (unlikely(!hba->card_status_changed)) {
355955 + spin_unlock_irqrestore(hba->host->host_lock, flags);
355958 + hba->card_status_changed = false;
355959 + spin_unlock_irqrestore(hba->host->host_lock, flags);
355972 + dev_err(hba->dev, "card inserted\n");
355973 + hba->latest_card_status = current_status;
355974 + hba->error_count = 0;
355982 + spin_lock_irqsave(hba->host->host_lock, flags);
355983 + outstanding_reqs = hba->outstanding_reqs;
355984 + spin_unlock_irqrestore(hba->host->host_lock, flags);
355986 + for_each_set_bit(tag, &outstanding_reqs, hba->nutrs)
355994 + spin_lock_irqsave(hba->host->host_lock, flags);
355996 + hba->ufshcd_state = UFSHCD_STATE_OFFLINE;
355997 + spin_unlock_irqrestore(hba->host->host_lock, flags);
356002 + if (!list_empty(&hba->host->__targets)) {
356003 + starget = list_first_entry(&hba->host->__targets,
356005 + scsi_remove_device(hba->sdev_rpmb);
356006 + scsi_remove_device(hba->sdev_boot);
356007 + scsi_remove_device(hba->sdev_ufs_device);
356008 + scsi_remove_target(&starget->dev);
356011 + dev_err(hba->dev, "card removed\n");
356012 + hba->latest_card_status = current_status;
356015 + dev_err(hba->dev, "returned\n");
356019 + pm_runtime_put_sync(hba->dev);
356026 @@ -7532,6 +7705,10 @@ static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
356031 + if (hba->ufshcd_state == UFSHCD_STATE_OFFLINE)
356034 hba->pm_op_in_progress = 1;
356037 @@ -7958,6 +8135,9 @@ void ufshcd_remove(struct ufs_hba *hba)
356040 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
356042 + destroy_workqueue(hba->cd_wq);
356047 @@ -8113,6 +8293,14 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int i…
356048 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
356049 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
356052 + INIT_WORK(&hba->cd_work, ufshcd_card_detect_handler);
356053 + hba->cd_wq = alloc_workqueue("ufshcd_cd_wq", WQ_FREEZABLE, 0);
356054 + if (!hba->cd_wq) {
356055 + err = -ENOMEM;
356060 mutex_init(&hba->uic_cmd_mutex);
356062 @@ -8195,7 +8383,37 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int i…
356070 + if (gpio_is_valid(hba->cd_gpio) &&
356071 + !gpio_request(hba->cd_gpio, "UFSCARD")) {
356072 + cd_irq = gpio_to_irq(hba->cd_gpio);
356073 + dev_err(hba->dev, "card detection interrupt number = %d\n", cd_irq);
356075 + devm_request_irq(hba->dev, cd_irq, ufshcd_intr_card_detect,
356080 + dev_warn(hba->dev, "success to request irq for card detect.\n");
356082 + hba->is_cd_irq_enabled = true;
356083 + hba->cd_irq = cd_irq;
356085 + dev_warn(hba->dev, "cannot request irq for card detect.\n");
356089 + hba->latest_card_status = true;
356092 + hba->latest_card_status = false;
356094 + hba->ufshcd_state = UFSHCD_STATE_OFFLINE;
356097 ufs_sysfs_add_nodes(hba->dev);
356100 diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
356102 --- a/drivers/scsi/ufs/ufshcd.h
356104 @@ -71,6 +71,7 @@
356112 @@ -326,6 +327,7 @@ struct ufs_hba_variant_ops {
356120 @@ -447,6 +449,20 @@ struct ufs_stats {
356126 + D_IGNORED = -1,
356133 + H_BREAK = -1,
356139 * struct ufs_hba - per adapter private structure
356141 @@ -640,6 +656,18 @@ struct ufs_hba {
356160 @@ -648,6 +676,7 @@ struct ufs_hba {
356168 @@ -685,6 +714,10 @@ struct ufs_hba {
356177 * This capability allows the device auto-bkops to be always enabled
356179 @@ -1048,4 +1081,9 @@ static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
356185 + if (hba->vops && hba->vops->clk_hareware_init_notify)
356186 + hba->vops->clk_hareware_init_notify();
356189 diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c
356191 --- a/drivers/spi/spi-gpio.c
356192 +++ b/drivers/spi/spi-gpio.c
356193 @@ -417,8 +417,10 @@ static int spi_gpio_probe(struct platform_device *pdev)
356195 status = spi_gpio_request(&pdev->dev, spi_gpio,
356196 pdata->num_chipselect, &master_flags);
356197 - if (status)
356203 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
356204 master->mode_bits = SPI_3WIRE | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
356205 diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
356207 --- a/drivers/spi/spi-pl022.c
356208 +++ b/drivers/spi/spi-pl022.c
356209 @@ -43,6 +43,7 @@
356217 @@ -136,6 +137,18 @@
356234 * SSP Status Register - SSP_SR
356236 @@ -296,6 +309,10 @@
356247 @@ -337,6 +354,15 @@ struct vendor_data {
356261 * struct pl022 - This is the private SSP driver data structure
356263 @@ -403,6 +429,9 @@ struct pl022 {
356273 @@ -459,13 +488,41 @@ static void null_cs_control(u32 command)
356278 + struct amba_device *adev = pl022->adev;
356279 + struct amba_driver *adrv = container_of(adev->dev.driver,
356282 + if (pl022->vendor->extended_cr && (adev->periphid ==
356283 + adrv->id_table[PL022_IDS_INDEX_HISI].id)) {
356284 + if (pl022->cs_data) {
356285 + tmp = readl(pl022->cs_data->virt_addr);
356286 + tmp &= ~(pl022->cs_data->cs_mask_bit);
356287 + tmp |= ((u32)pl022->cur_cs) << pl022->cs_data->cs_sb;
356288 + writel(tmp, pl022->cs_data->virt_addr);
356291 - tmp = readw(SSP_CSR(pl022->virtbase));
356292 - if (command == SSP_CHIP_SELECT)
356293 - tmp &= ~BIT(pl022->cur_cs);
356294 - else
356295 - tmp |= BIT(pl022->cur_cs);
356296 - writew(tmp, SSP_CSR(pl022->virtbase));
356299 + writew((readw(SSP_CR1(pl022->virtbase)) |
356301 + SSP_CR1(pl022->virtbase));
356304 + writew((readw(SSP_CR1(pl022->virtbase)) &
356306 + SSP_CR1(pl022->virtbase));
356309 + tmp = readw(SSP_CSR(pl022->virtbase));
356311 + tmp &= ~BIT(pl022->cur_cs);
356313 + tmp |= BIT(pl022->cur_cs);
356314 + writew(tmp, SSP_CSR(pl022->virtbase));
356321 @@ -566,8 +623,16 @@ static int flush(struct pl022 *pl022)
356324 struct chip_data *chip = pl022->cur_chip;
356326 + struct amba_device *adev = pl022->adev;
356327 + struct amba_driver *adrv = container_of(adev->dev.driver,
356330 + if (pl022->vendor->extended_cr && (adev->periphid !=
356331 + adrv->id_table[PL022_IDS_INDEX_HISI].id))
356333 if (pl022->vendor->extended_cr)
356335 writel(chip->cr0, SSP_CR0(pl022->virtbase));
356337 writew(chip->cr0, SSP_CR0(pl022->virtbase));
356338 @@ -640,6 +705,15 @@ static void restore_state(struct pl022 *pl022)
356354 @@ -659,8 +733,22 @@ static void load_ssp_default_config(struct pl022 *pl022)
356355 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
356356 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
356357 } else if (pl022->vendor->extended_cr) {
356359 + struct amba_device *adev = pl022->adev;
356360 + struct amba_driver *adrv = container_of(adev->dev.driver,
356363 + if (adev->periphid == adrv->id_table[PL022_IDS_INDEX_HISI].id) {
356364 + writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
356366 + SSP_CR1(pl022->virtbase));
356369 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
356370 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
356375 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
356376 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
356377 @@ -1144,7 +1232,7 @@ static int pl022_dma_probe(struct pl022 *pl022)
356378 if (!pl022->dummypage)
356381 - dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
356382 + dev_dbg(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
356383 dma_chan_name(pl022->dma_rx_channel),
356384 dma_chan_name(pl022->dma_tx_channel));
356386 @@ -1835,6 +1923,13 @@ static int pl022_setup(struct spi_device *spi)
356387 unsigned int bits = spi->bits_per_word;
356389 struct device_node *np = spi->dev.of_node;
356391 + struct amba_device *adev = pl022->adev;
356392 + struct amba_driver *adrv = container_of(adev->dev.driver,
356394 + writel(0, SSP_TX_FIFO_CR(pl022->virtbase));
356395 + writel(0, SSP_RX_FIFO_CR(pl022->virtbase));
356398 if (!spi->max_speed_hz)
356399 return -EINVAL;
356400 @@ -1977,7 +2072,12 @@ static int pl022_setup(struct spi_device *spi)
356401 chip->cpsr = clk_freq.cpsdvsr;
356405 + if (pl022->vendor->extended_cr && (adev->periphid !=
356406 + adrv->id_table[PL022_IDS_INDEX_HISI].id)) {
356408 if (pl022->vendor->extended_cr) {
356412 if (pl022->vendor->pl023) {
356413 @@ -2011,6 +2111,22 @@ static int pl022_setup(struct spi_device *spi)
356415 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
356418 + } else if (pl022->vendor->extended_cr && (adev->periphid ==
356419 + adrv->id_table[PL022_IDS_INDEX_HISI].id)) {
356420 + SSP_WRITE_BITS(chip->cr0, bits - 1,
356422 + SSP_WRITE_BITS(chip->cr0, chip_info->iface,
356425 + if (spi->mode & SPI_LSB_FIRST)
356430 + SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_BIGEND_HISI, 4);
356431 + SSP_WRITE_BITS(chip->cr1, 0x1, SSP_CR1_MASK_ALTASENS_HISI, 6);
356434 SSP_WRITE_BITS(chip->cr0, bits - 1,
356436 @@ -2099,6 +2215,8 @@ pl022_platform_data_dt_get(struct device *dev)
356439 struct device *dev = &adev->dev;
356440 + struct amba_driver *adrv = container_of(adev->dev.driver,
356443 dev_get_platdata(&adev->dev);
356445 @@ -2106,7 +2224,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
356446 struct device_node *np = adev->dev.of_node;
356449 - dev_info(&adev->dev,
356450 + dev_dbg(&adev->dev,
356451 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
356454 @@ -2162,6 +2280,43 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
356455 } else if (pl022->vendor->internal_cs_ctrl) {
356457 pl022->chipselects[i] = i;
356460 + if ((adev->periphid == adrv->id_table[PL022_IDS_INDEX_HISI].id)
356461 + && pl022->vendor->extended_cr
356463 + pl022->cs_data = devm_kzalloc(dev,
356466 + if (!pl022->cs_data) {
356467 + status = -ENOMEM;
356472 + &pl022->cs_data->res)) {
356473 + status = -EPROBE_DEFER;
356478 + &pl022->cs_data->cs_sb)) {
356479 + status = -EPROBE_DEFER;
356484 + &pl022->cs_data->cs_mask_bit)) {
356485 + status = -EPROBE_DEFER;
356489 + pl022->cs_data->virt_addr = devm_ioremap(dev,
356490 + pl022->cs_data->res.start,
356491 + resource_size(&pl022->cs_data->res));
356493 + pl022->cs_data = NULL;
356497 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
356498 @@ -2207,7 +2362,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
356499 status = -ENOMEM;
356502 - dev_info(&adev->dev, "mapped registers from %pa to %p\n",
356503 + dev_dbg(&adev->dev, "mapped registers from %pa to %p\n",
356504 &adev->res.start, pl022->virtbase);
356506 pl022->clk = devm_clk_get(&adev->dev, NULL);
356507 @@ -2267,7 +2422,7 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
356510 if (platform_info->autosuspend_delay > 0) {
356511 - dev_info(&adev->dev,
356512 + dev_dbg(&adev->dev,
356514 platform_info->autosuspend_delay);
356516 @@ -2288,6 +2443,10 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
356521 + if (pl022->cs_data)
356522 + devm_iounmap(&adev->dev, pl022->cs_data->virt_addr);
356527 @@ -2314,6 +2473,10 @@ pl022_remove(struct amba_device *adev)
356529 clk_disable_unprepare(pl022->clk);
356532 + if (pl022->cs_data)
356533 + devm_iounmap(&adev->dev, pl022->cs_data->virt_addr);
356535 tasklet_disable(&pl022->pump_transfers);
356538 @@ -2429,6 +2592,17 @@ static struct vendor_data vendor_lsi = {
356556 @@ -2469,6 +2643,17 @@ static const struct amba_id pl022_ids[] = {
356574 diff --git a/drivers/tty/vt/selection.c b/drivers/tty/vt/selection.c
356576 --- a/drivers/tty/vt/selection.c
356578 @@ -207,6 +207,7 @@ static int __set_selection(const struct tiocl_selection __user *sel, struct tty_
356586 @@ -252,9 +253,10 @@ static int __set_selection(const struct tiocl_selection __user *sel, struct tt…
356590 - return 0;
356593 - return -EINVAL;
356594 + ret = -EINVAL;
356599 @@ -276,7 +278,7 @@ static int __set_selection(const struct tiocl_selection __user *sel, struct tty_
356603 - return 0;
356608 @@ -304,7 +306,8 @@ static int __set_selection(const struct tiocl_selection __user *sel, struct tty_
356612 - return -ENOMEM;
356613 + ret = -ENOMEM;
356618 @@ -329,7 +332,8 @@ static int __set_selection(const struct tiocl_selection __user *sel, struct tty_
356621 sel_buffer_lth = bp - sel_buffer;
356622 -
356628 diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c
356630 --- a/drivers/tty/vt/vc_screen.c
356632 @@ -234,6 +234,9 @@ vcs_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
356637 + return -EOPNOTSUPP;
356641 return -ENOMEM;
356642 diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
356644 --- a/drivers/usb/core/hub.c
356646 @@ -1382,6 +1382,10 @@ static int hub_configure(struct usb_hub *hub,
356647 ret = -ENODEV;
356649 } else if (hub->descriptor->bNbrPorts == 0) {
356650 + if (!hdev->parent) {
356652 + return -ENODEV;
356655 ret = -ENODEV;
356657 diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
356659 --- a/drivers/usb/dwc3/Makefile
356661 @@ -2,10 +2,9 @@
356663 CFLAGS_trace.o := -I$(src)
356665 -obj-$(CONFIG_USB_DWC3) += dwc3.o
356666 -
356667 -dwc3-y := core.o
356668 +obj-$(CONFIG_USB_DWC3) += dwc3.o dwc3-hisi.o
356670 +dwc3-y := core.o proc.o
356672 dwc3-y += trace.o
356674 diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
356676 --- a/drivers/usb/dwc3/core.c
356678 @@ -37,9 +37,25 @@
356682 +#include "dwc3-hisi.h"
356695 + reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1);
356698 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg);
356702 * dwc3_get_dr_mode - Validates and sets dr_mode
356704 @@ -1230,7 +1246,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
356708 - dwc->maximum_speed = usb_get_maximum_speed(dev);
356709 + dwc->maximum_speed = usb_get_max_speed(dev);
356711 dwc->dr_mode = usb_get_dr_mode(dev);
356712 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
356714 @@ -1260,6 +1277,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
356715 device_property_read_u8(dev, "snps,tx-max-burst-prd",
356718 + dwc->usb2_lpm_disable = device_property_read_bool(dev,
356719 + "snps,usb2-lpm-disable");
356721 dwc->disable_scramble_quirk = device_property_read_bool(dev,
356723 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
356724 @@ -1293,6 +1313,16 @@ static void dwc3_get_properties(struct dwc3 *dwc)
356725 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
356726 "snps,parkmode-disable-ss-quirk");
356728 + dwc->dis_initiate_u1 = device_property_read_bool(dev,
356730 + dwc->dis_initiate_u2 = device_property_read_bool(dev,
356733 + dwc->eps_new_init = device_property_read_bool(dev,
356736 + &dwc->eps_directions);
356738 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
356741 @@ -1460,6 +1490,10 @@ static int dwc3_probe(struct platform_device *pdev)
356746 + dwc->dwceps_map_to_usbeps,
356747 + DWC3_NUM_EPS(&dwc->hwparams));
356749 spin_lock_init(&dwc->lock);
356752 @@ -1494,6 +1528,8 @@ static int dwc3_probe(struct platform_device *pdev)
356761 @@ -1564,6 +1600,10 @@ static int dwc3_remove(struct platform_device *pdev)
356763 clk_bulk_put(dwc->num_clks, dwc->clks);
356772 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
356774 --- a/drivers/usb/dwc3/core.h
356776 @@ -30,6 +30,8 @@
356785 @@ -457,6 +459,9 @@
356795 @@ -636,7 +641,7 @@ struct dwc3_event_buffer {
356799 -#define DWC3_TRB_NUM 256
356803 * struct dwc3_ep - device side endpoint representation
356804 @@ -696,8 +701,8 @@ struct dwc3_ep {
356808 - u8 trb_enqueue;
356809 - u8 trb_dequeue;
356815 @@ -1033,6 +1038,8 @@ struct dwc3 {
356824 @@ -1124,6 +1131,12 @@ struct dwc3 {
356837 @@ -1138,6 +1151,13 @@ struct dwc3 {
356851 @@ -1154,6 +1174,7 @@ struct dwc3 {
356859 @@ -1171,6 +1192,10 @@ struct dwc3 {
356870 @@ -1421,6 +1446,9 @@ static inline void dwc3_otg_host_init(struct dwc3 *dwc)
356880 diff --git a/drivers/usb/dwc3/dwc3-hisi.c b/drivers/usb/dwc3/dwc3-hisi.c
356883 --- /dev/null
356884 +++ b/drivers/usb/dwc3/dwc3-hisi.c
356885 @@ -0,0 +1,446 @@
356887 + * dwc3-hisi.c
356891 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
356908 +#include <linux/clk-provider.h>
356911 +#include <linux/dma-mapping.h>
356925 +#include "dwc3-hisi.h"
356979 + return -EINVAL;
356981 + usb_priv->speed_id = -1;
356983 + reg = readl(usb_priv->sys_ctrl + REG_SYS_STAT);
356991 + if (of_property_read_u32(np, "port_speed", &usb_priv->speed_id))
356992 + usb_priv->speed_id = -1;
356994 + if (usb_priv->speed_id == 0)
356996 + else if (usb_priv->speed_id == 1)
357020 + return -EINVAL;
357022 + reg = readl(usb_priv->sys_ctrl + REG_SYS_STAT);
357037 + struct device_node *np = dev->of_node;
357040 + return -EINVAL;
357044 + return -ENOMEM;
357046 + usb_priv->peri_crg = of_iomap(np, DEV_NODE_FLAG1);
357047 + if (IS_ERR(usb_priv->peri_crg)) {
357050 + return -ENOMEM;
357053 + usb_priv->sys_ctrl = of_iomap(np, DEV_NODE_FLAG2);
357054 + if (IS_ERR(usb_priv->sys_ctrl)) {
357055 + iounmap(usb_priv->peri_crg);
357059 + return -ENOMEM;
357070 + iounmap(usb_priv->sys_ctrl);
357071 + iounmap(usb_priv->peri_crg);
357090 + return -EINVAL;
357093 + ret = of_property_read_u32(np, "crg_offset", &hisi->crg_offset);
357097 + ret = of_property_read_u32(np, "crg_ctrl_def_mask", &hisi->crg_ctrl_def_mask);
357101 + ret = of_property_read_u32(np, "crg_ctrl_def_val", &hisi->crg_ctrl_def_val);
357106 + reg = readl(hisi->crg_base + hisi->crg_offset);
357107 + reg &= ~hisi->crg_ctrl_def_mask;
357108 + reg |= hisi->crg_ctrl_def_val;
357109 + writel(reg, hisi->crg_base + hisi->crg_offset);
357116 + struct device *dev = hisi->dev;
357117 + struct device_node *np = dev->of_node;
357121 + return -EINVAL;
357124 + return -EINVAL;
357126 + hisi->num_clocks = count;
357128 + hisi->clks = devm_kcalloc(dev, hisi->num_clocks, sizeof(struct clk *),
357130 + if (hisi->clks == NULL)
357131 + return -ENOMEM;
357133 + for (i = 0; i < hisi->num_clocks; i++) {
357138 + while (--i >= 0)
357139 + clk_put(hisi->clks[i]);
357147 + while (--i >= 0) {
357148 + clk_disable_unprepare(hisi->clks[i]);
357149 + clk_put(hisi->clks[i]);
357156 + hisi->clks[i] = clk;
357161 + devm_kfree(dev, hisi->clks);
357162 + hisi->clks = NULL;
357174 + reg = readl(hisi->ctrl_base + GUSB2PHYCFG_OFFSET);
357176 + writel(reg, hisi->ctrl_base + GUSB2PHYCFG_OFFSET);
357178 + reg = readl(hisi->ctrl_base + GCTL_OFFSET);
357180 + writel(reg, hisi->ctrl_base + GCTL_OFFSET);
357182 + reg = readl(hisi->ctrl_base + GUCTL_OFFSET);
357185 + writel(reg, hisi->ctrl_base + GUCTL_OFFSET);
357187 + reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
357189 + writel(reg, hisi->ctrl_base + GFLADJ_OFFSET);
357191 + reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
357194 + writel(reg, hisi->ctrl_base + GFLADJ_OFFSET);
357196 + reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
357198 + writel(reg, hisi->ctrl_base + GFLADJ_OFFSET);
357200 + reg = readl(hisi->ctrl_base + GFLADJ_OFFSET);
357203 + writel(reg, hisi->ctrl_base + GFLADJ_OFFSET);
357209 + return -EINVAL;
357211 + hisi->ctrl_base = of_iomap(np, DEV_NODE_FLAG0);
357212 + if (IS_ERR(hisi->ctrl_base))
357213 + return -ENOMEM;
357215 + hisi->crg_base = of_iomap(np, DEV_NODE_FLAG1);
357216 + if (IS_ERR(hisi->crg_base)) {
357217 + iounmap(hisi->ctrl_base);
357218 + return -ENOMEM;
357227 + struct device *dev = &pdev->dev;
357228 + struct device_node *np = dev->of_node;
357233 + return -ENOMEM;
357236 + hisi->dev = dev;
357243 + return -ENOMEM;
357246 + hisi->port_rst = devm_reset_control_get(dev, "vcc_reset");
357247 + if (IS_ERR_OR_NULL(hisi->port_rst)) {
357248 + ret = PTR_ERR(hisi->port_rst);
357256 + reset_control_assert(hisi->port_rst);
357262 + reset_control_deassert(hisi->port_rst);
357270 + for (i = 0; i < hisi->num_clocks; i++) {
357271 + clk_disable_unprepare(hisi->clks[i]);
357272 + clk_put(hisi->clks[i]);
357279 + iounmap(hisi->ctrl_base);
357280 + iounmap(hisi->crg_base);
357291 + struct device *dev = &pdev->dev;
357294 + for (i = 0; i < hisi->num_clocks; i++) {
357295 + clk_disable_unprepare(hisi->clks[i]);
357296 + clk_put(hisi->clks[i]);
357299 + reset_control_assert(hisi->port_rst);
357303 + iounmap(hisi->ctrl_base);
357304 + iounmap(hisi->crg_base);
357323 + .name = "hisi-dwc3",
357332 diff --git a/drivers/usb/dwc3/dwc3-hisi.h b/drivers/usb/dwc3/dwc3-hisi.h
357335 --- /dev/null
357336 +++ b/drivers/usb/dwc3/dwc3-hisi.h
357337 @@ -0,0 +1,54 @@
357339 + * dwc3-hisi.h
357343 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
357392 diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
357394 --- a/drivers/usb/dwc3/ep0.c
357396 @@ -281,6 +281,24 @@ void dwc3_ep0_out_start(struct dwc3 *dwc)
357408 + for (i = 0; i < dwc->num_eps; i++) {
357409 + if (dwc->dwceps_map_to_usbeps[i] == num) {
357421 @@ -291,6 +309,9 @@ static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
357425 + if (dwc->eps_new_init)
357428 dep = dwc->eps[epnum];
357429 if (dep->flags & DWC3_EP_ENABLED)
357431 @@ -380,6 +401,9 @@ static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
357432 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
357433 return -EINVAL;
357435 + if (dwc->dis_initiate_u1)
357436 + return -EINVAL;
357438 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
357441 @@ -402,6 +426,9 @@ static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
357442 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
357443 return -EINVAL;
357445 + if (dwc->dis_initiate_u2)
357446 + return -EINVAL;
357448 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
357451 @@ -626,7 +653,15 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
357454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
357455 - reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
357456 + if (dwc->dis_initiate_u1)
357461 + if (dwc->dis_initiate_u2)
357465 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
357468 diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
357470 --- a/drivers/usb/dwc3/gadget.c
357472 @@ -27,6 +27,8 @@
357478 #define DWC3_ALIGN_FRAME(d) (((d)->frame_number + (d)->interval) \
357479 & ~((d)->interval - 1))
357481 @@ -144,7 +146,7 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
357485 -static void dwc3_ep_inc_trb(u8 *index)
357489 if (*index == (DWC3_TRB_NUM - 1))
357490 @@ -583,7 +585,11 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
357494 - params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
357495 + if (dwc->eps_new_init)
357497 + DWC3_DEPCFG_EP_NUMBER(dwc->dwceps_map_to_usbeps[dep->number]);
357499 + params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
357503 @@ -635,7 +641,12 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
357504 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
357506 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
357507 - reg |= DWC3_DALEPENA_EP(dep->number);
357509 + if (dwc->eps_new_init)
357510 + reg |= DWC3_DALEPENA_EP(dwc->dwceps_map_to_usbeps[dep->number]);
357512 + reg |= DWC3_DALEPENA_EP(dep->number);
357514 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
357517 @@ -740,7 +751,12 @@ static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
357520 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
357521 - reg &= ~DWC3_DALEPENA_EP(dep->number);
357523 + if (dwc->eps_new_init)
357524 + reg &= ~DWC3_DALEPENA_EP(dwc->dwceps_map_to_usbeps[dep->number]);
357526 + reg &= ~DWC3_DALEPENA_EP(dep->number);
357528 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
357530 dep->stream_capable = false;
357531 @@ -868,9 +884,9 @@ static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
357535 -static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
357538 - u8 tmp = index;
357542 tmp = DWC3_TRB_NUM - 1;
357543 @@ -881,7 +897,7 @@ static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
357547 - u8 trbs_left;
357552 @@ -914,6 +930,7 @@ static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
357553 struct dwc3 *dwc = dep->dwc;
357554 struct usb_gadget *gadget = &dwc->gadget;
357555 enum usb_device_speed speed = gadget->speed;
357558 trb->size = DWC3_TRB_SIZE_LENGTH(length);
357559 trb->bpl = lower_32_bits(dma);
357560 @@ -962,8 +979,19 @@ static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
357561 mult--;
357563 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
357577 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
357580 @@ -1000,7 +1028,7 @@ static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
357582 trb->ctrl |= DWC3_TRB_CTRL_IOC;
357584 - if (chain)
357586 trb->ctrl |= DWC3_TRB_CTRL_CHN;
357588 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
357589 @@ -1053,6 +1081,9 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
357593 + struct dwc3 *dwc = dep->dwc;
357594 + struct usb_gadget *gadget = &dwc->gadget;
357595 + enum usb_device_speed speed = gadget->speed;
357596 struct scatterlist *sg = req->start_sg;
357599 @@ -1134,7 +1165,11 @@ static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
357600 req->request.no_interrupt);
357603 - dwc3_prepare_one_trb(dep, req, trb_length, chain, i);
357605 + usb_endpoint_xfer_isoc(dep->endpoint.desc))
357612 @@ -1278,6 +1313,14 @@ static void dwc3_prepare_trbs(struct dwc3_ep *dep)
357620 + reg = dwc3_readl(dwc->regs, DWC3_DSTS);
357627 @@ -1303,6 +1346,14 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
357629 params.param0 = upper_32_bits(req->trb_dma);
357630 params.param1 = lower_32_bits(req->trb_dma);
357632 + if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
357634 + dep->frame_number = DWC3_ALIGN_FRAME(dep);
357636 + dep->frame_number = DWC3_ALIGN_FRAME(dep);
357641 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
357642 @@ -1334,12 +1385,15 @@ static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
357646 -static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
357647 -{
357648 - u32 reg;
357650 + u16 cframe = __dwc3_gadget_get_frame(dep->dwc);
357651 + u16 eframe = dep->frame_number & DWC3_EVENT_PRAM_SOFFN_MASK;
357653 - reg = dwc3_readl(dwc->regs, DWC3_DSTS);
357654 - return DWC3_DSTS_SOFFN(reg);
357658 + return (((eframe - cframe) & DWC3_EVENT_PRAM_SOFFN_MASK)
357663 @@ -1351,6 +1405,9 @@ static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
357668 + dep->frame_number = DWC3_ALIGN_FRAME(dep);
357670 dep->frame_number = DWC3_ALIGN_FRAME(dep);
357673 @@ -1388,8 +1445,10 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *…
357675 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
357676 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
357677 - !(dep->flags & DWC3_EP_TRANSFER_STARTED))
357678 + list_empty(&dep->started_list)) {
357683 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
357684 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
357685 @@ -1472,6 +1531,9 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
357687 spin_lock_irqsave(&dwc->lock, flags);
357689 + if (list_empty(&dep->pending_list) && list_empty(&dep->started_list) )
357692 list_for_each_entry(r, &dep->pending_list, list) {
357695 @@ -2235,12 +2297,78 @@ static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
357702 + struct dwc3_hwparams *parms = &dwc->hwparams;
357703 + u32 direction = dwc->eps_directions;
357722 + return -ENOMEM;
357724 + dep->dwc = dwc;
357725 + dep->number = i;
357726 + dep->direction = !!(direction & 0x1);
357727 + dep->regs = dwc->regs + DWC3_DEP_BASE(i);
357728 + dwc->eps[i] = dep;
357730 + snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
357733 + dep->endpoint.name = dep->name;
357734 + spin_lock_init(&dep->lock);
357737 + dep->endpoint.desc = &dwc3_gadget_ep0_desc;
357738 + dep->endpoint.comp_desc = NULL;
357740 + } else if (dep->direction) {
357749 + dep->endpoint.caps.dir_in = !!(direction & 0x1);
357750 + dep->endpoint.caps.dir_out = !(direction & 0x1);
357753 + INIT_LIST_HEAD(&dep->pending_list);
357754 + INIT_LIST_HEAD(&dep->started_list);
357755 + INIT_LIST_HEAD(&dep->cancelled_list);
357765 INIT_LIST_HEAD(&dwc->gadget.ep_list);
357767 + if (dwc->eps_new_init) {
357774 @@ -3290,6 +3418,8 @@ int dwc3_gadget_init(struct dwc3 *dwc)
357780 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
357782 dev_err(dwc->dev, "failed to register udc\n");
357783 diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
357785 --- a/drivers/usb/dwc3/host.c
357787 @@ -46,7 +46,7 @@ static int dwc3_host_get_irq(struct dwc3 *dwc)
357791 - struct property_entry props[3];
357796 @@ -93,6 +93,9 @@ int dwc3_host_init(struct dwc3 *dwc)
357797 if (dwc->usb3_lpm_capable)
357798 props[prop_idx++].name = "usb3-lpm-capable";
357800 + if (dwc->usb2_lpm_disable)
357801 + props[prop_idx++].name = "usb2-lpm-disable";
357806 diff --git a/drivers/usb/dwc3/proc.c b/drivers/usb/dwc3/proc.c
357809 --- /dev/null
357811 @@ -0,0 +1,139 @@
357817 + * Copyright (C) Hisilicon Technologies Co., Ltd. 2018-2019. All rights reserved.
357850 + struct dwc3 *dwc = s->private;
357852 + switch (dwc->udc_connect_status) {
357869 + return -EINVAL;
357879 + return -EINVAL;
357897 + return -EINVAL;
357910 + proc_entry = proc_mkdir(to_platform_device(dwc->dev)->name, proc_dwc3_dir);
357913 + __func__, to_platform_device(dwc->dev)->name);
357914 + return -1;
357916 + dwc->parent_entry = proc_entry;
357919 + 0, dwc->parent_entry,
357924 + return -1;
357926 + dwc->csts_entry = proc_entry;
357937 + remove_proc_entry(DWC3_PROC_CONNECTED_STATUS, dwc->parent_entry);
357938 + remove_proc_entry(to_platform_device(dwc->dev)->name, proc_dwc3_dir);
357942 + proc_dwc3_dir_cnt--;
357951 diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
357953 --- a/drivers/usb/gadget/composite.c
357955 @@ -675,7 +675,7 @@ static int bos_desc(struct usb_composite_dev *cdev)
357956 usb_ext->bLength = USB_DT_USB_EXT_CAP_SIZE;
357957 usb_ext->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
357958 usb_ext->bDevCapabilityType = USB_CAP_TYPE_EXT;
357959 - usb_ext->bmAttributes = cpu_to_le32(USB_LPM_SUPPORT | USB_BESL_SUPPORT);
357960 + usb_ext->bmAttributes = cpu_to_le32(0x0);
357964 diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
357966 --- a/drivers/usb/gadget/epautoconf.c
357968 @@ -78,9 +78,16 @@ struct usb_ep *usb_ep_autoconfig_ss(
357972 - list_for_each_entry (ep, &gadget->ep_list, ep_list) {
357973 - if (usb_gadget_ep_match_desc(gadget, ep, desc, ep_comp))
357974 - goto found_ep;
357976 + list_for_each_entry_reverse(ep, &gadget->ep_list, ep_list) {
357981 + list_for_each_entry(ep, &gadget->ep_list, ep_list) {
357988 diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_stor…
357990 --- a/drivers/usb/gadget/function/f_mass_storage.c
357992 @@ -306,6 +306,7 @@ struct fsg_common {
358000 @@ -1337,7 +1338,7 @@ static int do_start_stop(struct fsg_common *common)
358002 up_read(&common->filesem);
358003 down_write(&common->filesem);
358004 - fsg_lun_close(curlun);
358005 + common->actived = 0;
358006 up_write(&common->filesem);
358007 down_read(&common->filesem);
358009 @@ -1774,7 +1775,7 @@ static int check_command(struct fsg_common *common, int cmnd_size,
358013 - if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
358014 + if (curlun && !common->actived && needs_medium) {
358015 curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
358016 return -EINVAL;
358018 @@ -2234,6 +2235,7 @@ static int do_set_interface(struct fsg_common *common, struct fsg_dev *new_fs…
358021 common->running = 0;
358022 + common->actived = 0;
358026 @@ -2277,7 +2279,7 @@ static int do_set_interface(struct fsg_common *common, struct fsg_dev *new_fs…
358027 bh->inreq->complete = bulk_in_complete;
358028 bh->outreq->complete = bulk_out_complete;
358030 -
358031 + common->actived = 1;
358032 common->running = 1;
358033 for (i = 0; i < ARRAY_SIZE(common->luns); ++i)
358034 if (common->luns[i])
358035 diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c
358037 --- a/drivers/usb/gadget/function/f_uac1.c
358039 @@ -48,6 +48,16 @@ static inline struct f_uac1 *func_to_uac1(struct usb_function *f)
358056 @@ -246,7 +256,46 @@ static struct uac_iso_endpoint_descriptor as_iso_in_desc = {
358103 @@ -262,6 +311,7 @@ static struct usb_descriptor_header *f_audio_desc[] = {
358111 @@ -271,6 +321,7 @@ static struct usb_descriptor_header *f_audio_desc[] = {
358119 @@ -523,6 +574,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
358127 @@ -559,6 +611,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
358133 uac1->ac_intf = status;
358134 uac1->ac_alt = 0;
358135 @@ -568,6 +621,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
358140 uac1->as_out_intf = status;
358141 uac1->as_out_alt = 0;
358143 @@ -576,6 +630,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
358148 uac1->as_in_intf = status;
358149 uac1->as_in_alt = 0;
358151 @@ -597,8 +652,8 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f)
358152 audio->in_ep->desc = &as_in_ep_desc;
358155 - status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, NULL,
358156 - NULL);
358162 diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c
358164 --- a/drivers/usb/gadget/function/f_uvc.c
358166 @@ -649,7 +649,7 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f)
358169 uvc_ss_streaming_ep.bInterval = opts->streaming_interval;
358170 - uvc_ss_streaming_comp.bmAttributes = max_packet_mult - 1;
358172 uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst;
358175 @@ -793,6 +793,11 @@ static struct usb_function_instance *uvc_alloc_inst(void)
358186 return ERR_PTR(-ENOMEM);
358187 @@ -827,6 +832,20 @@ static struct usb_function_instance *uvc_alloc_inst(void)
358188 pd->bmControls[1] = 0;
358189 pd->iProcessing = 0;
358191 + ed = &opts->uvc_extension;
358192 + ed->bLength = UVC_DT_EXTENSION_UNIT_SIZE(1, 2);
358193 + ed->bDescriptorType = USB_DT_CS_INTERFACE;
358194 + ed->bDescriptorSubType = UVC_VC_EXTENSION_UNIT;
358195 + ed->bUnitID = 10;
358196 + memcpy(ed->guidExtensionCode, extension_guid, sizeof(extension_guid));
358197 + ed->bNrInPins = 1;
358198 + ed->baSourceID[0] = 2;
358199 + ed->bNumControls = 15;
358200 + ed->bControlSize = 2;
358201 + ed->bmControls[0] = 1;
358202 + ed->bmControls[1] = 0;
358203 + ed->iExtension = 0;
358205 od = &opts->uvc_output_terminal;
358206 od->bLength = UVC_DT_OUTPUT_TERMINAL_SIZE;
358207 od->bDescriptorType = USB_DT_CS_INTERFACE;
358208 @@ -850,8 +869,9 @@ static struct usb_function_instance *uvc_alloc_inst(void)
358212 - ctl_cls[3] = (struct uvc_descriptor_header *)od;
358213 - ctl_cls[4] = NULL; /* NULL-terminate */
358216 + ctl_cls[5] = NULL; /* NULL-terminate */
358217 opts->fs_control =
358220 @@ -860,13 +880,15 @@ static struct usb_function_instance *uvc_alloc_inst(void)
358224 - ctl_cls[3] = (struct uvc_descriptor_header *)od;
358225 - ctl_cls[4] = NULL; /* NULL-terminate */
358228 + ctl_cls[5] = NULL; /* NULL-terminate */
358229 opts->ss_control =
358232 opts->streaming_interval = 1;
358233 - opts->streaming_maxpacket = 1024;
358234 + opts->streaming_maxpacket = 3072;
358235 + opts->streaming_maxburst = 15;
358238 return &opts->func_inst;
358239 diff --git a/drivers/usb/gadget/function/u_uvc.h b/drivers/usb/gadget/function/u_uvc.h
358241 --- a/drivers/usb/gadget/function/u_uvc.h
358243 @@ -49,6 +49,7 @@ struct f_uvc_opts {
358250 * Control descriptors pointers arrays for full-/high-speed and
358251 @@ -57,8 +58,8 @@ struct f_uvc_opts {
358255 - struct uvc_descriptor_header *uvc_fs_control_cls[5];
358256 - struct uvc_descriptor_header *uvc_ss_control_cls[5];
358261 * Streaming descriptors for full-speed, high-speed and super-speed.
358262 diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h
358264 --- a/drivers/usb/gadget/function/uvc.h
358266 @@ -63,8 +63,11 @@ extern unsigned int uvc_gadget_trace_param;
358267 /* ------------------------------------------------------------------------
358270 -
358271 -#define UVC_NUM_REQUESTS 4
358280 @@ -83,6 +86,9 @@ struct uvc_video {
358290 diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c
358292 --- a/drivers/usb/gadget/function/uvc_configfs.c
358294 @@ -266,7 +266,49 @@ static ssize_t uvcg_default_processing_bm_controls_show(
358298 -UVC_ATTR_RO(uvcg_default_processing_, bm_controls, bmControls);
358305 + struct mutex *su_mutex = &dp->group.cg_subsys->su_mutex;
358315 + opts_item = dp->group.cg_item.ci_parent->ci_parent->ci_parent;
358317 + pd = &opts->uvc_processing;
358320 + while (pg - page < len) {
358322 + while (i < sizeof(buf) && (pg - page < len) &&
358325 + while ((pg - page < len) && (*pg == '\0' || *pg == '\n'))
358328 + ret = kstrtou8(buf, 0, &pd->bmControls[idx++]);
358331 + if (idx >= pd->bControlSize)
358336 + mutex_unlock(&opts->lock);
358345 @@ -289,7 +331,111 @@ static struct uvcg_processing_grp {
358349 -static const struct config_item_type uvcg_processing_grp_type = {
358373 + struct mutex *su_mutex = &dp->group.cg_subsys->su_mutex; \
358379 + opts_item = dp->group.cg_item.ci_parent->ci_parent->ci_parent; \
358381 + ed = &opts->uvc_extension; \
358383 + mutex_lock(&opts->lock); \
358384 + result = sprintf(page, "%d\n", conv(ed->aname)); \
358385 + mutex_unlock(&opts->lock); \
358409 + struct mutex *su_mutex = &dp->group.cg_subsys->su_mutex;
358416 + opts_item = dp->group.cg_item.ci_parent->ci_parent->ci_parent;
358418 + ed = &opts->uvc_extension;
358420 + mutex_lock(&opts->lock);
358421 + for (result = 0, i = 0; i < ed->bControlSize; ++i) {
358422 + result += sprintf(pg, "%d\n", ed->bmControls[i]);
358425 + mutex_unlock(&opts->lock);
358458 @@ -380,7 +526,50 @@ static ssize_t uvcg_default_camera_bm_controls_show(
358462 -UVC_ATTR_RO(uvcg_default_camera_, bm_controls, bmControls);
358469 + struct mutex *su_mutex = &dc->group.cg_subsys->su_mutex;
358479 + opts_item = dc->group.cg_item.ci_parent->ci_parent->ci_parent->
358482 + cd = &opts->uvc_camera_terminal;
358485 + while (pg - page < len) {
358487 + while (i < sizeof(buf) && (pg - page < len) &&
358490 + while ((pg - page < len) && (*pg == '\0' || *pg == '\n'))
358493 + ret = kstrtou8(buf, 0, &cd->bmControls[idx++]);
358496 + if (idx >= cd->bControlSize)
358501 + mutex_unlock(&opts->lock);
358510 @@ -633,14 +822,21 @@ static struct uvcg_mjpeg_grp {
358532 @@ -1212,6 +1408,7 @@ static struct config_item *uvcg_frame_make(struct config_group *group,
358533 return ERR_PTR(-EINVAL);
358535 ++fmt->num_frames;
358536 + h->frame.b_frame_index = fmt->num_frames;
358537 mutex_unlock(&opts->lock);
358539 config_item_init_type_name(&h->item, name, &uvcg_frame_type);
358540 @@ -1236,6 +1433,263 @@ static void uvcg_frame_drop(struct config_group *group, struct config_item …
358541 mutex_unlock(&opts->lock);
358575 + struct mutex *su_mutex = &f->item.ci_group->cg_subsys->su_mutex;\
358580 + opts_item = f->item.ci_parent->ci_parent->ci_parent->ci_parent; \
358583 + mutex_lock(&opts->lock); \
358584 + result = sprintf(page, "%d\n", to_cpu_endian(f->frame.cname)); \
358585 + mutex_unlock(&opts->lock); \
358598 + struct mutex *su_mutex = &f->item.ci_group->cg_subsys->su_mutex;\
358608 + opts_item = f->item.ci_parent->ci_parent->ci_parent->ci_parent; \
358610 + fmt = to_uvcg_format(f->item.ci_parent); \
358612 + mutex_lock(&opts->lock); \
358613 + if (fmt->linked || opts->refcnt) { \
358614 + ret = -EBUSY; \
358618 + f->frame.cname = to_little_endian(num); \
358621 + mutex_unlock(&opts->lock); \
358651 + struct mutex *su_mutex = &frm->item.ci_group->cg_subsys->su_mutex;
358657 + opts_item = frm->item.ci_parent->ci_parent->ci_parent->ci_parent;
358660 + mutex_lock(&opts->lock);
358661 + for (result = 0, i = 0; i < frm->frame.b_frame_interval_type; ++i) {
358663 + le32_to_cpu(frm->dw_frame_interval[i]));
358666 + mutex_unlock(&opts->lock);
358679 + struct mutex *su_mutex = &ch->item.ci_group->cg_subsys->su_mutex;
358685 + opts_item = ch->item.ci_parent->ci_parent->ci_parent->ci_parent;
358687 + fmt = to_uvcg_format(ch->item.ci_parent);
358689 + mutex_lock(&opts->lock);
358690 + if (fmt->linked || opts->refcnt) {
358691 + ret = -EBUSY;
358701 + ret = -ENOMEM;
358711 + kfree(ch->dw_frame_interval);
358712 + ch->dw_frame_interval = frm_intrv;
358713 + ch->frame.b_frame_interval_type = n;
358717 + mutex_unlock(&opts->lock);
358751 + return ERR_PTR(-ENOMEM);
358753 + h->frame.b_descriptor_type = USB_DT_CS_INTERFACE;
358754 + h->frame.b_frame_index = 1;
358755 + h->frame.w_width = cpu_to_le16(640);
358756 + h->frame.w_height = cpu_to_le16(360);
358757 + h->frame.dw_min_bit_rate = cpu_to_le32(18432000);
358758 + h->frame.dw_max_bit_rate = cpu_to_le32(55296000);
358759 + h->frame.dw_default_frame_interval = cpu_to_le32(333333);
358760 + h->frame.dw_bytes_per_line = cpu_to_le32(0);
358762 + opts_item = group->cg_item.ci_parent->ci_parent->ci_parent;
358765 + mutex_lock(&opts->lock);
358766 + fmt = to_uvcg_format(&group->cg_item);
358767 + if (fmt->type == UVCG_FRAME_FRAME_BASED) {
358768 + h->frame.b_descriptor_subtype = UVC_VS_FRAME_FRAME_BASED;
358769 + h->fmt_type = UVCG_FRAME_FRAME_BASED;
358771 + mutex_unlock(&opts->lock);
358773 + return ERR_PTR(-EINVAL);
358775 + ++fmt->num_frames;
358776 + h->frame.b_frame_index = fmt->num_frames;
358777 + mutex_unlock(&opts->lock);
358779 + config_item_init_type_name(&h->item, name, &uvcg_frame_based_frame_type);
358781 + return &h->item;
358791 + opts_item = group->cg_item.ci_parent->ci_parent->ci_parent;
358794 + mutex_lock(&opts->lock);
358795 + fmt = to_uvcg_format(&group->cg_item);
358796 + --fmt->num_frames;
358798 + mutex_unlock(&opts->lock);
358804 @@ -1447,10 +1901,17 @@ static const struct config_item_type uvcg_uncompressed_type = {
358822 @@ -1461,7 +1922,11 @@ static struct config_group *uvcg_uncompressed_make(struct config_group *grou…
358823 h->desc.bDescriptorType = USB_DT_CS_INTERFACE;
358824 h->desc.bDescriptorSubType = UVC_VS_FORMAT_UNCOMPRESSED;
358825 memcpy(h->desc.guidFormat, guid, sizeof(guid));
358827 h->desc.bBitsPerPixel = 16;
358829 + h->desc.bBitsPerPixel = 12;
358831 h->desc.bDefaultFrameIndex = 1;
358832 h->desc.bAspectRatioX = 0;
358833 h->desc.bAspectRatioY = 0;
358834 @@ -1687,6 +2152,205 @@ static const struct config_item_type uvcg_mjpeg_grp_type = {
358862 + struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \
358867 + opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\
358870 + mutex_lock(&opts->lock); \
358871 + result = sprintf(page, "%d\n", conv(u->desc.aname)); \
358872 + mutex_unlock(&opts->lock); \
358886 + struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \
358891 + opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\
358894 + mutex_lock(&opts->lock); \
358895 + result = sprintf(page, "%d\n", conv(u->desc.aname)); \
358896 + mutex_unlock(&opts->lock); \
358909 + struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \
358915 + opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\
358918 + mutex_lock(&opts->lock); \
358919 + if (u->fmt.linked || opts->refcnt) { \
358920 + ret = -EBUSY; \
358929 + ret = -EINVAL; \
358932 + u->desc.aname = num; \
358935 + mutex_unlock(&opts->lock); \
358959 + return uvcg_format_bma_controls_show(&u->fmt, page);
358967 + return uvcg_format_bma_controls_store(&u->fmt, page, len);
358998 + return ERR_PTR(-ENOMEM);
359000 + h->desc.bLength = UVC_DT_FRAME_BASED_FORMAT_SIZE;
359001 + h->desc.bDescriptorType = USB_DT_CS_INTERFACE;
359002 + h->desc.bDescriptorSubType = UVC_VS_FORMAT_FRAME_BASED;
359003 + memcpy(h->desc.guidFormat, guid, sizeof(guid));
359004 + h->desc.bBitsPerPixel = 16;
359005 + h->desc.bDefaultFrameIndex = 1;
359006 + h->desc.bAspectRatioX = 0;
359007 + h->desc.bAspectRatioY = 0;
359008 + h->desc.bmInterfaceFlags = 0;
359009 + h->desc.bCopyProtect = 0;
359010 + h->desc.bVariableSize = 1;
359012 + h->fmt.type = UVCG_FRAME_FRAME_BASED;
359013 + config_group_init_type_name(&h->fmt.group, name,
359016 + return &h->fmt.group;
359040 @@ -1882,6 +2546,11 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n,
359043 *size += sizeof(m->desc);
359044 + } else if (fmt->type == UVCG_FRAME_FRAME_BASED) {
359048 + *size += sizeof(h->desc);
359050 return -EINVAL;
359052 @@ -1890,7 +2559,14 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n,
359055 int sz = sizeof(frm->dw_frame_interval);
359056 + if (frm->frame.b_descriptor_subtype == UVC_VS_FRAME_FRAME_BASED) {
359058 + *size += sizeof(fb_frm->frame);
359059 + *size += fb_frm->frame.b_frame_interval_type * sizeof(fb_frm->dw_frame_interval);
359064 *size += sizeof(frm->frame);
359065 *size += frm->frame.b_frame_interval_type * sz;
359067 @@ -1958,6 +2634,15 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n,
359068 *dest += sizeof(m->desc);
359069 mjp->bNumFrameDescriptors = fmt->num_frames;
359070 mjp->bFormatIndex = n + 1;
359071 + } else if (fmt->type == UVCG_FRAME_FRAME_BASED) {
359076 + memcpy(*dest, &h->desc, sizeof(h->desc));
359077 + *dest += sizeof(h->desc);
359078 + ffb->bNumFrameDescriptors = fmt->num_frames;
359079 + ffb->bFormatIndex = n + 1;
359081 return -EINVAL;
359083 @@ -1967,6 +2652,19 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n,
359087 + if (frm->frame.b_descriptor_subtype == UVC_VS_FRAME_FRAME_BASED) {
359089 + sz = sizeof(fb_frm->frame);
359090 + memcpy(*dest, &fb_frm->frame, sz);
359092 + sz = fb_frm->frame.b_frame_interval_type *
359093 + sizeof(*fb_frm->dw_frame_interval);
359094 + memcpy(*dest, fb_frm->dw_frame_interval, sz);
359096 + h->bLength = UVC_DT_FRAME_BASED_FRAME_SIZE(
359097 + fb_frm->frame.b_frame_interval_type);
359100 sz = sizeof(frm->frame);
359101 memcpy(*dest, &frm->frame, sz);
359103 @@ -2224,6 +2922,13 @@ int uvcg_attach_configfs(struct f_uvc_opts *opts)
359117 @@ -2278,6 +2983,9 @@ int uvcg_attach_configfs(struct f_uvc_opts *opts)
359127 @@ -2310,6 +3018,8 @@ int uvcg_attach_configfs(struct f_uvc_opts *opts)
359136 diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c
359138 --- a/drivers/usb/gadget/function/uvc_v4l2.c
359140 @@ -56,8 +56,13 @@ struct uvc_format {
359154 diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c
359156 --- a/drivers/usb/gadget/function/uvc_video.c
359158 @@ -12,13 +12,15 @@
359162 -
359164 #include <media/v4l2-dev.h>
359172 /* --------------------------------------------------------------------------
359175 @@ -98,9 +100,45 @@ static void
359186 + for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) {
359187 + mem = sg_virt(&req->sg[sg_idx]);
359188 + len = video->req_size;
359193 + len -= ret;
359197 + len -= ret;
359200 + sg_set_buf(&req->sg[sg_idx], sg_virt(&req->sg[sg_idx]),
359201 + video->req_size - len);
359202 + ttllen += video->req_size - len;
359204 + if (buf->bytesused == video->queue.buf_used) {
359205 + video->queue.buf_used = 0;
359206 + buf->state = UVC_BUF_STATE_DONE;
359207 + uvcg_queue_next_buffer(&video->queue, buf);
359208 + video->fid ^= UVC_STREAM_FID;
359212 + req->num_sgs = sg_idx + 1;
359213 + sg_mark_end(&req->sg[sg_idx]);
359214 + req->length = ttllen;
359216 void *mem = req->buf;
359217 int len = video->req_size;
359218 - int ret;
359222 @@ -119,6 +157,7 @@ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video,
359223 uvcg_queue_next_buffer(&video->queue, buf);
359224 video->fid ^= UVC_STREAM_FID;
359229 /* --------------------------------------------------------------------------
359230 @@ -129,6 +168,15 @@ static int uvcg_video_ep_queue(struct uvc_video *video, struct usb_request *re…
359240 + if (!video->ep->enabled)
359241 + return -EINVAL;
359243 ret = usb_ep_queue(video->ep, req, GFP_ATOMIC);
359246 @@ -201,7 +249,9 @@ uvc_video_complete(struct usb_ep *ep, struct usb_request *req)
359247 spin_unlock_irqrestore(&video->queue.irqlock, flags);
359250 -
359252 + sg_unmark_end(&req->sg[req->num_sgs - 1]);
359254 video->encode(req, video, buf);
359257 @@ -216,6 +266,9 @@ uvc_video_complete(struct usb_ep *ep, struct usb_request *req)
359260 spin_lock_irqsave(&video->req_lock, flags);
359262 + sg_unmark_end(&req->sg[req->num_sgs - 1]);
359264 list_add_tail(&req->list, &video->req_free);
359265 spin_unlock_irqrestore(&video->req_lock, flags);
359267 @@ -224,9 +277,22 @@ static int
359276 if (video->req[i]) {
359278 + for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++)
359279 + if (sg_page(&video->req[i]->sg[sg_idx]))
359280 + kfree(sg_virt(&video->req[i]->sg[sg_idx]));
359282 + if (video->req[i]->sg) {
359283 + kfree(video->req[i]->sg);
359284 + video->req[i]->sg = NULL;
359287 usb_ep_free_request(video->ep, video->req[i]);
359288 video->req[i] = NULL;
359290 @@ -248,6 +314,11 @@ uvc_video_alloc_requests(struct uvc_video *video)
359293 int ret = -ENOMEM;
359300 BUG_ON(video->req_size);
359302 @@ -255,6 +326,35 @@ uvc_video_alloc_requests(struct uvc_video *video)
359303 * max_t(unsigned int, video->ep->maxburst, 1)
359304 * (video->ep->mult);
359307 + num_sgs = ((video->imagesize / (req_size - 2)) + 1);
359308 + video->num_sgs = num_sgs;
359316 + video->req[i] = usb_ep_alloc_request(video->ep, GFP_KERNEL);
359317 + if (video->req[i] == NULL)
359321 + video->sg_buf = kmalloc(req_size, GFP_KERNEL);
359322 + if (video->sg_buf == NULL)
359324 + sg_set_buf(&sg[sg_idx], video->sg_buf, req_size);
359326 + video->req[i]->sg = sg;
359327 + video->req[i]->num_sgs = num_sgs;
359328 + video->req[i]->length = 0;
359329 + video->req[i]->complete = uvc_video_complete;
359330 + video->req[i]->context = video;
359332 + list_add_tail(&video->req[i]->list, &video->req_free);
359336 video->req_buffer[i] = kmalloc(req_size, GFP_KERNEL);
359337 if (video->req_buffer[i] == NULL)
359338 @@ -271,7 +371,7 @@ uvc_video_alloc_requests(struct uvc_video *video)
359340 list_add_tail(&video->req[i]->list, &video->req_free);
359342 -
359344 video->req_size = req_size;
359347 @@ -391,12 +491,17 @@ int uvcg_video_init(struct uvc_video *video)
359349 INIT_LIST_HEAD(&video->req_free);
359350 spin_lock_init(&video->req_lock);
359351 -
359353 video->fcc = V4L2_PIX_FMT_YUYV;
359354 + video->imagesize = 320 * 240 * 2;
359355 video->bpp = 16;
359357 + video->fcc = V4L2_PIX_FMT_NV21;
359358 + video->imagesize = 320 * 240 * 3 / 2; /* YUV420: w*h*1.5 */
359359 + video->bpp = 12;
359361 video->width = 320;
359362 video->height = 240;
359363 - video->imagesize = 320 * 240 * 2;
359366 uvcg_queue_init(&video->queue, V4L2_BUF_TYPE_VIDEO_OUTPUT,
359367 diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
359369 --- a/drivers/usb/serial/option.c
359371 @@ -97,6 +97,10 @@ static void option_instat_callback(struct urb *urb);
359382 @@ -575,6 +579,7 @@ static void option_instat_callback(struct urb *urb);
359390 diff --git a/drivers/vfio/pci/vfio_pci_intrs.c b/drivers/vfio/pci/vfio_pci_intrs.c
359392 --- a/drivers/vfio/pci/vfio_pci_intrs.c
359394 @@ -645,6 +645,8 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_device *vdev, uint32_t flags,
359403 @@ -692,5 +694,19 @@ int vfio_pci_set_irqs_ioctl(struct vfio_pci_device *vdev, uint32_t flags,
359405 return -ENOTTY;
359407 - return func(vdev, index, start, count, flags, data);
359409 + down_write(&vdev->memory_lock);
359410 + pci_read_config_word(vdev->pdev, PCI_COMMAND, &cmd);
359411 + pci_write_config_word(vdev->pdev, PCI_COMMAND,
359418 + pci_write_config_word(vdev->pdev, PCI_COMMAND, cmd);
359419 + up_write(&vdev->memory_lock);
359424 diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c b/drivers/vfio/vfio_iommu_spapr_tce.c
359426 --- a/drivers/vfio/vfio_iommu_spapr_tce.c
359428 @@ -23,9 +23,9 @@
359432 -#include <asm/iommu.h>
359433 -#include <asm/tce.h>
359434 -#include <asm/mmu_context.h>
359441 diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
359443 --- a/drivers/vfio/vfio_iommu_type1.c
359445 @@ -30,6 +30,7 @@
359453 @@ -65,6 +66,7 @@ MODULE_PARM_DESC(dma_entry_limit,
359461 @@ -97,6 +99,14 @@ struct vfio_dma {
359469 +#define VFIO_PASID_INVALID (-1)
359476 diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c
359478 --- a/fs/9p/vfs_inode.c
359480 @@ -1074,6 +1074,7 @@ v9fs_vfs_getattr(const struct path *path, struct kstat *stat,
359483 struct dentry *dentry = path->dentry;
359488 @@ -1081,7 +1082,7 @@ v9fs_vfs_getattr(const struct path *path, struct kstat *stat,
359491 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) {
359492 - generic_fillattr(d_inode(dentry), stat);
359497 @@ -1092,8 +1093,10 @@ v9fs_vfs_getattr(const struct path *path, struct kstat *stat,
359501 - v9fs_stat2inode(st, d_inode(dentry), dentry->d_sb, 0);
359502 - generic_fillattr(d_inode(dentry), stat);
359503 + spin_lock(&inode->i_lock);
359504 + v9fs_stat2inode(st, inode, dentry->d_sb);
359505 + spin_unlock(&inode->i_lock);
359510 diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c
359512 --- a/fs/9p/vfs_inode_dotl.c
359514 @@ -474,6 +474,7 @@ v9fs_vfs_getattr_dotl(const struct path *path, struct kstat *stat,
359517 struct dentry *dentry = path->dentry;
359522 @@ -481,7 +482,7 @@ v9fs_vfs_getattr_dotl(const struct path *path, struct kstat *stat,
359525 if (v9ses->cache == CACHE_LOOSE || v9ses->cache == CACHE_FSCACHE) {
359526 - generic_fillattr(d_inode(dentry), stat);
359531 @@ -496,8 +497,10 @@ v9fs_vfs_getattr_dotl(const struct path *path, struct kstat *stat,
359535 - v9fs_stat2inode_dotl(st, d_inode(dentry), 0);
359536 - generic_fillattr(d_inode(dentry), stat);
359537 + spin_lock(&inode->i_lock);
359539 + spin_unlock(&inode->i_lock);
359542 stat->blksize = st->st_blksize;
359544 diff --git a/fs/aio.c b/fs/aio.c
359546 --- a/fs/aio.c
359548 @@ -1759,6 +1759,12 @@ static ssize_t aio_poll(struct aio_kiocb *aiocb, const struct iocb *iocb)
359549 INIT_LIST_HEAD(&req->wait.entry);
359550 init_waitqueue_func_entry(&req->wait, aio_poll_wake);
359555 + * an extra reference is needed here to prevent use-after-free.
359557 + get_file(req->file);
359558 mask = vfs_poll(req->file, &apt.pt) & req->events;
359559 spin_lock_irq(&ctx->ctx_lock);
359560 if (likely(req->head)) {
359561 @@ -1786,6 +1792,8 @@ static ssize_t aio_poll(struct aio_kiocb *aiocb, const struct iocb *iocb)
359562 spin_unlock_irq(&ctx->ctx_lock);
359566 + fput(req->file);
359570 diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
359572 --- a/fs/btrfs/extent-tree.c
359573 +++ b/fs/btrfs/extent-tree.c
359574 @@ -9870,6 +9870,40 @@ btrfs_create_block_group_cache(struct btrfs_fs_info *fs_info,
359581 + struct btrfs_mapping_tree *map_tree = &fs_info->mapping_tree;
359585 + read_lock(&map_tree->map_tree.lock);
359586 + em = lookup_extent_mapping(&map_tree->map_tree, start, len);
359587 + read_unlock(&map_tree->map_tree.lock);
359593 + ret = -ENOENT;
359596 + if (em->start != start || em->len != len ||
359597 + (em->map_lookup->type & BTRFS_BLOCK_GROUP_TYPE_MASK) !=
359602 + em->start, em->len, em->map_lookup->type &
359604 + ret = -EUCLEAN;
359615 @@ -9959,6 +9993,9 @@ int btrfs_read_block_groups(struct btrfs_fs_info *info)
359625 @@ -9966,7 +10003,20 @@ int btrfs_read_block_groups(struct btrfs_fs_info *info)
359628 leaf = path->nodes[0];
359629 - btrfs_item_key_to_cpu(leaf, &found_key, path->slots[0]);
359630 + slot = path->slots[0];
359647 @@ -9991,7 +10041,7 @@ int btrfs_read_block_groups(struct btrfs_fs_info *info)
359650 read_extent_buffer(leaf, &cache->item,
359651 - btrfs_item_ptr_offset(leaf, path->slots[0]),
359653 sizeof(cache->item));
359654 cache->flags = btrfs_block_group_flags(&cache->item);
359656 diff --git a/fs/fat/dir.c b/fs/fat/dir.c
359658 --- a/fs/fat/dir.c
359660 @@ -564,7 +564,8 @@ static int __fat_readdir(struct inode *inode, struct file *file,
359664 - int short_len = 0, fill_len = 0;
359669 mutex_lock(&sbi->s_lock);
359670 @@ -613,12 +614,13 @@ static int __fat_readdir(struct inode *inode, struct file *file,
359674 - } else if (status == PARSE_INVALID)
359677 - else if (status == PARSE_NOT_LONGNAME)
359680 - else if (status == PARSE_EOF)
359687 @@ -671,8 +673,9 @@ static int __fat_readdir(struct inode *inode, struct file *file,
359689 inum = tmp->i_ino;
359691 - } else
359696 (de->attr & ATTR_DIR) ? DT_DIR : DT_REG))
359698 @@ -782,6 +785,388 @@ static int fat_ioctl_readdir(struct inode *inode, struct file *file,
359739 + return ctx->actor(ctx, name, namelen, ctx->pos, ino,
359747 + return ctx->actor(ctx, ".", 1, ctx->pos,
359748 + file->f_path.dentry->d_inode->i_ino,
359756 + return ctx->actor(ctx, "..", 2, ctx->pos,
359757 + parent_ino(file->f_path.dentry),
359766 + if (ctx->pos == 0) {
359769 + ctx->pos = 1;
359771 + if (ctx->pos == 1) {
359774 + ctx->pos = 2;
359784 + struct super_block *sb = inode->i_sb;
359791 + int isvfat = sbi->options.isvfat;
359799 + mutex_lock(&sbi->s_lock);
359801 + cpos = ctx->pos;
359803 + if (inode->i_ino == MSDOS_ROOT_INO) {
359806 + if (ctx->pos == 2) {
359811 + if (cpos & (sizeof(struct msdos_dir_entry) - 1)) {
359812 + ret = -ENOENT;
359818 + if (fat_get_entry(inode, &cpos, &bh, &de) == -1)
359827 + if (de->name[0] == DELETED_FLAG)
359829 + if (de->attr != ATTR_EXT && (de->attr & ATTR_VOLUME))
359831 + if (de->attr != ATTR_EXT && IS_FREE(de->name))
359834 + if ((de->attr & ATTR_VOLUME) || IS_FREE(de->name))
359838 + if (isvfat && de->attr == ATTR_EXT) {
359842 + ctx->pos = cpos;
359854 + int size = PATH_MAX - FAT_MAX_UNI_SIZE;
359861 + sbi->options.dotsOK);
359866 + both->longname = fill_name;
359867 + both->long_len = fill_len;
359868 + both->shortname = bufname;
359869 + both->short_len = short_len;
359876 + short_len = fat_parse_short(sb, de, bufname, sbi->options.dotsOK);
359885 + ctx->pos = cpos - (nr_slots + 1)
359889 + fat_time_fat2str(sbi, d_createtime, de->ctime,
359890 + de->cdate, de->ctime_cs);
359892 + if (!memcmp(de->name, MSDOS_DOT, MSDOS_NAME)) {
359895 + } else if (!memcmp(de->name, MSDOS_DOTDOT, MSDOS_NAME)) {
359904 + inum = tmp->i_ino;
359909 + (de->attr & ATTR_DIR) ? DT_DIR : DT_REG,
359916 + ctx->pos = cpos;
359919 + ctx->pos = cpos;
359925 + mutex_unlock(&sbi->s_lock);
359950 + longname = buf->longname;
359951 + long_len = buf->long_len;
359952 + shortname = buf->shortname;
359953 + short_len = buf->short_len;
359958 + buf->error = -EINVAL; /* only used if we fail.. */
359960 + if (reclen >= buf->count)
359961 + return -EINVAL;
359966 + buf->error = -EOVERFLOW;
359967 + return -EOVERFLOW;
359970 + dirent = buf->previous;
359973 + if (__put_user(offset, &dirent->d_off))
359977 + dirent = buf->current_dir;
359979 + if (__put_user(d_ino, &dirent->d_ino))
359982 + if (__put_user(reclen, &dirent->d_reclen))
359986 + if (copy_to_user(dirent->d_name, name, name_len))
359988 + if (__put_user(0, dirent->d_name + name_len))
359991 + if (copy_to_user(dirent->d_name, longname, long_len))
359993 + if (__put_user(0, dirent->d_name + long_len))
359997 + if (__put_user(d_type, &dirent->d_type))
360002 + if (copy_to_user(&dirent->d_size, &u_size, sizeof(u64)))
360004 + if (copy_to_user(&dirent->d_size, &de->size, sizeof(u32)))
360009 + if (copy_to_user(dirent->d_createtime, d_createtime, 8))
360012 + buf->previous = dirent;
360014 + buf->current_dir = dirent;
360015 + buf->count -= reclen;
360016 + buf->usecount += reclen;
360019 + buf->error = -EFAULT;
360020 + return -EFAULT;
360035 + buf.current_dir = &(userbuf->direntall);
360041 + if (get_user(buf.count, &(userbuf->d_count)))
360042 + return -EFAULT;
360044 + up_read(&inode->i_rwsem);
360045 + buf.ctx.pos = file->f_pos;
360046 + ret = -ENOENT;
360050 + file->f_pos = buf.ctx.pos;
360052 + down_read(&inode->i_rwsem);
360054 + if (__put_user(buf.usecount, &(userbuf->d_usecount)))
360055 + return -EFAULT;
360064 + struct inode *inode = filp->f_path.dentry->d_inode;
360072 + return -EFAULT;
360073 + if (put_user(0, &(direntallbuf->direntall.d_reclen)))
360074 + return -EFAULT;
360075 + if (put_user(0, &(direntallbuf->d_usecount)))
360076 + return -EFAULT;
360087 @@ -789,7 +1174,10 @@ static long fat_dir_ioctl(struct file *filp, unsigned int cmd,
360091 -
360099 @@ -1097,11 +1485,15 @@ static int fat_zeroed_cluster(struct inode *dir, sector_t blknr, int nr_use…
360100 err = -ENOMEM;
360107 memset(bhs[n]->b_data, 0, sb->s_blocksize);
360115 @@ -1158,8 +1550,10 @@ int fat_alloc_new_dir(struct inode *dir, struct timespec64 *ts)
360118 de = (struct msdos_dir_entry *)bhs[0]->b_data;
360126 @@ -1182,7 +1576,9 @@ int fat_alloc_new_dir(struct inode *dir, struct timespec64 *ts)
360128 memset(de + 2, 0, sb->s_blocksize - 2 * sizeof(*de));
360136 @@ -1240,11 +1636,15 @@ static int fat_add_new_entries(struct inode *dir, void *slots, int nr_slots,
360139 copy = min(size, sb->s_blocksize);
360144 memcpy(bhs[n]->b_data, slots, copy);
360151 size -= copy;
360152 diff --git a/fs/fat/fat.h b/fs/fat/fat.h
360154 --- a/fs/fat/fat.h
360156 @@ -416,6 +416,10 @@ extern void fat_time_fat2unix(struct msdos_sb_info *sbi, struct timespec64 *ts,
360167 diff --git a/fs/fat/fatent.c b/fs/fat/fatent.c
360169 --- a/fs/fat/fatent.c
360171 @@ -381,6 +381,9 @@ static int fat_mirror_bhs(struct super_block *sb, struct buffer_head **bhs,
360178 for (copy = 1; copy < sbi->fats; copy++) {
360179 sector_t backup_fat = sbi->fat_length * copy;
360181 @@ -390,11 +393,15 @@ static int fat_mirror_bhs(struct super_block *sb, struct buffer_head **bhs,
360182 err = -ENOMEM;
360189 memcpy(c_bh->b_data, bhs[n]->b_data, sb->s_blocksize);
360194 mark_buffer_dirty_inode(c_bh, sbi->fat_inode);
360195 if (sb->s_flags & SB_SYNCHRONOUS)
360197 diff --git a/fs/fat/file.c b/fs/fat/file.c
360199 --- a/fs/fat/file.c
360201 @@ -205,8 +205,17 @@ int fat_file_fsync(struct file *filp, loff_t start, loff_t end, int datasync)
360203 return blkdev_issue_flush(inode->i_sb->s_bdev, GFP_KERNEL, NULL);
360208 + struct address_space * mapping = file->f_mapping;
360209 + struct inode *inode = mapping->host;
360211 + inode->i_sb->s_op->write_inode(inode, NULL);
360219 @@ -220,6 +229,9 @@ const struct file_operations fat_file_operations = {
360229 @@ -470,7 +482,13 @@ static int fat_allow_set_time(struct msdos_sb_info *sbi, struct inode *inode)
360233 -
360237 + MSDOS_I(inode)->mmu_private = offset;
360238 + inode->i_ctime = inode->i_mtime = ((struct timespec64) { get_seconds(), 0 });
360244 @@ -503,6 +521,7 @@ int fat_setattr(struct dentry *dentry, struct iattr *attr)
360249 if (attr->ia_valid & ATTR_SIZE) {
360252 @@ -513,7 +532,7 @@ int fat_setattr(struct dentry *dentry, struct iattr *attr)
360253 attr->ia_valid &= ~ATTR_SIZE;
360256 -
360258 if (((attr->ia_valid & ATTR_UID) &&
360259 (!uid_eq(attr->ia_uid, sbi->options.fs_uid))) ||
360260 ((attr->ia_valid & ATTR_GID) &&
360261 @@ -543,6 +562,9 @@ int fat_setattr(struct dentry *dentry, struct iattr *attr)
360263 down_write(&MSDOS_I(inode)->truncate_lock);
360264 truncate_setsize(inode, attr->ia_size);
360266 + reset_mmu_private(inode, attr->ia_size);
360268 fat_truncate_blocks(inode, attr->ia_size);
360269 up_write(&MSDOS_I(inode)->truncate_lock);
360271 diff --git a/fs/fat/inode.c b/fs/fat/inode.c
360273 --- a/fs/fat/inode.c
360275 @@ -622,8 +622,9 @@ static void fat_free_eofblocks(struct inode *inode)
360276 round_up(MSDOS_I(inode)->mmu_private,
360277 MSDOS_SB(inode->i_sb)->cluster_size)) {
360279 -
360281 fat_truncate_blocks(inode, MSDOS_I(inode)->mmu_private);
360286 @@ -900,7 +901,70 @@ static int __fat_write_inode(struct inode *inode, int wait)
360293 + struct super_block *sb = inode->i_sb;
360302 + if (inode->i_ino == MSDOS_ROOT_INO)
360315 + return -EIO;
360317 + spin_lock(&sbi->inode_hash_lock);
360318 + if (i_pos != MSDOS_I(inode)->i_pos) {
360319 + spin_unlock(&sbi->inode_hash_lock);
360324 + raw_entry = &((struct msdos_dir_entry *) (bh->b_data))[offset];
360325 + if (S_ISDIR(inode->i_mode)) {
360326 + raw_entry->size = 0;
360328 + if ((raw_entry->start != 0) || (raw_entry->starthi != 0)) {
360329 + spin_unlock(&sbi->inode_hash_lock);
360332 + raw_entry->size = cpu_to_le32(inode->i_size);
360334 + raw_entry->attr = fat_make_attrs(inode);
360335 + fat_set_start(raw_entry, MSDOS_I(inode)->i_logstart);
360336 + fat_time_unix2fat(sbi, &inode->i_mtime, &raw_entry->time,
360337 + &raw_entry->date, NULL);
360338 + if (sbi->options.isvfat) {
360340 + fat_time_unix2fat(sbi, &inode->i_ctime, &raw_entry->ctime,
360341 + &raw_entry->cdate, &raw_entry->ctime_cs);
360342 + fat_time_unix2fat(sbi, &inode->i_atime, &atime,
360343 + &raw_entry->adate, NULL);
360345 + spin_unlock(&sbi->inode_hash_lock);
360357 @@ -911,8 +975,17 @@ static int fat_write_inode(struct inode *inode, struct writeback_control *wbc)
360358 mutex_lock(&MSDOS_SB(sb)->s_lock);
360360 mutex_unlock(&MSDOS_SB(sb)->s_lock);
360361 - } else
360362 - err = __fat_write_inode(inode, wbc->sync_mode == WB_SYNC_ALL);
360368 + err = __fat_write_inode_(inode, wbc->sync_mode == WB_SYNC_ALL);
360371 + err = __fat_write_inode(inode, wbc->sync_mode == WB_SYNC_ALL);
360377 diff --git a/fs/fat/misc.c b/fs/fat/misc.c
360379 --- a/fs/fat/misc.c
360381 @@ -189,7 +189,8 @@ static long days_in_year[] = {
360385 - u16 time = le16_to_cpu(__time), date = le16_to_cpu(__date);
360391 @@ -262,6 +263,34 @@ void fat_time_unix2fat(struct msdos_sb_info *sbi, struct timespec64 *ts,
360392 *time_cs = (ts->tv_sec & 1) * 100 + ts->tv_nsec / 10000000;
360404 + day = max(1, date & 0x1f) - 1;
360413 + if (!sbi->options.tz_set)
360416 + d_createtime[4] -= sbi->options.time_offset;
360426 diff --git a/fs/jffs2/compr.h b/fs/jffs2/compr.h
360428 --- a/fs/jffs2/compr.h
360430 @@ -29,9 +29,15 @@
360442 -
360447 diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c
360449 --- a/fs/ubifs/file.c
360451 @@ -1507,6 +1507,9 @@ static int ubifs_releasepage(struct page *page, gfp_t unused_gfp_flags)
360461 diff --git a/include/dt-bindings/clock/hi3516a-clock.h b/include/dt-bindings/clock/hi3516a-clock.h
360464 --- /dev/null
360465 +++ b/include/dt-bindings/clock/hi3516a-clock.h
360466 @@ -0,0 +1,105 @@
360468 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
360572 diff --git a/include/dt-bindings/clock/hi3516cv500-clock.h b/include/dt-bindings/clock/hi3516cv500-…
360575 --- /dev/null
360576 +++ b/include/dt-bindings/clock/hi3516cv500-clock.h
360577 @@ -0,0 +1,98 @@
360579 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
360676 diff --git a/include/dt-bindings/clock/hi3516dv200-clock.h b/include/dt-bindings/clock/hi3516dv200-…
360679 --- /dev/null
360680 +++ b/include/dt-bindings/clock/hi3516dv200-clock.h
360681 @@ -0,0 +1,89 @@
360771 diff --git a/include/dt-bindings/clock/hi3516dv300-clock.h b/include/dt-bindings/clock/hi3516dv300-…
360774 --- /dev/null
360775 +++ b/include/dt-bindings/clock/hi3516dv300-clock.h
360776 @@ -0,0 +1,100 @@
360778 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
360877 diff --git a/include/dt-bindings/clock/hi3516ev200-clock.h b/include/dt-bindings/clock/hi3516ev200-…
360880 --- /dev/null
360881 +++ b/include/dt-bindings/clock/hi3516ev200-clock.h
360882 @@ -0,0 +1,89 @@
360884 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
360972 diff --git a/include/dt-bindings/clock/hi3516ev300-clock.h b/include/dt-bindings/clock/hi3516ev300-…
360975 --- /dev/null
360976 +++ b/include/dt-bindings/clock/hi3516ev300-clock.h
360977 @@ -0,0 +1,89 @@
360979 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361067 diff --git a/include/dt-bindings/clock/hi3518ev20x-clock.h b/include/dt-bindings/clock/hi3518ev20x-…
361070 --- /dev/null
361071 +++ b/include/dt-bindings/clock/hi3518ev20x-clock.h
361072 @@ -0,0 +1,86 @@
361074 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361159 diff --git a/include/dt-bindings/clock/hi3518ev300-clock.h b/include/dt-bindings/clock/hi3518ev300-…
361162 --- /dev/null
361163 +++ b/include/dt-bindings/clock/hi3518ev300-clock.h
361164 @@ -0,0 +1,89 @@
361166 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361254 diff --git a/include/dt-bindings/clock/hi3519av100-clock.h b/include/dt-bindings/clock/hi3519av100-…
361257 --- /dev/null
361258 +++ b/include/dt-bindings/clock/hi3519av100-clock.h
361259 @@ -0,0 +1,127 @@
361387 diff --git a/include/dt-bindings/clock/hi3521a-clock.h b/include/dt-bindings/clock/hi3521a-clock.h
361390 --- /dev/null
361391 +++ b/include/dt-bindings/clock/hi3521a-clock.h
361392 @@ -0,0 +1,97 @@
361394 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361414 +#include <dt-bindings/interrupt-controller/irq.h>
361490 diff --git a/include/dt-bindings/clock/hi3521dv200-clock.h b/include/dt-bindings/clock/hi3521dv200-…
361493 --- /dev/null
361494 +++ b/include/dt-bindings/clock/hi3521dv200-clock.h
361495 @@ -0,0 +1,94 @@
361497 + * Copyright (c) 2019-2020 HiSilicon Technologies Co., Ltd.
361590 diff --git a/include/dt-bindings/clock/hi3531a-clock.h b/include/dt-bindings/clock/hi3531a-clock.h
361593 --- /dev/null
361594 +++ b/include/dt-bindings/clock/hi3531a-clock.h
361595 @@ -0,0 +1,105 @@
361597 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361617 +#include <dt-bindings/interrupt-controller/irq.h>
361701 diff --git a/include/dt-bindings/clock/hi3531dv200-clock.h b/include/dt-bindings/clock/hi3531dv200-…
361704 --- /dev/null
361705 +++ b/include/dt-bindings/clock/hi3531dv200-clock.h
361706 @@ -0,0 +1,132 @@
361708 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361839 diff --git a/include/dt-bindings/clock/hi3535av100-clock.h b/include/dt-bindings/clock/hi3535av100-…
361842 --- /dev/null
361843 +++ b/include/dt-bindings/clock/hi3535av100-clock.h
361844 @@ -0,0 +1,132 @@
361846 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
361977 diff --git a/include/dt-bindings/clock/hi3536dv100-clock.h b/include/dt-bindings/clock/hi3536dv100-…
361980 --- /dev/null
361981 +++ b/include/dt-bindings/clock/hi3536dv100-clock.h
361982 @@ -0,0 +1,82 @@
361984 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
362065 diff --git a/include/dt-bindings/clock/hi3556av100-clock.h b/include/dt-bindings/clock/hi3556av100-…
362068 --- /dev/null
362069 +++ b/include/dt-bindings/clock/hi3556av100-clock.h
362070 @@ -0,0 +1,121 @@
362192 diff --git a/include/dt-bindings/clock/hi3556v200-clock.h b/include/dt-bindings/clock/hi3556v200-cl…
362195 --- /dev/null
362196 +++ b/include/dt-bindings/clock/hi3556v200-clock.h
362197 @@ -0,0 +1,98 @@
362199 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
362296 diff --git a/include/dt-bindings/clock/hi3559av100-clock.h b/include/dt-bindings/clock/hi3559av100-…
362299 --- /dev/null
362300 +++ b/include/dt-bindings/clock/hi3559av100-clock.h
362301 @@ -0,0 +1,176 @@
362303 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
362478 diff --git a/include/dt-bindings/clock/hi3559v200-clock.h b/include/dt-bindings/clock/hi3559v200-cl…
362481 --- /dev/null
362482 +++ b/include/dt-bindings/clock/hi3559v200-clock.h
362483 @@ -0,0 +1,98 @@
362485 + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
362582 diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
362584 --- a/include/linux/blkdev.h
362586 @@ -1433,7 +1433,11 @@ extern int blk_verify_command(unsigned char *cmd, fmode_t mode);
362598 diff --git a/include/linux/cpu.h b/include/linux/cpu.h
362600 --- a/include/linux/cpu.h
362602 @@ -41,6 +41,7 @@ extern bool arch_match_cpu_phys_id(int cpu, u64 phys_id);
362610 diff --git a/include/linux/fb.h b/include/linux/fb.h
362612 --- a/include/linux/fb.h
362614 @@ -321,6 +321,12 @@ struct fb_ops {
362627 diff --git a/include/linux/hi_cma.h b/include/linux/hi_cma.h
362630 --- /dev/null
362632 @@ -0,0 +1,54 @@
362655 +#include <linux/dma-mapping.h>
362656 +#include <linux/dma-contiguous.h>
362687 diff --git a/include/linux/hiedmac.h b/include/linux/hiedmac.h
362690 --- /dev/null
362692 @@ -0,0 +1,65 @@
362758 diff --git a/include/linux/i2c.h b/include/linux/i2c.h
362760 --- a/include/linux/i2c.h
362762 @@ -131,6 +131,23 @@ static inline int i2c_master_send_dmasafe(const struct i2c_client *client,
362786 diff --git a/include/linux/mfd/hisi_fmc.h b/include/linux/mfd/hisi_fmc.h
362789 --- /dev/null
362791 @@ -0,0 +1,477 @@
363150 + ((host->addr_value[0] >> 16) | (host->addr_value[1] << 16))
363156 + (readl((char *)_host->regbase + (_reg)))
363165 + (writel((u_int)(_value), ((char *)_host->regbase + (_reg))))
363177 + --timeout; \
363188 + --timeout; \
363199 + --timeout; \
363212 +#define AC_DBG 0 /* 3-4byte Address Cycle */
363269 diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
363271 --- a/include/linux/mmc/host.h
363273 @@ -168,6 +168,7 @@ struct mmc_host_ops {
363281 @@ -276,6 +277,12 @@ struct mmc_host {
363292 u32 ocr_avail_sdio; /* SDIO-specific OCR */
363293 u32 ocr_avail_sd; /* SD-specific OCR */
363294 @@ -417,6 +424,11 @@ struct mmc_host {
363306 diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
363308 --- a/include/linux/mtd/mtd.h
363310 @@ -30,6 +30,12 @@
363320 #define MTD_FAIL_ADDR_UNKNOWN -1LL
363323 @@ -40,9 +46,18 @@ struct mtd_info;
363342 @@ -67,11 +82,9 @@ struct mtd_erase_region_info {
363343 * @datbuf: data buffer - if NULL only oob data are read/written
363346 - * Note, some MTD drivers do not allow you to write more than one OOB area at
363347 - * one go. If you try to do that on such an MTD device, -EINVAL will be
363348 - * returned. If you want to make your implementation portable on all kind of MTD
363349 - * devices you should split the write request into several sub-requests when the
363350 - * request crosses a page boundary.
363357 @@ -286,6 +299,10 @@ struct mtd_info {
363368 @@ -328,6 +345,11 @@ struct mtd_info {
363373 + * - provides mmap capabilities
363380 @@ -377,13 +399,11 @@ static inline void mtd_set_of_node(struct mtd_info *mtd,
363383 mtd->dev.of_node = np;
363384 - if (!mtd->name)
363385 - of_property_read_string(np, "label", &mtd->name);
363390 - return dev_of_node(&mtd->dev);
363391 + return mtd->dev.of_node;
363395 @@ -478,34 +498,6 @@ static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
363396 return do_div(sz, mtd->erasesize);
363399 -/**
363400 - * mtd_align_erase_req - Adjust an erase request to align things on eraseblock
363401 - * boundaries.
363402 - * @mtd: the MTD device this erase request applies on
363403 - * @req: the erase request to adjust
363404 - *
363405 - * This function will adjust @req->addr and @req->len to align them on
363406 - * @mtd->erasesize. Of course we expect @mtd->erasesize to be != 0.
363407 - */
363408 -static inline void mtd_align_erase_req(struct mtd_info *mtd,
363409 - struct erase_info *req)
363410 -{
363411 - u32 mod;
363412 -
363413 - if (WARN_ON(!mtd->erasesize))
363414 - return;
363415 -
363416 - mod = mtd_mod_by_eb(req->addr, mtd);
363417 - if (mod) {
363418 - req->addr -= mod;
363419 - req->len += mod;
363420 - }
363421 -
363422 - mod = mtd_mod_by_eb(req->addr + req->len, mtd);
363423 - if (mod)
363424 - req->len += mtd->erasesize - mod;
363425 -}
363426 -
363429 if (mtd->writesize_shift)
363430 @@ -584,6 +576,8 @@ extern void register_mtd_user (struct mtd_notifier *new);
363437 return err == -EUCLEAN;
363439 diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
363441 --- a/include/linux/mtd/rawnand.h
363443 @@ -1435,10 +1435,18 @@ static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
363455 -#define NAND_MFR_WINBOND 0xef
363463 @@ -1541,7 +1549,6 @@ nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
363467 -
363471 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
363473 --- a/include/linux/mtd/spi-nor.h
363474 +++ b/include/linux/mtd/spi-nor.h
363475 @@ -29,6 +29,43 @@
363512 +#define LOCK_LEVEL_MAX(bp_num) (((0x01) << bp_num) - 1)
363519 @@ -108,6 +145,17 @@
363525 +#define SPINOR_OP_RDSR3 0x15 /* Read Status Register-3 */
363526 +#define SPINOR_OP_WRSR3 0x11 /* Write Status Register-3 1 byte*/
363537 @@ -173,6 +221,23 @@
363561 @@ -314,6 +379,15 @@ struct spi_nor {
363577 @@ -403,6 +477,13 @@ struct spi_nor_hwcaps {
363591 diff --git a/include/linux/netdev_features.h b/include/linux/netdev_features.h
363593 --- a/include/linux/netdev_features.h
363595 @@ -35,6 +35,7 @@ enum {
363603 @@ -128,6 +129,7 @@ enum {
363611 @@ -205,7 +207,7 @@ static inline int find_next_netdev_feature(u64 feature, unsigned long start)
363615 -#define NETIF_F_GSO_SOFTWARE (NETIF_F_ALL_TSO | \
363620 diff --git a/include/linux/phy.h b/include/linux/phy.h
363622 --- a/include/linux/phy.h
363624 @@ -1043,6 +1043,7 @@ void phy_start_machine(struct phy_device *phydev);
363632 diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
363634 --- a/include/linux/skbuff.h
363636 @@ -502,6 +502,7 @@ struct skb_shared_info {
363644 diff --git a/include/linux/sunrpc/xprt.h b/include/linux/sunrpc/xprt.h
363646 --- a/include/linux/sunrpc/xprt.h
363648 @@ -149,6 +149,7 @@ struct rpc_xprt_ops {
363656 diff --git a/include/linux/types.h b/include/linux/types.h
363658 --- a/include/linux/types.h
363660 @@ -230,5 +230,8 @@ struct callback_head {
363669 diff --git a/include/net/addrconf.h b/include/net/addrconf.h
363671 --- a/include/net/addrconf.h
363673 @@ -227,49 +227,6 @@ bool ipv6_chk_mcast_addr(struct net_device *dev, const struct in6_addr *group,
363677 -/* A stub used by vxlan module. This is ugly, ideally these
363678 - * symbols should be built into the core kernel.
363679 - */
363680 -struct ipv6_stub {
363681 - int (*ipv6_sock_mc_join)(struct sock *sk, int ifindex,
363682 - const struct in6_addr *addr);
363683 - int (*ipv6_sock_mc_drop)(struct sock *sk, int ifindex,
363684 - const struct in6_addr *addr);
363685 - struct dst_entry *(*ipv6_dst_lookup_flow)(struct net *net,
363686 - const struct sock *sk,
363687 - struct flowi6 *fl6,
363688 - const struct in6_addr *final_dst);
363689 -
363690 - struct fib6_table *(*fib6_get_table)(struct net *net, u32 id);
363691 - struct fib6_info *(*fib6_lookup)(struct net *net, int oif,
363692 - struct flowi6 *fl6, int flags);
363693 - struct fib6_info *(*fib6_table_lookup)(struct net *net,
363694 - struct fib6_table *table,
363695 - int oif, struct flowi6 *fl6,
363696 - int flags);
363697 - struct fib6_info *(*fib6_multipath_select)(const struct net *net,
363698 - struct fib6_info *f6i,
363699 - struct flowi6 *fl6, int oif,
363700 - const struct sk_buff *skb,
363701 - int strict);
363702 - u32 (*ip6_mtu_from_fib6)(struct fib6_info *f6i, struct in6_addr *daddr,
363703 - struct in6_addr *saddr);
363704 -
363705 - void (*udpv6_encap_enable)(void);
363706 - void (*ndisc_send_na)(struct net_device *dev, const struct in6_addr *daddr,
363707 - const struct in6_addr *solicited_addr,
363708 - bool router, bool solicited, bool override, bool inc_opt);
363709 - struct neigh_table *nd_tbl;
363710 -};
363711 -extern const struct ipv6_stub *ipv6_stub __read_mostly;
363712 -
363713 -/* A stub used by bpf helpers. Similarly ugly as ipv6_stub */
363714 -struct ipv6_bpf_stub {
363715 - int (*inet6_bind)(struct sock *sk, struct sockaddr *uaddr, int addr_len,
363716 - bool force_bind_address_no_port, bool with_lock);
363717 -};
363718 -extern const struct ipv6_bpf_stub *ipv6_bpf_stub __read_mostly;
363719 -
363723 diff --git a/include/net/ipv6_stubs.h b/include/net/ipv6_stubs.h
363726 --- /dev/null
363728 @@ -0,0 +1,60 @@
363729 +/* SPDX-License-Identifier: GPL-2.0 */
363789 diff --git a/include/net/udp_tunnel.h b/include/net/udp_tunnel.h
363791 --- a/include/net/udp_tunnel.h
363793 @@ -7,7 +7,7 @@
363797 -#include <net/addrconf.h>
363802 diff --git a/include/uapi/linux/i2c-dev.h b/include/uapi/linux/i2c-dev.h
363804 --- a/include/uapi/linux/i2c-dev.h
363805 +++ b/include/uapi/linux/i2c-dev.h
363806 @@ -52,6 +52,8 @@
363815 diff --git a/include/uapi/linux/i2c.h b/include/uapi/linux/i2c.h
363817 --- a/include/uapi/linux/i2c.h
363819 @@ -22,7 +22,7 @@
363820 MA 02110-1301 USA. */
363821 /* ------------------------------------------------------------------------- */
363823 -/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and
363828 @@ -81,8 +81,14 @@ struct i2c_msg {
363832 +#define I2C_M_16BIT_REG 0x0002 /* indicate reg bit-width is 16bit */
363833 +#define I2C_M_16BIT_DATA 0x0008 /* indicate data bit-width is 16bit */
363843 diff --git a/include/uapi/linux/msdos_fs.h b/include/uapi/linux/msdos_fs.h
363845 --- a/include/uapi/linux/msdos_fs.h
363847 @@ -98,7 +98,23 @@ struct __fat_dirent {
363871 @@ -109,7 +125,9 @@ struct __fat_dirent {
363875 -
363881 __u8 system_id[8]; /* Name - can be used to special case
363882 diff --git a/include/uapi/linux/usb/g_uvc.h b/include/uapi/linux/usb/g_uvc.h
363884 --- a/include/uapi/linux/usb/g_uvc.h
363886 @@ -12,6 +12,7 @@
363894 diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h
363896 --- a/include/uapi/linux/usb/video.h
363898 @@ -304,7 +304,7 @@ struct uvc_processing_unit_descriptor {
363902 -#define UVC_DT_PROCESSING_UNIT_SIZE(n) (9+(n))
363907 @@ -341,6 +341,8 @@ struct UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) { \
363916 @@ -566,5 +568,64 @@ struct UVC_FRAME_MJPEG(n) { \
363981 diff --git a/init/main.c b/init/main.c
363983 --- a/init/main.c
363985 @@ -526,7 +526,33 @@ static void __init mm_init(void)
364011 + child_node->sibling = child_node->sibling->sibling;
364019 @@ -578,6 +604,9 @@ asmlinkage __visible void __init start_kernel(void)
364020 parse_args("Setting init args", after_dashes, NULL, 0, -1, -1,
364029 diff --git a/kernel/cpu.c b/kernel/cpu.c
364031 --- a/kernel/cpu.c
364033 @@ -325,6 +325,19 @@ void lockdep_assert_cpus_held(void)
364053 diff --git a/kernel/dma/contiguous.c b/kernel/dma/contiguous.c
364055 --- a/kernel/dma/contiguous.c
364057 @@ -104,6 +104,11 @@ static inline __maybe_unused phys_addr_t cma_early_percent_memory(void)
364069 @@ -113,6 +118,11 @@ void __init dma_contiguous_reserve(phys_addr_t limit)
364078 if (size_cmdline != -1) {
364081 @@ -197,6 +207,7 @@ struct page *dma_alloc_from_contiguous(struct device *dev, size_t count,
364088 * dma_release_from_contiguous() - release allocated pages
364089 @@ -213,6 +224,12 @@ bool dma_release_from_contiguous(struct device *dev, struct page *pages,
364102 diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
364104 --- a/kernel/printk/printk.c
364106 @@ -1397,7 +1397,7 @@ static int syslog_print_all(char __user *buf, int size, bool clear)
364110 - text = kmalloc(LOG_LINE_MAX + PREFIX_MAX, GFP_KERNEL);
364113 return -ENOMEM;
364115 diff --git a/kernel/relay.c b/kernel/relay.c
364117 --- a/kernel/relay.c
364119 @@ -581,7 +581,8 @@ struct rchan *relay_open(const char *base_filename,
364123 - chan->buf = alloc_percpu(struct rchan_buf *);
364124 + chan->buf = alloc_percpu_gfp(struct rchan_buf *,
364126 if (!chan->buf) {
364129 diff --git a/mm/init-mm.c b/mm/init-mm.c
364131 --- a/mm/init-mm.c
364132 +++ b/mm/init-mm.c
364133 @@ -38,3 +38,4 @@ struct mm_struct init_mm = {
364138 diff --git a/mm/madvise.c b/mm/madvise.c
364140 --- a/mm/madvise.c
364142 @@ -24,6 +24,7 @@
364150 @@ -836,6 +837,23 @@ SYSCALL_DEFINE3(madvise, unsigned long, start, size_t, len_in, int, behavior)
364152 if (down_write_killable(¤t->mm->mmap_sem))
364153 return -EINTR;
364167 + if (!mmget_still_valid(current->mm)) {
364168 + up_write(¤t->mm->mmap_sem);
364169 + return -EINTR;
364172 down_read(¤t->mm->mmap_sem);
364174 diff --git a/mm/mincore.c b/mm/mincore.c
364176 --- a/mm/mincore.c
364178 @@ -42,72 +42,14 @@ static int mincore_hugetlb(pte_t *pte, unsigned long hmask, unsigned long addr,
364182 -/*
364183 - * Later we can get more picky about what "in core" means precisely.
364184 - * For now, simply check to see if the page is in the page cache,
364185 - * and is up to date; i.e. that no page-in operation would be required
364186 - * at this time if an application were to map and access this page.
364187 - */
364188 -static unsigned char mincore_page(struct address_space *mapping, pgoff_t pgoff)
364189 -{
364190 - unsigned char present = 0;
364191 - struct page *page;
364192 -
364193 - /*
364194 - * When tmpfs swaps out a page from a file, any process mapping that
364195 - * file will not get a swp_entry_t in its pte, but rather it is like
364196 - * any other file mapping (ie. marked !present and faulted in with
364197 - * tmpfs's .fault). So swapped out tmpfs mappings are tested here.
364198 - */
364199 -#ifdef CONFIG_SWAP
364200 - if (shmem_mapping(mapping)) {
364201 - page = find_get_entry(mapping, pgoff);
364202 - /*
364203 - * shmem/tmpfs may return swap: account for swapcache
364204 - * page too.
364205 - */
364206 - if (radix_tree_exceptional_entry(page)) {
364207 - swp_entry_t swp = radix_to_swp_entry(page);
364208 - page = find_get_page(swap_address_space(swp),
364209 - swp_offset(swp));
364210 - }
364211 - } else
364212 - page = find_get_page(mapping, pgoff);
364213 -#else
364214 - page = find_get_page(mapping, pgoff);
364215 -#endif
364216 - if (page) {
364217 - present = PageUptodate(page);
364218 - put_page(page);
364219 - }
364220 -
364221 - return present;
364222 -}
364223 -
364224 -static int __mincore_unmapped_range(unsigned long addr, unsigned long end,
364225 - struct vm_area_struct *vma, unsigned char *vec)
364226 -{
364227 - unsigned long nr = (end - addr) >> PAGE_SHIFT;
364228 - int i;
364229 -
364230 - if (vma->vm_file) {
364231 - pgoff_t pgoff;
364232 -
364233 - pgoff = linear_page_index(vma, addr);
364234 - for (i = 0; i < nr; i++, pgoff++)
364235 - vec[i] = mincore_page(vma->vm_file->f_mapping, pgoff);
364236 - } else {
364237 - for (i = 0; i < nr; i++)
364238 - vec[i] = 0;
364239 - }
364240 - return nr;
364241 -}
364242 -
364246 - walk->private += __mincore_unmapped_range(addr, end,
364247 - walk->vma, walk->private);
364248 + unsigned char *vec = walk->private;
364249 + unsigned long nr = (end - addr) >> PAGE_SHIFT;
364252 + walk->private += nr;
364256 @@ -127,8 +69,9 @@ static int mincore_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end,
364262 - __mincore_unmapped_range(addr, end, vma, vec);
364267 @@ -137,28 +80,17 @@ static int mincore_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end,
364271 - __mincore_unmapped_range(addr, addr + PAGE_SIZE,
364272 - vma, vec);
364279 - if (non_swap_entry(entry)) {
364280 - /*
364281 - * migration or hwpoison entries are always
364282 - * uptodate
364283 - */
364284 - *vec = 1;
364285 - } else {
364286 -#ifdef CONFIG_SWAP
364287 - *vec = mincore_page(swap_address_space(entry),
364288 - swp_offset(entry));
364289 -#else
364290 - WARN_ON(1);
364291 - *vec = 1;
364292 -#endif
364293 - }
364302 diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
364304 --- a/net/bluetooth/hci_event.c
364306 @@ -5261,7 +5261,8 @@ static void process_adv_report(struct hci_dev *hdev, u8 type, bdaddr_t *bdadd…
364310 - if (type == LE_ADV_IND || type == LE_ADV_SCAN_IND) {
364316 diff --git a/net/bridge/br_arp_nd_proxy.c b/net/bridge/br_arp_nd_proxy.c
364318 --- a/net/bridge/br_arp_nd_proxy.c
364320 @@ -21,6 +21,7 @@
364328 diff --git a/net/core/ethtool.c b/net/core/ethtool.c
364330 --- a/net/core/ethtool.c
364332 @@ -78,6 +78,7 @@ static const char netdev_features_strings[NETDEV_FEATURE_COUNT][ETH_GSTRING_LEN]
364333 [NETIF_F_LRO_BIT] = "rx-lro",
364335 [NETIF_F_TSO_BIT] = "tx-tcp-segmentation",
364336 + [NETIF_F_UFO_BIT] = "tx-udp-fragmentation",
364337 [NETIF_F_GSO_ROBUST_BIT] = "tx-gso-robust",
364338 [NETIF_F_TSO_ECN_BIT] = "tx-tcp-ecn-segmentation",
364339 [NETIF_F_TSO_MANGLEID_BIT] = "tx-tcp-mangleid-segmentation",
364340 @@ -279,6 +280,9 @@ static netdev_features_t ethtool_get_feature_mask(u32 eth_cmd)
364350 @@ -2836,6 +2840,7 @@ int dev_ethtool(struct net *net, struct ifreq *ifr)
364358 @@ -2844,6 +2849,7 @@ int dev_ethtool(struct net *net, struct ifreq *ifr)
364366 diff --git a/net/core/filter.c b/net/core/filter.c
364368 --- a/net/core/filter.c
364370 @@ -68,6 +68,7 @@
364377 * sk_filter_trim_cap - run a packet through a socket filter
364378 diff --git a/net/core/lwt_bpf.c b/net/core/lwt_bpf.c
364380 --- a/net/core/lwt_bpf.c
364382 @@ -16,6 +16,7 @@
364390 diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
364392 --- a/net/ipv4/tcp_output.c
364394 @@ -1303,6 +1303,11 @@ int tcp_fragment(struct sock *sk, enum tcp_queue tcp_queue,
364395 return -ENOMEM;
364398 + if (unlikely((sk->sk_wmem_queued >> 1) > sk->sk_sndbuf)) {
364400 + return -ENOMEM;
364404 return -ENOMEM;
364406 diff --git a/net/ipv6/addrconf_core.c b/net/ipv6/addrconf_core.c
364408 --- a/net/ipv6/addrconf_core.c
364410 @@ -5,7 +5,7 @@
364414 -#include <net/addrconf.h>
364419 diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c
364421 --- a/net/ipv6/af_inet6.c
364423 @@ -56,6 +56,7 @@
364431 diff --git a/net/ipv6/fib6_rules.c b/net/ipv6/fib6_rules.c
364433 --- a/net/ipv6/fib6_rules.c
364435 @@ -287,7 +287,8 @@ static bool fib6_rule_suppress(struct fib_rule *rule, struct fib_lookup_arg *arg
364439 - ip6_rt_put(rt);
364440 + if (!(arg->flags & FIB_LOOKUP_NOREF))
364445 diff --git a/net/sunrpc/auth_gss/gss_mech_switch.c b/net/sunrpc/auth_gss/gss_mech_switch.c
364447 --- a/net/sunrpc/auth_gss/gss_mech_switch.c
364449 @@ -58,11 +58,14 @@ gss_mech_free(struct gss_api_mech *gm)
364455 for (i = 0; i < gm->gm_pf_num; i++) {
364456 pf = &gm->gm_pfs[i];
364457 - if (pf->domain)
364458 - auth_domain_put(pf->domain);
364459 + test = auth_domain_find(pf->auth_domain_name);
364461 + test->flavour->domain_release(test);
364463 kfree(pf->auth_domain_name);
364464 pf->auth_domain_name = NULL;
364466 diff --git a/net/sunrpc/svc.c b/net/sunrpc/svc.c
364468 --- a/net/sunrpc/svc.c
364470 @@ -1453,15 +1453,22 @@ int
364474 + struct net *net = req->rq_xprt->xprt_net;
364475 struct kvec *argv = &rqstp->rq_arg.head[0];
364476 struct kvec *resv = &rqstp->rq_res.head[0];
364484 + s_xprt = req->rq_xprt->ops->bc_get_xprt(serv, net);
364489 + rqstp->rq_xprt = s_xprt;
364490 rqstp->rq_xid = req->rq_xid;
364491 rqstp->rq_prot = req->rq_xprt->prot;
364492 rqstp->rq_server = serv;
364493 @@ -1497,13 +1504,11 @@ bc_svc_process(struct svc_serv *serv, struct rpc_rqst *req,
364497 + svc_xprt_put(rqstp->rq_xprt);
364499 atomic_inc(&req->rq_xprt->bc_free_slots);
364500 - if (!proc_error) {
364501 - /* Processing error: drop the request */
364502 - xprt_free_bc_request(req);
364503 - return 0;
364504 - }
364509 memcpy(&req->rq_snd_buf, &rqstp->rq_res, sizeof(req->rq_snd_buf));
364510 @@ -1520,6 +1525,12 @@ bc_svc_process(struct svc_serv *serv, struct rpc_rqst *req,
364518 + error = -EINVAL;
364523 diff --git a/net/sunrpc/xprtrdma/backchannel.c b/net/sunrpc/xprtrdma/backchannel.c
364525 --- a/net/sunrpc/xprtrdma/backchannel.c
364527 @@ -134,6 +134,11 @@ int xprt_rdma_bc_up(struct svc_serv *serv, struct net *net)
364533 + return svc_find_xprt(serv, "rdma-bc", net, AF_UNSPEC, 0);
364537 * xprt_rdma_bc_maxpayload - Return maximum backchannel message size
364539 diff --git a/net/sunrpc/xprtrdma/transport.c b/net/sunrpc/xprtrdma/transport.c
364541 --- a/net/sunrpc/xprtrdma/transport.c
364543 @@ -842,6 +842,7 @@ static const struct rpc_xprt_ops xprt_rdma_procs = {
364551 diff --git a/net/sunrpc/xprtrdma/xprt_rdma.h b/net/sunrpc/xprtrdma/xprt_rdma.h
364553 --- a/net/sunrpc/xprtrdma/xprt_rdma.h
364555 @@ -662,6 +662,7 @@ void xprt_rdma_cleanup(void);
364563 diff --git a/net/sunrpc/xprtsock.c b/net/sunrpc/xprtsock.c
364565 --- a/net/sunrpc/xprtsock.c
364567 @@ -1431,6 +1431,12 @@ static int xs_tcp_bc_up(struct svc_serv *serv, struct net *net)
364574 + return svc_find_xprt(serv, "tcp-bc", net, AF_UNSPEC, 0);
364580 @@ -2831,6 +2837,7 @@ static const struct rpc_xprt_ops xs_tcp_ops = {
364588 diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
364590 --- a/net/wireless/nl80211.c
364592 @@ -1649,7 +1649,7 @@ static int nl80211_send_wiphy(struct cfg80211_registered_device *rdev,
364596 - return -ENOBUFS;
364600 return -EINVAL;
364601 diff --git a/net/wireless/wext-sme.c b/net/wireless/wext-sme.c
364603 --- a/net/wireless/wext-sme.c
364604 +++ b/net/wireless/wext-sme.c
364605 @@ -201,8 +201,8 @@ int cfg80211_mgd_wext_giwessid(struct net_device *dev,
364609 - struct wireless_dev *wdev = dev->ieee80211_ptr;
364611 + struct wireless_dev *wdev = dev->ieee80211_ptr;
364614 if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION))
364615 diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
364617 --- a/scripts/Makefile.lib
364619 @@ -164,7 +164,9 @@ cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \
364621 ld_flags = $(KBUILD_LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F))
364623 -DTC_INCLUDE := $(srctree)/scripts/dtc/include-prefixes
364624 +DTC_INCLUDE := $(srctree)/scripts/dtc/include-prefixes \
364626 + $(srctree)/include/dt-bindings
364628 dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
364629 $(addprefix -I,$(DTC_INCLUDE)) \
364630 diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
364632 --- a/scripts/dtc/checks.c
364634 @@ -790,8 +790,8 @@ static void check_pci_bridge(struct check *c, struct dt_info *dti, struct node *
364636 node->bus = &pci_bus;
364638 - if (!strprefixeq(node->name, node->basenamelen, "pci") &&
364639 - !strprefixeq(node->name, node->basenamelen, "pcie"))
364640 + if (!strprefixeq(node->name, 3, "pci") &&
364641 + !strprefixeq(node->name, 4, "pcie"))
364645 diff --git a/sound/core/control.c b/sound/core/control.c
364647 --- a/sound/core/control.c
364649 @@ -1288,7 +1288,7 @@ static int snd_ctl_elem_add(struct snd_ctl_file *file,
364650 return -ENOMEM;
364653 - count = info->owner;
364654 + count = info->count;
364658 diff --git a/tools/testing/selftests/net/fib_tests.sh b/tools/testing/selftests/net/fib_tests.sh
364660 --- a/tools/testing/selftests/net/fib_tests.sh
364662 @@ -9,7 +9,7 @@ ret=0
364665 # all tests in this script. Can be overridden with -t option
364666 -TESTS="unregister down carrier nexthop ipv6_rt ipv4_rt ipv6_addr_metric ipv4_addr_metric"
364671 @@ -577,6 +577,20 @@ fib_nexthop_test()
364679 + $IP -6 route add default dev dummy1
364680 + $IP -6 rule add table main suppress_prefixlength 0
364681 + ping -f -c 1000 -W 1 1234::1 || true
364682 + $IP -6 rule del table main suppress_prefixlength 0
364692 @@ -1423,6 +1437,7 @@ do