Lines Matching refs:assigned
273 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
274 assigned-clock-rates = <24000000>;
289 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
290 assigned-clock-rates = <24000000>;
304 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
305 assigned-clock-rates = <24000000>;
320 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
321 assigned-clock-rates = <24000000>;
423 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
424 assigned-clock-rates = <80000000>;
436 assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
437 assigned-clock-rates = <80000000>;
449 assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
450 assigned-clock-rates = <80000000>;
462 assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
463 assigned-clock-rates = <80000000>;
477 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
478 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
479 assigned-clock-rates = <0>, <400000000>;
495 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
496 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
497 assigned-clock-rates = <0>, <200000000>;
513 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
514 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
515 assigned-clock-rates = <0>, <200000000>;
530 assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
531 assigned-clock-rates = <125000000>, <125000000>;
548 assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
549 assigned-clock-rates = <125000000>, <125000000>;