Lines Matching refs:assigned
76 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
78 assigned-clock-parents = <&clks IMX7D_CKIL>;
79 assigned-clock-rates = <0>, <32768>;
92 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
94 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
95 assigned-clock-rates = <0>, <100000000>;
237 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
239 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
240 assigned-clock-rates = <0>, <24576000>;
270 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
271 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
278 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
287 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
288 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
336 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
337 assigned-clock-rates = <400000000>;