Lines Matching refs:clks
78 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
83 &clks {
84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
208 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
225 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
226 <&clks IMX7D_SAI1_ROOT_CLK>;
227 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
235 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
236 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
243 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
244 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
252 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
253 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
279 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;