Lines Matching refs:assigned

214 			assigned-clock-rates = <48000000>;
215 			assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
216 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
225 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
226 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
227 			assigned-clock-rates = <48000000>;
237 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C5>;
238 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
239 			assigned-clock-rates = <48000000>;
249 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
250 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
251 			assigned-clock-rates = <48000000>;
261 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
262 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
263 			assigned-clock-rates = <48000000>;
273 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART4>;
274 			assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>;
275 			assigned-clock-rates = <24000000>;
285 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART5>;
286 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
287 			assigned-clock-rates = <48000000>;
356 			assigned-clocks = <&clks IMX7ULP_CLK_WDG1>;
357 			assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
371 			assigned-clocks = <&clks IMX7ULP_CLK_WDG2>;
372 			assigned-clocks-parents = <&clks IMX7ULP_CLK_FIRC>;
384 			assigned-clocks = <&clks IMX7ULP_CLK_LPTPM5>,
386 			assigned-clock-parents = <&clks IMX7ULP_CLK_OSC>,
420 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C6>;
421 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
422 			assigned-clock-rates = <48000000>;
432 			assigned-clocks = <&clks IMX7ULP_CLK_LPI2C7>;
433 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
434 			assigned-clock-rates = <48000000>;
444 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART6>;
445 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
446 			assigned-clock-rates = <48000000>;
458 			assigned-clocks = <&clks IMX7ULP_CLK_LPUART7>;
459 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
460 			assigned-clock-rates = <50000000>;