Lines Matching refs:clocks
15 clocks {
46 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
55 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
76 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
85 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
115 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
136 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
144 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
165 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
174 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
189 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
198 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
214 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
236 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
252 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
266 clocks = <&rcc 1 CLK_RTC>;
268 assigned-clocks = <&rcc 1 CLK_RTC>;
281 clocks = <&rcc 1 CLK_USART2>;
289 clocks = <&rcc 1 CLK_USART3>;
297 clocks = <&rcc 1 CLK_UART4>;
305 clocks = <&rcc 1 CLK_UART5>;
315 clocks = <&rcc 1 CLK_I2C1>;
327 clocks = <&rcc 1 CLK_I2C2>;
339 clocks = <&rcc 1 CLK_I2C3>;
351 clocks = <&rcc 1 CLK_I2C4>;
361 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
370 clocks = <&rcc 1 CLK_UART7>;
378 clocks = <&rcc 1 CLK_UART8>;
387 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
409 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
430 clocks = <&rcc 1 CLK_USART1>;
438 clocks = <&rcc 1 CLK_USART6>;
446 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
457 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
482 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
504 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
520 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
539 clocks = <&rcc 0 12>;
548 clocks = <&clk_hse>, <&clk_i2s_ckin>;
550 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
565 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
581 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
591 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
603 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
611 clocks = <&rcc 1 0>;