22 		reg = readl(&scg1_regs->sosccsr);  in scg_src_get_rate()
28 		reg = readl(&scg1_regs->firccsr);  in scg_src_get_rate()
34 		reg = readl(&scg1_regs->sirccsr);  in scg_src_get_rate()
40 		reg = readl(&scg1_regs->rtccsr);  in scg_src_get_rate()
74 	reg = readl(&scg1_regs->sirccsr);  in scg_sircdiv_get_rate()
78 	reg = readl(&scg1_regs->sircdiv);  in scg_sircdiv_get_rate()
112 	reg = readl(&scg1_regs->firccsr);  in scg_fircdiv_get_rate()
116 	reg = readl(&scg1_regs->fircdiv);  in scg_fircdiv_get_rate()
150 	reg = readl(&scg1_regs->sosccsr);  in scg_soscdiv_get_rate()
154 	reg = readl(&scg1_regs->soscdiv);  in scg_soscdiv_get_rate()
200 	reg = readl(&scg1_regs->apllpfd);  in scg_apll_pfd_get_rate()
250 	reg = readl(&scg1_regs->spllpfd);  in scg_spll_pfd_get_rate()
270 	reg = readl(&scg1_regs->apllcfg);  in scg_apll_get_rate()
298 	reg = readl(&scg1_regs->spllcfg);  in scg_spll_get_rate()
333 	reg = readl(&scg1_regs->ddrccr);  in scg_ddr_get_rate()
341 		reg = readl(&scg1_regs->apllcfg);  in scg_ddr_get_rate()
358 	reg = readl(&scg1_regs->niccsr);  in scg_nic_get_rate()
441 	reg = readl(&scg1_regs->csr);  in scg_sys_get_rate()
488 		reg = readl(&scg1_regs->spllcsr);  in decode_pll()
493 		reg = readl(&scg1_regs->spllcfg);  in decode_pll()
509 		num = readl(&scg1_regs->spllnum);  in decode_pll()
510 		denom = readl(&scg1_regs->splldenom);  in decode_pll()
520 		reg = readl(&scg1_regs->apllcsr);  in decode_pll()
525 		reg = readl(&scg1_regs->apllcfg);  in decode_pll()
541 		num = readl(&scg1_regs->apllnum);  in decode_pll()
542 		denom = readl(&scg1_regs->aplldenom);  in decode_pll()
552 		reg = readl(&scg1_regs->upllcsr);  in decode_pll()
692 	reg = readl(addr);  in scg_enable_pll_pfd()
710 		reg = readl(addr);  in scg_enable_pll_pfd()
730 	reg = readl(SIM0_RBASE + 0x3C);  in scg_enable_usb_pll()
737 	if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {  in scg_enable_usb_pll()
770 			if (readl(&usbphy->usb1_pll_480_ctrl) &  in scg_enable_usb_pll()
792 			if (readl(&scg1_regs->upllcsr) &  in scg_enable_usb_pll()
798 			reg = readl(SIM0_RBASE + 0x3C);  in scg_enable_usb_pll()
824 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_rccr_init()
866 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
880 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
893 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
898 	while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))  in scg_a7_spll_init()
902 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
908 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
913 	while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_spll_init()
963 	while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))  in scg_a7_firc_init()
1005 	while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))  in scg_a7_soscdiv_init()
1028 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_sys_clk_sel()
1036 	debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));  in scg_a7_info()
1037 	debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));  in scg_a7_info()
1038 	debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));  in scg_a7_info()
1039 	debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));  in scg_a7_info()
1052 		if ((readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK)) {  in scg_a7_init_core_clk()
1053 			val = readl(&scg1_regs->rccr);  in scg_a7_init_core_clk()
1059 			val = readl(&scg1_regs->spllcfg);  in scg_a7_init_core_clk()
1070 			val = readl(&scg1_regs->spllcfg);  in scg_a7_init_core_clk()
1075 			val = readl(&scg1_regs->rccr);  in scg_a7_init_core_clk()