Lines Matching refs:BIT
85 #define CPM_CPCSR_H2DIV_BUSY BIT(2)
86 #define CPM_CPCSR_H0DIV_BUSY BIT(1)
87 #define CPM_CPCSR_CDIV_BUSY BIT(0)
100 #define CPM_CPXPCR_XLOCK BIT(6)
101 #define CPM_CPXPCR_XPLL_ON BIT(4)
102 #define CPM_CPXPCR_XF_MODE BIT(3)
103 #define CPM_CPXPCR_XPLLBP BIT(1)
104 #define CPM_CPXPCR_XPLLEN BIT(0)
111 #define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/
112 #define CPM_USBPCR_AVLD_REG BIT(30)
115 #define CPM_USBPCR_INCR_MASK BIT(27)
116 #define CPM_USBPCR_CLK12_EN BIT(26)
117 #define CPM_USBPCR_COMMONONN BIT(25)
118 #define CPM_USBPCR_VBUSVLDEXT BIT(24)
119 #define CPM_USBPCR_VBUSVLDEXTSEL BIT(23)
120 #define CPM_USBPCR_POR BIT(22)
121 #define CPM_USBPCR_SIDDQ BIT(21)
122 #define CPM_USBPCR_OTG_DISABLE BIT(20)
131 #define CPM_USBPCR_TXPREEMPHTUNE BIT(6)
143 #define CPM_DDRCDR_CE_DDR BIT(29)
144 #define CPM_DDRCDR_DDR_BUSY BIT(28)
145 #define CPM_DDRCDR_DDR_STOP BIT(27)
150 #define CPM_USBRDT_VBFIL_LD_EN BIT(25)
151 #define CPM_USBRDT_IDDIG_EN BIT(24)
152 #define CPM_USBRDT_IDDIG_REG BIT(23)
157 #define CPM_USBCDR_UCS BIT(31)
158 #define CPM_USBCDR_UPCS BIT(30)
159 #define CPM_USBCDR_CEUSB BIT(29)
160 #define CPM_USBCDR_USB_BUSY BIT(28)
165 #define CPM_I2SCDR_I2CS BIT(31)
166 #define CPM_I2SCDR_I2PCS BIT(30)
173 #define CPM_LPCDR_CELCD BIT(28)
174 #define CPM_LPCDR_LCD_BUSY BIT(27)
175 #define CPM_LPCDR_LCD_STOP BIT(26)
185 #define CPM_MSCCDR_CE BIT(29)
186 #define CPM_MSCCDR_MSC_BUSY BIT(28)
187 #define CPM_MSCCDR_MSC_STOP BIT(27)
188 #define CPM_MSCCDR_MSC_CLK0_SEL BIT(15)
199 #define CPM_UHCCDR_CE_UHC BIT(29)
200 #define CPM_UHCCDR_UHC_BUSY BIT(28)
201 #define CPM_UHCCDR_UHC_STOP BIT(27)
206 #define CPM_SSICDR_SCS BIT(31)
215 #define CPM_GPSCDR_GPCS BIT(31)
220 #define CPM_PCMCDR_PCMS BIT(31)
221 #define CPM_PCMCDR_PCMPCS BIT(30)
226 #define CPM_GPUCDR_GPCS BIT(31)
233 #define CPM_HDMICDR_CEHDMI BIT(29)
234 #define CPM_HDMICDR_HDMI_BUSY BIT(28)
235 #define CPM_HDMICDR_HDMI_STOP BIT(26)
240 #define CPM_LCR_PD_SCPU BIT(31)
241 #define CPM_LCR_PD_VPU BIT(30)
242 #define CPM_LCR_PD_GPU BIT(29)
243 #define CPM_LCR_PD_GPS BIT(28)
244 #define CPM_LCR_SCPUS BIT(27)
245 #define CPM_LCR_VPUS BIT(26)
246 #define CPM_LCR_GPUS BIT(25)
247 #define CPM_LCR_GPSS BIT(24)
248 #define CPM_LCR_GPU_IDLE BIT(20)
253 #define CPM_LCR_DOZE_ON BIT(2)
260 #define CPM_CLKGR0_DDR1 BIT(31)
261 #define CPM_CLKGR0_DDR0 BIT(30)
262 #define CPM_CLKGR0_IPU BIT(29)
263 #define CPM_CLKGR0_LCD1 BIT(28)
264 #define CPM_CLKGR0_LCD BIT(27)
265 #define CPM_CLKGR0_CIM BIT(26)
266 #define CPM_CLKGR0_I2C2 BIT(25)
267 #define CPM_CLKGR0_UHC BIT(24)
268 #define CPM_CLKGR0_MAC BIT(23)
269 #define CPM_CLKGR0_GPS BIT(22)
270 #define CPM_CLKGR0_PDMAC BIT(21)
271 #define CPM_CLKGR0_SSI2 BIT(20)
272 #define CPM_CLKGR0_SSI1 BIT(19)
273 #define CPM_CLKGR0_UART3 BIT(18)
274 #define CPM_CLKGR0_UART2 BIT(17)
275 #define CPM_CLKGR0_UART1 BIT(16)
276 #define CPM_CLKGR0_UART0 BIT(15)
277 #define CPM_CLKGR0_SADC BIT(14)
278 #define CPM_CLKGR0_KBC BIT(13)
279 #define CPM_CLKGR0_MSC2 BIT(12)
280 #define CPM_CLKGR0_MSC1 BIT(11)
281 #define CPM_CLKGR0_OWI BIT(10)
282 #define CPM_CLKGR0_TSSI BIT(9)
283 #define CPM_CLKGR0_AIC BIT(8)
284 #define CPM_CLKGR0_SCC BIT(7)
285 #define CPM_CLKGR0_I2C1 BIT(6)
286 #define CPM_CLKGR0_I2C0 BIT(5)
287 #define CPM_CLKGR0_SSI0 BIT(4)
288 #define CPM_CLKGR0_MSC0 BIT(3)
289 #define CPM_CLKGR0_OTG BIT(2)
290 #define CPM_CLKGR0_BCH BIT(1)
291 #define CPM_CLKGR0_NEMC BIT(0)
294 #define CPM_CLKGR1_P1 BIT(15)
295 #define CPM_CLKGR1_X2D BIT(14)
296 #define CPM_CLKGR1_DES BIT(13)
297 #define CPM_CLKGR1_I2C4 BIT(12)
298 #define CPM_CLKGR1_AHB BIT(11)
299 #define CPM_CLKGR1_UART4 BIT(10)
300 #define CPM_CLKGR1_HDMI BIT(9)
301 #define CPM_CLKGR1_OTG1 BIT(8)
302 #define CPM_CLKGR1_GPVLC BIT(7)
303 #define CPM_CLKGR1_AIC1 BIT(6)
304 #define CPM_CLKGR1_COMPRES BIT(5)
305 #define CPM_CLKGR1_GPU BIT(4)
306 #define CPM_CLKGR1_PCM BIT(3)
307 #define CPM_CLKGR1_VPU BIT(2)
308 #define CPM_CLKGR1_TSSI1 BIT(1)
309 #define CPM_CLKGR1_I2C3 BIT(0)
314 #define CPM_OPCR_SPENDN BIT(7)
315 #define CPM_OPCR_GPSEN BIT(6)
316 #define CPM_OPCR_SPENDH BIT(5)
317 #define CPM_OPCR_O1SE BIT(4)
318 #define CPM_OPCR_ERCS BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
319 #define CPM_OPCR_USBM BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
322 #define CPM_RSR_P0R BIT(2)
323 #define CPM_RSR_WR BIT(1)
324 #define CPM_RSR_PR BIT(0)
333 #define CPM_BCHCDR_CE_BCH BIT(29)
334 #define CPM_BCHCDR_BCH_BUSY BIT(28)
335 #define CPM_BCHCDR_BCH_STOP BIT(27)