45 	im->ddr.csbnds[0].csbnds =  in fixed_sdram()
49 	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;  in fixed_sdram()
52 	im->ddr.cs_config[1] = 0;  in fixed_sdram()
53 	im->ddr.cs_config[2] = 0;  in fixed_sdram()
54 	im->ddr.cs_config[3] = 0;  in fixed_sdram()
56 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);  in fixed_sdram()
57 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);  in fixed_sdram()
62 	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;  in fixed_sdram()
63 	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */  in fixed_sdram()
64 	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;  in fixed_sdram()
65 	im->ddr.sdram_mode =  in fixed_sdram()
67 	im->ddr.sdram_interval =  in fixed_sdram()
70 	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;  in fixed_sdram()
74 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;  in fixed_sdram()
76 	debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);  in fixed_sdram()
77 	debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);  in fixed_sdram()
78 	debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);  in fixed_sdram()
79 	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);  in fixed_sdram()
80 	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);  in fixed_sdram()
128 	volatile ddr83xx_t *ddr = &im->ddr;  in dram_init()  local
143 	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)  in dram_init()