Lines Matching refs:t0
31 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
32 lw t0, 0(t0)
33 srl t0, t0, MALTA_REVISION_CORID_SHF
34 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
39 beq t0, t1, _gt64120
43 beq t0, t1, _msc01
66 li t0, CPU_TO_GT32(0xdf000000)
67 sw t0, GT_ISD_OFS(t1)
73 li t0, CPU_TO_GT32(0xc0000000)
74 sw t0, GT_PCI0IOLD_OFS(t1)
75 li t0, CPU_TO_GT32(0x40000000)
76 sw t0, GT_PCI0IOHD_OFS(t1)
79 li t0, CPU_TO_GT32(0x80000000)
80 sw t0, GT_PCI0M0LD_OFS(t1)
81 li t0, CPU_TO_GT32(0x3f000000)
82 sw t0, GT_PCI0M0HD_OFS(t1)
84 li t0, CPU_TO_GT32(0xc1000000)
85 sw t0, GT_PCI0M1LD_OFS(t1)
86 li t0, CPU_TO_GT32(0x5e000000)
87 sw t0, GT_PCI0M1HD_OFS(t1)
97 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
99 sw t1, MSC01_PBC_CLKCFG_OFS(t0)
104 sw t1, MSC01_PBC_CS0TIM_OFS(t0)
109 sw t1, MSC01_PBC_CS0RW_OFS(t0)
110 lw t1, MSC01_PBC_CS0CFG_OFS(t0)
116 sw t1, MSC01_PBC_CS0CFG_OFS(t0)
119 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
122 sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
123 sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
124 sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
125 sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
130 sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
131 sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
132 sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
133 sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
138 sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
139 sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
142 sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
143 sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
148 sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
149 sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
150 sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
151 sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
154 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
158 sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
159 sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
160 sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
166 sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
167 sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
168 sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
172 sw t1, MSC01_PCI_BAR0_OFS(t0)
175 sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
176 sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
181 sw t1, MSC01_PCI_HEAD0_OFS(t0)
184 sw t1, MSC01_PCI_HEAD11_OFS(t0)
189 sw t1, MSC01_PCI_HEAD2_OFS(t0)
192 sw zero, MSC01_PCI_HEAD3_OFS(t0)
193 sw zero, MSC01_PCI_HEAD4_OFS(t0)
194 sw zero, MSC01_PCI_HEAD5_OFS(t0)
195 sw zero, MSC01_PCI_HEAD6_OFS(t0)
196 sw zero, MSC01_PCI_HEAD7_OFS(t0)
197 sw zero, MSC01_PCI_HEAD8_OFS(t0)
198 sw zero, MSC01_PCI_HEAD9_OFS(t0)
199 sw zero, MSC01_PCI_HEAD10_OFS(t0)
200 sw zero, MSC01_PCI_HEAD12_OFS(t0)
201 sw zero, MSC01_PCI_HEAD13_OFS(t0)
202 sw zero, MSC01_PCI_HEAD14_OFS(t0)
203 sw zero, MSC01_PCI_HEAD15_OFS(t0)
211 sw t1, MSC01_PCI_HEAD1_OFS(t0)
217 sw t1, MSC01_PCI_SWAP_OFS(t0)
219 sw zero, MSC01_PCI_SWAP_OFS(t0)
223 lw t1, MSC01_PCI_CFG_OFS(t0)
228 sw t1, MSC01_PCI_CFG_OFS(t0)