402 	u32 parent_rate, parent_id;  in versal_clock_get_pll_rate()  local
412 	parent_id = clock[clock[id].parent[0].id].clk_id;  in versal_clock_get_pll_rate()
413 	parent_rate = versal_clock_ref(parent_id);  in versal_clock_get_pll_rate()
439 	u32 parent_id = 0;  in versal_clock_get_parentid()  local
446 		parent_id = ret_payload[1];  in versal_clock_get_parentid()
449 	debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);  in versal_clock_get_parentid()
450 	return clock[clock[id].parent[parent_id].id].clk_id;  in versal_clock_get_parentid()
492 	u32 parent_id;  in versal_clock_calc()  local
499 	parent_id = versal_clock_get_parentid(clk_id);  in versal_clock_calc()
500 	if (((parent_id >> NODE_SUBCLASS_SHIFT) &  in versal_clock_calc()
504 	clk_rate = versal_clock_calc(parent_id);  in versal_clock_calc()