Lines Matching refs:GATE_PERI0

630 #define GATE_PERI0(_id, _parent, _shift) {			\  macro
647 	GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
648 	GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
649 	GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
650 	GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
651 	GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
652 	GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
653 	GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
654 	GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
655 	GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
656 	GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
657 	GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
658 	GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
659 	GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
660 	GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
661 	GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
662 	GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
663 	GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
664 	GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
665 	GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
666 	GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
667 	GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
668 	GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
669 	GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
670 	GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
671 	GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
672 	GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
673 	GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
674 	GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
675 	GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
676 	GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
677 	GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
678 	GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),