Lines Matching refs:GATE_PERI0
454 #define GATE_PERI0(_id, _parent, _shift) { \ macro
471 GATE_PERI0(CLK_PERI_PWM1_PD, CLK_TOP_PWM_QTR_26M, 2),
472 GATE_PERI0(CLK_PERI_PWM2_PD, CLK_TOP_PWM_QTR_26M, 3),
473 GATE_PERI0(CLK_PERI_PWM3_PD, CLK_TOP_PWM_QTR_26M, 4),
474 GATE_PERI0(CLK_PERI_PWM4_PD, CLK_TOP_PWM_QTR_26M, 5),
475 GATE_PERI0(CLK_PERI_PWM5_PD, CLK_TOP_PWM_QTR_26M, 6),
476 GATE_PERI0(CLK_PERI_PWM6_PD, CLK_TOP_PWM_QTR_26M, 7),
477 GATE_PERI0(CLK_PERI_PWM7_PD, CLK_TOP_PWM_QTR_26M, 8),
478 GATE_PERI0(CLK_PERI_PWM_PD, CLK_TOP_PWM_QTR_26M, 9),
479 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_FAXI, 12),
480 GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1, 14),
481 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_FAXI, 17),
482 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_FAXI, 18),
483 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_FAXI, 19),
484 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_FAXI, 20),
485 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_FAXI, 22),
486 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_FAXI, 23),
487 GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI, 28),
488 GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_SF, 29),
489 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_FAXI, 30),
490 GATE_PERI0(CLK_PERI_NFIECC_PD, CLK_TOP_FAXI, 31),