Lines Matching refs:rate
33 .rate = _rate##U, \
44 .rate = _rate##U, \
94 struct pll_rate_table *rate = &auto_table; in pll_clk_set_by_auto() local
124 rate->postdiv1 = postdiv1; in pll_clk_set_by_auto()
125 rate->postdiv2 = postdiv2; in pll_clk_set_by_auto()
145 rate->refdiv = refdiv; in pll_clk_set_by_auto()
146 rate->fbdiv = fbdiv; in pll_clk_set_by_auto()
156 return rate; in pll_clk_set_by_auto()
159 static const struct pll_rate_table *get_pll_settings(unsigned long rate) in get_pll_settings() argument
165 if (rate == px30_pll_rates[i].rate) in get_pll_settings()
169 return pll_clk_set_by_auto(rate); in get_pll_settings()
172 static const struct cpu_rate_table *get_cpu_settings(unsigned long rate) in get_cpu_settings() argument
178 if (rate == px30_cpu_rates[i].rate) in get_cpu_settings()
204 const struct pll_rate_table *rate; in rkclk_set_pll() local
207 rate = get_pll_settings(drate); in rkclk_set_pll()
208 if (!rate) { in rkclk_set_pll()
214 vco_hz = OSC_HZ / 1000 * rate->fbdiv / rate->refdiv * 1000; in rkclk_set_pll()
215 output_hz = vco_hz / rate->postdiv1 / rate->postdiv2; in rkclk_set_pll()
218 pll, rate->fbdiv, rate->refdiv, rate->postdiv1, in rkclk_set_pll()
219 rate->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
237 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); in rkclk_set_pll()
239 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
240 rate->refdiv << PLL_REFDIV_SHIFT)); in rkclk_set_pll()
1115 const struct cpu_rate_table *rate; in px30_armclk_set_clk() local
1118 rate = get_cpu_settings(hz); in px30_armclk_set_clk()
1119 if (!rate) { in px30_armclk_set_clk()
1136 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in px30_armclk_set_clk()
1137 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
1144 rate->aclk_div << CORE_ACLK_DIV_SHIFT | in px30_armclk_set_clk()
1145 rate->pclk_div << CORE_DBG_DIV_SHIFT | in px30_armclk_set_clk()
1158 ulong rate = 0; in px30_clk_get_rate() local
1168 rate = px30_clk_get_pll_rate(priv, APLL); in px30_clk_get_rate()
1171 rate = px30_clk_get_pll_rate(priv, DPLL); in px30_clk_get_rate()
1174 rate = px30_clk_get_pll_rate(priv, CPLL); in px30_clk_get_rate()
1177 rate = px30_clk_get_pll_rate(priv, NPLL); in px30_clk_get_rate()
1180 rate = px30_clk_get_pll_rate(priv, APLL); in px30_clk_get_rate()
1187 rate = px30_mmc_get_clk(priv, clk->id); in px30_clk_get_rate()
1193 rate = px30_i2c_get_clk(priv, clk->id); in px30_clk_get_rate()
1196 rate = px30_i2s_get_clk(priv, clk->id); in px30_clk_get_rate()
1199 rate = px30_nandc_get_clk(priv); in px30_clk_get_rate()
1203 rate = px30_pwm_get_clk(priv, clk->id); in px30_clk_get_rate()
1206 rate = px30_saradc_get_clk(priv); in px30_clk_get_rate()
1209 rate = px30_tsadc_get_clk(priv); in px30_clk_get_rate()
1213 rate = px30_spi_get_clk(priv, clk->id); in px30_clk_get_rate()
1219 rate = px30_vop_get_clk(priv, clk->id); in px30_clk_get_rate()
1225 rate = px30_bus_get_clk(priv, clk->id); in px30_clk_get_rate()
1229 rate = px30_peri_get_clk(priv, clk->id); in px30_clk_get_rate()
1234 rate = px30_crypto_get_clk(priv, clk->id); in px30_clk_get_rate()
1241 return rate; in px30_clk_get_rate()
1244 static ulong px30_clk_set_rate(struct clk *clk, ulong rate) in px30_clk_set_rate() argument
1254 debug("%s %ld %ld\n", __func__, clk->id, rate); in px30_clk_set_rate()
1257 ret = px30_clk_set_pll_rate(priv, NPLL, rate); in px30_clk_set_rate()
1260 ret = px30_armclk_set_clk(priv, rate); in px30_clk_set_rate()
1266 ret = px30_mmc_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1272 ret = px30_i2c_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1275 ret = px30_i2s_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1278 ret = px30_nandc_set_clk(priv, rate); in px30_clk_set_rate()
1282 ret = px30_pwm_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1285 ret = px30_saradc_set_clk(priv, rate); in px30_clk_set_rate()
1288 ret = px30_tsadc_set_clk(priv, rate); in px30_clk_set_rate()
1292 ret = px30_spi_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1298 ret = px30_vop_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1303 ret = px30_bus_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1307 ret = px30_peri_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1312 ret = px30_crypto_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1315 ret = px30_i2s1_mclk_set_clk(priv, clk->id, rate); in px30_clk_set_rate()
1319 ret = px30_mac_set_clk(priv, rate); in px30_clk_set_rate()
1322 ret = px30_mac_set_speed_clk(priv, rate); in px30_clk_set_rate()
1549 ulong rate = 0; in px30_pmuclk_get_rate() local
1554 rate = px30_pmuclk_get_gpll_rate(priv); in px30_pmuclk_get_rate()
1557 rate = px30_pclk_pmu_get_pmuclk(priv); in px30_pmuclk_get_rate()
1563 return rate; in px30_pmuclk_get_rate()
1566 static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate) in px30_pmuclk_set_rate() argument
1571 debug("%s %ld %ld\n", __func__, clk->id, rate); in px30_pmuclk_set_rate()
1574 ret = px30_pmuclk_set_gpll_rate(priv, rate); in px30_pmuclk_set_rate()
1577 ret = px30_pclk_pmu_set_pmuclk(priv, rate); in px30_pmuclk_set_rate()