Lines Matching refs:BIT

16 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
17 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
18 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
19 	[CLK_BUS_EMAC]		= GATE(0x060, BIT(17)),
20 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
21 	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
22 	[CLK_BUS_OTG]		= GATE(0x060, BIT(23)),
23 	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(24)),
24 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(25)),
25 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
26 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
28 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
29 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
30 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
31 	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
32 	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
34 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
35 	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
37 	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
38 	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
39 	[CLK_USB_HSIC]		= GATE(0x0cc, BIT(10)),
40 	[CLK_USB_HSIC_12M]	= GATE(0x0cc, BIT(11)),
41 	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
42 	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
46 	[RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
47 	[RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
48 	[RST_USB_HSIC]          = RESET(0x0cc, BIT(2)),
50 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
51 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
52 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
53 	[RST_BUS_EMAC]		= RESET(0x2c0, BIT(17)),
54 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
55 	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
56 	[RST_BUS_OTG]           = RESET(0x2c0, BIT(23)),
57 	[RST_BUS_EHCI0]         = RESET(0x2c0, BIT(24)),
58 	[RST_BUS_EHCI1]         = RESET(0x2c0, BIT(25)),
59 	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
60 	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
62 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
63 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
64 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
65 	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
66 	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),