39 	u32 bank, max_pins;  in xilinx_gpio_get_bank_pin()  local
43 	for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {  in xilinx_gpio_get_bank_pin()
44 		max_pins = platdata->bank_max[bank];  in xilinx_gpio_get_bank_pin()
47 			      bank, pin_num);  in xilinx_gpio_get_bank_pin()
48 			*bank_num = bank;  in xilinx_gpio_get_bank_pin()
64 	u32 bank, pin;  in xilinx_gpio_set_value()  local
66 	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);  in xilinx_gpio_set_value()
70 	val = priv->output_val[bank];  in xilinx_gpio_set_value()
73 	      __func__, (ulong)platdata->regs, value, offset, bank, pin, val);  in xilinx_gpio_set_value()
80 	writel(val, &platdata->regs->gpiodata + bank * 2);  in xilinx_gpio_set_value()
82 	priv->output_val[bank] = val;  in xilinx_gpio_set_value()
92 	u32 bank, pin;  in xilinx_gpio_get_value()  local
94 	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);  in xilinx_gpio_get_value()
99 	      (ulong)platdata->regs, offset, bank, pin);  in xilinx_gpio_get_value()
101 	if (platdata->bank_output[bank]) {  in xilinx_gpio_get_value()
103 		val = priv->output_val[bank];  in xilinx_gpio_get_value()
106 		val = readl(&platdata->regs->gpiodata + bank * 2);  in xilinx_gpio_get_value()
118 	u32 bank, pin;  in xilinx_gpio_get_function()  local
120 	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);  in xilinx_gpio_get_function()
125 	if (platdata->bank_input[bank])  in xilinx_gpio_get_function()
129 	if (platdata->bank_output[bank])  in xilinx_gpio_get_function()
133 	val = readl(&platdata->regs->gpiodir + bank * 2);  in xilinx_gpio_get_function()
147 	u32 bank, pin;  in xilinx_gpio_direction_output()  local
149 	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);  in xilinx_gpio_direction_output()
154 	if (platdata->bank_input[bank])  in xilinx_gpio_direction_output()
159 	if (!platdata->bank_output[bank]) {  in xilinx_gpio_direction_output()
160 		val = readl(&platdata->regs->gpiodir + bank * 2);  in xilinx_gpio_direction_output()
162 		writel(val, &platdata->regs->gpiodir + bank * 2);  in xilinx_gpio_direction_output()
172 	u32 bank, pin;  in xilinx_gpio_direction_input()  local
174 	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);  in xilinx_gpio_direction_input()
179 	if (platdata->bank_input[bank])  in xilinx_gpio_direction_input()
183 	if (platdata->bank_output[bank])  in xilinx_gpio_direction_input()
186 	val = readl(&platdata->regs->gpiodir + bank * 2);  in xilinx_gpio_direction_input()
188 	writel(val, &platdata->regs->gpiodir + bank * 2);  in xilinx_gpio_direction_input()